Analog-to-digital conversion circuit based on clock signal bootstrap module, chip and electronic equipment

Abstract

The invention relates to the field of analog-to-digital conversion, and provides an analog-to-digital conversion circuit based on a clock signal bootstrap module, a chip and electronic equipment. The circuit comprises a clock signal bootstrap module, a conversion module and a feedback module, the power supply voltage of the clock signal bootstrap module, the power supply voltage of the conversion module and the power supply voltage of the feedback module are equal and smaller than or equal to a first threshold value, and the clock signal bootstrap module is used for generating at least one pair of clock signals with the swing larger than the first threshold value. Outputting the clock signal to the conversion module to drive at least one unit in the conversion module; the conversion module is used for obtaining a digital output signal according to an analog input signal and a feedback signal; the feedback module is used for generating the feedback signal according to the latest digital output signal and outputting the feedback signal to the conversion module. The analog-to-digital conversion circuit disclosed by the embodiment of the invention occupies a smaller chip area, is lower in power consumption, and can realize high-quality analog-to-digital conversion under low voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of analog-to-digital conversion, and in particular to an analog-to-digital conversion circuit, a chip, and an electronic device based on a clock signal bootstrap module. Background Art

[0002] With the application and development of the Internet of Things (IoT), it has become indispensable to obtain real-time information and data from IoT devices. The power supply of IoT devices is an important aspect in the design of IoT systems because it directly affects the reliability, durability and cost of the devices. IoT devices are generally powered by batteries, solar power, cable power, wireless charging and energy harvesting (Energy Harvesting, EH). Among them, energy harvesting refers to the use of ambient energy such as solar energy, wind energy, mechanical vibration or temperature difference to provide power, reducing dependence on batteries.

[0003] However, in some environments, the density of energy that can be collected is often low, and the voltage that can be generated is also low, so that IoT devices must operate at low voltage. This poses a great challenge to the performance of some circuits in IoT devices (such as analog-to-digital conversion circuits). Some existing technologies cannot maintain high-quality analog-to-digital conversion when the power supply voltage is low. Although the analog-to-digital conversion circuits proposed in some existing technologies can maintain high-quality analog-to-digital conversion when the power supply voltage is low, they will increase the power consumption of the analog-to-digital conversion circuit and the chip area occupied. Summary of the invention

[0004] In view of this, the present disclosure proposes an analog-to-digital conversion circuit, chip, and electronic device based on a clock signal bootstrap module. The analog-to-digital conversion circuit of the present disclosure embodiment occupies a smaller chip area and has lower power consumption, and can achieve high-quality analog-to-digital conversion at low voltage.

[0005] According to one aspect of the present disclosure, an analog-to-digital conversion circuit based on a clock signal bootstrap module is provided, the circuit comprising a clock signal bootstrap module, a conversion module and a feedback module, the power supply voltages of the clock signal bootstrap module, the conversion module and the feedback module are equal and less than or equal to a first threshold value, the clock signal bootstrap module is used to generate at least one pair of clock signals with a swing greater than the first threshold value, and output the clock signal to the conversion module to drive at least one unit in the conversion module; the conversion module is used to obtain a digital output signal according to an analog input signal and a feedback signal; the feedback module is used to generate the feedback signal according to the latest digital output signal and output it to the conversion module.

[0006] In a possible implementation, the conversion module includes a first chopping unit, a capacitor filtering unit, a dead zone control unit, a voltage-current conversion unit, a second chopping unit, an integration unit, a quantization unit, and an output unit. The analog input signal includes a differential first input signal and a second input signal. The feedback signal includes a differential first feedback signal and a second feedback signal. The first end of the first chopping unit receives the first input signal, and the second end of the first chopping unit receives the second input signal. The third end of the first chopping unit is connected to the first end of the capacitor filtering unit, and the fourth end of the first chopping unit is connected to the second end of the capacitor filtering unit; the third end of the capacitor filtering unit is connected to the first end of the dead zone control unit and the fourth end of the feedback module, the fourth end of the capacitor filtering unit is connected to the second end of the dead zone control unit and the third end of the feedback module, and the fourth end of the feedback module outputs the first feedback signal. The third end of the feedback module outputs the second feedback signal; the third end of the dead zone control unit is connected to the first end of the voltage-current conversion unit, and the fourth end of the dead zone control unit is connected to the second end of the voltage-current conversion unit; the third end of the voltage-current conversion unit is connected to the first end of the second chopping unit, and the fourth end of the voltage-current conversion unit is connected to the second end of the second chopping unit; the third end of the second chopping unit is connected to the first end of the integration unit, and the fourth end of the second chopping unit is connected to the second end of the integration unit; the third end of the integration unit is connected to the first end of the quantization unit, the fourth end of the integration unit is connected to the second end of the quantization unit, the third end of the quantization unit is connected to the first end of the output unit and the first end of the feedback module, and the fourth end of the quantization unit is connected to the second end of the output unit and the second end of the feedback module; the third end of the output unit outputs the digital output signal.

[0007] In a possible implementation manner, the quantization unit is a time-domain quantization unit, the integration unit is a time-domain integration unit, and the quantization unit and the integration unit are implemented by digital circuits.

[0008] In a possible implementation manner, the clock signal is used to drive the first chopping unit, the dead zone control unit, and the second chopping unit.

[0009] In one possible implementation, the clock signal bootstrap module includes at least one cascaded clock signal bootstrap unit, each clock signal bootstrap unit outputs a pair of clock signals, the clock signal output by the preceding clock signal bootstrap unit is used as the clock signal input by the succeeding clock signal bootstrap unit, and the swing of the clock signal output by the succeeding clock signal bootstrap unit is higher than the swing of the clock signal output by the preceding clock signal bootstrap unit.

[0010] In a possible implementation, the swing of the clock signal used to drive the dead zone control unit is greater than or equal to a second threshold, the swing of the clock signal used to drive the first chopping unit and the second chopping unit is greater than or equal to a third threshold, and the second threshold is greater than the third threshold.

[0011] In a possible implementation, the feedback module includes a logic control unit, a third chopping unit, and a capacitive digital-to-analog conversion unit, the first end of the logic control unit serves as the first end of the feedback module, the second end of the logic control unit serves as the second end of the feedback module, the third end of the logic control unit is connected to the first end of the third chopping unit, and the fourth end of the logic control unit is connected to the second end of the third chopping unit; the third end of the third chopping unit is connected to the first end of the capacitive digital-to-analog conversion unit, and the fourth end of the third chopping unit is connected to the second end of the capacitive digital-to-analog conversion unit; the third end of the capacitive digital-to-analog conversion unit serves as the third end of the feedback module, and the fourth end of the capacitive digital-to-analog conversion unit serves as the fourth end of the feedback module.

[0012] In a possible implementation, the clock signal bootstrap unit includes a first bootstrap subunit and a second bootstrap subunit, the first bootstrap subunit includes a first transistor, a second transistor, a third transistor, and a first capacitor, the second bootstrap subunit includes a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitor, the first electrode of the first transistor is connected to the first electrode of the second transistor and serves as the first input terminal of the first bootstrap subunit, the second electrode of the first transistor is connected to the first end of the first capacitor and serves as the second input terminal of the first bootstrap subunit, the third electrode of the first transistor is connected to the third electrode of the second transistor and the first electrode of the third transistor and serves as the output terminal of the first bootstrap subunit, the second electrode of the second transistor is connected to the second electrode of the third transistor and the second end of the first capacitor, and the third electrode of the third transistor is connected to the power supply voltage; the first electrode of the fourth transistor is connected to the first electrode of the fifth transistor and serves as the first input terminal of the second bootstrap subunit, and the second electrode of the fourth transistor is connected The first end of the second capacitor serves as the second input end of the second bootstrap subunit, the third electrode of the fourth transistor is connected to the third electrode of the fifth transistor and the first electrode of the sixth transistor and serves as the output end of the second bootstrap subunit, the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor and the second end of the second capacitor, and the third electrode of the sixth transistor is connected to the power supply voltage; the first input end of the second bootstrap subunit is connected to the second input end of the first bootstrap subunit to receive the first clock signal, the second input end of the second bootstrap subunit is connected to the first input end of the first bootstrap subunit to receive the second clock signal, the output end of the first bootstrap subunit outputs the third clock signal, and the output end of the second bootstrap subunit outputs the fourth clock signal; the first clock signal and the second clock signal are a pair of differential signals and serve as the clock signal input to the clock signal bootstrap unit, and the third clock signal and the fourth clock signal are a pair of differential signals and serve as the clock signal output from the clock signal bootstrap unit.

[0013] According to another aspect of the present disclosure, a chip is provided, comprising any one of the above analog-to-digital conversion circuits.

[0014] According to another aspect of the present disclosure, an electronic device is provided, comprising the chip described above.

[0015] According to the analog-to-digital conversion circuit of the embodiment of the present disclosure, by setting a clock signal bootstrap module, a clock signal with a swing higher than the first threshold can be obtained when the power supply voltage is lower than the first threshold, and the conversion module is driven by the clock signal. The conversion module obtains a digital output signal according to the analog input signal and the feedback signal, and the feedback module generates a feedback signal according to the latest digital output signal and outputs it to the conversion module, thereby achieving high-quality analog-to-digital conversion. In the analog-to-digital conversion circuit, only some units in the conversion module are driven by a clock signal with a high swing, and other units of the conversion module, as well as the clock signal bootstrap module and the feedback module, can still be powered by a power supply voltage lower than the first threshold, so the power consumption of the analog-to-digital conversion circuit as a whole is relatively low. And the analog-to-digital conversion circuit does not involve boosting, so no additional charge storage is required, and there is no need to set a large area of ​​capacitors, and the chip area occupied is smaller. In summary, the chip area occupied by the analog-to-digital conversion circuit of the embodiment of the present disclosure is smaller, the power consumption is also lower, and high-quality analog-to-digital conversion can be achieved at low voltage.

[0016] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0018] Figure 1 Schematic showing an energy harvesting system powering circuits in an IoT device.

[0019] Figure 2 A working scheme of the ADC when the supply voltage is low is shown.

[0020] Figure 3 Another working scheme of the ADC when the supply voltage is low is shown.

[0021] Figure 4 An exemplary application scenario of the analog-to-digital conversion circuit according to an embodiment of the present disclosure is shown.

[0022] Figure 5 A schematic diagram showing the structure of an analog-to-digital conversion circuit according to an embodiment of the present disclosure.

[0023] Figure 6 A schematic diagram showing the structure of a clock signal bootstrap module according to an embodiment of the present disclosure.

[0024] Figure 7 A schematic diagram showing the structure of a clock signal bootstrap unit according to an embodiment of the present disclosure.

[0025] Figure 8A schematic diagram showing another structure of a clock signal bootstrap module according to an embodiment of the present disclosure.

[0026] Figure 9a A schematic diagram showing the structure of a conversion module according to an embodiment of the present disclosure.

[0027] Figure 9b A schematic diagram showing the structure of a conversion module according to an embodiment of the present disclosure.

[0028] Fig.10 A schematic diagram showing the structure of a feedback module according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0030] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0031] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0032] Figure 1 Schematic showing an energy harvesting system powering circuits in an IoT device.

[0033] like Figure 1 As shown in the figure, the energy harvesting system can collect energy from an external energy source, convert it into a power supply voltage (VDD) and output it to the data transceiver module, digital signal processor (DSP), analog to digital converter (ADC) and other devices in the Internet of Things. The energy density collected by the energy harvesting system is often less than 100uW / cm 2 , and its corresponding output voltage is generally less than 300mV. This voltage is used to power the ADC, DSP, data transceiver module, etc. in the system. For the ADC, it is very difficult to achieve high-quality analog-to-digital conversion at such a low voltage.

[0034] Figure 2 A working scheme of the ADC when the supply voltage is low is shown.

[0035] like Figure 2 As shown in the figure, a DC-DC converter can be used to directly increase the low voltage VDD output by the energy harvesting system to a high voltage VDD' that can enable the ADC to work normally, and provide it to the ADC as the power supply voltage. The ADC converts the input analog signal V IN Converted into digital signal D OUT And output. But this will cause the overall power consumption of ADC to increase a lot. In addition, when using DC-DC converter to increase the voltage, it is necessary to add a very large capacitor on the chip to store the charge, which increases the chip area and thus increases the cost of the chip.

[0036] Figure 3 Another working scheme of the ADC when the supply voltage is low is shown.

[0037] like Figure 3 As shown in the figure, another method is to use some ADCs that can still work normally under low voltage, such as oversampling ADC based on inverter amplifier, oversampling ADC based on ring oscillator, successive approximation register (SAR) ADC based on well-designed comparator, etc., to directly realize analog-to-digital conversion under the low voltage VDD output by the energy harvesting system, and convert the input analog signal V IN Converted into digital signal D OUT However, the circuit modules in these ADCs are often very sensitive to the power supply voltage, and the quality of analog-to-digital conversion fluctuates greatly. In addition, the analog-to-digital conversion quality of these ADCs at low voltages, such as conversion linearity and conversion accuracy, is significantly different from that of ADCs that perform analog-to-digital conversion at normal voltages.

[0038] In summary, some prior arts cannot maintain high-quality analog-to-digital conversion when the power supply voltage is low. Although the analog-to-digital conversion circuits proposed by some prior arts can maintain high-quality analog-to-digital conversion when the power supply voltage is low, they will increase the power consumption and chip area occupied by the analog-to-digital conversion circuit. How to reduce the power consumption and chip area occupied by the analog-to-digital conversion circuit and maintain high-quality analog-to-digital conversion has become a technical problem to be solved in this field.

[0039] In view of this, the present disclosure proposes an analog-to-digital conversion circuit, chip, and electronic device based on a clock signal bootstrap module. The analog-to-digital conversion circuit of the present disclosure embodiment occupies a smaller chip area and has lower power consumption, and can achieve high-quality analog-to-digital conversion at low voltage.

[0040] Figure 4 An exemplary application scenario of the analog-to-digital conversion circuit according to an embodiment of the present disclosure is shown.

[0041] like Figure 4 As shown, the electronic device may include an energy harvesting system and a chip. The analog-to-digital conversion circuit of the embodiment of the present disclosure may be arranged on the chip. The energy harvesting system may power the chip. The value of the power supply voltage output by the energy harvesting system may be less than the first threshold value, that is, the energy harvesting system outputs an ultra-low voltage. The value of the first threshold value may be set according to the application scenario requirements, for example, set to 0.3V. The embodiment of the present disclosure does not limit the specific value of the first threshold value.

[0042] The analog-to-digital conversion circuit can receive an analog input signal to be converted, perform analog-to-digital conversion to obtain a digital output signal, and then output it.

[0043] A data transceiver module (not shown) and a digital signal processor (not shown) may be further provided on the chip. The analog input signal may be a signal received by the data transceiver module, and then transmitted to the analog-to-digital conversion circuit by the data transceiver module. The digital output signal may be output to the DSP for processing, or may be transmitted to the data transceiver module, and then transmitted to other devices / modules by the data transceiver module, which is not limited in the embodiments of the present disclosure.

[0044] Those skilled in the art should understand that if the electronic device itself carries a power supply, the chip can also be powered by the power supply, and when the power supply is insufficient and outputs a voltage signal with a voltage value less than the first threshold, the analog-to-digital conversion circuit on the chip can also achieve high-quality analog-to-digital conversion. The embodiments of the present disclosure do not limit the power source of the chip.

[0045] Figure 5 A schematic diagram showing the structure of an analog-to-digital conversion circuit according to an embodiment of the present disclosure.

[0046] like Figure 5 As shown, in a possible implementation, the circuit includes a clock signal bootstrap module, a conversion module and a feedback module, and the power supply voltages of the clock signal bootstrap module, the conversion module and the feedback module are equal and less than or equal to the first threshold.

[0047] The clock signal bootstrap module is used to generate at least one pair of clock signals with a swing amplitude greater than a first threshold, and output the clock signals to the conversion module to drive at least one unit in the conversion module;

[0048] The conversion module is used to obtain a digital output signal according to an analog input signal and a feedback signal;

[0049] The feedback module is used to generate a feedback signal according to the latest digital output signal and output it to the conversion module.

[0050] For example, the analog-to-digital conversion circuit may include a clock signal bootstrap module, a conversion module, and a feedback module, and all three modules are powered by a power supply voltage that is less than a first threshold.

[0051] The clock signal bootstrap module can generate at least one pair of clock signals with a swing greater than a first threshold, and output the clock signals to the conversion module to drive at least one unit in the conversion module. The conversion module may include multiple units, and some key units may maintain higher performance under the drive of a clock signal with a high swing. In this case, the clock signal generated by the clock signal bootstrap module can be used to drive these key units.

[0052] The embodiments of the present disclosure do not limit the specific structures of the clock signal bootstrap module and the conversion module, as long as the clock signal bootstrap module and the conversion module can achieve the above functions. Examples of the structure of the clock signal bootstrap module, examples of the structure of the conversion module, and examples of key units are given below.

[0053] The analog-to-digital conversion process can include three main stages: voltage-current conversion, integration, and quantization, all of which can be completed by the conversion module. Before the analog input signal enters the voltage-current conversion stage, it can also be subjected to chopping and other operations to optimize the signal quality. When performing the voltage-current conversion operation, the higher the swing of the analog input signal, the greater the deviation of the final digital output signal. Therefore, the conversion module can use the feedback signal to adjust the swing of the analog input signal, and then perform voltage-current conversion, integration, quantization and other operations on the adjusted analog input signal to obtain a digital output signal.

[0054] The analog input signal is periodically input to the conversion module, so the conversion module may output a digital output signal more than once. The feedback signal can be generated by the feedback module based on the latest digital output signal. In this way, the accuracy of the analog-to-digital conversion process regulated by the feedback signal can be improved. The embodiment of the present disclosure does not limit the specific structure of the feedback module, as long as the feedback module can achieve the above functions. An example of the structure of the feedback module is given later.

[0055] According to the analog-to-digital conversion circuit of the embodiment of the present disclosure, by setting a clock signal bootstrap module, a clock signal with a swing higher than the first threshold can be obtained when the power supply voltage is lower than the first threshold, and the conversion module is driven by the clock signal. The conversion module obtains a digital output signal according to the analog input signal and the feedback signal, and the feedback module generates a feedback signal according to the latest digital output signal and outputs it to the conversion module, thereby achieving high-quality analog-to-digital conversion. In the analog-to-digital conversion circuit, only some units in the conversion module are driven by a clock signal with a high swing, and other units of the conversion module, as well as the clock signal bootstrap module and the feedback module, can still be powered by a power supply voltage lower than the first threshold, so the power consumption of the analog-to-digital conversion circuit as a whole is relatively low. And the analog-to-digital conversion circuit does not involve boosting, so no additional charge storage is required, and there is no need to set a large area of ​​capacitors, and the chip area occupied is smaller. In summary, the chip area occupied by the analog-to-digital conversion circuit of the embodiment of the present disclosure is smaller, the power consumption is also lower, and high-quality analog-to-digital conversion can be achieved at low voltage.

[0056] Figure 6 A schematic diagram showing the structure of a clock signal bootstrap module according to an embodiment of the present disclosure.

[0057] like Figure 6 As shown, in a possible implementation, the clock signal bootstrap module includes at least one cascaded clock signal bootstrap unit, each clock signal bootstrap unit outputs a pair of clock signals, the clock signal output by the preceding clock signal bootstrap unit is used as the clock signal input by the succeeding clock signal bootstrap unit, and the swing of the clock signal output by the succeeding clock signal bootstrap unit is higher than the swing of the clock signal output by the preceding clock signal bootstrap unit.

[0058] For example, if the swing of the clock signal obtained by a single clock signal bootstrap unit can meet the driving requirements, the clock signal bootstrap module only needs to include one clock signal bootstrap unit. If the swing of the clock signal obtained by a single clock signal bootstrap unit cannot meet the driving requirements, the clock signal bootstrap module may include a plurality of cascaded clock signal bootstrap units, each clock signal bootstrap unit outputs a pair of clock signals, and the clock signal output by the preceding clock signal bootstrap unit serves as the clock signal input by the succeeding clock signal bootstrap unit. Since the clock signal bootstrap unit can increase the swing of the clock signal, the swing of the clock signal output by the succeeding clock signal bootstrap unit is higher than the swing of the clock signal output by the preceding clock signal bootstrap unit.

[0059] The circuit structure of each stage of the clock signal bootstrap unit can be the same or different. The disclosed embodiment does not limit the specific structure of each stage of the clock signal bootstrap unit, as long as the number of clock signals output by the previous stage clock signal bootstrap unit is consistent with the number of clock signals input by the subsequent stage clock signal bootstrap unit.

[0060] The high level of the first clock signal received by the first-stage clock signal bootstrap unit may be equal to the power supply voltage, and the high level of the first clock signal received by the second-stage and subsequent clock signal bootstrap units may be greater than the power supply voltage. Ideally, the high level of the clock signal output by the k-th stage (k is a positive integer) clock signal bootstrap unit may be equal to k+1 times the power supply voltage.

[0061] In this way, the clock signal bootstrap circuit can output a clock signal that meets the requirements of the application scenario.

[0062] Figure 7 A schematic diagram showing the structure of a clock signal bootstrap unit according to an embodiment of the present disclosure.

[0063] like Figure 7 As shown, in a possible implementation, the clock signal bootstrap unit includes a first bootstrap subunit 51 and a second bootstrap subunit 52, the first bootstrap subunit 51 includes a first transistor M1, a second transistor M2, a third transistor M3, and a first capacitor C1, and the second bootstrap subunit 52 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a second capacitor C2.

[0064] The first electrode m11 of the first transistor is connected to the first electrode m21 of the second transistor and serves as the first input terminal w11 of the first bootstrap subunit, the second electrode m12 of the first transistor is connected to the first terminal c11 of the first capacitor and serves as the second input terminal w12 of the first bootstrap subunit, the third electrode m13 of the first transistor is connected to the third electrode m23 of the second transistor and the first electrode m31 of the third transistor and serves as the output terminal w13 of the first bootstrap subunit, the second electrode m22 of the second transistor is connected to the second electrode m32 of the third transistor and the second terminal c12 of the first capacitor, and the third electrode m33 of the third transistor is connected to the power supply voltage VDD;

[0065] The first electrode m41 of the fourth transistor is connected to the first electrode m51 of the fifth transistor and serves as the first input terminal w21 of the second bootstrap subunit, the second electrode m42 of the fourth transistor is connected to the first terminal c21 of the second capacitor and serves as the second input terminal w22 of the second bootstrap subunit, the third electrode m43 of the fourth transistor is connected to the third electrode m53 of the fifth transistor and the first electrode m61 of the sixth transistor and serves as the output terminal w23 of the second bootstrap subunit, the second electrode m52 of the fifth transistor is connected to the second electrode m62 of the sixth transistor and the second terminal c22 of the second capacitor, and the third electrode m63 of the sixth transistor is connected to the power supply voltage VDD;

[0066] The first input terminal w21 of the second bootstrap sub-unit is connected to the second input terminal w12 of the first bootstrap sub-unit and receives the first clock signal CLK PThe second input terminal w22 of the second bootstrap subunit is connected to the first input terminal w11 of the first bootstrap subunit, receiving the second clock signal CLK N The output terminal w13 of the first bootstrap sub-unit outputs the third clock signal CLK BSTP The output terminal w23 of the second bootstrap sub-unit outputs the fourth clock signal CLK BSTN ;

[0067] The first clock signal CLK P and the second clock signal CLK N It is a pair of differential signals and serves as the clock signal input to the clock signal bootstrap unit. The third clock signal CLK BSTP and the fourth clock signal CLK BSTN It is a pair of differential signals and serves as the clock signal output by the clock signal bootstrap unit.

[0068] For example, the clock signal bootstrap unit may include a first bootstrap sub-unit and a second bootstrap sub-unit.

[0069] The first bootstrap sub-unit may include a first transistor, a second transistor, a third transistor and a first capacitor.

[0070] The second bootstrap subunit may include a fourth transistor, a fifth transistor, a sixth transistor and a second capacitor. The first transistor may be an N-channel transistor, and the second and third transistors may be P-channel transistors. The fourth transistor may be an N-channel transistor, and the fifth and sixth transistors may be P-channel transistors. The first electrode of each transistor may be a gate, the second electrode may be a source, and the third electrode may be a drain.

[0071] Since the signal received by the first input terminal of the first bootstrap subunit is the same as the signal received by the second input terminal of the second bootstrap subunit, the first input terminal of the first bootstrap subunit can be connected to the second input terminal of the second bootstrap subunit, and together serve as one input terminal of the clock signal bootstrap unit. Since the signal received by the second input terminal of the first bootstrap subunit is the same as the signal received by the first input terminal of the second bootstrap subunit, the second input terminal of the first bootstrap subunit can be connected to the first input terminal of the second bootstrap subunit, and together serve as another input terminal of the clock signal bootstrap unit. The output terminal of the first bootstrap subunit and the output terminal of the second bootstrap subunit can be respectively used as two output terminals of the clock signal bootstrap circuit.

[0072] The first clock signal CLK P It can be a low-swing clock signal input from the clock signal bootstrap circuit, and its voltage value can be 0~V clk . V clk can be greater than or equal to the power supply voltage VDD. clkThe specific value of is not limited. The clock signal bootstrap unit may further include a clock generator (not shown) for generating a first clock signal CLK P The second clock signal CLK N The clock signal bootstrap unit may be input from outside, or the clock signal bootstrap unit may be input from outside according to the first clock signal CLK P The embodiment of the present disclosure is for the first clock signal CLK P and the second clock signal CLK N The source is not restricted.

[0073] Since the first clock signal CLK P and the second clock signal CLK N It is a pair of differential signals. The first clock signal CLK P The voltage value is 0~V clk , so CLK P = 0 when CLK N =V clk , that is, when the first clock signal is at a low level, the second clock signal is at a high level. Similarly, CLK P =V clk CLK N =0, that is, when the first clock signal is at a high level, the second clock signal is at a low level.

[0074] The third clock signal CLK is introduced below BSTP The level of the first clock signal CLK P and the second clock signal CLK N relationship.

[0075] In a possible implementation, the first clock signal CLK P When the voltage is low, the second electrode m12 and the third electrode m13 of the first transistor are turned on, the second electrode m32 and the third electrode m33 of the third transistor are turned on, the second electrode m22 and the third electrode m23 of the second transistor are turned off, and the gate-source voltage is greater than or equal to 0, the power supply voltage VDD charges the first capacitor C1 through the third transistor, and the third clock signal CLK BSTP is low level;

[0076] The first clock signal CLK P When the voltage is high, the second electrode m12 and the third electrode m13 of the first transistor are disconnected and the gate-source voltage is less than 0, the second electrode m32 and the third electrode m33 of the third transistor are disconnected, the second electrode m22 and the third electrode m23 of the second transistor are turned on, the first capacitor C1 is discharged, and the third clock signal CLK BSTP is high level and the third clock signal CLK BSTP The level is greater than the first clock signal CLK PThe level of

[0077] The first clock signal CLK P When the high level of is equal to the power supply voltage, when the second electrode and the third electrode of the second transistor are disconnected, the gate-source voltage of the second transistor is equal to 0;

[0078] The first clock signal CLK P When the high level of is greater than the power supply voltage, when the second electrode and the third electrode of the second transistor are disconnected, the gate-source voltage of the second transistor is greater than 0.

[0079] See also Figure 7 Since the first terminal c11 of the first capacitor receives the first clock signal CLK P , so CLK P =0, the voltage at the first terminal c11 of the first capacitor is 0.

[0080] The first electrode m11 of the first transistor receives the second clock signal CLK N The second electrode m12 of the first transistor receives the first clock signal CLK P , so CLK P =0, the voltage of the first electrode m11 of the first transistor is V clk , the voltage of the second electrode m12 is 0. The first transistor is an N-channel transistor, so the second electrode m12 and the third electrode m13 of the first transistor are turned on. The third electrode m13 of the first transistor outputs the third clock signal CLK BSTP , so the third clock signal CLK BSTP The voltage value is also 0.

[0081] The first electrode m21 of the second transistor receives the second clock signal CLK N , so CLK P = 0, the voltage of the first electrode m21 of the second transistor is V clk The second transistor is a P-channel transistor, so the second electrode m22 and the third electrode m23 of the second transistor are disconnected.

[0082] The third transistor is a P-channel transistor and CLK BSTP =0, so the second terminal m32 and the third terminal m33 of the third transistor are turned on. At this time, the power supply voltage VDD charges the first capacitor C1 through the third transistor M3, so that the voltage at the second end c12 of the first capacitor C1 is VDD.

[0083] The second end c12 of the first capacitor C1 is connected to the second electrode m22 of the second transistor, so the voltage of the second electrode m22 of the second transistor is also VDD. clk is greater than or equal to the power supply voltage VDD, so the gate-source voltage of the second transistor (V clk-VDD) is greater than or equal to 0.

[0084] In this case, as long as V clk >VDD, the gate-source voltage of the second transistor will be greater than 0. When the second transistor is a P-channel transistor, the leakage level of the second transistor will be greatly reduced.

[0085] In this way, when the first clock signal is at a high level, the leakage level of the clock signal bootstrap circuit is reduced, thereby reducing the power consumption of the clock signal bootstrap circuit.

[0086] Similarly, CLK P =V clk When the voltage at the first terminal c11 of the first capacitor is VDD, the voltage at the second terminal c12 of the first capacitor reaches VDD+V clk .

[0087] CLK P =V clk CLK N =0, that is, the first clock signal CLK P When the second clock signal CLK is high, N is low level.

[0088] The first electrode m11 of the first transistor receives the second clock signal CLK N The second electrode m12 of the first transistor receives the first clock signal CLK P , so CLK P =V clk When the voltage of the first electrode m11 of the first transistor is 0, the voltage of the second electrode m12 is V clk The first transistor is an N-channel transistor, and thus the second electrode m12 and the third electrode m13 of the first transistor are disconnected.

[0089] The first electrode m21 of the second transistor receives the second clock signal CLK N , so CLK P =V clk When , the voltage of the first electrode m21 of the second transistor is 0. The second transistor is a P-channel transistor, so the second electrode m22 and the third electrode m23 of the second transistor are turned on.

[0090] The voltage at the second terminal c12 of the first capacitor is equal to VDD+V clk , when the second and third electrodes of the second transistor are turned on, if leakage is not considered, the voltage of the third electrode m23 of the second transistor and the first electrode m31 of the third transistor is also equal to VDD+V clk ,CLK BSTP =VDD+V clkThe third transistor is a P-channel transistor, so the second electrode m32 and the third electrode m33 of the third transistor are disconnected.

[0091] At this time, the voltage difference between the second electrode m12 and the third electrode m13 of the first transistor is VDD, so the first transistor has leakage. However, since the voltage of the first electrode m11 of the first transistor is equal to 0, the voltage of the second electrode m12 is equal to V clk Therefore, the gate-source voltage of the first transistor is less than 0. When the first transistor is an N-channel transistor, the leakage level of the first transistor will be greatly reduced.

[0092] The fourth clock signal CLK is introduced below BSTN The level of the first clock signal CLK P and the second clock signal CLK N relationship.

[0093] In a possible implementation, the second clock signal CLK N When the gate-source voltage is greater than or equal to 0, the power supply voltage charges the second capacitor C2 through the sixth transistor, and the fourth clock signal CLK BSTN is low level;

[0094] The second clock signal CLK N When the fourth transistor is at a high level, the second electrode m42 and the third electrode m43 are disconnected and the gate-source voltage is less than 0, the second electrode m62 and the third electrode m63 of the sixth transistor are disconnected, the second electrode m52 and the third electrode m53 of the fifth transistor are turned on, the second capacitor is discharged, and the fourth clock signal CLK BSTN is high level and the fourth clock signal CLK BSTN The level of the second clock signal CLK N The level of

[0095] The second clock signal CLK N When the high level of is equal to the power supply voltage, when the second electrode and the third electrode of the fifth transistor are disconnected, the gate-source voltage of the fifth transistor is equal to 0;

[0096] The second clock signal CLK N When the high level of is greater than the power supply voltage, when the second electrode and the third electrode of the fifth transistor are disconnected, the gate-source voltage of the fifth transistor is less than 0.

[0097] See also Figure 7 Since the first terminal c21 of the second capacitor receives the second clock signal CLK N , and the first clock signal CLKP and the second clock signal CLK N It is a pair of differential signals, so CLK N =0, CLK P =V clk When the voltage at the first terminal c21 of the second capacitor is 0, the first electrode m41 of the fourth transistor receives the first clock signal CLK P The second electrode m42 of the fourth transistor receives the second clock signal CLK N , so CLK P =V clk When the voltage of the first electrode m41 of the fourth transistor is V clk , the voltage of the second electrode m42 is 0. The fourth transistor is an N-channel transistor, so the second electrode m42 and the third electrode m43 of the fourth transistor are turned on. The third electrode m43 of the fourth transistor outputs the fourth clock signal CLK BSTN , so the fourth clock signal CLK BSTN The voltage value is also 0.

[0098] The first electrode m51 of the fifth transistor receives the first clock signal CLK P , so CLK P =V clk When the voltage of the first electrode m51 of the fifth transistor is V clk The fifth transistor is a P-channel transistor, and thus the second electrode m52 and the third electrode m53 of the fifth transistor are disconnected.

[0099] The sixth transistor is a P-channel transistor and CLK BSTP =0, so the second electrode m62 and the third electrode m63 of the sixth transistor are turned on. At this time, the power supply voltage VDD charges the second capacitor C2 through the sixth transistor, so that the voltage at the second end c22 of the second capacitor is VDD.

[0100] The second end c22 of the second capacitor is connected to the second electrode m52 of the fifth transistor, so the voltage of the second electrode m52 of the fifth transistor is also VDD. clk is greater than or equal to the power supply voltage VDD, so the gate-source voltage (V clk -VDD) is greater than or equal to 0.

[0101] In this case, as long as V clk >VDD, the gate-source voltage of the fifth transistor (V clk -VDD) will be greater than 0. When the fifth transistor is a P-channel transistor, the leakage level of the fifth transistor can be reduced.

[0102] Similarly, CLK P=0, the voltage at the first terminal c21 of the second capacitor is VDD. The second capacitor discharges so that the voltage at the second terminal c22 of the second capacitor reaches VDD+V clk .

[0103] CLK P = 0 when CLK N =V clk The first electrode m41 of the fourth transistor receives the first clock signal CLK P The second electrode m42 of the fourth transistor receives the second clock signal CLK N , so CLK P =0, the voltage of the first electrode m41 of the fourth transistor is 0, and the voltage of the second electrode m42 is V clk The fourth transistor is an N-channel transistor, and thus the second electrode m42 and the third electrode m43 of the fourth transistor are disconnected.

[0104] The first electrode m51 of the fifth transistor receives the first clock signal CLK P , so CLK P = 0, the voltage of the first electrode m51 of the fifth transistor is 0. The fifth transistor is a P-channel transistor, so the second electrode m52 and the third electrode m53 of the fifth transistor are turned on.

[0105] The voltage at the second terminal c22 of the second capacitor is equal to VDD+V clk , when the second electrode m52 and the third electrode m53 of the fifth transistor are turned on, if leakage is not considered, the voltage of the third electrode m53 of the fifth transistor and the first electrode m61 of the sixth transistor is also equal to VDD+V clk ,CLK BSTN =VDD+V clk The sixth transistor is a P-channel transistor, and thus the second electrode m62 and the third electrode m63 of the sixth transistor are disconnected.

[0106] At this time, the voltage difference between the second electrode m42 and the third electrode m43 of the fourth transistor is VDD, so the fourth transistor has leakage. However, since the voltage of the first electrode of the fourth transistor is equal to 0, the voltage of the second electrode is equal to V clk Therefore, the gate-source voltage of the fourth transistor is less than 0. When the fourth transistor is an N-channel transistor, the leakage level of the fourth transistor will be greatly reduced.

[0107] In this way, no matter when the first clock signal is at a high level or a low level, the leakage level of at least one transistor in the clock signal bootstrap unit is reduced, thereby reducing the power consumption of the clock signal bootstrap unit.

[0108] Since the clock signal bootstrap unit can output a differential clock signal, the differential clock signal can drive a device with higher linearity, and thus can support the setting of a device with higher linearity in the conversion module, thereby improving the performance of the analog-to-digital conversion circuit.

[0109] Those skilled in the art should understand that the embodiments of the present disclosure do not impose any restrictions on the types of each transistor, nor on the type of each pole of each transistor, as long as the leakage level of at least one transistor in the clock signal bootstrap unit is reduced regardless of whether the first clock signal is at a high level or a low level.

[0110] Figure 8 A schematic diagram showing another structure of a clock signal bootstrap module according to an embodiment of the present disclosure.

[0111] like Figure 8 As shown, the clock signal bootstrap unit also includes an inverter, the input end of the inverter is connected to the second input end w12 of the first bootstrap sub-unit and the first input end w21 of the second bootstrap sub-unit, the output end of the inverter is connected to the first input end w11 of the first bootstrap sub-unit and the second input end w22 of the second bootstrap sub-unit, and the second clock signal is generated by the inverter.

[0112] At this time, the input end of the inverter, the second input end of the first bootstrap subunit and the first input end of the second bootstrap subunit can be used as the input end of the clock signal bootstrap subunit, and the output end of the first bootstrap subunit and the output end of the second bootstrap subunit can be used as the two output ends of the clock signal bootstrap subunit respectively.

[0113] For example, if the clock signal bootstrap unit receives a single-ended clock signal (such as the first clock signal), it can be Figure 7 Based on the circuit structure of the clock signal bootstrap unit shown in the figure, an inverter is added, so that the input end of the inverter is connected to the second input end of the first bootstrap sub-unit and the first input end of the second bootstrap sub-unit, and the output end of the inverter is connected to the first input end of the first bootstrap sub-unit and the second input end of the second bootstrap sub-unit. That is, the input end of the inverter is connected to the first end c11 of the first capacitor, the second electrode m12 of the first transistor, the first electrode m41 of the fourth transistor, and the first electrode m51 of the fifth transistor, and the output end of the inverter is connected to the first end c21 of the second capacitor, the second electrode m42 of the fourth transistor, the first electrode m11 of the first transistor, and the first electrode m21 of the second transistor.

[0114] In this case, the first clock signal is simultaneously input to the second input terminal of the first bootstrap subunit, the first input terminal of the second bootstrap subunit and the input terminal of the inverter. The inverter can directly invert the first clock signal to obtain the second clock signal, which is then input to the first input terminal of the first bootstrap subunit and the second input terminal of the second bootstrap subunit.

[0115] In this way, the adaptability of the clock signal bootstrap unit to different application scenarios is improved.

[0116] Figure 9a and Figure 9b A schematic diagram showing the structure of a conversion module according to an embodiment of the present disclosure.

[0117] like Figure 9a and Figure 9b As shown, in a possible implementation, the conversion module includes a first chopping unit 10, a capacitor filtering unit 20, a dead zone control unit 30, a voltage-current conversion unit 40, a second chopping unit 50, an integration unit 60, a quantization unit 70, and an output unit 80.

[0118] The analog input signal includes a differential first input signal VINP and a second input signal VINN, the feedback signal includes a differential first feedback signal VFP and a second feedback signal VFN,

[0119] The first end a1 of the first chopping unit receives the first input signal VINP, the second end a2 of the first chopping unit receives the second input signal VINN, the third end a3 of the first chopping unit is connected to the first end b1 of the capacitor filter unit, and the fourth end a4 of the first chopping unit is connected to the second end b2 of the capacitor filter unit;

[0120] The third terminal b3 of the capacitor filter unit is connected to the first terminal d1 of the dead zone control unit and the fourth terminal n4 of the feedback module, the fourth terminal b4 of the capacitor filter unit is connected to the second terminal d2 of the dead zone control unit and the third terminal n3 of the feedback module, the fourth terminal n4 of the feedback module outputs the first feedback signal VFP, and the third terminal n3 of the feedback module outputs the second feedback signal VFN;

[0121] The third terminal d3 of the dead zone control unit is connected to the first terminal e1 of the voltage-current conversion unit, and the fourth terminal d4 of the dead zone control unit is connected to the second terminal e2 of the voltage-current conversion unit;

[0122] The third terminal e3 of the voltage-current conversion unit is connected to the first terminal f1 of the second chopping unit, and the fourth terminal e4 of the voltage-current conversion unit is connected to the second terminal f2 of the second chopping unit;

[0123] The third end f3 of the second chopping unit is connected to the first end g1 of the integration unit, and the fourth end f4 of the second chopping unit is connected to the second end g2 of the integration unit;

[0124] The third terminal g3 of the integration unit is connected to the first terminal h1 of the quantization unit, the fourth terminal g4 of the integration unit is connected to the second terminal h2 of the quantization unit, the third terminal h3 of the quantization unit is connected to the first terminal j1 of the output unit and the first terminal n1 of the feedback unit, and the fourth terminal h4 of the quantization unit is connected to the second terminal j2 of the output unit and the second terminal n2 of the feedback unit;

[0125] The third terminal j3 of the output unit outputs the digital output signal DOUT.

[0126] For example, the conversion module may include a first chopping unit, a capacitor filtering unit, a dead zone control unit, a voltage-current conversion unit, a second chopping unit, an integration unit, a quantization unit, and an output unit.

[0127] The first chopping unit may receive an analog input signal input from the outside. The analog input signal may be a differential signal, including a first input signal and a second input signal. In this case, the first chopping unit, the capacitor filter unit, the dead zone control unit, the voltage-current conversion unit, the second chopping unit, the integration unit, and the quantization unit may include two input terminals and two output terminals respectively; the output unit may include two input terminals and one output terminal.

[0128] The first end of the first chopping unit receives a first input signal, the second end receives a second input signal, the third end outputs a signal VAP obtained by chopping the first input signal, and the fourth end outputs a signal VAN obtained by chopping the second input signal.

[0129] like Figure 9b As shown, the first chopping unit may include switches S1-S4. The first end s11 of S1 is connected to the first end s31 of S3 and serves as the first end of the first chopping unit. The second end s12 of S1 is connected to the first end s41 of S4 and serves as the third end of the first chopping unit. The first end s21 of S2 is connected to the second end s42 of S4 and serves as the second end of the first chopping unit. The second end s22 of S2 is connected to the second end s32 of S3 and serves as the fourth end of the first chopping unit.

[0130] Those skilled in the art should understand that the first chopping unit may also be implemented using other structures, as long as it has a chopping function and can chop the differential input signal to obtain a differential output signal. The embodiments of the present disclosure do not limit the specific structure of the first chopping unit.

[0131] After being outputted by the first chopping unit, the signal VAP and the signal VAN are inputted to the first end and the second end of the capacitor filtering unit. Figure 9bAs shown, the capacitive filter unit may include a capacitor C3 and a capacitor C4. One end of the capacitor C3 serves as the first end of the capacitive filter unit, and the other end of the capacitor C3 serves as the third end of the capacitive filter unit; one end of the capacitor C4 serves as the second end of the capacitive filter unit, and the other end of the capacitor C4 serves as the fourth end of the capacitive filter unit.

[0132] Capacitor C3 can be used to filter out interference components in signal VAP. Capacitor C4 can be used to filter out interference components in signal VAN. Since the third end of the capacitor filter unit is also connected to the fourth end of the feedback module, and the fourth end of the capacitor filter unit is also connected to the third end of the feedback module, the feedback signal output by the feedback module is a differential signal and includes a first feedback signal VFP and a second feedback signal VFN. The fourth end and the third end of the feedback module output the first feedback signal VFP and the second feedback signal VFN respectively. Therefore, after the interference components in signal VAP are filtered out, the swing amplitude is adjusted by the first feedback signal VFP to obtain signal VBP and output to the first end of the dead zone control unit. After the interference components in signal VAN are filtered out, the swing amplitude is adjusted by the second feedback signal VFN to obtain signal VBN and output to the second end of the dead zone control unit.

[0133] like Figure 9b As shown, the dead zone control unit may include a switch S5 and a switch S6. One end of the switch S5 serves as the first end of the dead zone control unit, and the other end serves as the third end of the dead zone control unit; one end of the switch S6 serves as the second end of the dead zone control unit, and the other end serves as the fourth end of the dead zone control unit. The third end of the dead zone control unit is connected to the first end of the voltage-current conversion unit, and the fourth end is connected to the second end of the voltage-current conversion unit. After the signal VBP and the signal VBN enter the voltage-current conversion unit, they enter the voltage-current conversion stage described above. Therefore, the switch S5 and the switch S6 can be controlled to be disconnected within a short period of time in each cycle (the cycle frequency can be the sampling frequency of the analog-to-digital conversion circuit) to prevent the signal VBP and the signal VBN from entering the voltage-current conversion unit, so as to optimize the quality of the signal output by the voltage-current conversion unit (for example, to remove the burrs in the signal output by the voltage-current conversion unit). The time period for controlling the switch S5 and the switch S6 to be disconnected can be set according to the application scenario requirements, and the embodiment of the present disclosure is not limited to this.

[0134] The voltage-to-current conversion unit can convert the input signal VBP into a current signal IEP and the input signal VBN into a current signal IEN. The function of the voltage-to-current conversion unit can be realized by a transconductance amplifier in the prior art, which will not be described in detail here.

[0135] The current signal IEP can be input to the first end of the second chopping unit, and the current signal IEN can be input to the second end of the second chopping unit. The structure and function of the second chopping unit can be the same as those of the first chopping unit, and will not be repeated here. The third end of the second chopping unit outputs the signal IEP after chopping to obtain the signal IFP, and the fourth end outputs the signal IEN after chopping to obtain the signal IFN.

[0136] like Figure 9b As shown, the integration unit may include a first integrator and a second integrator. The signal IFP may be input to one end of the first integrator (the first end of the integration unit), the first integrator integrates the signal IFP, and outputs the signal IGP through the other end (the third end of the integration unit). The signal IFN may be input to one end of the second integrator (the second end of the integration unit), the second integrator integrates the signal IFN, and outputs the signal IGN through the other end (the fourth end of the integration unit). The first integrator and the second integrator may be implemented based on the prior art, and the structures of the first integrator and the second integrator will not be described in detail herein.

[0137] The signal IGP can be input to the first terminal of the quantization unit, and the signal IGN can be input to the second terminal of the quantization unit. The quantization unit can quantize the signal IGP into a value A and quantize the signal IGN into a value B. The value A can be output through the third terminal of the quantization unit, and the value B can be output through the fourth terminal of the quantization unit. The quantization unit can be implemented based on the existing technology, and the structure of the quantization unit will not be described in detail here.

[0138] The value A can be input to the first terminal of the output unit, and the value B can be input to the second terminal of the output unit. Figure 9b As shown, the output unit can perform a subtraction operation on the value A and the value B, and use the operation result as a digital output signal DOUT. The digital output signal DOUT can be output from the third terminal of the output unit. The output unit can be implemented based on the existing technology, and the specific structure of the output unit will not be repeated here.

[0139] See also Figure 9a , the value A and the value B are also input to the feedback module. The feedback module can output a first feedback signal VFP and a second feedback signal VFN according to the value A and the value B. The structure of the feedback module and the example of the feedback module implementing the above functions can be found in Fig.10 .

[0140] In a possible implementation manner, the quantization unit is a time-domain quantization unit, the integration unit is a time-domain integration unit, and the quantization unit and the integration unit are implemented using digital circuits.

[0141] For example, since the characteristics of the time domain integration unit and the time domain quantization unit are to process signals in the time domain instead of in the analog domain, the time domain integration unit and the time domain quantization unit can be implemented by digital circuits. Digital circuits can work at low voltages (especially digital circuits under advanced processes, the more advanced the process, the lower the voltage at which they can work), so the time domain integration unit and the time domain quantization unit can maintain high performance at a power supply voltage lower than the first threshold. This further increases the proportion of digital circuits in the analog-to-digital converter circuit and further reduces the power consumption of the analog-to-digital conversion circuit.

[0142] In a possible implementation, the clock signal is used to drive the first chopping unit, the dead zone control unit, and the second chopping unit.

[0143] The clock signal output by the clock signal bootstrap module mentioned above can be used to drive at least one unit in the conversion module. In one example, the driven units may be the first chopping unit, the dead zone control unit, and the second chopping unit.

[0144] In a possible implementation, the swing of the clock signal used to drive the dead zone control unit is greater than or equal to the second threshold, the swing of the clock signal used to drive the first chopping unit and the second chopping unit is greater than or equal to the third threshold, and the second threshold is greater than the third threshold.

[0145] For example, the higher the swing of the clock signal, the better the effect of driving the first chopping unit, the dead zone control unit, and the second chopping unit, but the greater the power consumption. Therefore, the clock signal driving the first chopping unit, the dead zone control unit, and the second chopping unit can be determined according to the requirements of the first chopping unit, the dead zone control unit, and the second chopping unit for the swing of the clock signal.

[0146] The first chopping unit and the second chopping unit may have a clock signal swing requirement equal to a third threshold value (e.g., 0.9V). The dead zone control unit may have a higher clock signal swing requirement, which may be equal to a second threshold value (e.g., 1.1V). The swing of the first pair of clock signals output by the clock signal bootstrap unit may be 0.9V, the swing of the second pair of clock signals may be 1V, and the swing of the third pair of clock signals may be 1.1V. In this case, the first pair of clock signals may be used to drive the first chopping unit and the second chopping unit, and the third pair of clock signals may be used to drive the dead zone control unit.

[0147] If the swing of the pair of clock signals with the lowest swing output by the clock signal bootstrap module exceeds the second threshold, the pair of clock signals with the lowest swing can be used to drive the first chopping unit, the dead zone control unit and the second chopping unit.

[0148] That is, the swing of the clock signal used to drive the dead zone control unit is greater than or equal to the second threshold, the swing of the clock signal used to drive the first chopping unit and the second chopping unit is greater than or equal to the third threshold, and the second threshold is greater than the third threshold.

[0149] In this way, the power consumption of the analog-to-digital conversion circuit can be reduced while ensuring the quality of the analog-to-digital conversion.

[0150] Fig.10 A schematic diagram showing the structure of a feedback module according to an embodiment of the present disclosure.

[0151] like Fig.10 As shown, in a possible implementation, the feedback module includes a logic control unit, a third chopping unit, and a capacitive digital-to-analog conversion unit.

[0152] The first end of the logic control unit serves as the first end of the feedback module, the second end of the logic control unit serves as the second end of the feedback module, the third end of the logic control unit is connected to the first end of the third chopping unit, and the fourth end of the logic control unit is connected to the second end of the third chopping unit;

[0153] The third end of the third chopping unit is connected to the first end of the capacitive digital-to-analog conversion unit, and the fourth end of the third chopping unit is connected to the second end of the capacitive digital-to-analog conversion unit;

[0154] The third terminal of the capacitive digital-to-analog conversion unit serves as the third terminal of the feedback module, and the fourth terminal of the capacitive digital-to-analog conversion unit serves as the fourth terminal of the feedback module.

[0155] For example, the entire feedback module can be implemented using a digital circuit, and may include a logic control unit 11 , a third chopping unit 21 , and a capacitive digital-to-analog conversion unit 31 .

[0156] The first terminal n1 of the logic control unit serves as the first terminal of the feedback module to receive the value A, and the second terminal n2 of the logic control unit serves as the second terminal of the feedback module to receive the value B. According to the values ​​A and B, the logic control unit can obtain a digital control signal, which can be a differential signal, including a signal ctrl1 and a signal ctrl2. The digital control signal is used to control the degree of regulation of the analog input signal by the feedback module. The logic control unit can be implemented based on the prior art, and the specific implementation method of the logic control unit will not be repeated here.

[0157] The third terminal p3 of the logic control unit can be connected to the first terminal q1 of the third chopping unit, and the fourth terminal p4 of the logic control unit can be connected to the second terminal q2 of the third chopping unit, and the signal ctrl1 and the signal ctrl2 are input to the third chopping unit for chopping. The signal ctrl1 is chopped to obtain the signal ctrl11, and the signal ctrl2 is chopped to obtain the signal ctrl22. The third chopping unit can be implemented based on the prior art, and the specific implementation method of the third chopping unit will not be repeated here.

[0158] The third terminal q3 of the third chopping unit can input the signal ctrl11 to the first terminal p1 of the capacitive digital-to-analog conversion unit, and the fourth terminal q4 of the third chopping unit can input the signal ctrl22 to the second terminal p2 of the capacitive digital-to-analog conversion unit. The capacitive digital-to-analog conversion unit can perform digital-to-analog conversion on the signal ctrl11 to obtain the signal VFN, and perform digital-to-analog conversion on the signal ctrl22 to obtain the signal VFP, and the signal VFP and the signal VFN can be analog signals. In this case, the signal VFP can be operated with the signal VAP, and the signal VFN can be operated with the signal VAN. The third terminal n3 of the capacitive digital-to-analog conversion unit can output the signal VFN, and the fourth terminal n4 can output the signal VFP. The capacitive digital-to-analog conversion unit can be implemented based on the prior art, and the specific implementation method of the capacitive digital-to-analog conversion unit will not be repeated here.

[0159] The present disclosure also provides a chip, including the analog-to-digital conversion circuit described above. The schematic diagram of the chip structure can be found in Figure 4 .

[0160] The embodiment of the present disclosure also provides an electronic device, comprising the chip described above. The electronic device may be a terminal device or a server, and the embodiment of the present disclosure does not limit the specific type of the electronic device.

[0161] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0162] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An analog-to-digital conversion circuit based on a clock signal bootstrap module, characterized in that: The circuit comprises a clock signal bootstrap module, a conversion module and a feedback module, wherein the power supply voltages of the clock signal bootstrap module, the conversion module and the feedback module are equal and less than or equal to a first threshold, The clock signal bootstrap module is used to generate at least one pair of clock signals with a swing greater than the first threshold, and output the clock signals to the conversion module to drive at least one unit in the conversion module; The conversion module is used to obtain a digital output signal according to the analog input signal and the feedback signal; The feedback module is used to generate the feedback signal according to the latest digital output signal and output the feedback signal to the conversion module.

2. The circuit according to claim 1, characterized in that The conversion module includes a first chopping unit, a capacitor filtering unit, a dead zone control unit, a voltage-current conversion unit, a second chopping unit, an integration unit, a quantization unit, and an output unit. The analog input signal includes a differential first input signal and a second input signal, and the feedback signal includes a differential first feedback signal and a second feedback signal. The first end of the first chopping unit receives the first input signal, the second end of the first chopping unit receives the second input signal, the third end of the first chopping unit is connected to the first end of the capacitor filtering unit, and the fourth end of the first chopping unit is connected to the second end of the capacitor filtering unit; The third end of the capacitor filtering unit is connected to the first end of the dead zone control unit and the fourth end of the feedback module, the fourth end of the capacitor filtering unit is connected to the second end of the dead zone control unit and the third end of the feedback module, the fourth end of the feedback module outputs the first feedback signal, and the third end of the feedback module outputs the second feedback signal; The third end of the dead zone control unit is connected to the first end of the voltage-current conversion unit, and the fourth end of the dead zone control unit is connected to the second end of the voltage-current conversion unit; The third end of the voltage-current conversion unit is connected to the first end of the second chopping unit, and the fourth end of the voltage-current conversion unit is connected to the second end of the second chopping unit; The third end of the second chopping unit is connected to the first end of the integration unit, and the fourth end of the second chopping unit is connected to the second end of the integration unit; The third end of the integration unit is connected to the first end of the quantization unit, the fourth end of the integration unit is connected to the second end of the quantization unit, the third end of the quantization unit is connected to the first end of the output unit and the first end of the feedback module, and the fourth end of the quantization unit is connected to the second end of the output unit and the second end of the feedback module; The third terminal of the output unit outputs the digital output signal.

3. The circuit according to claim 2, characterized in that The quantization unit is a time domain quantization unit, the integration unit is a time domain integration unit, and the quantization unit and the integration unit are implemented by digital circuits.

4. The circuit according to claim 2, characterized in that The clock signal is used to drive the first chopping unit, the dead zone control unit, and the second chopping unit.

5. The circuit according to claim 4, characterized in that The clock signal bootstrap module includes at least one cascaded clock signal bootstrap unit, each clock signal bootstrap unit outputs a pair of clock signals, the clock signal output by the preceding clock signal bootstrap unit is used as the clock signal input by the succeeding clock signal bootstrap unit, and the swing amplitude of the clock signal output by the succeeding clock signal bootstrap unit is higher than the swing amplitude of the clock signal output by the preceding clock signal bootstrap unit.

6. The circuit according to claim 5, characterized in that The swing of the clock signal used to drive the dead zone control unit is greater than or equal to a second threshold, the swing of the clock signal used to drive the first chopping unit and the second chopping unit is greater than or equal to a third threshold, and the second threshold is greater than the third threshold.

7. The circuit according to claim 5, characterized in that The feedback module includes a logic control unit, a third chopping unit, and a capacitive digital-to-analog conversion unit. The first end of the logic control unit serves as the first end of the feedback module, the second end of the logic control unit serves as the second end of the feedback module, the third end of the logic control unit is connected to the first end of the third chopping unit, and the fourth end of the logic control unit is connected to the second end of the third chopping unit; The third end of the third chopping unit is connected to the first end of the capacitive digital-to-analog conversion unit, and the fourth end of the third chopping unit is connected to the second end of the capacitive digital-to-analog conversion unit; The third terminal of the capacitive digital-to-analog conversion unit serves as the third terminal of the feedback module, and the fourth terminal of the capacitive digital-to-analog conversion unit serves as the fourth terminal of the feedback module.

8. The circuit according to claim 5, characterized in that The clock signal bootstrap unit includes a first bootstrap subunit and a second bootstrap subunit, the first bootstrap subunit includes a first transistor, a second transistor, a third transistor, and a first capacitor, and the second bootstrap subunit includes a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitor. The first electrode of the first transistor is connected to the first electrode of the second transistor and serves as the first input terminal of the first bootstrap subunit, the second electrode of the first transistor is connected to the first terminal of the first capacitor and serves as the second input terminal of the first bootstrap subunit, the third electrode of the first transistor is connected to the third electrode of the second transistor and the first electrode of the third transistor and serves as the output terminal of the first bootstrap subunit, the second electrode of the second transistor is connected to the second electrode of the third transistor and the second terminal of the first capacitor, and the third electrode of the third transistor is connected to a power supply voltage; a first electrode of the fourth transistor connected to the first electrode of the fifth transistor and serving as a first input terminal of the second bootstrap subunit, a second electrode of the fourth transistor connected to the first terminal of the second capacitor and serving as a second input terminal of the second bootstrap subunit, a third electrode of the fourth transistor connected to the third electrode of the fifth transistor and the first electrode of the sixth transistor and serving as an output terminal of the second bootstrap subunit, a second electrode of the fifth transistor connected to the second electrode of the sixth transistor and the second terminal of the second capacitor, and a third electrode of the sixth transistor connected to a power supply voltage; The first input terminal of the second bootstrap subunit is connected to the second input terminal of the first bootstrap subunit to receive the first clock signal, the second input terminal of the second bootstrap subunit is connected to the first input terminal of the first bootstrap subunit to receive the second clock signal, the output terminal of the first bootstrap subunit outputs the third clock signal, and the output terminal of the second bootstrap subunit outputs the fourth clock signal; The first clock signal and the second clock signal are a pair of differential signals and are clock signals input to the clock signal bootstrap unit, and the third clock signal and the fourth clock signal are a pair of differential signals and are clock signals output from the clock signal bootstrap unit.

9. A chip, characterized in that: The analog-to-digital conversion circuit comprises the analog-to-digital conversion circuit described in any one of claims 1-8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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