Offset mismatch calibration method for SAR ADC with dual-comparator structure and storage medium

Abstract

The invention discloses an offset mismatch calibration method for a dual-comparator structure SAR ADC and a storage medium. The offset mismatch calibration method comprises the steps that S1, the ADC starts calibration; s2, counting the last comparison result of n times; s3, respectively calculating mathematical expectations P1 (1) and P2 (1) of comparison results of the comparator 1 and the comparator 2; s4, calculating whether the interpolation is in a set range or not; if yes, the calibration is completed; if not, calculating an error function; and adjusting the offset of the comparator according to the set step length, and returning to the step S2. The storage medium is used for storing a computer program for executing the method. The method has the advantages of simple principle, simplicity and convenience in operation, wide application range, good calibration effect, high precision and the like.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of analog-to-digital converters (ADCs), and in particular to an offset mismatch calibration method and a storage medium for a SARADC with a dual comparator structure. Background Art

[0002] As a key interface module in mixed signal systems, analog-to-digital converters (ADCs) are used to quantize analog signals and convert them into digital signals for storage and calculation. In high-speed serial interfaces (Serializer / Deserializer, SerDes) based on digital signal processing, high-speed ADCs play a vital role in the structure.

[0003] The high-speed ADC in PAM4 SerDes usually adopts a time interleaved (TI) structure. Among the current mainstream ADC structures, the successive approximation register (SAR) ADC with a multi-digital structure, no op amp, low power consumption, and small area is becoming more and more popular, especially as the process develops towards deep sub-micron, the characteristics of SAR ADC are more prominent. Therefore, the sub-ADC in the TI ADC mainly uses the SAR structure. The TI-ADC based on the SAR structure has the advantages of small area and low power consumption.

[0004] As we all know, increasing the speed of the sub-channel ADC can effectively increase the speed of the overall time-interleaved ADC, while reducing the number of channels, which in turn helps reduce the mismatch effect. In addition, doing so is also conducive to reducing the complexity, power consumption and area of ​​the calibration circuit. Since PAM4 SerDes does not require high ADC resolution, usually only 7-8 bits are required, the setup time of the capacitor array will not restrict the speed of the SAR ADC, while the comparison time and reset time of the comparator will become the main factors limiting the speed of the SAR ADC.

[0005] The SAR ADC with dual comparator structure can effectively reduce the impact of reset time on speed. Figure 1 , the SAR ADC with dual comparator structure uses two comparators to work alternately. When one comparator is comparing, the other comparator is reset. This can avoid the reset time of the comparator affecting the rate of the ADC and improve the conversion rate of the SAR ADC. The sub-channel SAR ADC in TI-ADC usually adopts a dual comparator structure. In addition, TI-ADC has a special offset calibration circuit to calibrate the absolute offset of each sub-channel SAR ADC, so the absolute offset of the SAR ADC has little effect on the TI-ADC. However, the problem with the SAR ADC with dual comparator structure is that it will be affected by the offset mismatch between the two comparators, which will seriously reduce the performance of the ADC.

[0006] At present, the calibration methods for dual comparator structure SAR ADC mainly include the following: 1) Calibration method based on reference comparator: add an additional reference comparator to the circuit. During the conversion period, the reference comparator is triggered simultaneously with one of the other comparators for comparison. The comparison results of the other comparators are compared with the results of the reference comparator to obtain the calibration direction of the offset. Finally, the offset of each comparator is consistent with the offset of the reference comparator, eliminating the mismatch between the comparators.

[0007] 2) Low-power comparator calibration method based on charge sharing: After the SAR ADC completes normal conversion, add another comparison clock cycle, short-circuit the input of the comparator before starting the comparison, and then compare and measure the offset of the comparator. Adjust the calibration voltage according to the comparison result.

[0008] However, the above two methods still have the following defects: 1. The calibration method based on reference comparator requires an additional comparator, which has large hardware overhead and requires a more complex clock.

[0009] 2. The low-power comparator calibration method based on charge sharing requires an additional comparator clock phase to be reserved for calibration. This additional clock phase will cause the conversion time to be longer and slow down the working speed of the ADC.

[0010] There is an offset mismatch between the dual comparators in the SAR ADC, which will seriously deteriorate the performance of the ADC. Figure 2 shown. Summary of the invention

[0011] The technical problem to be solved by the present invention is: in view of the technical problems existing in the prior art, the present invention provides an offset mismatch calibration method and storage medium for a dual comparator structure SAR ADC with simple principle, simple operation, wide application range, good calibration effect and high precision.

[0012] In order to solve the above technical problems, the present invention adopts the following technical solutions: A method for offset mismatch calibration of a dual comparator structure SAR ADC, comprising: Step S1: ADC starts calibration; Step S2: Count the last comparison results n times; Step S3: Calculate the mathematical expectations P1(1) and P2(1) of the comparison results of comparator 1 and comparator 2 respectively; Step S4: Calculate whether the interpolation value is within the set range; if yes, the calibration is completed; if not, calculate the error function; adjust the comparator offset according to the set step size, and return to step S2. As a further improvement of the present invention: by using a random signal to control the start order of comparator 1 and comparator 2, the probability of comparator 1 and comparator 2 starting first in one conversion is the same, and then the mathematical expectation of the last comparison result of comparator 1 and the mathematical expectation of the comparison result of comparator 2 are counted at intervals to calculate the error function :

[0013] As a further improvement of the present invention: when comparator 1 starts to compare first and the input signal obeys a uniform distribution, the probability that the Nth comparison result is 1 is for:

[0014] In the above formula, when N is an even number, is "0"; when N is an odd number, is "1".

[0015] As a further improvement of the present invention: when comparator 2 starts to compare first, the probability that the Nth comparison result is 1 for:

[0016] In the above formula, when N is an even number, is "0"; when N is an odd number, is "1".

[0017] As a further improvement of the present invention: using LMS iterative algorithm to make the offset mismatch between the two comparators approach 0:

[0018] In the above formula, Vos1(n) is the offset of comparator 1 at the nth statistical time, μ is the iteration step size, is the error function for the nth statistical calculation.

[0019] As a further improvement of the present invention: the calibration is realized by using the mathematical expectation of the last comparison result.

[0020] The present invention further provides a storage medium, which can be read by a computer or a processor, and stores a computer program for executing any one of the above methods.

[0021] Compared with the prior art, the advantages of the present invention are: 1. The offset mismatch calibration method and storage medium for dual comparator structure SAR ADC of the present invention have simple principle, simple operation, wide application range, good calibration effect and high precision. The present invention is a background calibration algorithm for offset mismatch of successive approximation (SAR) analog-to-digital converter (ADC) of dual comparator structure. The present invention mainly aims at the offset mismatch problem between comparators. By counting the last comparison result under normal working condition of SAR ADC, the least mean square algorithm (LMS) is used to minimize the offset mismatch error between comparators, thereby improving the performance of SAR ADC. The design does not occupy additional clock phases and does not require additional reference comparators.

[0022] 2. The offset mismatch calibration method and storage medium for dual comparator structure SAR ADC of the present invention is a background calibration algorithm for comparator offset mismatch, which neither occupies additional comparison clock phases, slows down the speed of SAR ADC, nor requires a reference comparator, and has low hardware overhead. When the SAR ADC is working normally, the last comparison result of the comparator is detected, and the adjustment direction of the comparator offset can be obtained according to the statistical distribution of the comparison result.

[0023] 3. The offset mismatch calibration method and storage medium for the dual comparator structure SAR ADC of the present invention can avoid performance degradation caused by the offset mismatch between the two comparators. The method of the present invention detects the last comparison result when the SAR ADC is working normally, and obtains the comparator offset adjustment direction based on the statistical distribution of the comparison result. The use of the LMS algorithm can minimize the offset mismatch. The algorithm does not introduce additional calibration cycles in the circuit, so it does not affect the speed of the SAR ADC, and is very suitable for high-speed application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the dual comparator SAR ADC structure.

[0025] Figure 2 This is a diagram showing the effect of offset mismatch on the number of effective bits.

[0026] Figure 3 It is a schematic diagram of a SAR ADC with a 4-bit dual comparator structure in a specific application example of the present invention.

[0027] FIG4 is a schematic diagram of the change of the DAC bottom plate voltage after the first comparison of the comparator 1 in a specific embodiment of the present invention; wherein (a) is the comparison result of 0, and the DAC bottom plate voltage is flipped; and (b) is the result of 1, and the DAC bottom plate voltage is flipped.

[0028] FIG5 is a schematic diagram of the change of the DAC bottom plate voltage after the first comparison of the comparator 2 in a specific embodiment of the present invention; wherein (a) is the comparison result of 0, and the DAC bottom plate voltage is flipped; and (b) is the result of 1, and the DAC bottom plate voltage is flipped.

[0029] FIG6 is a schematic diagram of the change in the DAC bottom plate voltage when the differential voltage of the DAC top plate is different values ​​after the first comparison in a specific embodiment of the present invention; wherein (a) is the comparison result of 0, and the DAC bottom plate voltage is flipped; and (b) is the result of 1, and the DAC bottom plate voltage is flipped.

[0030] Figure 7 It is a schematic diagram of the flow chart of the present invention in a specific embodiment.

[0031] Figure 8 It is a schematic diagram of the convergence of the offset voltage when a sinusoidal signal is input in a specific embodiment of the present invention.

[0032] Fig. 9 It is a schematic diagram of the convergence of the effective number of bits when a sinusoidal signal is input in a specific embodiment of the present invention.

[0033] Fig.10 It is a schematic diagram of the convergence speed and accuracy of different inputs in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] The present invention provides an offset mismatch calibration method for a dual-comparator structure SAR ADC, the core principle and idea of ​​which are: using the last comparison result of the comparator to obtain offset information, and then using the LMS algorithm to make the offset mismatch of the two comparators tend to zero.

[0036] like Figure 7 As shown, the present invention is used for the offset mismatch calibration method of the dual comparator structure SAR ADC, which includes: Step S1: ADC starts calibration; Step S2: Count the last comparison results n times; Step S3: Calculate the mathematical expectations P1(1) and P2(1) of the comparison results of comparator 1 and comparator 2 respectively; Step S4: Calculate whether the interpolation value is within the set range; if yes, the calibration is completed; if not, calculate the error function; adjust the comparator offset according to the set step size, and return to step S2.

[0037] In this example, a 4-bit dual comparator SAR ADC is used as an example. Figure 3As shown, the quantization range is from -Vref to Vref; two comparators (Comparator 1 and Comparator 2) work alternately. Assume the offset of Comparator 1 is Vos1, the offset of Comparator 2 is Vos2, and LSB = 2 * Vref / 2^4. The input differential voltage Vinp - Vinn = u, that is, the differential voltage of the top plate of the capacitor array (DAC) after sampling ends is u.

[0038] When Comparator 1 starts the comparison first, due to the offset voltage of Comparator 1 being Vos1, when u < Vos1, the comparison result is 0, and the voltage of the bottom plate of the DAC flips as shown in Figure 4(a); otherwise the result is 1, and the voltage of the bottom plate of the DAC flips as shown in Figure 4(b).

[0039] The differential voltages of the top plate of the DAC in these two cases are respectively:

[0040] If the differential voltage of the top plate of the DAC after the first comparison is u , for the second comparison by Comparator 2 with the offset voltage of Comparator 1 being Vos2, when u , the result of the second comparison is 0, and the voltage of the bottom plate of the DAC flips as shown in Figure 5(a); otherwise the result is 1, and the voltage of the bottom plate of the DAC flips as shown in Figure 5(b).

[0041] Similarly, if the differential voltage of the top plate of the DAC after the first comparison is u , there will also be two cases where the result is 0 and the result is 1, and the voltage flips of the bottom plate of the DAC are shown in Figure 6(a) and Figure 6(b) respectively.

[0042] In the above four cases, the differential voltages of the top plate of the DAC are respectively:

[0043] After the second comparison, there are four differential voltages of the top plate of the DAC; For the third comparison by Comparator 1, there will be two cases where the comparison result is 0 and 1 for each input signal, and finally there will be 8 different voltage flips of the bottom plate of the DAC. Similarly, the differential voltages of the top plate of the DAC in these eight cases are respectively:

[0044] From the above formula, it can be seen that after the third comparison, there are eight differential voltages of the top plate of the DAC; For the fourth comparison by Comparator 2, if the input signal is uniformly distributed between -Vref and Vref, the probability that the result of the fourth comparison is 1 is;

[0045] By analogy, for an N-bit (N ≥ 2) SAR ADC, when comparator 1 starts comparing first and the input signal follows a uniform distribution, the probability that the Nth comparison result is 1 is for:

[0046] In the above formula, when N is an even number, is "0"; when N is an odd number, is "1".

[0047] Similarly, when comparator 2 starts comparing first, the probability that the Nth comparison result is 1 is for:

[0048] It can be seen that when N is the same and Vos1 and Vos2 are different, the probability that the last comparison result is 1 when comparator 1 starts comparing first is different from the probability when comparator 1 starts comparing first. Therefore, the calibration direction of the misalignment can be obtained based on the mathematical expectation of its statistical distribution.

[0049] As can be seen from the above, the specific implementation method of the present invention is: by using a random signal to control the start order of comparator 1 and comparator 2, the probability of comparator 1 and comparator 2 starting first in one conversion is the same, and then the mathematical expectation of the last comparison result of comparator 1 and the mathematical expectation of the comparison result of comparator 2 are counted at intervals, and the error function is calculated. :

[0050] The following LMS iterative algorithm can be used to make the offset mismatch between the two comparators approach 0:

[0051] In the above formula, Vos1(n) is the offset of comparator 1 at the nth statistical time, μ is the iteration step size, is the error function at the time of the nth statistics. Here, the offset of the two comparators is calibrated simultaneously to speed up the convergence. There are many ways to achieve this goal in the actual circuit, such as changing the load capacitance or using a switched capacitor circuit to adjust the offset voltage.

[0052] It is worth noting that although the input signal is a uniformly distributed random signal when deriving the probability formula, even if the input is a sinusoidal signal, there will be a similar distribution, and the mathematical expectation of the last comparison result can also be used to achieve calibration. This algorithm does not increase the dedicated calibration cycle, does not reduce the speed of the ADC, does not require an additional reference comparator, and has a small hardware overhead. The result of the last comparator comparison can be statistically analyzed to obtain the calibration direction of the comparator offset.

[0053] In a specific application example of the present invention, an 8-bit SAR ADC behavioral model is constructed to verify the calibration process, Vref=1V is set, and the behavior of the calibration algorithm under different conditions is simulated.

[0054] Convergence speed: Set Vos1 = -5 mV, Vos2 = 3 mV, and input a fully differential sinusoidal signal with a peak-to-peak value of 0.8V; Sample 256 sets of data, and calculate the mathematical expectations of the last comparison results of comparator 1 and comparator 2 respectively; then find the difference, and make adjustments based on the calculated results; next, resample 256 sets of data, calculate the difference of the new mathematical expectations, and make adjustments based on the calculated results again; and repeat this process.

[0055] As a preferred embodiment, the calibration step size can be set to 0.2mV, because if the amount of data sampled each time is too large, the convergence speed is slow, and if it is too small, the randomness is too strong, affecting the calibration accuracy. In addition, the size of the calibration step size will also affect the calibration accuracy and speed.

[0056] During the calibration process, the offset of the two comparators changes as follows: Figure 8 As shown in the figure, it can be seen that after 20 iterations and 5000 samples, convergence is achieved. The change of SAR ADC effective number of bits (ENOB) is as follows: Fig. 9 As shown in the figure, after calibration, ENOB increases from 7.01bit to 7.93bit.

[0057] Impact of input signal: The calibration accuracy of the background calibration algorithm usually depends on the amplitude distribution of the input signal. The larger the amplitude of the input signal, the higher the calibration accuracy. If the input signal changes in amplitude very little, the calibration accuracy will be affected.

[0058] like Fig.10 As shown, it shows the impact of different input signals on the calibration accuracy, including DC signal, uniformly distributed random signal, and sinusoidal signal with frequencies 0.1 times, 0.5 times, and 0.9 times the sampling frequency respectively.

[0059] It can be seen that the calibration effect is poor only when the input signal is a DC signal. However, when sinusoidal signals of different frequencies and uniformly distributed random signals are input, the convergence speed of the calibration and the final calibration effect are better.

[0060] The present invention further provides a storage medium, which can be read by a computer or a processor and stores a computer program for executing the above method.

[0061] Those skilled in the art should understand that the above-mentioned embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0062] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. An offset mismatch calibration method for a dual comparator structure SAR ADC, characterized in that: include: Step S1: ADC starts calibration; Step S2: Count the last comparison results n times; Step S3: Calculate the mathematical expectations P1(1) and P2(1) of the comparison results of comparator 1 and comparator 2 respectively; Step S4: Calculate whether the interpolation value is within the set range; if yes, the calibration is completed; if not, calculate the error function; adjust the comparator offset according to the set step size, and return to step S2.

2. The offset mismatch calibration method for a dual comparator structure SAR ADC according to claim 1, characterized in that: By using a random signal to control the start order of comparator 1 and comparator 2, the probability of comparator 1 and comparator 2 starting first in a conversion is the same, and then the mathematical expectation of the last comparison result of comparator 1 and the mathematical expectation of the comparison result of comparator 2 are counted at intervals to calculate the error function : 。 3. The offset mismatch calibration method for a dual comparator structure SAR ADC according to claim 2, characterized in that: When comparator 1 starts comparing first and the input signal follows a uniform distribution, the probability that the Nth comparison result is 1 is for: In the above formula, when N is an even number, is "0"; when N is an odd number, is "1".

4. The offset mismatch calibration method for a dual comparator structure SAR ADC according to claim 2, characterized in that: When comparator 2 starts comparing first, the probability that the Nth comparison result is 1 for: In the above formula, when N is an even number, is "0"; when N is an odd number, is "1".

5. The offset mismatch calibration method for a dual comparator structure SAR ADC according to claim 2, characterized in that: The LMS iterative algorithm is used to make the offset mismatch between the two comparators approach 0: In the above formula, Vos1(n) is the offset of comparator 1 at the nth statistical time, μ is the iteration step size, is the error function at the nth statistical time.

6. The offset mismatch calibration method for a dual comparator structure SAR ADC according to any one of claims 2 to 5, characterized in that: Calibration is achieved using the mathematical expectation of the last comparison result.

7. A storage medium, which can be read by a computer or a processor, characterized in that: The storage medium stores a computer program for executing any one of the methods in claims 1 to 6.

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