Calibration method for sampling time offset mismatch of TI-ADC for SerDes and storage medium

Abstract

The invention discloses a calibration method for sampling time offset mismatch of TI-ADC for SerDes and a storage medium. The calibration method comprises the following steps: performing operation on a current output value obtained by quantization of each sub-ADC and a previous beat of data recovered by judgment of SerDes; taking a certain sub-ADC channel as a reference to obtain an error function of offset of sampling time of other sub-ADCs relative to the reference time; and the sampling time of the sub-ADCs is adjusted by adopting an LMS algorithm to minimize an error function, so that the calibration of the sampling time offset mismatch is completed. The storage medium is used for storing a computer program for executing the method. The method has the advantages of simple principle, simplicity and convenience in operation, wide application range, good calibration effect, high precision and the like.

Description

Technical Field

[0001] The invention mainly relates to the field of SerDes receiver design, and in particular to a calibration method and a storage medium for TI-ADC sampling time offset mismatch of SerDes. Background Art

[0002] Time-interleaved analog-to-digital converters (TI-ADCs) are widely used in ultra-high-speed SerDes. TI-ADCs use multiple sub-ADCs to work alternately to increase the sampling rate, among which the sub-ADC sampling time offset mismatch is the key factor limiting the performance of TI-ADCs.

[0003] like Figure 1 The figure shows the schematic diagram of a high-speed SerDes receiver based on an ADC structure. The PAM4 or NRZ signal is quantized by the ADC after passing through the channel and the front-end analog circuit in the SerDes, completing the conversion from analog signal to digital signal. The performance of the ADC is one of the main factors affecting the bit error rate of the SerDes.

[0004] High-speed ADCs used in SerDes usually use a time-interleaved structure, such as Figure 2 As shown in (a), the unmatched input buffers, unequal input signal routing, unmatched sampling switches, and non-ideal clock generator circuits in the TI-ADC will cause mismatches in the sub-ADC sampling time offsets. Figure 2 (b) shows the impact of sampling time deviation mismatch on output value error. Ideally, the sampling interval between adjacent sampling channels should be one sampling period Ts of the TI-ADC. Due to the sampling time mismatch, the adjacent sampling interval is not Ts. The time deviation will be converted into amplitude deviation, which will seriously deteriorate the performance of the TI-ADC.

[0005] Some practitioners have proposed a technical solution: cross-correlation calibration algorithm (Time skew extraction of interleaved analog-to-digital converters. US 8830094 B1.). Figure 3 (a) shows the case where ADC2 in the two-channel TI-ADC has a time offset error. If the time offset is positive, then y2(n-1) is more biased towards y1(n), and the mutual correlation coefficient between the two is greater than the mutual correlation coefficient when y2(n-1) is more biased towards y1(n-1). Therefore, the difference between the two mutual correlation coefficients can be used as an error function. When the error function tends to 0, it means that the sampling time offset of ADC2 has been calibrated to the ideal value. The specific implementation method is as follows: Figure 3 (b) as shown.

[0006] It can be seen that the existing multi-channel TI-ADC using the cross-correlation calibration algorithm needs to be calibrated in steps, that is: first use the reference channel to calibrate the middle channel, and then use the calibrated channel and the reference channel to calibrate the remaining channels. However, when the number of channels increases, the convergence speed will be greatly reduced, and the convergence accuracy will also be reduced. The calibration accuracy mainly depends on the calibration accuracy of the first step. In the first step of calibration, the reference channel is used to calibrate the middle channel. Since the sampling time interval between the middle channel and the reference channel is the largest and the correlation is small, the calibration effect is deteriorated. Summary of the invention

[0007] The technical problem to be solved by the present invention is: in view of the technical problems existing in the prior art, the present invention provides a calibration method and storage medium for TI-ADC sampling time offset mismatch of SerDes, which has simple principle, simple operation, wide application range, good calibration effect and high precision.

[0008] In order to solve the above technical problems, the present invention adopts the following technical solutions: A calibration method for TI-ADC sampling time offset mismatch for SerDes, comprising: The current output value obtained by quantization of each sub-ADC is respectively calculated with the previous beat data recovered by SerDes judgment; Taking a certain sub-ADC channel as a reference, an error function of the sampling time offset of the remaining sub-ADCs relative to the reference time is obtained; The LMS algorithm is used to adjust the sampling time of the sub-ADC to minimize the error function, thereby completing the calibration of the sampling time offset mismatch.

[0009] As a further improvement of the present invention: the sampling clock of the first channel sub-ADC is kMT S , where k represents the kth sampling, T S Indicates the sampling period of TI-ADC; the sampling clock of the second channel sub-ADC is kMT S +T S , and so on, the sampling clock of the mth channel is kMT S +(m-1)T S ; Considering the sampling time offset error, the output signal of the first channel of TI-ADC is expressed as follows:

[0010] in, Indicates the kth sampling value of the first channel of TI-ADC, Represents the input code element, Indicates the sampling clock deviation of the first channel.

[0011] As a further improvement of the present invention: when only the data of the current beat and the previous beat are considered, the current beat is the kth sampling value, and the previous beat is the k-1th sampling value, then:

[0012]

[0013] In the above formula, the last term on the right side of the formula represents the inter-symbol interference ISI caused by the remaining data at the current sampling moment.

[0014] As a further improvement of the present invention: Find the mean, and we get:

[0015] As the mth channel, It is expressed as:

[0016] As a constant, we get:

[0017]

[0018] in, express hour The slope of Send the above formula as the error function to the LMS module, so that tends to 0, achieving calibration of sampling clock offset.

[0019] As a further improvement of the present invention: the TI-ADC includes an input data prediction module, an LMS module and a delay adjustment module.

[0020] As a further improvement of the present invention: the input codewords are provided by an input data prediction module.

[0021] As a further improvement of the present invention: the reference value of the calibration is the output value of the first channel The previous shot data with the prediction The product of Depend on Similarly, the product value of the output of each calibration channel and the previous beat prediction data is obtained, and then the sampling clock offset error value of each channel is obtained by subtracting the product value to be calibrated from the reference product value.

[0022] As a further improvement of the present invention: the error value is sent to the LMS module, and the output of the LMS will generate a corresponding control code to adjust the delay of each channel so that the sampling clock offset of each channel is aligned with the clock offset of the reference channel.

[0023] The present invention further provides a storage medium, which can be read by a computer or a processor, and stores a computer program for executing any one of the above methods.

[0024] Compared with the prior art, the advantages of the present invention are: 1. The calibration method and storage medium for TI-ADC sampling time offset mismatch of SerDes of the present invention have simple principle, easy operation, wide application range, good calibration effect and high precision. The calibration method of the present invention performs correlation operation on the current output value obtained by quantization of each sub-ADC and the previous beat data recovered by SerDes judgment, and the correlation value includes the offset information of each sub-ADC sampling time. Taking a certain sub-ADC channel as a reference, the error function of the sampling time offset of the remaining sub-ADCs relative to the reference time can be obtained, and finally the LMS algorithm is used to adjust the sampling time of the sub-ADC to minimize the error function, thereby completing the calibration of the sampling time offset mismatch.

[0025] 2. The calibration method and storage medium for the TI-ADC sampling time offset mismatch of SerDes of the present invention utilizes the correlation coefficient between the output data of the calibration channel and the input code element of the previous beat. Since the two data are separated by only one sampling cycle, the correlation is very high, so that a better calibration effect can be achieved. On the other hand, the calibration algorithm is independent of the number of channels, and it is not necessary to calibrate a certain channel first and then calibrate the remaining channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is the schematic diagram of the SerDes receiver based on ADC structure.

[0027] Figure 2 (a) is a schematic diagram of the M-channel TI-ADC structure; Figure 2 (b) is a schematic diagram showing that the TI-ADC sampling time offset mismatch causes errors in the sampling output.

[0028] Figure 3 (a) The two-channel TI-ADC uses the cross-correlation algorithm to obtain the time offset information; Figure 3 (b) Sampling time diagram of two-channel TI-ADC.

[0029] Figure 4 It is a schematic diagram of an M-channel TI-ADC and its input front-end circuit in a specific implementation of the present invention.

[0030] Figure 5 It is a schematic diagram of the influence of the previous code element on the current sampled data in a specific implementation of the present invention.

[0031] Figure 6 It is a schematic diagram of the implementation principle of the method of the present invention in a specific application example.

[0032] Figure 7 It is a schematic diagram of using a 4-channel TI-ADC in a specific application example of the present invention.

[0033] Figure 8 It is a schematic diagram of a sampling clock offset calibration circuit implemented in a specific application example of the present invention. DETAILED DESCRIPTION

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] like Figure 6 As shown, the present invention provides a calibration method for TI-ADC sampling time offset mismatch of SerDes, which is a calibration method for sampling time offset mismatch based on SerDes decision output, and includes: Perform correlation operations on the current output value obtained by quantization of each sub-ADC and the previous beat data recovered by SerDes judgment; Taking a certain sub-ADC channel as a reference, an error function of the sampling time offset of the remaining sub-ADCs relative to the reference time is obtained; The LMS algorithm is used to adjust the sampling time of the sub-ADC to minimize the error function, thereby completing the calibration of the sampling time offset mismatch.

[0036] like Figure 5 As shown, by adopting the above scheme, the present invention utilizes the correlation coefficient between the output data of the calibration channel and the input code element of the previous beat. Since the two data are separated by only one sampling period, the correlation is very high, so that a better calibration effect can be achieved. On the other hand, the calibration algorithm is independent of the number of channels, and it is not necessary to calibrate a certain channel first and then calibrate the remaining channels.

[0037] like Figure 4 The figure shows the input front-end circuit of an M-channel TI-ADC. The ideal PAM4 or NRZ signal is sent to the M-channel TI-ADC after passing through the cascade system composed of the channel and CTLE. The sampling clock of the first channel sub-ADC is kMT S (where k represents the kth sampling, T S Indicates the sampling period of TI-ADC), the sampling clock of the second channel sub-ADC is kMT S +T S, and so on, the sampling clock of the mth channel is kMT S +(m-1)T S If the sampling time offset error is taken into account, the output signal of the first channel of TI-ADC can be expressed as follows: (1) in, Indicates the kth sampling value of the first channel of TI-ADC, Represents the input code element, represents the sampling clock deviation of the first channel. If only the data of the current beat (kth sampling value) and the previous beat (k-1th sampling value) are considered, the above formula can be further rewritten as:

[0038] (2) In the above formula, the last term on the right side represents the inter-symbol interference (ISI) caused by the remaining data at the current sampling time. and The cross-correlation of can be obtained:

[0039] (3) Since the input PAM4 or NRZ signal will be encoded into a PRBS signal using the corresponding encoding method, this also means that the code elements are independent of each other, resulting in the following formula: (4) (5) The above formula shows that if two different code elements are independent of each other, their correlation is 0. With the above conclusion, we can Finding the mean, we get: (6) From the above formula, we can see that Just depends on .and It represents the impact of the previous code element on the current sampled data. The size of the code element depends on the input code element pulse width, channel attenuation, CTLE equalization size and the current sampling clock offset. Therefore Contains the sampling clock offset information. For each subchannel of the TI-ADC, the input code element pulse width, channel attenuation, and CTLE equalization size are the same. The only difference is the current sampling clock offset. Use this as a reference to calibrate the sampling clock offset of other channels.

[0040] Taking the mth channel as an example, according to formula (6), It can be expressed as: (7) because is a constant, and by subtracting (6) from (7) we get:

[0041] (8) in, express hour The above formula is sent to the LMS module as the error function, and finally tends to 0, which means , thus the sampling clock offset can be calibrated.

[0042] It can be seen from the above that the method of the present invention adds an input data prediction module, an LMS module and a delay adjustment module on the basis of the original TI-ADC.

[0043] The input codewords in formula (8) are provided by the input data prediction module.

[0044] In this figure, the reference value of the calibration is the output value of the first channel. The previous shot data with the prediction The product of . Depend on Similarly, the product value of the output of each calibration channel and the previous beat prediction data can be obtained, and then the sampling clock offset error value of each channel is obtained by subtracting the product value to be calibrated from the reference product value.

[0045] Finally, the error value is sent to the LMS module, and the output of the LMS will generate a corresponding control code to adjust the delay of each channel so that the sampling clock offset of each channel is aligned with the clock offset of the reference channel.

[0046] In the design of the SerDes receiver circuit, the input front-end circuits of TI-ADC are CTLE and VGA. The CTLE circuit will perform equalization processing on the input signal, and the VGA will amplify the swing of the input signal to the input effective range of TI_ADC. The subsequent circuits of TI-ADC are FFE and DFE. DFE not only performs data equalization, but also plays the function of recovering the input codewords. In other words, DFE can be used as an input data prediction module. FFE performs equalization processing on the output of TI-ADC. The equalization of data by FFE can improve the accuracy of DFE's prediction of input data. Because the method of the present invention uses the output of DFE, the method of the present invention is called a clock offset calibration algorithm based on decision output. The above analysis shows that the clock offset calibration algorithm based on decision output can well reuse the existing circuit modules in the SerDes circuit and realize sampling clock offset calibration without adding additional circuit overhead.

[0047] The present invention is used in specific applications, such as Figure 7 As shown, a SerDes receiver based on a 4-channel TI-ADC is taken as an example to specifically illustrate the working process of TI-ADC.

[0048] The output of the 4-channel TI-ADC is first calibrated for offset and gain errors and then sent to the FFE and DFE modules to recover the input codewords after equalization judgment.

[0049] Then, the recovered input codewords and the output of TI-ADC are sent to the clock data recovery module and the sampling clock calibration module respectively. The clock data recovery module can recover the sampling clock from the input data and ensure that the sampling point of the sampling clock is near the middle of the input codeword eye diagram. However, since the sampling clock of each subchannel of TI-ADC has a clock offset, the sampling clock of each channel is offset from the ideal sampling point, which will reduce the bit error rate of the SerDes receiver. The sampling clock calibration module is used to solve this problem.

[0050] The clock Fs recovered by the clock data recovery module is sent to the sampling clock calibration circuit. The specific implementation method of the sampling clock offset calibration circuit is as follows: Figure 8As shown. After passing through the sampling clock generation circuit, Fs outputs a 4-phase sampling clock, which is then sent to four groups of digital clock converters (DTCs). DTC can adjust the delay of the input clock according to the input control code value, and it can be regarded as a digitally controlled delay device. The core of the clock offset calibration algorithm is to obtain the control code value of DTC through an adaptive algorithm so that it can output a sampling clock that meets the delay requirements. Its core principle is to calculate the correlation between the output of each sub-channel of TI-ADC and the predicted previous beat input code element; and use the correlation of the first channel as a reference value to make the correlation values ​​of other channels converge to the reference value. Because the output value of TI-ADC will generate data delay after passing through FFE and DFE, in order to offset the data delay, the output of TI-ADC will be delayed by a corresponding period after entering the clock offset calibration module to align it with the output of DFE.

[0051] According to formula (8), the error function of clock offset can be obtained, and the control code value of DTC can be obtained by using the following LMS iterative algorithm:

[0052] (9) In the above formula is the control code value of the DTC of the mth channel, is the iteration step length, is the error function of the mth channel.

[0053] The present invention further provides a storage medium, which can be read by a computer or a processor and stores a computer program for executing the above method.

[0054] Those skilled in the art should understand that the above-mentioned embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0055] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A calibration method for TI-ADC sampling time offset mismatch for SerDes, characterized in that: include: The current output value obtained by quantization of each sub-ADC is respectively calculated with the previous beat data recovered by SerDes judgment; Taking a certain sub-ADC channel as a reference, an error function of the sampling time offset of the remaining sub-ADCs relative to the reference time is obtained; The LMS algorithm is used to adjust the sampling time of the sub-ADC to minimize the error function, thereby completing the calibration of the sampling time offset mismatch.

2. The calibration method for TI-ADC sampling time offset mismatch for SerDes according to claim 1, characterized in that: The sampling clock of the first channel sub-ADC is kMT S , where k represents the kth sampling, T S Indicates the sampling period of TI-ADC; the sampling clock of the second channel sub-ADC is kMT S +T S , and so on, the sampling clock of the mth channel is kMT S +(m-1)T S ; Considering the sampling time offset error, the output signal of the first channel of TI-ADC is expressed as follows: in, Indicates the kth sampling value of the first channel of TI-ADC, Represents the input code element, Indicates the sampling clock deviation of the first channel.

3. The calibration method for TI-ADC sampling time offset mismatch for SerDes according to claim 2, characterized in that: When only the data of the current beat and the previous beat are considered, the current beat is the kth sampling value, and the previous beat is the k-1th sampling value, then: In the above formula, the last term on the right side of the formula represents the inter-symbol interference ISI caused by the remaining data at the current sampling moment.

4. The calibration method for TI-ADC sampling time offset mismatch for SerDes according to claim 2, characterized in that: right Find the mean, and we get: As the mth channel, It is expressed as: As a constant, we get: in, express hour The slope of Send the above formula as the error function to the LMS module, so that tends to 0, achieving calibration of sampling clock offset.

5. The method for calibrating TI-ADC sampling time offset mismatch for SerDes according to any one of claims 2 to 4, characterized in that: The TI-ADC includes an input data prediction module, an LMS module and a delay adjustment module.

6. The method for calibrating TI-ADC sampling time offset mismatch for SerDes according to claim 5, characterized in that: The input codewords are provided by the input data prediction module.

7. The calibration method for TI-ADC sampling time offset mismatch for SerDes according to claim 5, characterized in that: The reference value for calibration is the output value of the first channel. The previous shot data with the prediction The product of Depend on Similarly, the product value of the output of each calibration channel and the previous beat prediction data is obtained, and then the sampling clock offset error value of each channel is obtained by subtracting the product value to be calibrated from the reference product value.

8. The method for calibrating TI-ADC sampling time offset mismatch for SerDes according to claim 5, characterized in that: The error value is sent to the LMS module, and the output of the LMS will generate a corresponding control code to adjust the delay of each channel so that the sampling clock offset of each channel is aligned with the clock offset of the reference channel.

9. A storage medium, which can be read by a computer or a processor, characterized in that: The storage medium stores a computer program for executing any one of the methods in claims 1 to 8.

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