Phase adjustment sampling circuit, sampling control method and electronic equipment

Abstract

The invention discloses a phase adjustment sampling circuit, a sampling control method and electronic equipment. According to the sampling circuit, a first differential branch is connected between a first port and a first input end of a sub analog-to-digital converter; the second differential branch is connected between the second port and the second input end of the sub analog-to-digital converter; the first correction circuit is connected between the second port and the first difference branch circuit; the second correction circuit is connected between the first port and the second difference branch circuit; the third correction circuit is coupled to the output end of the sub-analog-to-digital converter, the first output end is coupled to the first correction circuit, the second output end is coupled to the second correction circuit, and the third correction circuit is configured to adjust the capacitance parameter of at least one of the first correction circuit and the second correction circuit based on the output result of the sub-analog-to-digital converter. Therefore, even harmonics in the sampling result of the sampling circuit are corrected. The analog-to-digital conversion chip has the technical effects that the mismatch of the differential input signal is reduced, and the even harmonic energy of the analog-to-digital conversion chip is reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of circuit technology, and in particular to a phase-adjustable sampling circuit, a sampling control method, and an electronic device. Background Art

[0002] The development of wireless communication technology has continuously increased the signal frequency requirements of high-speed and high-precision analog-to-digital converters. In high-sampling-rate analog-to-digital converters, time-domain interleaved sampling is usually used to increase the sampling rate. The spectrum finally output by the analog-to-digital converter contains the higher-order harmonics of each sub-channel analog-to-digital converter itself, as well as the multi-channel spurious generated by the mismatch of amplitude and phase between multiple channels. In addition, due to non-ideal factors such as asymmetric routing and device mismatch, the even-order linearity of the differential signal becomes worse with frequency. Therefore, the harmonic problem of the differential signal input to the analog-to-digital converter deserves attention. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a phase-adjusted sampling circuit, a sampling control method, and an electronic device, in order to reduce the harmonic effects in the differential signal of the input analog-to-digital converter. In the first aspect, a sampling circuit is provided, including: a first differential branch, a second differential branch, a first correction circuit, a second correction circuit, a sub-analog-to-digital converter, and a third correction circuit; the first differential branch is connected between the first port and the first input end of the sub-analog-to-digital converter; the second differential branch is connected between the second port and the second input end of the sub-analog-to-digital converter; the first correction circuit is connected between the second port and the first differential branch; the second correction circuit is connected between the first port and the second differential branch; the third correction circuit is coupled to the output end of the sub-analog-to-digital converter, and its first output end is coupled to the first correction circuit, and the second output end is coupled to the second correction circuit, and is configured to adjust the capacitance parameters of at least one of the first correction circuit and the second correction circuit based on the output result of the sub-analog-to-digital converter to correct the even harmonics in the sampling result of the sampling circuit.

[0004] The above phase-adjusted sampling circuit can adjust the sampling capacitors of the two input ends of the differential signal respectively through the correction capacitors provided by the first correction circuit and the second correction circuit to reduce the mismatch of the differential input signal, thereby reducing the even harmonic energy of the entire analog-to-digital conversion chip.

[0005] Optionally, the first differential branch includes: a first sampling switch and a first sampling capacitor, the first sampling switch is connected between the first port and the first end of the first sampling capacitor; the second differential branch includes: a second sampling switch and a second sampling capacitor, the second sampling switch is connected between the second port and the first end of the second sampling capacitor.

[0006] Optionally, the first correction circuit includes multiple first correction branches, which are connected in parallel, wherein the first correction branch includes a first switch and a first correction capacitor; the second correction circuit includes multiple second correction branches, which are connected in parallel, wherein the second correction branch includes a second switch and a second correction capacitor.

[0007] Optionally, the second end of the first sampling capacitor is grounded, and the second end of the second sampling capacitor is grounded; one end of the first switch is coupled to the second port, and the other end is coupled to the first end of the first correction capacitor, and the second end of the first correction capacitor is grounded; one end of the second switch is coupled to the first port, and the other end is coupled to the first end of the second correction capacitor, and the second end of the second correction capacitor is grounded.

[0008] Optionally, the second end of the first sampling capacitor is coupled to the first input end, and the second end of the second sampling capacitor is coupled to the second input end; the first correction branch includes a first switch and a first correction capacitor connected in series between the second port and the first input end; the second correction branch includes a second switch and a second correction capacitor connected in series between the first port and the second input end.

[0009] Optionally, it also includes: a common-mode voltage source, a first access switch and a second access switch connected in series between the first input terminal and the second input terminal; the common-mode voltage source is configured to provide a common-mode voltage to the first input terminal or the second input terminal based on control of the first access switch or the second access switch.

[0010] Optionally, the capacitance values ​​of the first correction capacitors in the plurality of first correction branches are the same or different; the capacitance values ​​of the second correction capacitors in the plurality of second correction branches are the same or different.

[0011] In a second aspect, a sampling control method is provided for controlling the sampling circuit of the first aspect, including: configuring a first correction capacitor parameter of the first correction circuit and a second correction capacitor parameter of the second correction circuit to be a first preset correction capacitor value; adjusting the first preset correction capacitor value to be a second preset correction capacitor value, wherein the first preset correction capacitor value is less than the second preset correction capacitor value; obtaining a first output result of the sub-analog-to-digital converter; when the first output result satisfies the first preset parameter, adjusting one or more of the first correction capacitor value and the second correction capacitor value respectively; obtaining a second output result of the sub-analog-to-digital converter; when the second output result satisfies the second preset parameter, causing the sub-analog-to-digital converter to output the second output result.

[0012] Optionally, the first preset parameter includes an even harmonic parameter; and the second preset parameter includes one or more of a phase error parameter and an amplitude error parameter.

[0013] According to a third aspect, an electronic device is provided, comprising the sampling circuit according to the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following is a brief introduction to the drawings used in describing the embodiments of the present disclosure: Figure 1 A schematic diagram of a conventional test scenario provided in some embodiments of the present application is shown; Figure 2 A circuit structure diagram of a phase-adjusted sampling circuit provided in some embodiments of the present application is shown; Figure 3 A circuit structure schematic diagram of another phase-adjustable sampling circuit provided in some embodiments of the present application is shown; Figure 4 A circuit structure schematic diagram of another phase-adjustable sampling circuit provided in some embodiments of the present application is shown; Figure 5 A schematic flow chart of a sampling control method provided in some embodiments of the present application is shown; Figure 6 A diagram showing the relationship between the first preset correction capacitance value and the phase difference provided in some embodiments of the present application is shown; Figure 7 A diagram showing a proportional relationship between a first preset correction capacitance value and a phase difference provided in some embodiments of the present application is shown; Figure 8 A relationship diagram between a first correction capacitor parameter and a second correction capacitor parameter when a phase difference of 160 degrees is provided in some embodiments of the present application is shown; Fig. 9 A relationship diagram between a first correction capacitor parameter and a second correction capacitor parameter when the phase difference is 180 degrees provided in some embodiments of the present application is shown; Fig.10 A schematic structural diagram of a sampling control device provided in some embodiments of the present application is shown. DETAILED DESCRIPTION

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will illustrate examples of implementation of the present disclosure with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other accompanying drawings and other implementations can be obtained based on these drawings without creative work. Adjustments and improvements made without departing from the concept of the present disclosure are all within the protection scope of the present disclosure.

[0016] In order to simplify the drawings, each figure only schematically shows the parts related to the embodiments, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only a part of the components with the same structure or function is schematically drawn, and there may be more or less components with the same structure or function in reality.

[0017] In the present disclosure, unless otherwise clearly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish and describe associated objects, and cannot be understood as indicating or implying the relative importance or order between associated objects; in addition, they do not represent the number of associated objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between associated objects, which indicates the "or" relationship between associated objects. "And / or" is used to describe the relationship between associated objects, which includes any combination relationship between associated objects, such as "a and / or b" includes: "alone a", "alone b", or "a and b". "One or more" or "at least one" in multiple objects refers to any object or any combination of multiple objects, such as "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "alone a1", "alone a2", "alone a3", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0018] The development of wireless communication technology has continuously increased the signal frequency requirements of high-speed and high-precision analog-to-digital converters. In high-sampling-rate analog-to-digital converters, time-domain interleaved sampling is usually used to increase the sampling rate. The spectrum finally output by the analog-to-digital converter contains the higher-order harmonics of each sub-channel analog-to-digital converter itself, as well as the multi-channel spurious generated by the mismatch of amplitude and phase between multiple channels. In addition, due to non-ideal factors such as asymmetric routing and device mismatch, the even-order linearity of the differential signal is more severe with frequency. In the actual chip testing process, the even-order harmonic energy is often much higher than the other harmonic energies. This problem is difficult to accept in some special scenarios such as radar detection and other applications. Figure 1A schematic diagram of a conventional test scenario provided in some embodiments of the present application is shown. A high-frequency signal is provided by a signal source 10, converted into a differential signal by an external balun 20, and the differential signal is connected to the PCB board through two equal-length transmission lines, and then sent to the chip to be tested 30 through a series of RC matching network devices. However, the differential signal generated by the balun 20 cannot completely achieve a phase difference of 180 degrees, and the two transmission lines of the differential signal are also difficult to be completely symmetrical, so the differential signal sent to the chip to be tested 30 will produce a phase or amplitude difference. Inside the chip to be tested 30, the differential input is sent to the input port of the analog front-end circuit through a symmetrical routing, and then provided to each sub-analog-to-digital converter through a tree-like routing. In the actual layout, due to physical routing limitations, there is also a mismatch between the differential input routing and the tree-like routing, and there may also be a device mismatch in the analog front-end circuit, so the signal actually sent to the sampling input end of the sub-analog-to-digital converter must have a phase and amplitude mismatch, affecting the final test results or causing unexpected failures. Therefore, a sampling circuit provided in the present application can adjust the sampling capacitor sizes of the two input ends of the differential signal on the chip to reduce the mismatch of the differential input signal, thereby reducing the even harmonic energy of the entire analog-to-digital conversion chip.

[0019] Figure 2 A circuit structure diagram of a phase-adjusted sampling circuit provided in some embodiments of the present application is shown. The sampling circuit 200 includes: a first differential branch 210, a second differential branch 220, a first correction circuit 230, a second correction circuit 240, a sub-analog-to-digital converter 250, and a third correction circuit 260; the first differential branch is connected between the first port and the first input end of the sub-analog-to-digital converter; the second differential branch is connected between the second port and the second input end of the sub-analog-to-digital converter; the first correction circuit is connected between the second port and the first differential branch; the second correction circuit is connected between the first port and the second differential branch; the third correction circuit is coupled to the output end of the sub-analog-to-digital converter, and its first output end is coupled to the first correction circuit, and the second output end is coupled to the second correction circuit, and is configured to adjust the capacitance parameters of at least one circuit of the first correction circuit and the second correction circuit based on the output result of the sub-analog-to-digital converter to correct the even harmonics in the sampling result of the sampling circuit.

[0020] In an embodiment of the present application, the first differential branch 210 and the second differential branch 220 may include a sampling switch and a sampling capacitor. The sampling switch samples the input signal through the sampling capacitor under the control of a preset switching frequency to help the subsequent sub-analog-to-digital conversion circuit realize the function of analog-to-digital conversion. The sampling method can be top plate sampling or bottom plate sampling, which is not specifically limited here. The first correction circuit and the second correction circuit may include a correction capacitor and a switch. The first correction circuit and the second correction circuit are respectively controlled by a third correction circuit so that the correction capacitor cooperates with the sampling capacitor. Based on the output result of the sub-analog-to-digital converter, the size of the capacitor connected to the differential circuit is respectively adjusted to realize even harmonic correction. Taking the sampling method as top plate sampling as an example, for example, the input signal entering the sampling circuit from the first port IN1 and the second port IN2 can be expressed by formula 1:

[0021] The capacitance value provided by the second correction circuit can be set to a1, the capacitance value provided by the first correction circuit can be set to a2, and the sampling capacitance value of the first differential branch (or the second differential branch) can be set to 1. Therefore, the sampling and holding node VSP can be expressed as follows with reference to Formula 2:

[0022] make , then A1 and θ1 can be expressed by referring to Formula 3:

[0023] Similarly, the sample-and-hold node VSN can be expressed as follows with reference to Formula 4:

[0024] make , then A2 and θ2 can be expressed by referring to Formula 5:

[0025] If there is no phase difference between the final differential signals, that is, θ1=θ2+180°, combining equations 3 and 5 gives equation 6:

[0026] Therefore, the correction capacitor values ​​provided by the first correction circuit and the second correction circuit can be adjusted to make the phase difference between the two differential signals input to the sub-ADC close to or equal to 180°, thereby achieving phase error correction. On the other hand, in order to ensure that the amplitudes between the differential signals (i.e., between VSP and VSN) remain the same, formula 3 and formula 5 are combined, referring to formula 7:

[0027] According to Formula 7, by adjusting the capacitance value a1 provided by the second correction circuit and the capacitance value a2 provided by the first correction circuit, the errors of the amplitude and phase at both ends of the differential sampling are minimized, thereby reducing the energy of even harmonics.

[0028] Figure 3 A schematic diagram of the circuit structure of another phase-adjustable sampling circuit provided in some embodiments of the present application is shown. The sampling circuit 300 includes: a first differential branch, including: a first sampling switch Sc1 and a first sampling capacitor Cc1, the first sampling switch Sc1 is connected between the first port IN1 and the first end of the first sampling capacitor Cc1; a second differential branch includes: a second sampling switch Sc2 and a second sampling capacitor Cc2, the second sampling switch Sc2 is connected between the second port IN2 and the first end of the second sampling capacitor Cc2. The above circuit forms a top plate sampling structure, the first sampling switch Sc1 and the second sampling switch Sc2 can be switched on and off according to a certain sampling period according to the preset switch control requirements, so that the first sampling capacitor Cc1 or the second sampling capacitor Cc2 can collect the signal input through the first port IN1 or the second port IN2, and input the sampled differential signal into the sub-analog-to-digital converter 350 for analog-to-digital conversion. The capacitance specifications of the first sampling capacitor Cc1 and the second sampling capacitor Cc2 may be the same or different, and the sampling periods of the first sampling switch and the second sampling switch may be the same or different. For example, when there are phase and amplitude errors between differential signals, the even harmonic energy can be reduced by adjusting the sampling period or the parameters of the sampling capacitor.

[0029] Continue to refer Figure 3, the first correction circuit 330 includes a plurality of first correction branches, which are connected in parallel, wherein the first correction branch includes a first switch S1 and a first correction capacitor Cj1; the second correction circuit includes a plurality of second correction branches, which are connected in parallel, wherein the second correction branch includes a second switch S2 and a second correction capacitor Cj2. That is, the plurality of first correction branches include a plurality of first switches S1 and a plurality of first correction capacitors Cj1, and the plurality of second correction branches are similar to the first correction branches, wherein the number of the first correction branches and the second correction branches may be the same or different, the capacitance parameters of the plurality of first correction capacitors Cj1 may be the same or different, and the capacitance parameters of the plurality of second correction capacitors Cj2 may be the same or different, and may be set according to actual needs and adjustment requirements. The correction capacitors in the first correction circuit 330 and the second correction circuit 340 may be composed of the same unit capacitor or sub-capacitors in binary ratio. When adjusting the capacitance value provided in the first correction circuit 330 or the second correction circuit 340, the first correction capacitor Cj1 or the second correction capacitor Cj2 may be connected to the circuit by controlling the corresponding first switch S1 or the second switch S2 to adjust the phase and amplitude of the differential signal, thereby eliminating errors and reducing even harmonic energy.

[0030] In some embodiments, continue to refer to Figure 3 , the second end of the first sampling capacitor Cc1 is grounded, and the second end of the second sampling capacitor Cc2 is grounded; one end of the first switch S1 is coupled to the second port IN2, and the other end is coupled to the first end of the first correction capacitor Cj1, and the second end of the first correction capacitor Cj1 is grounded; one end of the second switch S2 is coupled to the first port IN1, and the other end is coupled to the first end of the second correction capacitor Cj2, and the second end of the second correction capacitor Cj2 is grounded.

[0031] Figure 4A circuit structure diagram of another phase-adjusted sampling circuit provided in some embodiments of the present application is shown. In the sampling circuit 400, the second end of the first sampling capacitor Cc1 is coupled to the first input end, and the second end of the second sampling capacitor Cc2 is coupled to the second input end; the first correction branch includes a first switch S1 and a first correction capacitor Cj1 connected in series between the second port IN2 and the first input end; the second correction branch includes a second switch S2 and a second correction capacitor Cj2 connected in series between the first port IN1 and the second input end. In the above embodiments, a structure of bottom plate sampling is formed, wherein, in the sampling stage of the top plate sampling, the top plate of the capacitor is connected to the input signal through a switch, and the bottom plate is equivalent to grounding. After the sampling is completed, the switch is disconnected, and the charge is stored on the top plate. When the bottom plate is sampled, the input signal is connected to the bottom plate, and the top plate is usually grounded. After the sampling is completed, the charge is transferred to other electrodes through a series of switch operations to complete the sampling. Top plate sampling is suitable for scenarios with high requirements for sampling speed but relatively low requirements for accuracy; bottom plate sampling is suitable for scenarios with high requirements for sampling accuracy and can accept more complex circuit designs. The circuit structure selection of the above embodiments can be designed based on actual application requirements.

[0032] Continue to refer Figure 4 , also includes: a common-mode voltage source VCM, a first access switch K1 and a second access switch K2 connected in series between the first input terminal and the second input terminal; the common-mode voltage source VCM is configured to provide a common-mode voltage to the first input terminal or the second input terminal based on the control of the first access switch or the second access switch. During the bottom plate sampling process, the bottom plate of the capacitor is connected to the input signal, and the top plate is usually grounded. For differential input signals, the common-mode part of the input signal (i.e., the average value of the two input signals) needs to be properly processed to avoid affecting the performance of the circuit. By introducing a common-mode voltage, it can be ensured that the common-mode level of the circuit remains stable. In addition, during the sampling process of the sampling switch, and during the opening and closing of the switch of the correction branch, the switch switching will generate noise, such as channel charge injection or clock feedthrough, which will affect the sampling accuracy. Accessing a common-mode voltage can help suppress the impact of these noises on the circuit performance, thereby improving the sampling accuracy.

[0033] Based on the same technical concept, Figure 5 , which shows a flow chart of a sampling control method provided in some embodiments of the present application. The method is used to control the sampling circuit of the phase adjustment of the first aspect, and at least includes the steps of: S510: configuring a first correction capacitor parameter of the first correction circuit and a second correction capacitor parameter of the second correction circuit to be a first preset correction capacitor value; S520: adjusting the first preset correction capacitance value to a second preset correction capacitance value, wherein the first preset correction capacitance value is smaller than the second preset correction capacitance value; S530: Obtain a first output result of the sub-analog-to-digital converter; S540: When the first output result satisfies the first preset parameter, adjust one or more of the first correction capacitance value and the second correction capacitance value respectively; S550: Obtain a second output result of the sub-analog-to-digital converter; S560: When the second output result satisfies the second preset parameter, the sub-analog-to-digital converter outputs the second output result.

[0034] In the method of the above embodiment, the first preset parameter includes an even harmonic parameter; the second preset parameter includes one or more of a phase error parameter and an amplitude error parameter. Figure 3 When the sampling circuit shown in the figure is controlled, the first correction capacitor parameter provided by the second correction circuit 340 can be set to a1, and the second correction capacitor parameter provided by the first correction circuit 330 can be set to a2, and they are respectively equal to the first preset correction capacitor value a. It can be determined through experimental testing that Figure 6 The relationship between the first preset correction capacitor value and the phase difference provided in some embodiments of the present application is shown. It can be seen from the figure that if the differential input signal VIP and VIN have a phase difference of 20 degrees, there is an a that can make the phase difference of the sampling end VSP / VSN 180 degrees, that is, the correction of the phase error is achieved. For the same phase error, there are multiple solutions of a that can make the equation valid, and the smaller a is, the smaller the capacitance in the connected circuit is, so the solution with a smaller a is preferred. Figure 6 It can be seen from the experimental results that when the input phase at both ends of the differential is about 168 degrees and 192 degrees, a takes the maximum value, which can be used as the maximum value of the sum of the capacitance values ​​provided by the first correction circuit 330 and the second correction circuit 340, which is about 0.7 times the capacitance value provided by the first sampling capacitor. On the other hand, in order to keep the amplitude of the sampling end VSP / VSN the same and satisfy Formula 7 in the above embodiment, when a1=a2=a, the relationship between the phase difference of the differential input signal VIP / VIN and the correction capacitor ratio a is as follows: Figure 7 As shown, Figure 7 A proportional relationship diagram of the first preset correction capacitance value and the phase difference provided in some embodiments of the present application is shown. Similar to the curve with a sampling end phase difference of 180 degrees, there are multiple different solutions for the same input phase difference that can satisfy the same amplitude at both ends of the differential sampling. It should be noted that there may not be a value of a1=a2=a that can simultaneously satisfy the same amplitude at both ends of the differential sampling and the phase difference of 180 degrees. Therefore, it is necessary to find the relationship between a1 and a2 to ensure that the equation of the same amplitude and the phase difference of 180 degrees are satisfied at the same time. For example, when the input phase difference is 160 degrees, Figure 8The relationship between the first correction capacitor parameter and the second correction capacitor parameter when the phase difference is 160 degrees provided in some embodiments of the present application is shown. In order to satisfy the same amplitude at both ends of the differential sampling and a phase difference of 180 degrees, the relationship between a1 and a2 is adjusted to Fig. 9 The relationship diagram shown. Figure 8 and Fig. 9 The values ​​of a1 and a2 can be obtained at the same time. The curves of a1 and a2 corresponding to each differential input phase difference can be obtained by the above method. Therefore, based on the above, a1=a2=a is first set, and then the value of a is roughly adjusted. The values ​​can be taken one by one from the minimum to the maximum value, and the size of the even harmonics in the quantization result of the sub-analog-to-digital converter is observed. When the even harmonics drop to the lowest value, a1 or a2 is finely adjusted to minimize the phase error and amplitude error at the sampling end, thereby further reducing the energy of the even harmonics.

[0035] Based on the same technical concept, the present application also provides an electronic device, including the sampling circuit provided in the above embodiment.

[0036] Based on the same technical concept, Fig.10 The schematic diagram of the structure of a sampling control device provided in some embodiments of the present application is shown. The sampling control device 1000 includes: a configuration unit 1010, configured to configure a first correction capacitor parameter of a first correction circuit and a second correction capacitor parameter of a second correction circuit to be a first preset correction capacitor value; an adjustment unit 1020, configured to adjust the first preset correction capacitor value to be a second preset correction capacitor value, wherein the first preset correction capacitor value is less than the second preset correction capacitor value; an acquisition unit 1030, configured to acquire a first output result of a sub-analog-to-digital converter; the adjustment unit 1020 is also configured to adjust one or more of the first correction capacitor value and the second correction capacitor value respectively when the first output result satisfies the first preset parameter; the acquisition unit 1030 is also configured to acquire a second output result of the sub-analog-to-digital converter; an output unit 1040, configured to enable the sub-analog-to-digital converter to output the second output result when the second output result satisfies the second preset parameter.

[0037] The division of the above units is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. In addition, the above units can be implemented in the form of a processor calling software; for example, a photovoltaic component roller brush cleaning control device includes a processor, the processor is connected to a memory, and instructions are stored in the memory. The processor calls the instructions stored in the memory to implement any of the above methods or realize the functions of each unit, wherein the processor is, for example, a general-purpose processor, such as a central processing unit (CPU), and the memory is a memory in the device or a memory outside the device. Alternatively, the above units can be implemented in the form of hardware circuits, and the functions of some or all of the units can be realized by designing the hardware circuits. The hardware circuit can be understood as one or more processors; for example, in some embodiments, the hardware circuit is an application specific integrated circuit (ASIC), and the functions of some or all of the above units are realized by designing the logical relationship of the components in the circuit; for example, in another implementation, the hardware circuit can be implemented by a programmable logic device (PLD), which can include a large number of logic gate circuits, and the logical relationship between the logic gate circuits is configured by a configuration file, so as to realize the functions of some or all of the above units. All units of the above device may be implemented entirely in the form of a processor calling a program, or entirely in the form of a hardware circuit, or partially in the form of a processor calling a program and the rest in the form of a hardware circuit.

[0038] In some embodiments of the present disclosure, the processor is a circuit with signal processing capability. In some embodiments, the processor may be a circuit with instruction reading and running capability, such as a CPU, a microprocessor, a graphics processing unit (GPU) or a digital signal processor (DSP), etc. In another implementation, the processor may implement certain functions through the logical relationship of a hardware circuit, and the logical relationship of the hardware circuit is fixed or reconfigurable, such as a hardware circuit implemented by an ASIC or PLD, such as a field programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document and implementing the hardware circuit configuration can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), a deep learning processing unit (DPU), etc. It can be seen that each unit in the above device can be one or more processors (or processing circuits) configured to implement the above method, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms. In addition, each unit in the above device can be integrated together in whole or in part, or can be implemented independently. In some embodiments, these units are integrated together and implemented in the form of a system on chip (SOC). The SOC may include at least one processor for implementing any of the above methods or implementing the functions of each unit of the above device.

[0039] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A phase-adjustable sampling circuit, characterized in that: include: A first differential branch, a second differential branch, a first correction circuit, a second correction circuit, a sub-analog-to-digital converter, and a third correction circuit; The first differential branch is connected between the first port and the first input terminal of the sub-ADC; The second differential branch is connected between the second port and the second input terminal of the sub-ADC; The first correction circuit is connected between the second port and the first differential branch; The second correction circuit is connected between the first port and the second differential branch; The third correction circuit is coupled to the output end of the sub-analog-to-digital converter, and its first output end is coupled to the first correction circuit, and its second output end is coupled to the second correction circuit. It is configured to adjust the capacitance parameters of at least one of the first correction circuit and the second correction circuit based on the output result of the sub-analog-to-digital converter to correct the even harmonics in the sampling result of the sampling circuit.

2. The sampling circuit according to claim 1, characterized in that: The first differential branch includes: a first sampling switch and a first sampling capacitor, wherein the first sampling switch is connected between the first port and a first end of the first sampling capacitor; The second differential branch includes: a second sampling switch and a second sampling capacitor, wherein the second sampling switch is connected between the second port and a first end of the second sampling capacitor.

3. The sampling circuit according to claim 2, characterized in that: The first correction circuit includes a plurality of first correction branches, the plurality of first correction branches are connected in parallel, wherein the first correction branch includes a first switch and a first correction capacitor; The second correction circuit includes a plurality of second correction branches, which are connected in parallel, wherein the second correction branch includes a second switch and a second correction capacitor.

4. The sampling circuit according to claim 3, characterized in that: The second end of the first sampling capacitor is grounded, and the second end of the second sampling capacitor is grounded; One end of the first switch is coupled to the second port, and the other end is coupled to the first end of the first correction capacitor, and the second end of the first correction capacitor is grounded; One end of the second switch is coupled to the first port, and the other end of the second switch is coupled to the first end of the second correction capacitor. The second end of the second correction capacitor is grounded.

5. The sampling circuit according to claim 3, characterized in that: The second end of the first sampling capacitor is coupled to the first input end, and the second end of the second sampling capacitor is coupled to the second input end; The first correction branch includes a first switch and a first correction capacitor connected in series between the second port and the first input terminal; The second correction branch includes a second switch and a second correction capacitor connected in series between the first port and the second input terminal.

6. The sampling circuit according to claim 5, characterized in that: Also includes: A common mode voltage source, a first access switch and a second access switch connected in series between the first input terminal and the second input terminal; The common mode voltage source is configured to provide a common mode voltage to the first input terminal or the second input terminal based on control of the first access switch or the second access switch.

7. The sampling circuit according to any one of claims 3 to 6, characterized in that: The capacitance values ​​of the first correction capacitors in the plurality of first correction branches are the same or different; The capacitance values ​​of the second correction capacitors in the plurality of second correction branches are the same or different.

8. A sampling control method, characterized in that: Used to control the sampling circuit according to any one of claims 1 to 7, comprising: configuring a first correction capacitor parameter of the first correction circuit and a second correction capacitor parameter of the second correction circuit to be a first preset correction capacitor value; Adjusting the first preset correction capacitance value to a second preset correction capacitance value, wherein the first preset correction capacitance value is smaller than the second preset correction capacitance value; Obtaining a first output result of the sub-analog-to-digital converter; When the first output result satisfies a first preset parameter, adjusting one or more of the first correction capacitance value and the second correction capacitance value respectively; Obtaining a second output result of the sub-analog-to-digital converter; When the second output result satisfies a second preset parameter, the sub-analog-to-digital converter is enabled to output the second output result.

9. The sampling control method according to claim 8, characterized in that: The first preset parameters include even harmonic parameters; The second preset parameter includes one or more of a phase error parameter and an amplitude error parameter.

10. An electronic device, characterized in that: The sampling circuit comprises the sampling circuit described in any one of claims 1 to 7.

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