A High-Order QAM Signal Demodulation Carrier Synchronization Design Method Based on Two-Level Loop Filtering

Abstract

This invention discloses a carrier synchronization design method for high-order QAM signal demodulation based on a two-stage loop filter, relating to the field of signal processing. It considers both steady-state phase difference and acquisition bandwidth for carrier synchronization, covering various application scenarios and providing good demodulation performance. This invention is implemented through the following technical solution: Loop one mainly includes a carrier compensator, a digital frequency discriminator, a digitally controlled oscillator, a first-stage digital loop filter, and a frequency lock detector; Loop two mainly includes a carrier compensator, a digital phase discriminator, a digitally controlled oscillator, a second-stage digital loop filter, and a phase lock detector. After the two loops are connected in series, the first-stage loop synchronously compensates for larger frequency offsets of the signal, while the second-stage loop synchronously compensates for smaller residual frequency and phase offsets. The lock detector monitors the design, achieving carrier synchronization for high-order QAM signal demodulation.

Description

Technical Field

[0001] This invention relates to the field of signal processing, and specifically to a design method for high-order QAM signal demodulation carrier synchronization based on two-stage loop filtering. Background Technology

[0002] The statements in this section are provided only as background information in connection with this disclosure and may not constitute prior art.

[0003] Since the mid-20th century, communication technology has developed rapidly. Modern communication technology has overcome the limitations of time and space, making it possible for people to obtain and exchange information anytime and anywhere. Among these, digital communication, due to its advantages of strong anti-interference capability, ease of modulation, high confidentiality, and ease of integration with computers, has been widely used in today's communication systems. A typical digital communication receiving system's signal processing includes: multiple access, frequency despreading, signal sampling, digital demodulation, channel decoding, decryption, and source decoding. The digital demodulator, as the most basic and core part of the digital receiving system, is equivalent to the "brain" of the entire receiving system. It processes the transmitted waveform, which has been degraded by the channel, and restores it to a digital sequence. High-order quadrature amplitude modulation (QAM), with its high bandwidth utilization and good power utilization, is widely used in ultra-shortwave communication and satellite communication. In practical applications, there is often a certain degree of time and frequency error between the transmitting and receiving systems. With changes in the electromagnetic environment, the signal may also experience carrier frequency changes such as Doppler shift during channel transmission. Therefore, carrier synchronization is crucial for the correct transmission of information during QAM signal demodulation. Its performance directly determines the quality of communication. Synchronization is a problem to be solved in almost all communication systems, and stable and accurate synchronization is essential for the demodulation of high-order QAM signals.

[0004] A typical carrier synchronization processing module includes a carrier compensator, a digital frequency discriminator, a digital loop filter, a numerically controlled oscillator, and a lock detector. The carrier synchronization processing module has two basic operating states: acquisition state and synchronization state. There are two main performance indicators for evaluating the acquisition process: one is the acquisition bandwidth of the digital loop, which is the maximum inherent frequency difference that the carrier synchronization module can achieve through the acquisition process to enter the synchronization state. If the frequency difference of the input signal is greater than the inherent frequency difference of the synchronization module, the synchronization module cannot enter the synchronization state. The other is the acquisition time, which is the time interval between the start of carrier synchronization and the moment of entering the synchronization state. The performance of the acquisition process mainly depends on the parameter settings of the digital loop filter, i.e., the determination of the loop bandwidth. Generally, the smaller the loop bandwidth, the lower the signal-to-noise ratio required for carrier synchronization locking, meaning the synchronization module is more likely to lock under harsh conditions, and the steady-state phase difference after locking is smaller, but the acquisition time is also longer. Conversely, the larger the loop bandwidth, the wider the acquisition bandwidth of the synchronization module, and the faster the acquisition, but the corresponding noise immunity and stability will be worse. In practical applications, conventional carrier synchronization processing methods are no longer sufficient to meet the ever-changing user needs in the face of increasingly complex and variable electromagnetic environments.

[0005] Balancing steady-state phase difference and acquisition bandwidth is crucial for ensuring signal demodulation carrier synchronization performance. In conventional methods, digital loop filter parameters determine demodulation carrier synchronization performance, but universally applicable parameters are difficult to determine for various situations. The two-stage digital loop filter design does not attempt to find a balance between steady-state phase difference and acquisition bandwidth. Instead, it designs different loop parameters to separately consider these two key performance indicators: the first-stage digital loop filter only considers the acquisition bandwidth, initially locking the frequency within a certain range, allowing for residual small frequency and phase offsets in the demodulation constellation diagram; the second-stage digital loop filter considers the steady-state phase difference, using a smaller loop bandwidth to track the residual frequency and phase offsets while achieving better noise immunity. Summary of the Invention

[0006] The purpose of this invention is to address the problems existing in the prior art by providing a high-order QAM signal demodulation carrier synchronization design method based on two-stage loop filtering, which takes into account the steady-state phase difference and acquisition bandwidth of carrier synchronization, covers a variety of application scenarios, and provides good demodulation performance.

[0007] The technical solution of the present invention is as follows:

[0008] A high-order QAM signal demodulation carrier synchronization design method based on two-stage loop filtering includes:

[0009] Step S1: Perform preliminary frequency offset acquisition on the high-order QAM complex signal with a large loop bandwidth, generate a carrier compensation signal, output the compensated high-order QAM complex signal, and perform lock detection on loop one;

[0010] Step S2: After the lock detection flag in step S1 is valid, perform secondary synchronous tracking on the compensated high-order QAM complex signal with a smaller loop bandwidth to generate a phase compensation signal, output the secondary compensated high-order QAM complex signal, and perform lock detection on loop two.

[0011] Step S3: After the lock detection flags of both loop one and loop two are valid, the high-order QAM complex signal after secondary compensation is the signal after carrier synchronization is completed.

[0012] Furthermore, the first loop includes: a carrier compensator, a digital frequency discriminator, a digitally controlled oscillator, a first-stage digital loop filter, and a frequency lock detector;

[0013] The second loop includes: a carrier compensator, a digital phase detector, a digitally controlled oscillator, a two-stage digital loop filter, and a phase-locked detector.

[0014] Further, step S1 includes:

[0015] Step S11: Perform digital frequency discrimination on the high-order QAM complex signal s1(n) using a digital frequency discriminator to obtain the frequency error ψ. a(n) ;

[0016] Step S12: Calculate the frequency error ψ a(n) The signal is fed into a first-stage digital loop filter, which outputs the frequency error control word ω. a(n) Simultaneously, the frequency lock detector begins to perform lock detection on the first-stage digital loop filter;

[0017] Step S13: Set the frequency error control word ω a(n) The signal is fed into a numerically controlled oscillator to generate a first-stage carrier compensation signal. The signal then enters the carrier compensator to compensate the higher-order QAM complex signal s1(n), and outputs the compensated higher-order QAM complex signal s2(n).

[0018] Further, step S2 includes:

[0019] Step S21: Perform digital frequency discrimination on the compensated high-order QAM complex signal s2(n) using a digital frequency discriminator to obtain the phase error ψ. b(n) ;

[0020] Step S22: Calculate the phase error ψ b(n) The signal is fed into a two-stage digital loop filter, which outputs the phase error control word ω. b(n) Simultaneously, the phase-locked detector begins locking detection on the second-stage digital loop filter;

[0021] Step S23: Set the phase error control word ωb(n) The signal is fed into a numerically controlled oscillator to generate a two-stage carrier compensation signal. The signal then enters the carrier compensator to compensate the higher-order QAM complex signal s2(n) after compensation, and outputs the higher-order QAM complex signal s3(n) after secondary compensation.

[0022] Furthermore, the frequency error control word ω a(n) Represented as:

[0023] ω a(n) =ω a(n-1) +C a1 (ψ a(n) -ψ a(n-1) )+C a2 ψ a(n)

[0024] Among them, C a1 C a2 These are the loop parameters of the first-stage digital loop filter. ω 1n Let ξ be the loop bandwidth, ξ be the damping coefficient, and T be the sampling period.

[0025] Furthermore, the phase error control word ω b(n) Represented as:

[0026] ω b(n) =ω b(n-1) +C b1 (ψ b(n) -ψ b(n-1) )+C b2 ψ b(n)

[0027] Among them, C b1 C b2 These are the loop parameters of the two-stage digital loop filter. ω 2n Let ξ be the loop bandwidth, ξ be the damping coefficient, and T be the sampling period.

[0028] Furthermore, the digital frequency discriminator employs a polarity-determined phase detection algorithm.

[0029] Furthermore, the input signal of the loop is the I and Q signals after down-conversion, resampling, matched filtering and bit synchronization.

[0030] Furthermore, the output signal of the loop is a carrier-locked output signal, i.e., the constellation diagram of the modulated signal.

[0031] Furthermore, the applicable modulation styles for the loop are 4QAM, 8QAM, 16QAM, 32QAM, 64QAM, 128QAM, 256QAM, 512QAM, and 1024QAM.

[0032] Compared with existing technologies, the advantages of this invention are:

[0033] 1. This invention optimizes carrier synchronization in high-order QAM signal demodulation by designing a two-stage digital loop filter. The first-stage digital loop filter quickly captures the carrier frequency offset of the signal with large frequency deviations and initially locks the frequency within a certain range. At this time, it is permissible for the demodulation constellation diagram to still have residual small frequency and phase offsets. The second-stage digital loop filter considers the steady-state phase difference and uses a smaller loop bandwidth to track the residual frequency and phase offsets, while obtaining better noise immunity. It effectively balances the steady-state phase difference of carrier synchronization and the acquisition bandwidth, providing good demodulation performance.

[0034] 2. This invention features a wide carrier synchronization acquisition range, high synchronization accuracy, strong noise resistance, and good adaptability and versatility. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the two-stage loop filter carrier synchronization process.

[0036] Figure 2 Schematic diagram of the first-stage loop filter feedback processing;

[0037] Figure 3 Schematic diagram of a digital frequency discriminator with single-stage loop filter feedback processing;

[0038] Figure 4 This is a schematic diagram of a two-stage loop filter feedback process. Detailed Implementation

[0039] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0040] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0041] Example 1

[0042] Please see Figure 1 A high-order QAM signal demodulation carrier synchronization design method based on two-stage loop filtering includes:

[0043] Step S1: Perform preliminary frequency offset acquisition on the high-order QAM complex signal with a large loop bandwidth, generate a carrier compensation signal, output the compensated high-order QAM complex signal, and perform lock detection on loop one;

[0044] Step S2: After the lock detection flag in step S1 is valid, perform secondary synchronous tracking on the compensated high-order QAM complex signal with a smaller loop bandwidth to generate a phase compensation signal, output the secondary compensated high-order QAM complex signal, and perform lock detection on loop two.

[0045] Step S3: After the lock detection flags of both loop one and loop two are valid, the high-order QAM complex signal after secondary compensation is the signal after carrier synchronization is completed.

[0046] In this embodiment, it should be noted that there are various design methods for the frequency lock detector, and the appropriate implementation structure can be selected in actual development. To better adapt to engineering practice, intermediate signals such as error signals and control word signals can also be appropriately smoothed. For example... Figure 2 As shown, loop one includes: a carrier compensator, a digital frequency discriminator, a first-stage digital loop filter, a digitally controlled oscillator, and a frequency lock detector.

[0047] Based on the signal characteristics, let the expression for the input baseband high-order QAM complex signal be:

[0048]

[0049] Specifically, step S1 includes:

[0050] Step S11: Perform digital frequency discrimination on the high-order QAM complex signal s1(n) using a digital frequency discriminator to obtain the frequency error ψ. a(n) ;

[0051] Step S12: Calculate the frequency error ψ a(n) The signal is fed into a first-stage digital loop filter, which outputs the frequency error control word ω. a(n) Simultaneously, the frequency lock detector begins locking the first-stage digital loop filter, i.e., when the frequency error ψ... a(n)Upon entering the first-stage digital loop filter, the frequency lock-in detector begins locking onto the filter. It's important to note that the first-stage digital loop filter is an infinite impulse response filter, capable of accumulating all previous frequency error signals to achieve a fixed control output in steady state. The frequency error control word ω output by the first-stage digital loop filter... a(n) Represented as:

[0052] ω a(n) =ω a(n-1) +C a1 (ψ a(n) -ψ a(n-1) )+C a2 ψ a(n)

[0053] Among them, C a1 C a2 These are the loop parameters of the first-stage digital loop filter. ω 1n Let ξ be the loop bandwidth, ξ be the damping coefficient, and T be the sampling period;

[0054] Step S13: Set the frequency error control word ω a(n) The signal is fed into a numerically controlled oscillator to generate a first-stage carrier compensation signal. The signal then enters the carrier compensator to compensate the higher-order QAM complex signal s1(n), and outputs the compensated higher-order QAM complex signal s2(n), denoted as...

[0055]

[0056] Figure 3 This is a schematic diagram of a digital frequency discriminator in the feedback processing of a first-stage loop filter. It should be noted that there are various design methods for digital frequency discriminators, and the appropriate implementation structure can be selected in actual development. To better adapt to engineering practice, this invention adopts a polarity-decision phase detection algorithm. Considering that the demodulated signal targeted in this invention is a high-order QAM signal with multiple levels, and the inner loop modulation symbol has a low signal-to-noise ratio (SNR) while the outer loop has a high SNR, a power detection method is incorporated into the detection algorithm—using only the high SNR symbols of the outer loop to calculate the phase error. When using outer loop modulation symbols, polarity-decision can be further used to replace level-by-level decision, further reducing the sensitivity of the phase detection output to accurate decision.

[0057] Let q(n) be the input signal of the digital frequency discriminator. The function of the power detector is to determine whether the power of the signal q(n) satisfies the condition |q(n)|. 2 >τ 2 τ is a set power threshold value, which varies depending on the modulation method, and determines the range of symbol points involved in frequency discrimination. That is, the power is greater than τ.2 The input symbols are first polarized, and then the phase error is calculated. Assume that within the nth symbol interval, i.e., t∈((n-1)T... s ,nT s When [the signal is], the input signal of the digital frequency discriminator is:

[0058]

[0059] Where, r n Let θ be the amplitude of the input signal q(n). n Let be the instantaneous phase of q(n). The signal output by the polarity decision unit is:

[0060]

[0061] The ratio of the input signal to the polarity decision unit output signal is:

[0062]

[0063] Considering that sin(x) ≈ x when x is very small, we can obtain the following by taking the imaginary part of the ratio of the input signal to the polarity decision circuit output signal:

[0064]

[0065] By taking the imaginary part of the ratio signal, we can obtain approximate phase difference information Δθ.

[0066] In summary, the phase error after polarity determination can be calculated using the following formula:

[0067]

[0068] Expressing the input signal q(n) in complex form, we have:

[0069] q(n) = I(n) + j·Q(n)

[0070] The polarity decision signal can be described as follows:

[0071] d(n)=A·{sgn[I(n)]+j·sgn[Q(n)]}

[0072] Substituting into the phase error formula, we get:

[0073]

[0074] As can be seen from the above equation, the extraction and calculation of this phase error does not require an actual multiplication unit, resulting in high efficiency. Power detection provides higher stability and reliability for phase detection of multi-level modulated signals.

[0075] Please see Figure 4 In this embodiment, both the digital phase detector and the phase-locked detector have multiple design methods, and their implementation structures can be selected as appropriate in actual development. For example... Figure 4 As shown, loop two includes: a carrier compensator, a digital phase detector, a digitally controlled oscillator, a two-stage digital loop filter, and a phase-locked detector. When Figure 2 After the locking flag output by the frequency lock detector shown is valid, Figure 2 The output s2(n) is used as input to enter... Figure 4 The loop-two feedback process is shown.

[0076] In this embodiment, specifically, step S2 includes:

[0077] Step S21: Perform digital frequency discrimination on the compensated high-order QAM complex signal s2(n) using a digital frequency discriminator to obtain the phase error ψ. b(n) ;

[0078] Step S22: Calculate the phase error ψ b(n) The signal is fed into a two-stage digital loop filter, which outputs the phase error control word ω. b(n) Simultaneously, the phase-locked detector begins locking the second-stage digital loop filter, i.e., when the phase error ψ... b(n) Upon entering the second-stage digital loop filter, the phase-locked detector begins locking onto the second-stage digital loop filter; the phase error control word ω b(n) Represented as:

[0079] ω b(n) =ω b(n-1) +C b1 (ψ b(n) -ψ b(n-1) )+C b2 ψ b(n)

[0080] Among them, C b1 C b2 These are the loop parameters of the two-stage digital loop filter. ω 2n Let ξ be the loop bandwidth, ξ be the damping coefficient, and T be the sampling period;

[0081] Step S23: Set the phase error control word ω b(n) The signal is fed into a numerically controlled oscillator to generate a two-stage carrier compensation signal. The signal then enters the carrier compensator to compensate the higher-order QAM complex signal s2(n), and outputs the higher-order QAM complex signal s3(n) after secondary compensation, with the expression:

[0082]

[0083] When the lock flag of the second-level digital loop filter is valid, s3(n) is the higher-order QAM signal after carrier synchronization is completed.

[0084] At this point, Δf3≈0 in the above equation. k = 0, 1, 2, 3.

[0085] In this embodiment, specifically, the input signal of the loop is the I and Q signals after down-conversion, resampling, matched filtering and bit synchronization.

[0086] In this embodiment, specifically, the output signal of the loop is the carrier-locked output signal, that is, the constellation diagram of the modulation signal.

[0087] In this embodiment, the specific modulation patterns applicable to the loop are 4QAM, 8QAM, 16QAM, 32QAM, 64QAM, 128QAM, 256QAM, 512QAM, and 1024QAM.

[0088] In this embodiment, specifically, Figure 2 and Figure 4 The structural differences mainly lie in the digital frequency discriminator, phase detector, and lock-on detector. However, the performance of the two loops depends primarily on the loop parameters of the digital loop filter.

[0089] Figure 1 This is a schematic diagram example of the entire two-stage loop filter for carrier synchronization processing, describing the high-order QAM carrier recovery process of the second-stage loop filter. The first-stage loop filter feedback performs initial frequency offset acquisition with a large loop bandwidth, requiring a long transient time, hence it is also called the slow loop; the second-stage loop filter feedback performs secondary synchronization tracking with a smaller loop bandwidth, requiring a shorter transient time, hence it is also called the fast loop. During the operation of the slow loop, the operation of the fast loop must be stopped, so a lock-in detector is used for control in the slow loop. After the slow loop locks in, it outputs a fixed phase deviation to compensate for the large fixed frequency deviation, while the remaining small frequency and phase deviations are tracked by the fast loop. The phase error signals generated by the slow and fast loops are accumulated and processed by a phase accumulator to generate a control word, which controls the numerically controlled oscillator to generate the corresponding carrier signal.

[0090] The carrier signal generated by the slow loop and the input signal s1(n) enter the carrier compensator. The output signal s2(n) after one-stage compensation is used as the input signal of the fast loop. After being captured by the fast loop, the carrier signal generated and s2(n) enter the carrier compensator. The output signal s3(n) is the high-order QAM signal after the carrier synchronization is completed.

[0091] The embodiments described above merely illustrate specific implementation methods of this application, and while the descriptions are detailed and specific, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the technical solution of this application, and these modifications and improvements all fall within the scope of protection of this application.

[0092] This background section is provided to generally present the context of the invention. The work of the currently named inventors, the work to the extent described in this background section, and aspects of this section that did not constitute prior art at the time of application are neither expressly nor impliedly acknowledged as prior art to the invention.

Claims

1. A high-order QAM signal demodulation carrier synchronization design method based on two-stage loop filtering, characterized in that, include: Step S1: Perform preliminary frequency offset acquisition on the high-order QAM complex signal with a large loop bandwidth, generate a carrier compensation signal, output the compensated high-order QAM complex signal, and perform lock detection on loop one; Step S2: After the lock detection flag in step S1 is valid, perform secondary synchronous tracking on the compensated high-order QAM complex signal with a smaller loop bandwidth to generate a phase compensation signal, output the secondary compensated high-order QAM complex signal, and perform lock detection on loop two. Step S3: After the lock detection flags of both loop one and loop two are valid, the high-order QAM complex signal after secondary compensation is the signal after carrier synchronization is completed; Step S1 includes: Step S11: Process the high-order QAM complex signal using a digital frequency discriminator. Digital frequency discrimination is performed to obtain the frequency error. ; Step S12: Convert the frequency error The signal is fed into a first-stage digital loop filter, which outputs a frequency error control word. Simultaneously, the frequency lock detector begins to perform lock detection on the first-stage digital loop filter; Step S13: Set the frequency error control word The signal is fed into a numerically controlled oscillator to generate a first-stage carrier compensation signal. And enter the carrier compensator for the high-order QAM complex signal. Perform compensation and output the compensated high-order QAM complex signal. ; Step S2 includes: Step S21: Analyze the compensated high-order QAM complex signal using a digital frequency discriminator. Digital frequency discrimination is performed to obtain the phase error. ; Step S22: Convert the phase error The signal is fed into a two-stage digital loop filter, which outputs a phase error control word. Simultaneously, the phase-locked detector begins locking detection on the second-stage digital loop filter; Step S23: Set the phase error control word The signal is fed into a numerically controlled oscillator to generate a two-stage carrier compensation signal. The signal then enters the carrier compensator to process the compensated high-order QAM complex signal. Perform compensation and output the higher-order QAM complex signal after secondary compensation. .

2. The high-order QAM signal demodulation carrier synchronization design method based on two-stage loop filtering according to claim 1, characterized in that, The first loop includes: a carrier compensator, a digital frequency discriminator, a digitally controlled oscillator, a first-stage digital loop filter, and a frequency lock detector; The second loop includes: a carrier compensator, a digital phase detector, a digitally controlled oscillator, a two-stage digital loop filter, and a phase-locked detector.

3. The high-order QAM signal demodulation carrier synchronization design method based on two-stage loop filtering according to claim 2, characterized in that, The frequency error control word Represented as: in, , These are the loop parameters of the first-stage digital loop filter. , , For loop bandwidth, The damping coefficient is... The sampling period.

4. The high-order QAM signal demodulation carrier synchronization design method based on two-stage loop filtering according to claim 3, characterized in that, The phase error control word Represented as: in, , These are the loop parameters of the two-stage digital loop filter. , , For loop bandwidth, The damping coefficient is... The sampling period.

5. The high-order QAM signal demodulation carrier synchronization design method based on two-stage loop filtering according to claim 2, characterized in that, The digital frequency discriminator employs a polarity-determined phase detection algorithm.

6. A high-order QAM signal demodulation carrier synchronization design method based on two-stage loop filtering according to any one of claims 1-5, characterized in that, The input signals of the loop are I and Q signals after down-conversion, resampling, matched filtering and bit synchronization.

7. A high-order QAM signal demodulation carrier synchronization design method based on two-stage loop filtering according to any one of claims 1-5, characterized in that, The output signal of the loop is the carrier-locked output signal, which is the constellation diagram of the modulated signal.

8. A high-order QAM signal demodulation carrier synchronization design method based on two-stage loop filtering according to any one of claims 1-5, characterized in that, The loop is compatible with the following modulation styles: 4QAM, 8QAM, 16QAM, 32QAM, 64QAM, 128QAM, 256QAM, 512QAM, and 1024QAM.

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