Verification method, device and equipment of network-on-chip, medium and program product

Abstract

The invention relates to the technical field of chips, and discloses a network-on-chip verification method, device and equipment, a medium and a program product. The method comprises the following steps: acquiring an application scene corresponding to a current on-chip subnet, and acquiring a target connection component, at least one target function component and at least one target constraint component according to the application scene; according to the target connection component, the at least one target function component, the at least one target constraint component and the adaptive adjustment component, establishing a subnet verification platform; and verifying the current on-chip subnet through the subnet verification platform to obtain a verification result. According to the scheme of the embodiment, the connection component, the function component, the constraint component and the adaptive adjustment component corresponding to different application scenes are arranged, so that various directional random verifications can be realized, and the verification convergence efficiency of the network-on-chip can be improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a verification method, device, equipment, medium and program product of an on-chip network. Background Art

[0002] As the scale of digital chip systems on chips continues to increase and the complexity of applications continues to increase, the scale and complexity of on-chip networks also increase. There are multiple subnets on a single chip, so there are many communication paths for on-chip networks. The application scenarios under multi-path conditions are also extremely complex, so the challenge of on-chip network verification and convergence is greatly increased, and long-term verification is required to ensure the robustness and robustness of the network.

[0003] At present, the existing verification methods of on-chip networks usually adopt a partition verification method, that is, the on-chip network is divided into multiple partitions, and each partition is verified separately. However, in the existing technology, the verification time is long and the resource consumption is large, and the verification efficiency of the on-chip network is low. Summary of the invention

[0004] The present invention provides a verification method, device, equipment, medium and program product of a network on chip, which can improve the verification convergence efficiency of the network on chip.

[0005] According to one aspect of the present invention, there is provided a verification method for a network on chip, comprising:

[0006] Acquire an application scenario corresponding to the current on-chip subnet, and acquire a target connection component, at least one target function component, and at least one target constraint component according to the application scenario;

[0007] Establishing a subnet verification platform according to the target connection component, the at least one target function component, the at least one target constraint component and the adaptive adjustment component;

[0008] The current on-chip subnet is verified through the subnet verification platform to obtain a verification result.

[0009] According to another aspect of the present invention, there is provided a verification device for a network on chip, comprising:

[0010] An application scenario acquisition module, used to acquire an application scenario corresponding to the current on-chip subnet, and acquire a target connection component, at least one target function component and at least one target constraint component according to the application scenario;

[0011] A subnet verification platform establishment module, used to establish a subnet verification platform according to the target connection component, the at least one target function component, the at least one target constraint component and the adaptive adjustment component;

[0012] The on-chip subnet verification module is used to verify the current on-chip subnet through the subnet verification platform and obtain a verification result.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the on-chip network verification method described in any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, wherein the computer program is used to enable a processor to implement the on-chip network verification method described in any embodiment of the present invention when executed.

[0018] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the verification method of the network on chip described in any embodiment of the present invention is implemented.

[0019] The technical solution of the embodiment of the present invention obtains the application scenario corresponding to the current on-chip subnet, and obtains the target connection component, at least one target function component and at least one target constraint component according to the application scenario; establishes a subnet verification platform according to the target connection component, at least one target function component, at least one target constraint component and an adaptive adjustment component; verifies the current on-chip subnet through the subnet verification platform to obtain a verification result; and by setting connection components, function components and constraint components corresponding to different application scenarios, as well as an adaptive adjustment component, a variety of directional random verifications can be achieved, which can improve the verification convergence efficiency of the on-chip network.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 is a flow chart of a verification method for a network on chip provided according to Embodiment 1 of the present invention;

[0023] Figure 2 is an extended schematic diagram of basic components provided according to the first embodiment of the present invention;

[0024] Figure 3 is a flow chart of another on-chip network verification method provided according to Embodiment 1 of the present invention;

[0025] Figure 4 is a schematic diagram of the structure of a network-on-chip verification device provided according to Embodiment 2 of the present invention;

[0026] Figure 5 It is a schematic diagram of the structure of an electronic device for implementing the verification method of the on-chip network according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first", "second", "target", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] Embodiment 1

[0030] Figure 1A flowchart of a verification method for a network on chip is provided for the first embodiment of the present invention. This embodiment is applicable to the case of performing directional random adaptive verification on a very large-scale network on chip. The method can be executed by a verification device for the network on chip. The verification device for the network on chip can be implemented in the form of hardware and / or software. Typically, the verification device for the network on chip can be configured in an electronic device, such as a computer device or a server. Figure 1 As shown, the method includes:

[0031] S110, obtaining an application scenario corresponding to the current on-chip subnet, and according to the application scenario, obtaining a target connection component, at least one target function component, and at least one target constraint component.

[0032] Among them, the on-chip subnet can be a regional subnet obtained by dividing the on-chip network. Each subnet can correspond to the same or different application scenarios. The application scenario can be composed of multiple functions, each of which has corresponding verification requirements. For example, the application scenario can include processor memory interconnection, artificial intelligence and machine learning, and communication between multiple processors.

[0033] In this embodiment, the development of basic connection components, basic functional components, basic constraint components and adaptive adjustment components can be carried out on the basis of Universal Verification Methodology (UVM). Among them, the basic connection component includes the connection between the Verification Internet Protocol (VIP) and the device under test (DUT) and the connection of the transaction level modeling (TLM) communication interface in the verification platform. The basic functional component includes various types of basic excitations and basic configuration components for different bus interfaces. The basic constraint component includes different types of basic scenario constraint components. The adaptive adjustment component is used to give a fuzzy interval and automatically generate precise directional excitations. Specifically, the basic functional components can be scheduled and controlled to generate different types of excitation signals.

[0034] Furthermore, through multiple levels of decoupling, different contents are developed and managed synchronously in partitions, and component functions are expanded according to different application scenarios. For example, the basic connection function can be expanded into the connection function of different subnets, the basic connection component can be expanded into different types of connection components, and the basic function component can be expanded into different types of excitation components. Secondly, the basic constraint component can be expanded into a constraint component for different scenarios to adapt to the verification requirements of multiple subnets. By integrating the basic components, the basic subnet component can be generated, and it can be expanded to the verification component of different types of subnets. Among them, by integrating the extended components, different types of on-chip network verification platforms can be customized. The adaptive adjustment component can be adapted to all verification platforms and automatically control the generation of different types of excitation signals.

[0035] For example, the extension of the basic component can be as follows Figure 2 As shown. The basic connection component, basic function component and basic constraint component can be respectively expanded into components suitable for different application scenarios and network environments. Among them, the target constraint component can include an attribute constraint component, a timing constraint component and / or a performance constraint component. The attribute constraint component is used to generate constraint conditions for attribute parameter values; the timing constraint component is used to generate constraint conditions for the time relationship of each element or operation; the performance constraint component is used to generate constraint conditions for performance parameter values. It can be understood that each constraint component can generate a series of constraints corresponding to different ranges, and each constraint condition can be composed of multiple parameters and corresponding value ranges. Among them, the excitation signal generated by the functional component needs to meet the corresponding constraint conditions.

[0036] In this embodiment, the application scenario corresponding to each connection component, functional component and constraint component can be preset, so that after obtaining the current application scenario, the target connection component, target functional component and target constraint component adapted to the current application scenario can be found according to the preset corresponding relationship. It should be noted that each application scenario can be adapted to one functional component and constraint component respectively, or multiple functional components and constraint components can be adapted at the same time.

[0037] In this embodiment, adaptive verification of different types of on-chip networks can be achieved by designing a large number of reusable basic components.

[0038] S120. Establish a subnet verification platform according to the target connection component, the at least one target function component, the at least one target constraint component and the adaptive adjustment component.

[0039] Specifically, the target connection component can be used to establish connections between the adaptive adjustment component, each target function component and each target constraint component, thereby realizing the integration of each component to establish a subnet verification platform. Secondly, the target connection component can also be used to establish a connection between the subnet verification platform and the current on-chip subnet for the transmission of verification-related information such as stimulus signals and verification results.

[0040] S130: Verify the current on-chip subnet through the subnet verification platform to obtain a verification result.

[0041] Specifically, the subnet verification platform can automatically send an excitation signal corresponding to the application scenario to the current on-chip subnet, and the operating status of the on-chip subnet can be monitored to obtain the operating result corresponding to the excitation signal; then, the operating result can be compared with the expected result. If it is detected that the operating result is the same as the expected result, or the difference is within the allowable range, then the verification result can be determined to be passed; if it is determined that the operating result is significantly different from the expected result, then the verification result can be determined to be failed.

[0042] In this embodiment, through scene decomposition, deep decoupling and multiple constraints, various directional random verifications such as precise control, fuzzy control and adaptation can be achieved. The adaptive mode can automatically analyze the results of each stimulus operation and automatically adjust the path of the next stimulus, greatly improving the network verification convergence efficiency.

[0043] The technical solution of the embodiment of the present invention obtains the application scenario corresponding to the current on-chip subnet, and obtains the target connection component, at least one target function component and at least one target constraint component according to the application scenario; establishes a subnet verification platform according to the target connection component, at least one target function component, at least one target constraint component and an adaptive adjustment component; verifies the current on-chip subnet through the subnet verification platform to obtain a verification result; and by setting connection components, function components and constraint components corresponding to different application scenarios, as well as an adaptive adjustment component, a variety of directional random verifications can be achieved, which can improve the verification convergence efficiency of the on-chip network.

[0044] In an optional implementation of this embodiment, verifying the current on-chip subnet through the subnet verification platform to obtain a verification result may include:

[0045] Generate scheduling instructions according to the application scenario through the adaptive adjustment component;

[0046] Acquiring multiple sets of parameter constraints through the at least one objective constraint component, and generating an excitation signal according to the scheduling instruction and the multiple sets of parameter constraints through the at least one objective function component;

[0047] The current on-chip subnet is verified according to the stimulus signal through the target connection component to obtain a verification result.

[0048] In this embodiment, through the adaptive adjustment component, multiple application functions that need to be verified and the verification order corresponding to each application function can be obtained according to the current application scenario; then, the target function component corresponding to each application function can be obtained, and the verification order corresponding to the application function can be used as the scheduling order of the corresponding target function component; finally, according to the target function component corresponding to each application function and the scheduling order of each target function component, the scheduling instruction corresponding to each target function component can be generated. Among them, the scheduling instruction can include the function component identifier and the corresponding scheduling order.

[0049] Afterwards, corresponding parameter constraints can be generated through each target constraint component to obtain multiple sets of parameter constraints. Furthermore, through each functional component, when it is determined that the current output excitation is required according to the scheduling order in the scheduling instruction, the expected parameter value is obtained according to each set of parameter constraints, and the corresponding excitation signal is output according to the parameter value. Finally, the excitation signal can be transmitted to the current on-chip subnet through the communication connection pre-established by the target connection component to verify the current on-chip subnet and obtain the corresponding verification result.

[0050] The advantage of the above setting is that it can realize automatic and efficient generation of different types of incentives and efficient verification of different application scenarios.

[0051] Optionally, generating the excitation signal according to the scheduling instruction and the plurality of sets of parameter constraints by the at least one target function component may include:

[0052] According to the scheduling instruction, the current target functional component is obtained, and the excitation signal is generated through the current target functional component according to the multiple groups of parameter constraints.

[0053] Specifically, the target functional component that currently needs to output excitation can be determined according to the scheduling order corresponding to each target functional component in the scheduling instruction; then, the target functional component can be controlled to solve the constraints according to each set of parameter constraints until the expected parameter values ​​are obtained; finally, the parameter values ​​corresponding to each set of parameter constraints can be mixed, and the current excitation signal can be generated according to the mixed parameter values.

[0054] Optionally, generating the excitation signal according to the plurality of sets of parameter constraints by the current objective function component may include:

[0055] By using the current target function component, solving the parameters according to the current parameter constraints, obtaining the current parameter values, and obtaining the standard parameter values ​​corresponding to the application scenario;

[0056] Performing collision analysis on the current parameter value and the standard parameter value to obtain collision density;

[0057] If it is detected that the collision density is greater than or equal to a preset expected value, an excitation signal is generated according to the current parameter value.

[0058] In a specific example, the process of the on-chip network verification method can be as follows: Figure 3 As shown. Specifically, first, select the current application scenario, and prepare to solve the constraints of all parameters in the application scenario; then, the parameter constraints can be solved according to the established formula to obtain a set of parameter values ​​under the current group of parameter constraints; wherein the established formula can be adaptively adjusted according to the type of parameter to be solved. Furthermore, the current parameter value can be subjected to data collision with the standard parameter value corresponding to the application scenario (the correspondence between the application scenario and the standard parameter value is pre-set) to obtain the collision density. Among them, data collision analysis is a method of using big data technology to find the correlation between data. The collision can be performed by comparing information such as the features, attributes or fingerprints of the data items. The collision density is used to indicate the degree of match between two sets of data. The larger the collision density, the higher the degree of match between the two sets of data. The smaller the collision density, the lower the degree of match between the two sets of data.

[0059] Then, when it is detected that the collision density reaches the expected value, that is, greater than or equal to the preset expected value, it can be determined that the parameter value matches successfully, and the current parameter value can be written into the cache. Further, the current parameter value can be mixed with the parameter value solved based on other sets of parameter constraints, and the mixed parameter value is written into the queue to be transmitted. Finally, the interface driver can be called to generate a corresponding excitation signal based on the parameter value in the queue to be transmitted and send it to the current on-chip subnet, and record the operation result of the current on-chip subnet, and then switch to the next application scenario.

[0060] Optionally, after performing collision analysis on the current parameter value and the standard parameter value to obtain the collision density, the following steps may also be included:

[0061] If it is detected that the collision density is less than the preset expected value, the current number of collisions is recorded, and the current parameter value is re-analyzed with the standard parameter value to obtain the collision density, until it is detected that the collision density is greater than or equal to the preset expected value, or the number of collisions is equal to the preset number threshold.

[0062] Specifically, Figure 3For example, in another case, if the collision result does not meet expectations, that is, the collision density is less than the preset expected value, the current number of collisions is recorded, and the collision analysis is performed again to obtain a new collision density. If the new collision density is still less than the preset expected value, the collision analysis is continued again. Then, if it is detected that the number of collisions is equal to the preset number threshold, and the collision density is always less than the preset expected value during this period, the collision analysis is terminated.

[0063] Optionally, for the current parameter value, when the number of collisions reaches a preset number threshold, the collision density obtained from the last collision analysis can be further analyzed. Specifically, if the collision density is less than the preset collision density lower limit, it can be considered that the collision density is very low, and then it can be considered that the scene does not match, and the system directly returns to the initial state. If the collision density is greater than or equal to the preset collision density lower limit, and less than the preset expected value, it can be considered that the collision density is considerable, and the system can return to step 2, that is, re-solve the parameter constraints according to the established formula, obtain a new set of parameter values ​​under the current set of parameter constraints, and re-perform the collision analysis for the new parameter values.

[0064] The solution of this embodiment can be developed in parallel quickly by adopting a deeply decoupled development model and a large number of reusable basic components; moreover, after completing the verification platform, the verification can be quickly converged through the adaptive mode.

[0065] Embodiment 2

[0066] Figure 4 This is a schematic diagram of the structure of a network-on-chip verification device provided by Embodiment 2 of the present invention. Figure 4 As shown, the device includes: an application scenario acquisition module 210, a subnet verification platform establishment module 220 and an on-chip subnet verification module 230; wherein,

[0067] The application scenario acquisition module 210 is used to acquire the application scenario corresponding to the current on-chip subnet, and acquire a target connection component, at least one target function component and at least one target constraint component according to the application scenario;

[0068] A subnet verification platform establishment module 220, configured to establish a subnet verification platform according to the target connection component, the at least one target function component, the at least one target constraint component and the adaptive adjustment component;

[0069] The on-chip subnet verification module 230 is used to verify the current on-chip subnet through the subnet verification platform and obtain a verification result.

[0070] The technical solution of the embodiment of the present invention obtains the application scenario corresponding to the current on-chip subnet, and obtains the target connection component, at least one target function component and at least one target constraint component according to the application scenario; establishes a subnet verification platform according to the target connection component, at least one target function component, at least one target constraint component and an adaptive adjustment component; verifies the current on-chip subnet through the subnet verification platform to obtain a verification result; and by setting connection components, function components and constraint components corresponding to different application scenarios, as well as an adaptive adjustment component, a variety of directional random verifications can be achieved, which can improve the verification convergence efficiency of the on-chip network.

[0071] Optionally, the on-chip subnet verification module 230 is specifically used to generate a scheduling instruction according to the application scenario through the adaptive adjustment component;

[0072] Acquiring multiple sets of parameter constraints through the at least one objective constraint component, and generating an excitation signal according to the scheduling instruction and the multiple sets of parameter constraints through the at least one objective function component;

[0073] The current on-chip subnet is verified according to the stimulus signal through the target connection component to obtain a verification result.

[0074] Optionally, the on-chip subnet verification module 230 is specifically configured to obtain a current target functional component according to the scheduling instruction, and generate an excitation signal through the current target functional component according to the multiple sets of parameter constraints.

[0075] Optionally, the on-chip subnet verification module 230 is specifically used to perform parameter solving according to the current parameter constraints through the current target functional component, obtain the current parameter value, and obtain the standard parameter value corresponding to the application scenario;

[0076] Performing collision analysis on the current parameter value and the standard parameter value to obtain collision density;

[0077] If it is detected that the collision density is greater than or equal to a preset expected value, an excitation signal is generated according to the current parameter value.

[0078] Optionally, the on-chip subnet verification module 230 is specifically used to record the current number of collisions if it is detected that the collision density is less than a preset expected value, and re-perform collision analysis on the current parameter value and the standard parameter value to obtain the collision density, until it is detected that the collision density is greater than or equal to the preset expected value, or the number of collisions is equal to a preset number threshold.

[0079] Optionally, the target constraint component includes an attribute constraint component, a timing constraint component and / or a performance constraint component.

[0080] The network-on-chip verification device provided in the embodiment of the present invention can execute the network-on-chip verification method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0081] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0082] Embodiment 3

[0083] Figure 5 A schematic diagram of the structure of an electronic device 30 that can be used to implement an embodiment of the present invention is shown. The electronic device 30 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 30 can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0084] like Figure 5 As shown, the electronic device 30 includes at least one processor 31, and a memory connected to the at least one processor 31, such as a read-only memory (ROM) 32, a random access memory (RAM) 33, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 31 can perform various appropriate actions and processes according to the computer program stored in the read-only memory 32 or the computer program loaded from the storage unit 38 to the random access memory 33. In the RAM 33, various programs and data required for the operation of the electronic device 30 can also be stored. The processor 31, the ROM 32 and the RAM 33 are connected to each other through a bus 34. The input / output (I / O) interface 35 is also connected to the bus 34.

[0085] A number of components in the electronic device 30 are connected to the I / O interface 35, including: an input unit 36, such as a keyboard, a mouse, etc.; an output unit 37, such as various types of displays, speakers, etc.; a storage unit 38, such as a disk, an optical disk, etc.; and a communication unit 39, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 39 allows the electronic device 30 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0086] The processor 31 may be a variety of general and / or dedicated processing components with processing and computing capabilities. Some examples of the processor 31 include, but are not limited to, a central processing unit, a graphics processing unit, various dedicated artificial intelligence computing chips, various processors running machine learning model algorithms, digital signal processors, and any appropriate processors, controllers, microcontrollers, etc. The processor 31 executes the various methods and processes described above, such as the verification method of the on-chip network.

[0087] In some embodiments, the verification method of the network on chip can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 38. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 30 via the ROM 32 and / or the communication unit 39. When the computer program is loaded into the RAM 33 and executed by the processor 31, one or more steps of the verification method of the network on chip described above can be performed. Alternatively, in other embodiments, the processor 31 can be configured to execute the verification method of the network on chip in any other appropriate manner (for example, by means of firmware).

[0088] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays, application specific integrated circuits, application specific standard products, systems on a chip, load programmable logic devices, computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0089] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0090] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical fiber, a portable compact disk read-only memory, an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0091] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device 30 having: a display device (e.g., a cathode ray tube or a liquid crystal display) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the electronic device 30. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0092] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local area networks, wide area networks, blockchain networks, and the Internet.

[0093] A computing system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship to each other. The server may be a cloud server.

[0094] This embodiment may also include a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the verification method of the network on chip provided by any embodiment of the present invention.

[0095] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0096] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A verification method for a network on chip, characterized in that: include: Acquire an application scenario corresponding to the current on-chip subnet, and acquire a target connection component, at least one target function component, and at least one target constraint component according to the application scenario; Establishing a subnet verification platform according to the target connection component, the at least one target function component, the at least one target constraint component and the adaptive adjustment component; The current on-chip subnet is verified through the subnet verification platform to obtain a verification result.

2. The method according to claim 1, characterized in that The current on-chip subnet is verified through the subnet verification platform to obtain a verification result, including: Generate scheduling instructions according to the application scenario through the adaptive adjustment component; Acquiring multiple sets of parameter constraints through the at least one objective constraint component, and generating an excitation signal according to the scheduling instruction and the multiple sets of parameter constraints through the at least one objective function component; The current on-chip subnet is verified according to the stimulus signal through the target connection component to obtain a verification result.

3. The method according to claim 2, characterized in that Generating an excitation signal according to the scheduling instruction and the plurality of sets of parameter constraints by the at least one target function component includes: According to the scheduling instruction, the current target functional component is obtained, and the excitation signal is generated through the current target functional component according to the multiple groups of parameter constraints.

4. The method according to claim 3, characterized in that Generate an excitation signal through the current target function component according to the plurality of sets of parameter constraints, including: By using the current target function component, solving the parameters according to the current parameter constraints, obtaining the current parameter values, and obtaining the standard parameter values ​​corresponding to the application scenario; Performing collision analysis on the current parameter value and the standard parameter value to obtain collision density; If it is detected that the collision density is greater than or equal to a preset expected value, an excitation signal is generated according to the current parameter value.

5. The method according to claim 4, characterized in that After performing collision analysis on the current parameter value and the standard parameter value to obtain the collision density, the method further includes: If it is detected that the collision density is less than the preset expected value, the current number of collisions is recorded, and the current parameter value is re-analyzed with the standard parameter value to obtain the collision density, until it is detected that the collision density is greater than or equal to the preset expected value, or the number of collisions is equal to the preset number threshold.

6. The method according to claim 1 or 2, characterized in that: The target constraint component includes an attribute constraint component, a timing constraint component and / or a performance constraint component.

7. A verification device for a network on chip, characterized in that: include: An application scenario acquisition module, used to acquire an application scenario corresponding to the current on-chip subnet, and acquire a target connection component, at least one target function component and at least one target constraint component according to the application scenario; A subnet verification platform establishment module, used to establish a subnet verification platform according to the target connection component, the at least one target function component, the at least one target constraint component and the adaptive adjustment component; The on-chip subnet verification module is used to verify the current on-chip subnet through the subnet verification platform and obtain a verification result.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor, and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the authentication method for the network on chip according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is used to enable a processor to implement the on-chip network verification method according to any one of claims 1 to 6 when the computer program is executed.

10. A computer program product, characterized in that The invention comprises a computer program, which implements the verification method of the network on chip according to any one of claims 1 to 6 when executed by a processor.

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