Systems, methods, and apparatus for upstream port replication on virtual switches

Abstract

An apparatus including a switch may include a first interface configured to communicate with at least one memory device; and a second interface configured to communicate with the first physical connector and the second physical connector; wherein the switch is configured to communicate with a device using the first physical connector using a memory access protocol. A second interface may be configured to communicate with a second device using the second physical connector using the memory access protocol. The apparatus may also include a second switch including: a third interface configured to communicate with the at least one memory device; and a fourth interface configured to communicate with a third physical connector and a fourth physical connector, where the second switch is configured to communicate with the device using the third physical connector using the memory access protocol.

Description

[0001] Citation of Related Applications

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application Serial No. 63 / 544,439, filed on October 16, 2023, and Korean Patent Application Serial No. 10-2024-0131071, filed on September 26, 2024, which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to virtual switches, and more particularly to systems, methods, and apparatus for upstream port replication on a virtual switch. Background Art

[0004] Generally speaking, a switch device allows one or more memory devices to connect to one or more host devices. The switch device may include a virtual switch that allows the one or more memory devices to be connected to the switch device using downstream ports and allows host devices to be connected to the switch device using upstream ports.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art. Summary of the invention

[0006] In some aspects, the technology described herein relates to an apparatus, comprising: a switch, comprising: a first interface configured to communicate with at least one memory device; and a second interface configured to communicate with a first physical connector and a second physical connector; wherein the switch is configured to communicate with the device using the first physical connector using a memory access protocol. In some aspects, the device is a first device; and wherein the second interface is configured to communicate with the second device using the second physical connector using the memory access protocol. In some aspects, the first physical connector is configured to connect to a connector on the device. In some aspects, the first physical connector is configured to send data from the at least one memory device to the device. In some aspects, the device is a first device; and wherein the second physical connector is configured to send data from the at least one memory device to the second device. In some aspects, the switch is a first switch; the apparatus further comprises a second switch; and the second switch comprises: a third interface configured to communicate with the at least one memory device; and a fourth interface configured to communicate with the third physical connector and a fourth physical connector, wherein the second switch is configured to communicate with the device using the third physical connector using the memory access protocol. In some aspects, the device is a first device; and wherein the apparatus is further configured to connect to a second device using the second physical connector on the first switch and the fourth physical connector on the second switch. In some aspects, the second physical connector is configured to connect to a connector on the second device. In some aspects, the fourth physical connector is configured to connect to a connector on the second device. In some aspects, the apparatus further comprises a second switch; wherein the device is a first device; wherein the second switch comprises: a third interface configured to communicate with the at least one memory device; and a fourth interface configured to communicate with a third physical connector and a fourth physical connector; wherein the third physical connector is configured to communicate with the first device; and wherein the second physical connector and the fourth physical connector are configured to communicate with the second device using the memory access protocol. In some aspects, the same data from the at least one memory device is sent to the first physical connector and the second physical connector.

[0007] In some aspects, the technology described herein relates to a system, the system comprising: a device; a memory device, and a switch device comprising a virtual switch, the virtual switch comprising a first interface and a second interface, wherein the first interface is configured to communicate with at least one memory device, wherein the second interface is configured to communicate with a first physical connector and a second physical connector, wherein the switch device is configured to communicate with the device using the first physical connector using a memory access protocol. In some aspects, the device is a first device; and the system further comprises a second device, wherein the second device is connected to the virtual switch using the first interface using the memory access protocol. In some aspects, the virtual switch is a first virtual switch; and wherein the switch device further comprises a second virtual switch, the second virtual switch comprising a third interface and a fourth interface; wherein the second virtual switch is connected to the memory device using the third interface using the memory access protocol, and wherein the second virtual switch is connected to the device using the fourth interface using the memory access protocol. In some aspects, the device is a first device; the virtual switch is a first virtual switch; the system includes a second device; and the switch device also includes a second virtual switch, the second virtual switch including a third interface and a fourth interface; wherein the second virtual switch is connected to the memory device using the third interface using the memory access protocol; wherein the second virtual switch is connected to the first device using the fourth interface using the memory access protocol, and wherein the second device is connected to the first virtual switch using the first interface and is connected to the second virtual switch using the fourth interface using the memory access protocol.

[0008] In some aspects, the technology described herein relates to a method comprising: receiving data from a memory device using a memory access protocol at a virtual switch using a first interface; and transmitting at least a portion of the data from the virtual switch to a first device and a second device using the memory access protocol using a second interface. In some aspects, the second interface includes a first connector and a second connector; and the transmitting includes: transmitting at least a portion of the data to the first device using the memory access protocol using the first connector; and transmitting at least a portion of the data to the second device using the memory access protocol using the second connector. In some aspects, the at least a portion of the data is a first portion of data; and wherein the method further comprises: transmitting at least a second portion of the data from the second interface to a second host device. In some aspects, the virtual switch is a first virtual switch; the data is first data; and the method further comprises: receiving second data from the memory device using the memory access protocol at a second virtual switch using a third interface; and transmitting at least a portion of the second data from the second virtual switch to the first device and the second device using a fourth interface. In some aspects, at least a portion of the first data is a first portion; at least a portion of the second data is a second portion; and the method further comprises interleaving the first portion and the second portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings are not necessarily drawn to scale, and throughout the drawings, for illustrative purposes, elements of similar structure or function may generally be represented by the same reference numerals or portions thereof. The drawings are intended only to facilitate the description of the various embodiments described herein. The drawings do not describe every aspect of the teachings disclosed herein and do not limit the scope of the claims. In order to prevent the drawings from becoming obscure, not all components, connections, etc. may be shown, and not all components may be shown with reference numerals. However, the pattern of the component configuration can be easily apparent from the drawings. The drawings, together with the specification, illustrate example embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0010] Figure 1a An example of a single virtual switch according to an example embodiment of the present disclosure is shown.

[0011] Figure 1b An example of multiple virtual switches according to an example embodiment of the present disclosure is shown.

[0012] Figure 1c Examples of multiple virtual switches with multiple logical devices and a single logical device are shown according to example embodiments of the present disclosure.

[0013] Figure 2a An example of an operating environment according to an example embodiment of the present disclosure is shown.

[0014] Figure 2b Another example of an operating environment according to an example embodiment of the present disclosure is shown.

[0015] Figure 2c Another example of an operating environment according to an example embodiment of the present disclosure is shown.

[0016] Figure 2d Another example of an operating environment according to an example embodiment of the present disclosure is shown.

[0017] Figure 3 An example of multiple host devices and multiple logical devices connected to multiple virtual switches according to an example embodiment of the present disclosure is shown.

[0018] Figure 4 Another example of multiple host devices and multiple logical devices connected to multiple virtual switches according to an example embodiment of the present disclosure is shown.

[0019] Figure 5 Another example of multiple host devices and multiple logical devices connected to multiple virtual switches according to an example embodiment of the present disclosure is shown.

[0020] Figure 6 Another example of multiple host devices and multiple logical devices connected to multiple virtual switches with upstream port replication according to an example embodiment of the present disclosure is shown.

[0021] Figure 7 An example of multiple decoders connected to multiple virtual switches according to an example embodiment of the present disclosure is shown.

[0022] Figure 8 An example of multiple decoders connected to multiple virtual switches with upstream port replication is shown according to an example embodiment of the present disclosure.

[0023] Fig. 9 An example of a switch according to an example embodiment of the present disclosure is shown.

[0024] Fig.10 An example of a switch with upstream port replication according to an example embodiment of the present disclosure is shown.

[0025] Fig.11 Another example of a switch with upstream port replication according to an example embodiment of the present disclosure is shown.

[0026] Fig.12 An example of a switch according to an example embodiment of the present disclosure is shown.

[0027] Fig.13 A flow chart of a method for upstream port replication in a virtual switch according to an example embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0028] A switch device may allow multiple memory devices to be connected to multiple host devices. The switch device may be connected to the device using one or more virtual switches, wherein the virtual switch allows multiple downstream ports and a single upstream port. For example, a virtual compute express link (CXL) switch (VCS) may support a single host (e.g., one upstream port) and multiple memory devices (e.g., multiple downstream ports). The downstream port may be connected to multiple memory devices, and the upstream port may be connected to the host using the VCS. Thus, multiple downstream ports may be used to transfer data from multiple memory devices to a single host device using an upstream port. However, the upstream port may not be able to receive the total bandwidth available from multiple downstream ports, and there may be unused capacity connected to the downstream ports. One solution may be to increase the number of upstream ports. However, this solution may add additional hardware to the switch device, and may not be cost effective or allow scalability as the number of host devices increases.

[0029] The amount of memory bandwidth available to a host device can generally be determined by the speed of the upstream port. However, a virtual switch may only allow a single connection (e.g., a single host device) for each upstream port. Therefore, although a virtual switch may allow a host device to connect to multiple memory devices, the total available bandwidth may be limited by the upstream port. For example, in the case of four memory devices, if the downstream port allows a transfer speed of 64GB / s, the total bandwidth available from the downstream port will be 256GB / s. The upstream port may also allow a transfer speed of 64GB / s, but since the upstream port can be connected to one host device, the bandwidth will be limited to 64GB / s. However, in some embodiments, by duplicating the upstream port, the total upstream transmission bandwidth can be increased, thereby allowing the virtual switch to perform transmissions between the host device and the memory device.

[0030] In some embodiments, the upstream port of the virtual switch can be connected to two or more duplicate ports (duplicated port). In some embodiments, the duplicate port can be mapped to a root port on the host device. Therefore, in some embodiments, the bandwidth of the upstream port can be increased by the number of duplicate ports. In addition, in some embodiments, the host device can have multiple root ports, thereby allowing multiple virtual switches to be mapped to a single host device. Therefore, the available bandwidth that the host device can use can be increased.

[0031] The present disclosure covers many aspects related to devices with memory and storage configurations. The aspects disclosed herein can have independent utility and can be embodied individually, and not every embodiment can utilize every aspect. In addition, these aspects can also be embodied in various combinations, some of which can amplify some benefits of various aspects in a collaborative manner.

[0032] For purposes of illustration, some embodiments may be described in the context of some specific implementation details, such as a device implemented as a storage device that may use specific interfaces, protocols, etc. However, aspects of the disclosure are not limited to these or any other implementation details.

[0033] Figure 1a An example of a single virtual switch according to an example embodiment of the present disclosure is shown. Figure 1a A virtual switch 100, a root port 150, and memory devices 180 and 182 are included. The virtual switch 100 may have bridges 110, 120, and 130. In some embodiments, the root port 150 may be part of a host device. In some embodiments, the virtual switch 100 may be part of an apparatus (e.g., a switch device). In some embodiments, the apparatus may have multiple virtual switches, and the virtual switch has multiple downstream ports and one upstream port. In some embodiments, the virtual switch 100 may be connected to the root port 150 using a bridge 110 (e.g., a virtual PCIe to PCIe bridge (vPPB)). In some embodiments, the bridge 110 may include an interface to the root port 150 (e.g., an upstream port). In some embodiments, the virtual switch may be connected to the memory device 180 using a bridge 120 (e.g., a vPPB), and may be connected to the memory device 182 using a bridge 130 (e.g., a vPPB). In some embodiments, the bridges 120 and 130 may use interfaces (e.g., downstream ports) to the memory devices 180 and 182. In some embodiments, root port 150 may be connected to virtual switch 100 via a connection (e.g., using a connector) between root port 150 and an interface of bridge 110 on virtual switch 100. In some embodiments, memory devices 180 and 182 may be connected to virtual switch 100 via physical connections to bridges 120 and 122, respectively.

[0034] In some embodiments, memory devices 180 and 182 may be CXL-compatible devices. Alternatively, memory devices 180 and 182 may be peripheral component interconnect express (PCIe) devices or any suitable memory devices that may be connected to a virtual switch. In addition, memory devices 180 and 182 may not be the same type of devices, for example, memory device 180 may be a CXL-compatible device and memory device 182 may be a PCIe device. In some embodiments, the virtual switch may communicate with memory devices 180 and 182 using a memory access protocol (e.g., a CXL protocol).

[0035] In some embodiments, bridge 110 may be a vPPB, which allows root port 150 to connect to virtual switch 100. In some embodiments, bridges 120 and 122 may also be vPPBs, allowing memory devices 180 and 182 to connect to virtual switch 100. In some embodiments, vPPBs may be connected to, for example, CXL-compatible devices via a physical PCIe-to-PCIe bridge (PPB). In some embodiments, the virtual switch may communicate with root port 150 using a memory access protocol (e.g., a CXL protocol).

[0036] although Figure 1a A single root port and upstream port are shown, but multiple root ports may be connected to the virtual switch 100 via corresponding upstream ports. In other words, if multiple virtual switches exist on a switch device, the upstream ports of the virtual switches may be connected to corresponding root ports of a host device.

[0037] Figure 1b An example of multiple virtual switches according to an example embodiment of the present disclosure is shown. Figure 1b The elements shown in the figure may be Figure 1a Elements similar to the elements shown in , where similar elements can be indicated by reference numerals ending with and / or containing the same numbers, letters, etc. Figure 1bAlso included is a virtual switch 102, a root port 152, a binding 160, and memory devices 190 and 192. The virtual switch 102 may include bridges 112, 122, and 132. In some embodiments, the virtual switches 100 and 102 may be virtual switches of the same switch device. In some embodiments, the virtual switch 100 may include an interface to the root port 150 (e.g., an upstream port) and an interface to memory devices 180 and 182 (e.g., a downstream port). In some embodiments, the virtual switch 102 may include an interface to the root port 152 (e.g., an upstream port) and an interface to memory devices 190 and 192 (e.g., a downstream port). In some embodiments, the root ports 150 and 152 may be ports to the same device or ports to different devices. In some embodiments, the binding 160 (e.g., a virtual to physical binding) may bind the vPPB (e.g., bridges 120, 122, 130, and 132) to the PPB to connect to memory devices 180, 182, 190, and 192, respectively. In some embodiments, root port 150 may be part of a host device and root port 152 may be part of the same or a different host device. In some embodiments, root port 150 may be connected to virtual switch 100 via a physical connection. In some embodiments, root port 152 may be connected to virtual switch 100 via a physical connection. Thus, in this example, the virtual switch may be connected to a root port and a plurality of memory devices.

[0038] Figure 1c An example of multiple virtual switches connected to a combination of single memory devices and pooled memory devices according to an example embodiment of the present disclosure is shown. Figure 1c The elements shown in the figure may be Figure 1b Elements similar to the elements shown in , where similar elements can be indicated by reference numerals ending with and / or containing the same numbers, letters, etc. Figure 1cAlso included is a bridge 170, a pooled memory device 194, and memory devices 196 and 198. In some embodiments, the virtual switch 100 may include an interface to the root port 150 (e.g., an upstream port) and an interface to the memory device 180 and the pooled memory device 194 (e.g., a downstream port). In some embodiments, the virtual switch 102 may include an interface to the root port 152 (e.g., an upstream port) and an interface to the memory device 190 and the pooled memory device 194 (e.g., a downstream port). In some embodiments, the bridge 120 may be connected to the memory device 180, and the bridge 132 may be connected to the memory device 190. In some embodiments, the bridges 130 and 132 may be connected to the pooled memory device 194 via the bridge 170. In some embodiments, the bridge 170 may be a PPB that allows multiple vPPBs (e.g., bridges 130 and 122) to be connected to the pooled memory device 194. In some embodiments, the pooled memory device 194 may be a multi-logical device (MLD) that may be divided into multiple logical devices (LDs) (e.g., memory devices 196 and 198), which allows multiple host devices to access different parts of the MLD simultaneously. In some embodiments, the MLD may accommodate multiple CXL-compatible devices (e.g., 16 LDs) and may be bound to a PPB consisting of multiple physical ports. In some embodiments, for an MLD configuration, multiple memory devices may support n-way interleaving, and interleaved partitions may be assigned to LDs. In some embodiments, an LD may be bound to an upstream port in a virtual switch. In other words, if the bridge 170 has sufficient bandwidth to support two root ports, the MLD configuration may support two host devices with a root port or one host device with two root ports. In some embodiments, the binding 160 may bind a vPPB (e.g., bridges 120, 130, 122, and 132) to a PPB to connect the virtual switches 100 and 102 to the memory devices 180 and 190 and the pooled memory device 194. In some embodiments, the virtual switches 100 and 102 may be bound to the root ports of the host devices. In some embodiments, root port 150 may be connected to virtual switch 100 via a physical connection between root port 150 and bridge 110. In some embodiments, root port 152 may be connected to virtual switch 102 via a physical connection between root port 152 and bridge 112. In some embodiments, virtual switches 100 and 102 may communicate with root ports 150 and 152 using a memory access protocol (e.g., CXL protocol).

[0039] In some embodiments, multiple MLDs can be connected to a single virtual switch. In addition, in some embodiments, the virtual switch can support various combinations of MLDs and SLDs. The maximum bandwidth of the virtual switch can be a combination of all transmission speeds of the downstream ports. For example, if the downstream port has 16 lanes, where the transmission speed of each lane is 4GB / s, the downstream port can support a transmission speed of 64GB / s. If the switch has four downstream ports, the maximum bandwidth can be 256GB / s.

[0040] In some embodiments, the switch device may set a limit on the total number of hosts that can be mapped on the virtual switch. For example, if a virtual switch with one upstream port using 16 lanes has a transfer speed of 4 GB / s per lane, the maximum transfer speed would be 64 GB / s. Therefore, the virtual switch may support a maximum transfer speed of 64 GB / s. Therefore, the limit on the number of upstream ports on the switch may limit the total number of hosts that can be mapped to the switch, even if the downstream ports and memory devices have sufficient internal load / store bandwidth.

[0041] In some embodiments, adding additional upstream ports can increase the total transfer speed available on the switch, but additional hardware may be required. Alternatively, as described in further detail below, port replication can be provided, in which ports are replicated, thereby allowing multiple connections to the upstream port of the virtual switch. For example, an upstream port can have multiple replicated ports (e.g., physical connectors) that can be connected to host devices. In the case of n-way interleaving, an upstream port can be bound to multiple LDs, and data from the LDs can be routed to different hosts or different root ports in a single host.

[0042] Figure 2a An example of an operating environment according to an example embodiment of the present disclosure is shown. Figure 2a Includes a switch 200, a host device 210, and memory devices 250, 252, 254, and 256. In some embodiments, the memory devices 250, 252, 254, and 256 can be connected to the switch 200 using a downstream port. In some embodiments, the downstream port can support 16 channels and 4GB / s per channel. Therefore, in some embodiments, the downstream port can support up to 64GB / s. In some embodiments, the memory devices 250, 252, 254, and 256 can use 4-way device interleaving to send data to the switch. In some embodiments, the total available bandwidth of the downstream port can be 256GB / s. In some embodiments, the host device 210 can be connected to the switch 200 using an upstream port. In some embodiments, the upstream port can support 16 channels and 4GB / s per channel. Therefore, the upstream port can support 64GB / s. Figure 2a In some embodiments, the upstream port may not be able to support the total bandwidth of the downstream port, resulting in the downstream port not using its total bandwidth capacity.

[0043] Figure 2b Another example of an operating environment according to an example embodiment of the present disclosure is shown. Figure 2b The elements shown in the figure may be Figure 2a , where similar elements may be indicated by reference numerals ending with and / or containing the same numbers, letters, etc. However, in Figure 2b In some embodiments, the downstream port may support 4 lanes, 4 GB / s per lane. Therefore, the total available bandwidth of the downstream port may be 64 GB / s. In some embodiments, since the upstream port bandwidth may be 64 GB / s and the downstream port bandwidth may be 64 GB / s, there may be no unused bandwidth. However, this may be the case when the storage device may only support 4 lanes.

[0044] Figure 2c Another example of an operating environment according to an example embodiment of the present disclosure is shown. Figure 2c The elements shown in the figure may be Figure 2a Elements similar to the elements shown in , where similar elements can be indicated by reference numerals ending with and / or containing the same numbers, letters, etc. Figure 2c A host device 220 is also included. In some embodiments, the host device 210 can be connected to the switch 200 using an interface (e.g., P0), and the host device 220 can be connected to the switch 200 using an interface (e.g., P1). In some embodiments, the memory devices 250 and 252 can correspond to the host device 210, and the memory devices 254 and 256 can correspond to the host device 220. In some embodiments, the memory devices 250 and 252 can use 2-way device interleaving, and the memory devices 254 and 256 can use 2-way device interleaving. In some embodiments, the downstream port can support 8 channels, 4GB / s per channel. Therefore, the total available bandwidth of the downstream port for 2-way device interleaving pairs can be 64GB / s. In some embodiments, the upstream port can support 16 channels and 4GB / s per channel. Therefore, the upstream port can support 64GB / s. In some embodiments, since the upstream port bandwidth can be 64GB / s and the downstream port bandwidth can be 64GB / s for the host device / storage device combination, there may be no unused bandwidth.

[0045] Figure 2dAnother example of an operating environment according to an example embodiment of the present disclosure is shown. Figure 2d The elements shown in the figure may be Figure 2a Elements similar to the elements shown in , where similar elements can be indicated by reference numerals ending with and / or containing the same numbers, letters, etc. Figure 2d Also included is a root device 230. In some embodiments, the root device 230 may include a decoder 232. In some embodiments, the decoder 232 may include ports 240 and 242. In some embodiments, the root device may be a root complex. In some embodiments, the root device 230 may allow a host to connect to the switch 200. In some embodiments, the decoder 232 may be a host managed device memory (HDM) decoder. In some embodiments, the decoder 232 may map a host physical address (HPA) to a device physical address (DPA) range on memory devices 250, 252, 254, and 256. In some embodiments, the root device 230 may connect to the switch 200 using port 240 and an interface (e.g., P0) on the switch 200 and using port 242 and an interface (e.g., P1) on the switch 200. In some embodiments, the memory devices 250 and 252 may correspond to port 240, and the memory devices 254 and 256 may correspond to port 242. In some embodiments, the memory devices 250 and 252 may use 2-way device interleaving, and the memory devices 254 and 256 may use 2-way device interleaving. In some embodiments, the downstream port may support 8 lanes at 4 GB / s per lane. Thus, the total available bandwidth of the downstream port for a 2-way device interleaved pair may be 64 GB / s. In some embodiments, the upstream port may support 16 lanes at 4 GB / s per lane. Thus, the upstream port may support 64 GB / s. In some embodiments, since the upstream port bandwidth may be 64 GB / s for a port and the downstream port bandwidth may be 64 GB / s for a port / storage device combination, there may be no unused bandwidth.

[0046] Figure 3 An example of multiple host devices and MLDs connected to multiple virtual switches according to an example embodiment of the present disclosure is shown. For illustration purposes, Figure 3 The virtual switch in is a VCS. However, the switch may not have a VCS and may include any other suitable type of virtual switch. Figure 4Includes a switch 300, root devices 320 and 330, a pooled memory device 360, and memory devices 370 and 372. In some embodiments, the switch 300 may include virtual switches 310, 312, 314, and 316. In some embodiments, the root device 320 may include a decoder 322, and the root device 330 may include a decoder 332. In some embodiments, the decoder 322 may include ports 340 and 342, and the decoder 332 may include ports 350 and 352. In some embodiments, the root device may be a root complex. In some embodiments, the decoder 232 may be an HDM decoder. In some embodiments, the pooled memory device 360 ​​may be an MLD having multiple LDs (e.g., LD0 to LD3). In some embodiments, the memory devices 370 and 372 may use 2-way device interleaving corresponding to the LDs in the pooled memory device 360. Although Figure 3 2-way memory device interleaving is shown, but in some embodiments, the pooled memory device 360 ​​can be connected to multiple devices, and multiple devices can use n-way device interleaving. In some embodiments, the pooled memory device 360 ​​can be connected to the switch 300 using 4 downstream ports with a maximum bandwidth of 256GB / s. In some embodiments, the virtual switches 310, 312, 314, and 316 can have physical connectors to ports 340, 342, 350, and 352. (For example, virtual switch 310 is mapped to port 340, virtual switch 312 is mapped to port 342, virtual switch 314 is mapped to port 350, and virtual switch 316 is mapped to port 352). In some embodiments, the virtual switch can have an interface to a root device that can be connected to a physical connector (e.g., P0, P1, P2, P3). In some embodiments, the port can support a bandwidth of 64GB / s. Therefore, in some embodiments, in order to support a total upstream port speed of 256GB / s, four virtual switches can be used.

[0047] Figure 4 Another example of multiple host devices and MLDs connected to multiple virtual switches according to an example embodiment of the present disclosure is shown. Figure 4 The elements shown in the figure may be Figure 3 Elements similar to those shown in , where similar elements can be indicated by reference numerals ending with and / or containing the same numbers, letters, etc. Figure 4 In the figure, the illustration of the virtual switch is omitted, but it should be understood that Figure 4 The interfaces in (P0, P1, P2, P3, P4, P5, P6, and P7) correspond to virtual switches. Figure 4Root devices 410 and 430 may also be included, root device 410 may include decoder 412, and root device 430 may include decoder 432. In some embodiments, decoder 412 may include ports 420, 422, 424, and 426; and decoder 432 may include ports 440, 442, 444, and 446. Figure 4 As shown, 8 virtual switches can support 8 ports on two root devices. In some embodiments, to support 256GB / s bandwidth to the root device, 4 ports can be used if the port supports 64GB / s bandwidth. Therefore, in some embodiments, when 4 ports are used in a given time period, 8 upstream ports may be available.

[0048] Figure 5 Another example of multiple host devices and MLDs connected to multiple virtual switches according to an example embodiment of the present disclosure is shown.

[0049] Figure 5 The elements shown in the figure may be Figure 4 Elements similar to the elements shown in , where similar elements can be indicated by reference numerals ending with and / or containing the same numbers, letters, etc. Figure 5 Also included is switch 500; virtual switches 510, 512, 514, 516, 518, 520, 522, and 524; interfaces 511, 513, 515, 517, 519, 521, 523, 525; pooled memory device 570; and memory devices 580 and 582. In some embodiments, virtual switches may correspond to logical devices (e.g., virtual switch 510 may correspond to LD0, virtual switch 512 may correspond to LD1, virtual switch 514 may correspond to LD2, virtual switch 516 may correspond to LD3, virtual switch 518 may correspond to LD4, virtual switch 520 may correspond to LD5, virtual switch 522 may correspond to LD6, and virtual switch 524 may correspond to LD7). In some embodiments, the virtual switch may have corresponding interfaces (e.g., virtual switch 510 may correspond to interface 511, virtual switch 512 may correspond to interface 513, virtual switch 514 may correspond to interface 515, virtual switch 516 may correspond to interface 517, virtual switch 518 may correspond to interface 519, virtual switch 520 may correspond to interface 521, virtual switch 522 may correspond to interface 523, and virtual switch 524 may correspond to interface 525). Therefore, in some embodiments, the virtual switch may be responsible for pooling logical devices on memory device 570.

[0050] like Figure 5As shown, 8 virtual switches can support 8 ports on two root devices. In some embodiments, to support 256GB / s bandwidth to the root device, 4 ports can be used if the port supports 64GB / s bandwidth. Therefore, in some embodiments, when 4 ports are used in a given time period, 8 upstream ports may be available.

[0051] Figure 6 Another example of multiple host devices and MLDs connected to multiple virtual switches with upstream port replication according to an example embodiment of the present disclosure is shown.

[0052] Figure 5 The elements shown in the figure may be Figure 4 , where similar elements may be indicated by reference numerals ending with and / or containing the same numbers, letters, etc. In some embodiments, switch 600 may include virtual switches 610, 612, 614, and 616, interfaces 611, 613, 615, 617, and physical connectors 620, 621, 622, 623, 624, 625, 626, and 627. In some embodiments, a virtual switch may correspond to multiple logical devices (e.g., virtual switch 610 may correspond to LD0 and LD4, virtual switch 612 may correspond to LD1 and LD5, virtual switch 614 may correspond to LD2 and LD6, and virtual switch 516 may correspond to LD3 and LD7). In some embodiments, a virtual switch may have corresponding interfaces (e.g., virtual switch 610 may correspond to interface 611, virtual switch 612 may correspond to interface 613, virtual switch 614 may correspond to interface 615, and virtual switch 616 may correspond to interface 617). In some embodiments, the interface may have one or more physical connectors (e.g., replication ports) (e.g., interface 611 may be connected to physical connectors 620 and 621, interface 613 may be connected to physical connectors 622 and 623, interface 615 may be connected to physical connectors 624 and 625, and interface 617 may be connected to physical connectors 626 and 627). Figure 6 In some embodiments, the LD can be mapped to a physical connector (e.g., a replication port) in a single interface (e.g., an upstream port). In some embodiments, since the channel is not split, bandwidth may not be sacrificed. In some embodiments, 4 upstream ports and 4 virtual switches may be utilized to support 256 GB / s bandwidth to two hosts.

[0053] In some embodiments, only four interfaces (e.g., upstream ports) may be used to support maximum bandwidth to facilitate eight root ports in two hosts. In some embodiments, port replication may enable the creation of multiple physical branch ports that may be connected to multiple root ports. In some embodiments, this may be achieved by having a virtual switch correspond to multiple LDs, where the LDs may be mapped to replicated ports in a single interface of a host device. In some embodiments, two LDs may be placed on a single virtual switch, and the LDs in the virtual switch may be mapped to replicated ports (e.g., upstream ports) of the interface.

[0054] Figure 7 An example of multiple decoders connected to multiple virtual switches according to an example embodiment of the present disclosure is shown. Figure 7 Included is a switch 700, decoders 710, 720, 730, 740, and 750, and a pooled memory device 760. Decoder 710 may include port 712, decoder 720 may include port 722, decoder 730 may include port 732, decoder 740 may include port 742, and decoder 750 may include port 752. The switch may include interfaces 714, 724, 734, 744, and 754. In some embodiments, interfaces 714, 724, 734, 744, and 754 may be interfaces for a virtual switch. In Figure 7 , 714, 724, 734, 744, and 754 are shown. However, there may be more virtual switches and interfaces. For example, if there are 64 decoders, there may be 64 corresponding virtual switches and interfaces. In some embodiments, when the virtual switch has a single interface (e.g., an upstream port), the switch 700 can use 64 virtual switches to support 64 decoders.

[0055] Figure 8 An example of multiple decoders connected to multiple virtual switches with upstream port replication is shown according to an example embodiment of the present disclosure.

[0056] Figure 8Includes switch 800, decoders 810, 820, 830, 840, 850, 860, 870, 880, and 890, and a pooled memory device 898. Decoder 810 may include port 812, decoder 820 may include port 822, decoder 830 may include port 832, decoder 840 may include port 842, decoder 850 may include port 852, decoder 860 may include port 862, decoder 870 may include port 872, decoder 880 may include port 882, and decoder 890 may include port 892. Switch 800 may include interfaces 816, 826, 836, and 846, and 16 physical connectors 814, 824, 834, 844. In some embodiments, interfaces 816, 826, 836, and 846 may be interfaces for virtual switches. In some embodiments, an interface may have multiple physical connectors. For example, Figure 8 16 physical connectors are shown for the interfaces (e.g., interface 816 can be connected to 16 physical connectors 814, interface 826 can be connected to 16 physical connectors 824, interface 836 can be connected to 16 physical connectors 834, and interface 846 can be connected to 16 physical connectors 844). Thus, in some embodiments, switch 800 can include a virtual switch with multiple physical connectors (e.g., upstream port replication). For example, an interface can be connected to 16 physical connectors, and therefore, to support 64 decoders, 4 virtual switches (e.g., 4 interfaces) can be used.

[0057] In some embodiments, the decoder can be coupled to the switch 800 at a transfer speed of 64 GB / s. To maximize bandwidth, in some embodiments, a given host device can occupy a physical port only for a given interval. In some embodiments, in the event that two host devices attempt to access a given upstream port at the same time, one host device can wait for the port to be idle before accessing the port, thereby reducing the bandwidth of the upstream port. In other words, by freeing up an upstream port for another host device to access the upstream port, the switch can achieve at least the same bandwidth as the switch without port replication, but can increase bandwidth utilization when host devices fairly share upstream ports.

[0058] Fig. 9 An example of a switch according to an example embodiment of the present disclosure is shown. Fig. 9Includes switch 900, host devices 910, 920, 930 and 940 and pooled memory device 960. In some embodiments, host devices 910, 920, 930 and 940 may include 4 ports. In other words, there are 16 ports between 4 host devices. In some embodiments, switch 900 may include interfaces 912, 914, 916, 918, 922, 924, 926, 928, 932, 934, 936, 938, 942, 944, 946 and 948. In some embodiments, interfaces 912, 914, 916, 918, 922, 924, 926, 928, 932, 934, 936, 938, 942, 944, 946 and 948 may correspond to virtual switches. In some embodiments, switch 900 may include 16 virtual switches with a single interface to support 4 host devices. In some embodiments, since the maximum downstream bandwidth may be 256 GB / s, the maximum upstream bandwidth may be 256 GB / s. Therefore, in some embodiments, 16 virtual switches may support 4 host devices with a maximum bandwidth of 256 GB / s.

[0059] Fig.10 An example of a switch with upstream port replication according to an example embodiment of the present disclosure is shown.

[0060] Fig.10 Includes a switch 1000, host devices 1010, 1020, 1030, and 1040, and a pooled memory device 1060. In some embodiments, host devices 1010, 1020, 1030, and 1040 may include 4 ports. In other words, 16 ports may be used between the 4 host devices. In some embodiments, switch 1000 may include interfaces 1014, 1024, 1034, and 1044, and 4 physical connectors 1012, 1022, 1032, and 1042. In some embodiments, interfaces 1014, 1024, 1034, and 1044 may be interfaces for a virtual switch (for example, interface 1014 may be part of a virtual switch, interface 1024 may be part of a different virtual switch, interface 1034 may be part of a different virtual switch, and interface 1044 may be part of a different virtual switch). In some embodiments, an interface may have multiple physical connectors. For example, Fig.10Four physical connectors for the interface are shown (e.g., interface 1014 can be connected to four physical connectors 1012, interface 1024 can be connected to four physical connectors 1022, interface 1034 can be connected to four physical connectors 1032, and interface 1044 can be connected to four physical connectors 1042). Therefore, in some embodiments, switch 1000 may include a virtual switch with multiple physical connectors (e.g., upstream port replication). For example, an interface can be connected to four physical connectors, and therefore, to support four host devices with four ports, four virtual switches (e.g., four interfaces) can be used. In some embodiments, since the maximum downstream bandwidth can be 256 GB / s, the maximum upstream bandwidth can also be 256 GB / s. Therefore, in some embodiments, four virtual switches with upstream port replication can support four host devices with a maximum bandwidth of 256 GB / s.

[0061] exist Fig.10 In the example of , full mesh port replication can be used, which supports 4-way interleaving in the host, and the host can have four upstream port mappings. This configuration can allow a maximum bandwidth of 256GB / s with only four upstream ports. In the worst case, if all ports in all hosts are fully utilized, the maximum bandwidth of the host can be reduced to one-fourth, such as 64GB / s, which will be the same bandwidth without port replication.

[0062] In some embodiments, it may not be necessary to change the virtual switch. In other words, the virtual switch may have a single interface (e.g., an upstream port). In this case, a port replication layer may be used to replicate the upstream port. In some embodiments, a selector for the upstream port may be used to direct data transfer between host devices. For example, the port replication layer may direct data to host 1 and / or host 2. In some embodiments, the virtual switch layer may not be aware of port replication and is connected to a single upstream port. In some embodiments, the port replication layer may use a selector so that the upstream port can use a physical connector between the switch and the host. In some embodiments, the host replication layer may be hardware or software. In addition, in some embodiments, a driver may synchronize data transfer between multiple hosts.

[0063] In some embodiments, when the host supports the HDM decoder, the host can implement 4-way interleaving. In some embodiments, if the host device maps four upstream ports with 16 lanes, the maximum bandwidth can be 256GB / s per host device. To support four hosts with 4-way interleaving, the switch can support 16 upstream ports and 16 lanes. Potentially, 16 upstream ports and 16 lanes can support bandwidth up to 16×16×4=1TB / s, but a switch for four hosts may only allow each host to support 256GB / s.

[0064] Fig.11 An example of a switch with upstream port replication according to an example embodiment of the present disclosure is shown. Fig.11 Includes switch 1100, host devices 1110 and 1120, and pooled memory device 1160. In some embodiments, pooled memory device 1160 can be connected to switch 1100 using 16 interfaces (e.g., downstream ports). In some embodiments, 16 interfaces can provide a maximum bandwidth of 1TB / s. In some embodiments, host devices 1110 and 1120 can have a total of 16 ports. In other words, host devices 1110 and 1120 can have a bandwidth that can be 1TB / s. The host device can use, for example, high bandwidth memory (HBM) for applications such as artificial intelligence (AI) to have a speed of 1TB / s. In some embodiments, if switch 1100 has port replication for 16 virtual switches 1130, switch 1100 can transmit 1TB / s to host devices 1110 and 1120. Therefore, in some embodiments, memory expansion for AI acceleration can be provided because the memory bandwidth can be comparable to HBM (1TB / s in this example).

[0065] Fig.12 An example of a switch device according to an example embodiment of the present disclosure is shown. Fig.12 The present invention includes an apparatus (e.g., a switch device 1200), a host device (e.g., a device 1240), and a memory device 1220. In some embodiments, the switch device may include a virtual switch 1210 and connectors 1230 and 1232. In some embodiments, the virtual switch 1210 may include a first interface 1212 and a second interface 1214. In some embodiments, the device 1240 may include a connector 1242. Although the memory device 1220 is shown, the switch device 1200 may be connected to multiple memory devices. In some embodiments, Fig.12 The switch device in can be used as Figure 6 , Figure 8 , Fig.10 or Fig.11 Any switch device in the .

[0066] In some embodiments, the switch device 1200 can communicate with the memory device 1220 using the virtual switch 1210. For example, the memory device 1220 can be connected to the first interface 1212. In some embodiments, the first interface can support 16 channels at 4 GB / s per channel or support a total of 64 GB / s per interface. In some embodiments, if the virtual switch 1210 has 4 interfaces to communicate with the memory device, 256 GB / s can be supported.

[0067] In some embodiments, the virtual switch 1210 can communicate with the device 1240 using the second interface 1214. For example, the second interface 1214 can communicate with the device 1240 using the connector 1230. In some embodiments, the second interface 1214 can also communicate with the device 1240 or another device using the connector 1232. Fig.12 As shown, connector 1230 can communicate with connector 1242 on device 1240. In some embodiments, connector 1230 can support 16 channels at 4GB / s per channel or support a total of 64GB / s per interface. In some embodiments, connector 1232 can also support 16 channels at 4GB / s per channel or support a total of 64GB / s per interface. Therefore, in this example, virtual switch 1210 can support 128GB / s to one or more devices (e.g., host devices). As more connectors are added to the second interface 1214 using port replication, the bandwidth available to the upstream port can be increased.

[0068] Fig.13 is a flow chart of an example method for upstream port replication in a virtual switch.

[0069] At step 1310, data may be received from a memory device using a first interface using a memory access protocol. For example, the switch may be connected to the memory device via one or more vPPBs. In some embodiments, the vPPB may be capable of a transfer speed of 64 GB / s. In some embodiments, the memory device may be a CXL compatible device or any other device capable of coupling with a virtual switch of a switch. In some embodiments, the switch may communicate with the memory device using a memory access protocol (e.g., a CXL protocol).

[0070] At step 1320, at least a first portion of the data may be transmitted to the first host device and the second host device using a second interface using a memory access protocol. For example, the switch may have a vPPB connected to a root port of the host device. In some embodiments, the vPPB may have a transmission speed of 64 GB / s. Therefore, the switch may read data from the memory device faster than it may transmit the data to the host device. In some embodiments, the vPPB may be connected to the root port of the second host device using a replication port. Therefore, for example, the vPPB may have a total transmission speed of 128 GB / s (e.g., 64 GB / s for the first host device and 64 GB / s for the second host device). In some embodiments, the second virtual switch may have a replication port coupled to the first host device and the second host device. Therefore, the total transmission speed may be 256 GB / s, wherein the upstream port may include a first replication port. In some embodiments, the switch may communicate with the first host device and the second host device using a memory access protocol (e.g., a CXL protocol).

[0071] The principles disclosed herein have independent utility and can be embodied separately, and not every embodiment can utilize every principle. However, these principles can also be embodied in various combinations, some of which can amplify the benefits of each principle in a synergistic manner.

[0072] For the purpose of illustrating the inventive principles of the present disclosure, some example embodiments may be described in the context of specific implementation details, such as a processing system that may implement a NUMA architecture, a memory device, and / or a pool that may be connected to the processing system using an interconnect interface and / or a protocol Compute Express Link (CXL), etc. However, the principles are not limited to these example details and may be implemented using any other type of system architecture, interface, protocol, etc.

[0073] Although some example embodiments may be described in the context of specific implementation details, such as a processing system that may implement a NUMA architecture, memory devices and / or pools that may be connected to the processing system using an interconnect interface and / or protocol CXL, etc., the principles are not limited to these example details and may be implemented using any other type of system architecture, interface, protocol, etc. For example, in some embodiments, one or more memory devices may be connected using any type of interface and / or protocol, including Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), NVMe over Fabric (NVMe oF), Advanced Extensible Interface (AXI), Ultra Path Interconnect (UPI), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Remote Direct Memory Access (RDMA), RDMA over Converged Ethernet (ROCE), Fibre Channel, InfiniBand, Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), iWARP, and / or the like, or any combination thereof. In some embodiments, the interconnect interface may be implemented using one or more memory semantics and / or memory consistency interfaces and / or protocols, including one or more CXL protocols (such as CXL.mem, CXL.io, and / or CXL.cache), Gen-Z, a consistent accelerator processor interface (CAPI), a cache coherent interconnect for accelerators (CCIX), etc., or any combination thereof. Any memory device may be implemented with one or more of any type of memory device interface, including DDR, DDR2, DDR3, DDR4, DDR5, LPDDRX, an open memory interface (OMI), NVLink, high bandwidth memory (HBM), HBM2, HBM3, etc.

[0074] In some embodiments, any of the memory devices, memory pools, hosts, etc., or components thereof may be implemented in any physical and / or electrical configuration and / or form factor, such as a standalone device, an add-in card such as a PCIe adapter or expansion card, a plug-in device that can be inserted into a connector and / or slot of a server chassis (e.g., a connector on a backplane and / or midplane of a server or other device), etc. In some embodiments, any of the memory devices, memory pools, hosts, etc., or components thereof may be implemented using any connector configuration for interconnect interfaces (such as SATA connectors, SCSI connectors, SAS connectors, M.2 connectors, U.2 connectors, U.3 connectors, etc.) in a form factor for storage devices (such as 3.5 inches, 2.5 inches, 1.8 inches, M.2, Enterprise and Data Center SSD Form Factor (EDSFF), NF1, etc.). Any device disclosed herein may be implemented and / or used in conjunction with, in whole or in part, a server chassis, a server rack, a data center, a data center, an edge data center, a mobile edge data center, and / or any combination thereof. In some embodiments, any of the memory devices, memory pools, hosts, and / or the like, or components thereof, may be implemented as CXL Type 1 devices, CXL Type 2 devices, CXL Type 3 devices, and / or the like.

[0075] In some embodiments, any functionality described herein, including, for example, any logic for implementing tiering, device selection, etc., may be implemented in hardware, software, or a combination thereof, including combinatorial logic, sequential logic, one or more timers, counters, registers, and / or state machines, one or more complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), central processing units (CPUs) such as complex instruction set computers (CISC) processors such as x86 processors and / or reduced instruction set computers (RISC) processors such as ARM processors, graphics processing units (GPUs), neural processing units (NPUs), tensor processing units (TPUs), etc., executing instructions stored in any type of memory, or any combination thereof. In some embodiments, one or more components may be implemented as a system on a chip (SOC).

[0076] In the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure, but the disclosed aspects can be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits are not described in detail to avoid obscuring the subject matter disclosed herein.

[0077] References throughout this specification to "one embodiment" or "an embodiment" mean that the specific features, structures, or characteristics described in conjunction with the embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment" or "in an embodiment" or "according to an embodiment" (or other phrases with similar meanings) that appear in various places throughout this specification may not necessarily all refer to the same embodiment. In addition, the specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "used as an example, instance, or illustration". Any embodiment described herein as "exemplary" should not be interpreted as necessarily being preferred or advantageous over other embodiments. In addition, the specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In addition, depending on the context discussed herein, a singular term may include a corresponding plural form, and a plural term may include a corresponding singular form. Similarly, hyphenated terms (e.g., "two-dimensional", "pre-determined", "pixel-specific", etc.) may occasionally be used interchangeably with corresponding non-hyphenated versions (e.g., "two dimensional", "predetermined", "pixel-specific", etc.), and capitalized terms (e.g., "Counter Clock", "Row Select", "PIXOUT", etc.) may be used interchangeably with corresponding non-capitalized versions (e.g., "counter clock", "row select", "pixout", etc.). Such occasional interchangeable usage should not be considered inconsistent with each other.

[0078] In addition, depending on the context of the discussion herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It should also be noted that the various drawings (including component drawings) shown and discussed herein are for illustrative purposes only and are not drawn to scale. For example, for clarity, the size of some elements may be enlarged relative to other elements. In addition, if deemed appropriate, reference numerals are repeated in the drawings to indicate corresponding and / or similar elements.

[0079] The terms used herein are only used for the purpose of describing some example embodiments and are not intended to limit the claimed subject matter. As used herein, the singular forms "a", "an", and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. When used in this specification, the terms "include" and / or "comprise" specify the presence of the features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0080] When an element or layer is referred to as being on, "connected to," or "coupled to" another element or layer, it may be directly on, connected to, or coupled to another element or layer, or there may be intermediate elements or layers. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. The same reference numerals always refer to the same elements. As used herein, the term "and / or" may include any and all combinations of one or more associated listed items.

[0081] As used herein, the terms "first", "second", etc. are used as labels for the nouns that precede them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. In addition, the same figure mark may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules with the same or similar functions. However, such use is only for simplicity of illustration and ease of discussion; it does not mean that the construction or architectural details of such components or units are the same in all embodiments, or that such commonly referenced parts / modules are the only way to implement some example embodiments disclosed herein.

[0082] The term "module" may refer to any combination of software, firmware, and / or hardware configured to provide the functions described herein in conjunction with the module. For example, software may be embodied as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any embodiment described herein may include, for example, components, hardwired circuits, programmable circuits, state machine circuits, and / or firmware storing instructions executed by programmable circuits, either alone or in any combination. Modules may be embodied together or individually as circuits forming part of a larger system, such as, but not limited to, integrated circuits (ICs), systems on chips (SoCs), components, and the like. The embodiments of the subject matter and operations described in this specification may be implemented in digital electronic circuits, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them. The embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, which are encoded on a computer storage medium for execution by a data processing device or for controlling the operation of a data processing device. Alternatively or additionally, program instructions may be encoded on an artificially generated propagation signal, for example, a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device for execution by a data processing device. A computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof, or be included therein. In addition, although a computer storage medium is not a propagation signal, a computer storage medium may be a source or destination of computer program instructions encoded in an artificially generated propagation signal. A computer storage medium may also be one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices), or be included in one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). In addition, the operations described in this specification may be implemented as operations performed by a data processing device on data stored on one or more computer-readable storage devices or received from other sources.

[0083] Although this specification may contain many specific implementation details, the implementation details should not be interpreted as a limitation on the scope of any claimed subject matter, but rather as a description of features specific to a particular embodiment. Certain features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as acting in certain combinations and even initially claimed as such, one or more features from the claimed combination may be excluded from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0084] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequence, or that all of the operations shown be performed, to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0085] Thus, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or in order to achieve the desired results. In some embodiments, multitasking and parallel processing may be advantageous.

[0086] Since the inventive concepts of this patent disclosure may be modified in arrangement and detail without departing from the inventive concept, such changes and modifications are considered to fall within the scope of the appended claims.

Claims

1. A device for upstream port replication on a virtual switch, comprising: Switches, including: a first interface configured to communicate with at least one memory device; and The second interface is configured to communicate with the first physical connector and the second physical connector; wherein the switch is configured to communicate with the device using the first physical connector using a memory access protocol.

2. The device according to claim 1, wherein: The device is a first device; and wherein the second interface is configured to communicate with a second device using the second physical connector using the memory access protocol.

3. The device according to claim 1, wherein: The first physical connector is configured to connect to a connector on the device.

4. The device according to claim 1, wherein: The first physical connector is configured to transmit data from the at least one memory device to the device.

5. The device according to claim 1, wherein: The device is a first device; and wherein the second physical connector is configured to transmit data from the at least one memory device to a second device.

6. The device according to claim 1, in, The switch is a first switch; Wherein, the device further includes a second switch; and Wherein, the second switch comprises: a third interface configured to communicate with the at least one memory device; and and a fourth interface configured to communicate with the third physical connector and the fourth physical connector, wherein the second switch is configured to communicate with the device using the third physical connector using the memory access protocol.

7. The device according to claim 6, wherein: The device is a first device; and wherein the apparatus is further configured to connect to a second device using the second physical connector on the first switch and the fourth physical connector on the second switch.

8. The device according to claim 6, wherein: The second physical connector is configured to connect to a connector on a second device.

9. The device according to claim 6, wherein: The fourth physical connector is configured to connect to a connector on a second device.

10. The apparatus according to claim 1, further comprising a second switch; in, The device is a first device; Wherein, the second switch comprises: a third interface configured to communicate with the at least one memory device; and a fourth interface configured to communicate with the third physical connector and the fourth physical connector; wherein the third physical connector is configured to communicate with the first device; and The second physical connector and the fourth physical connector are configured to communicate with the second device using the memory access protocol.

11. The device according to claim 1, wherein: The same data from the at least one memory device is sent to the first physical connector and the second physical connector.

12. A system for upstream port replication on a virtual switch, comprising: equipment; Memory devices, and A switch device comprising a virtual switch, the virtual switch comprising: a first interface configured to communicate with at least one memory device; and The second interface is configured to communicate with the first physical connector and the second physical connector; wherein the switch device is configured to communicate with the device using the first physical connector using a memory access protocol.

13. The system according to claim 12, wherein: The device is a first device; and wherein the system further comprises: A second device, wherein the second device is connected to the virtual switch using the first interface using the memory access protocol.

14. The system according to claim 12, wherein: The virtual switch is a first virtual switch; and wherein the switch device further comprises: A second virtual switch comprises a third interface and a fourth interface; wherein the second virtual switch uses the third interface to connect to the memory device using the memory access protocol, and wherein the second virtual switch uses the fourth interface to connect to the device using the memory access protocol.

15. The system according to claim 12, in, The device is a first device; Wherein, the virtual switch is a first virtual switch; Wherein, the system comprises a second device; and Wherein, the switch device further includes: The second virtual switch includes a third interface and a fourth interface; wherein the second virtual switch uses the memory access protocol to connect to the memory device using the third interface; wherein the second virtual switch uses the memory access protocol to connect to the first device using the fourth interface, and The second device is connected to the first virtual switch using the first interface, and is connected to the second virtual switch using the fourth interface using the memory access protocol.

16. A method for upstream port replication on a virtual switch, comprising: receiving data from the memory device using a memory access protocol at the virtual switch using the first interface; as well as At least a portion of the data is transmitted from the virtual switch to a first device and a second device using the memory access protocol using a second interface.

17. The method according to claim 16, wherein: The second interface includes a first connector and a second connector; And wherein transmitting at least a portion of the data to the first device and the second device using the memory access protocol comprises: using the first connector, transmitting the at least a portion of the data to the first device using the memory access protocol; and Using the second connector, the at least a portion of the data is transferred to the second device using the memory access protocol.

18. The method according to claim 16, wherein: The at least a portion of the data is a first portion of data; and wherein the method further comprises: At least a second portion of the data is transmitted from the second interface to a second host device.

19. The method according to claim 16, in, The virtual switch is a first virtual switch; wherein the data is first data; and Wherein, the method further comprises: receiving second data from the memory device using the memory access protocol at the second virtual switch using a third interface; and At least a portion of the second data is transmitted from the second virtual switch to the first device and the second device using a fourth interface.

20. The method according to claim 19, in, The at least one portion of the first data is a first portion; wherein the at least a portion of the second data is a second portion; and Wherein, the method further comprises interleaving the first portion and the second portion.

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