Load balancing and acceleration method for multiple cross-chip channels of lossless switch

Abstract

The invention provides a load balancing and acceleration method for a plurality of cross-chip channels of a lossless switch, which comprises the following steps: a crossbar node flow distribution module distributes data for nodes based on a source port mode, and each packet recombination module carries out data recombination according to a preset byte interval; the asynchronous clock arbitration module carries out asynchronous arbitration on the recombined data frame; the multi-channel balanced shunting module distributes the recombined data frames to each cross-chip channel in a pipeline mode, and then receives the recombined data frames of other FPGAs; the multi-channel flow convergence module converges data frames in a pipeline mode; and each packet recombination module de-recombines the converged data frames and distributes the data frames to the corresponding switching nodes. According to the invention, the data transmission efficiency and performance of the cross-chip channel can be effectively improved, and the efficient and balanced flow of data among different FPGAs is ensured, so that the stability and reliability of the whole communication network are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA data interaction, and in particular relates to a method for load balancing and accelerating multiple cross-chip channels of a lossless switch. Background Art

[0002] With the continuous advancement of communication technology, the role of switches in data exchange networks has become increasingly critical. They not only need to handle the growing data traffic, but also ensure the efficiency and stability of data transmission. By utilizing the internal resources of FPGA, switches have built an efficient crossbar architecture and input and output processing architecture, allowing data frames to be quickly exchanged between different ports. This architecture allows switches to maintain low latency and high throughput in high-speed data transmission, meeting the needs of modern communication networks.

[0003] However, with the explosive growth of user data traffic, traditional single-chip FPGA switches are beginning to be unable to cope with the situation, especially in scenarios where large-scale data exchange needs to be processed. The limited resources of a single FPGA cannot meet the growing demand for data exchange, which requires multiple FPGAs to work together to achieve larger-scale data exchange. This collaborative work requires real-time communication and large-scale data exchange between FPGAs to ensure data continuity and integrity.

[0004] In order to further improve cross-slice traffic, multiple cross-slice Aurora channels are used in cascade in the hope of achieving higher data transmission rates. However, due to the limitations of the crossbar architecture and the Aurora cross-slice channels themselves, there is often a lack of effective coordination mechanisms between these channels, resulting in some channels being overloaded while others are idle. This unbalanced load distribution not only reduces the overall data transmission efficiency, but can also cause network congestion and data delays, seriously affecting the performance of the communication network. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a method for load balancing and accelerating multiple cross-chip channels of a lossless switch. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] A method for load balancing and accelerating multiple cross-chip channels of a lossless switch is applied to each FPGA, wherein the FPGA includes a crossbar node traffic distribution module, an n-packet reassembly module, an asynchronous clock arbitration module, a multi-channel balancing and shunting module, a multi-channel traffic aggregation module, and a switching node. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch includes:

[0007] A crossbar node traffic distribution module distributes data frames to two switch nodes in each column of the switch nodes based on source ports, and sends the data frames of the two switch nodes to corresponding packet reassembly modules;

[0008] Each packet reassembly module reassembles the input data frame according to the predetermined byte interval to obtain two reassembled data frames, and sends them to the asynchronous clock arbitration module;

[0009] The asynchronous clock arbitration module performs asynchronous arbitration on the two reassembled data frames of each packet reassembly module to distinguish the reassembled data frames sent first and later to obtain an arbitration result; and sends the arbitration result to the multi-channel balancing and diversion module;

[0010] The multi-channel balanced distribution module evenly distributes all reassembled data frames to each cross-chip channel in a pipeline manner, and sends them to other FPGAs through the corresponding cross-chip channels; and receives the reassembled data frames sent by other FPGAs through the cross-chip channels;

[0011] The multi-channel traffic aggregation module selects data from the received reassembled data frames for aggregation using a pipeline mode, and then sends them to the corresponding packet reassembly module;

[0012] Each packet reassembly module decompresses and reassembles the aggregated data frames and distributes them to the corresponding switching nodes.

[0013] Beneficial effects:

[0014] 1. The present invention reorganizes data frames into a compromise length for cross-chip transmission, thereby solving the problem that too long data frames in the prior art consume too many FPGA resources, while too short data frames seriously affect the switching performance. The present invention takes into account both the cross-chip traffic rate and the use of FPGA resources, thereby improving the switching performance of the switch;

[0015] 2. The present invention provides a flow balancing solution that can ensure that the flow of n cross-chip channels is evenly distributed without causing frame disorder. At the same time, in order to improve the diversion speed of the channel balancing diversion module, the present invention adopts a channel balancing diversion module based on a pipeline architecture, so that multi-level channel arbitration can be carried out simultaneously, thereby improving the diversion speed. This solves the problem of switch traffic congestion caused by uneven flow sizes of multiple channels when the switch needs multiple cross-chip channels.

[0016] 3. The present invention is based on the traditional crossbar architecture, and adds an asynchronous clock arbitration module and a crossbar node traffic distribution module, which increases the upper limit of cross-chip traffic speed and further improves cross-chip efficiency.

[0017] 4. The present invention adds a lossless flow control module and uses NFC flow control frames to achieve lossless transmission of cross-chip traffic when multiple FPGAs are cascaded. This solves the problem that when traditional switches are cross-chip, the sending end is difficult to perceive the load situation of the receiving end and cannot dynamically adjust the data flow of the sending end, which is prone to data loss under high load conditions.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is an internal architecture diagram of the FPGA provided by an embodiment of the present invention;

[0020] Figure 2 is a simplified diagram of an internal module of an FPGA provided by an embodiment of the present invention;

[0021] Figure 3 It is a flow chart of a method for load balancing and accelerating multiple cross-chip channels of a lossless switch provided by an embodiment of the present invention;

[0022] Figure 4 It is a schematic diagram of crossbar node traffic distribution based on data frame destination port numbers provided by an embodiment of the present invention.

[0023] Figure 5 It is a schematic diagram of crossbar node traffic distribution based on data frame source port number provided by an embodiment of the present invention;

[0024] Figure 6 is a timing diagram of a packet reassembly module provided in an embodiment of the present invention;

[0025] Figure 7 It is an overall flow chart of cross-chip traffic aggregation and balanced distribution provided by an embodiment of the present invention;

[0026] Figure 8 It is a diagram of the architecture of a transmission channel balancing and splitting module provided in an embodiment of the present invention;

[0027] Fig. 9 is a channel flow arbitration flow chart of a sending channel provided by an embodiment of the present invention;

[0028] Fig.10 is a diagram of the architecture of a receiving channel equalization and shunting module provided in an embodiment of the present invention;

[0029] Fig.11 is a bus pipeline arbitration flow chart of a receiving channel provided by an embodiment of the present invention;

[0030] Fig.12 1 is a diagram of the architecture of a cross-chip channel lossless flow control module provided by an embodiment of the present invention;

[0031] Fig.13 This is a flow chart of cross-chip lossless flow control provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0033] The present invention proposes a method for load balancing and acceleration of multiple cross-chip channels of a lossless switch, which is used to achieve traffic load balancing and acceleration of multiple cross-chip channels of a lossless switch, aiming to solve the problems of channel traffic imbalance and low acceleration ratio encountered by traditional switches when processing cross-chip traffic. By optimizing key links such as data packet reassembly, asynchronous clock arbitration, and crossbar node traffic distribution, the present invention can effectively improve the data transmission efficiency and performance of cross-chip channels, ensure that data flows efficiently and evenly between different FPGAs, and thus improve the stability and reliability of the entire communication network.

[0034] The present invention provides a method for load balancing and accelerating multiple cross-chip channels of a lossless switch, which is applied to each FPGA and combined with Figure 1 and Figure 2 The FPGA includes a crossbar node traffic distribution module, an n-packet reassembly module, an asynchronous clock arbitration module, a multi-channel balanced shunting module, a multi-channel traffic aggregation module and a switching node. The switching node includes a common switching node and a cross-chip switching node. The number of columns of the cross-chip switching node is 4; the number of the packet reassembly module, the cross-chip channel and the FIFO is 4.

[0035] like Figure 3 As shown, the present invention provides a method for load balancing and accelerating multiple cross-chip channels of a lossless switch, including:

[0036] S100, a crossbar node traffic distribution module distributes data frames to two switch nodes in each column of the switch nodes based on source ports, and sends the data frames of the two switch nodes to corresponding packet reassembly modules;

[0037] refer to Figure 2 , a crossbar node traffic distribution module distributes data frames to the two cross-chip switching nodes in each column of the switching node based on the source port, and sends the data frames of the two cross-chip switching nodes to the corresponding packet reassembly module; wherein the cross-chip switching nodes are divided into 4 columns, and the source port-based method is that the number of cross-chip switching nodes to which the data frames are distributed in each column is the same.

[0038] It should be further explained that the present invention changes the traditional strategy of allocating cross-chip channels based on destination ports to allocating cross-chip channels based on source ports. The maximum processing efficiency of the latter is n times that of the former (n=the number of cross-chip channels).

[0039] If traffic is distributed by destination port, a column of crossbar nodes will have data packets, such as Figure 4 As shown, Figure 4 It is a strategy for allocating cross-chip channels based on the destination port. Assuming the arbitration module rate is 76 Gb / s, eight nodes are arbitrated, and the rate allocated to each node is 9.5 Gb / s.

[0040] refer to Figure 5 , Figure 5 This is a strategy for allocating cross-chip channels based on source ports. This strategy only requires arbitration between two nodes. When the arbitration rate is constant, the fewer nodes are arbitrated, the higher the rate allocated to each node. Assuming the arbitration module rate is 76Gb / s, and two nodes are arbitrated, the rate allocated to each node is 38Gb / s, which is 4 times that of the previous strategy.

[0041] S200, each packet reassembly module reassembles the input data frame according to the predetermined byte interval to obtain two reassembled data frames, and sends them to the asynchronous clock arbitration module;

[0042] Among them, each packet reassembly module reassembles the short data frame into a long data frame according to the 1518-3000 byte range, obtains 2 reassembled data frames, and sends them to the asynchronous clock arbitration module; among them, the short data frame is a data frame with less than 1518 bytes, and the long data frame is a data frame with more than 1518 bytes.

[0043] It should be further explained that, because the switch has a certain processing logic and clock frequency for data, when the traffic is large, the minimum interval between data packets is certain, from which the maximum processing rate of the switch data packet can be calculated, such as Figure 6 shown.

[0044] However, there is a minimum logical interval and a TAG header (a field used to store data frame information) between data packets. Assuming the frame length is M bytes, the theoretical maximum rate is P, and the minimum frame interval is 48*N bytes, where N is equal to 1 TAG header plus the minimum logical interval. Therefore, the relationship between the actual processing rate F and the byte length M is as follows:

[0045]

[0046] The following uses 1518-byte and 64-byte data frames as examples, assuming that the minimum frame interval N is TAG header + minimum logical processing interval = 1 + 5 = 6 beats (1 beat corresponds to 384 bits, i.e. 48 bytes). For a 200M clock and 384-bit processing module, the theoretical maximum data processing rate P is equal to 384bit*200M=76Gb / s.

[0047] For a data frame of M = 1518 bytes, substituting into the above formula, the theoretical maximum processing rate F is approximately equal to 64Gb / s

[0048] For a data frame of M = 64 bytes, substituting into the above formula, the theoretical maximum processing rate F is approximately equal to 19Gb / s

[0049] It can be concluded that the processing rate of short frames in the exchange process is much lower than that of long frames. Therefore, the present invention can combine short frames into long frames for cross-chip processing, which can greatly improve the cross-chip processing efficiency.

[0050] Considering that too long data frames will consume too much FPGA resources, and too short data frames will seriously affect the switching performance, according to the above formula, the present invention assembles the data packets into a more moderate length, that is, 1518-3000 bytes of data frames for cross-chip, while taking into account the cross-chip traffic rate and the use of FPGA resources. When the reassembled data frames enter the packet reassembly module of another chip, the module will unpack the spliced ​​data frames and distribute them to different end nodes according to the destination port number.

[0051] S300, the asynchronous clock arbitration module performs asynchronous arbitration on the two reassembled data frames of each packet reassembly module to distinguish the reassembled data frames sent first and later to obtain an arbitration result; and sends the arbitration result to the multi-channel balancing and diversion module;

[0052] Among them, the asynchronous clock arbitration module performs asynchronous arbitration on the two reorganized data frames of each packet reorganization module to distinguish the reorganized data frames sent first and later to obtain an arbitration result, and stores the reorganized data frames output by the arbitration module into the corresponding FIFO according to the arbitration result and sends the arbitration result to the multi-channel balancing and diversion module.

[0053] It should be further explained that for the synchronous arbitration module, the clock frequency used is the user clock 200M. The Crossbar arbitration module needs to take out data from the crossbar node and send the data to the channel balancing and diversion module. For a 10*10 crossbar switching architecture, the synchronous arbitration module needs to take out data from a column of crossbar nodes, that is, 10 nodes. Since arbitration uses fair polling, the highest processing speed obtained for each node is the highest processing rate of the arbitration module / 10, that is, P / 10=76 / 10=7.6Gb / s.

[0054] For the asynchronous arbitration module, the clock frequency used is the cross-chip clock 390M. In order to improve the processing rate of each node, the present invention can use an asynchronous clock arbitration module to change the clock frequency of the crossbar cross-chip switching node FIFO to 390M, while the data storage clock of the crossbar cross-chip switching node FIFO is still the user clock 200M. At this time, the maximum processing rate of the asynchronous clock arbitration module is Pˋ=390M*384=150Gb / s, and the average rate to each node is Pˋ / 10=15Gb / s, which improves the processing efficiency of cross-chip data.

[0055] S400, the multi-channel balancing and shunting module evenly distributes all reassembled data frames to each cross-chip channel in a pipeline manner, and sends them to other FPGAs through the corresponding cross-chip channels; and receives the reassembled data frames sent by other FPGAs through the cross-chip channels;

[0056] Among them, the channel balancing and diversion module includes 4 channel arbitration modules. When at least one of the 4 FIFOs has data; in the order of the first to the last FIFO with data, the 4 channel arbitration modules use a pipeline method to take data from the FIFO and evenly distribute it to the corresponding cross-chip channels.

[0057] The balancing principle of the channel balancing and distribution module is that when the FPGA is used as the transmitter, the traffic of a crossbar bus is evenly distributed to n cross-chip channels to achieve the purpose of load balancing. The receiver takes data frames from n cross-chip channels and converges them to the source crossbar bus of the data frame according to the source bus information in the TAG header field of the data frame.

[0058] The data frames from the asynchronous clock arbitration module enter the traffic aggregation module for aggregation. After the aggregation is completed, the data is sent to the channel balancing and distribution module. Through channel arbitration, the frames are sent to the four channels in sequence, that is, a frame is sent to channel 1 first, and then to channels 2, 3 and 4 in sequence, and then the cycle is repeated to achieve the purpose of balancing the data traffic of each cross-chip channel. Figure 7 shown.

[0059] In an optional implementation manner of the present invention, the four channel arbitration modules adopt a pipeline method to take data from the FIFOs and evenly distribute and send data to corresponding cross-chip channels in the order of the first to the last FIFOs with data, including:

[0060] In the order of 1 to 4, the 4 channel arbitration modules select their corresponding FIFO from the FIFO with data;

[0061] Each channel arbitration module takes data frames from the FIFO in a pipeline manner, and different channel arbitration modules start the same level of pipeline at different times.

[0062] The four channel arbitration modules of the present invention take data frames from FIFO in a pipeline manner, including: the first-level pipeline starts: the first-level pipeline takes out 1 frame of data from its corresponding FIFO and sends it to the first cross-chip channel; the second-level pipeline starts: according to different situations of whether the corresponding FIFO is empty, continues to take out a frame of data from the FIFO or sends an idle frame to the second cross-chip channel; the third-level pipeline starts: according to different situations of whether the corresponding FIFO is empty, continues to take out a frame of data from the FIFO or sends an idle frame to the third cross-chip channel; the fourth-level pipeline starts: according to different situations of whether the corresponding FIFO is empty, continues to take out a frame of data from the FIFO or sends an idle frame to the fourth cross-chip channel.

[0063] exist Figure 8 In the present invention, four FIFOs are instantiated for storing data from different buses. Channel 1 arbitration may use the FIFO of cross-chip buses 1 to 4. Therefore, in order to let the channel equalization module of the other receiving end know the source bus of the data for the correct diversion of the data frame, each FIFO needs to modify the TAG field of the data frame before storing the data to identify which bus the frame comes from. The field is 2 bits, 2'b00 represents bus 1, 2'b 01 represents bus 2, 2'b10 represents bus 3, and 2'b11 represents bus 4.

[0064] In order to improve the diversion speed of the module, a pipeline-based channel arbitration is adopted, that is, multi-level channel arbitration can be carried out simultaneously. Fig. 9 As shown:

[0065] When at least one of the four FIFOs has data, the pipeline arbitration module starts, that is: the first-level pipeline starts, and the channel 1 arbitration module arbitrates and fairly polls the first FIFO with data, takes out a frame, and sends it to cross-chip channel 1. After this level of pipeline ends, the second-level pipeline starts, and still takes out a frame from this FIFO and sends it to cross-chip channel 2. If the FIFO is empty at this time, an idle frame is sent to cross-chip channel 2. After this level of pipeline ends, the third-level pipeline starts, and still takes out a frame from this FIFO and sends it to cross-chip channel 3. If the FIFO is empty at this time, an idle frame is sent to cross-chip channel 3. After this level of pipeline ends, the fourth-level pipeline starts, and still takes out a frame from this FIFO and sends it to cross-chip channel 4. If the FIFO is empty at this time, an idle frame is sent to cross-chip channel 4. Because it uses a pipeline architecture, when a pipeline level is idle, it can be started immediately. During peak traffic, the pipeline architecture can meet the needs of four or N cross-chip channels to reach the full theoretical rate of 76Gb / s. Compared with the arbitration module of the non-pipeline architecture (each channel rate is 76 / N Gb / s, N is the number of cross-chip channels), it is N times higher.

[0066] If FPGA is used as the receiving end, the multi-channel balancing and distribution module is responsible for aggregating the received cross-chip traffic and sending it to the multi-channel traffic aggregation module.

[0067] S500, the multi-channel traffic aggregation module selects data from the received reassembled data frames for aggregation using a pipeline mode, and then sends the data to the corresponding packet reassembly module;

[0068] FPGA, as the receiving end, receives data frames from another FPGA across chips, aggregates them into the corresponding FIFO according to the cross-chip channel, and then distributes them to different cross-chip buses according to the source bus number of the data frame TAG header, such as Fig.10 shown.

[0069] In an optional implementation manner of the present invention, the multi-channel traffic convergence module is used to:

[0070] Start the first-level pipeline: determine the frame header of the first data frame of the first cross-chip channel from the received reorganized data frame, and extract the frame header information that is aggregated to the corresponding cross-chip bus from the frame header; aggregate the first data frame of the first cross-chip channel to the corresponding cross-chip bus according to the frame header information;

[0071] Start the second-level pipeline: according to the frame header information of the first-level pipeline, aggregate the first data frame of the second cross-chip channel to the corresponding cross-chip bus;

[0072] Start the third-level pipeline: according to the frame header information of the first-level pipeline, aggregate the first data frame of the third cross-chip channel to the corresponding cross-chip bus;

[0073] Start the fourth-level pipeline: according to the frame header information of the first-level pipeline, aggregate the first data frame of the fourth cross-chip channel to the corresponding cross-chip bus.

[0074] The receiving channel equalization module works as follows:

[0075] If all four FIFOs have data, determine the source bus number in the TAG of the data in the first FIFO, take out the frame and send it to the corresponding bus. Assuming that the bus is bus 1, start the first-level pipeline, take out the first frame of the cross-chip channel 1 data aggregation FIFO and send it to bus 1; after the first-level pipeline ends, start the second-level pipeline, and the second-level pipeline. Take out the first frame of the cross-chip channel 2 data aggregation FIFO and send it to bus 1; after the second-level pipeline ends, start the third-level pipeline, and the third-level pipeline. Take out the first frame of the cross-chip channel 3 data aggregation FIFO and send it to bus 1; after the third-level pipeline ends, start the fourth-level pipeline, and the fourth-level pipeline. Take out the first frame of the cross-chip channel 4 data aggregation FIFO and send it to bus 1. (Because a crossbar bus on the sending end will send a frame to each of the four cross-chip channels, the first frame of the four cross-chip channel data aggregation FIFOs on the receiving end must go to the same crossbar bus)

[0076] The difference between the sending channel and the receiving channel is that the sending channel performs pipeline arbitration based on the cross-chip channel, while the receiving channel performs pipeline arbitration based on the crossbar bus. Fig.11 shown.

[0077] The data frames from the four cross-chip channels enter the traffic aggregation module for aggregation. The traffic aggregation module aggregates the frames according to the crossbar bus. After the aggregation is completed, the channel arbitration module evenly distributes the transmitted data stream to n cross-chip channels. The traffic aggregation module aggregates the frames according to the crossbar channels. After the aggregation is completed, the bus arbitration module of the crossbar distributes the source bus number in the TAG header of the received data stream to the corresponding cross-chip bus.

[0078] S600, each packet reassembly module decombines the aggregated data frames and distributes them to the corresponding switching nodes.

[0079] In a specific implementation of the present invention, each cross-chip channel is provided with a flow control module, a FIFO waterline monitoring module and an NFC flow control frame group module; the FIFO waterline monitoring module monitors the flow of the data frames received by itself, and if it exceeds its own accommodation range, it feeds back to the NFC flow control frame group module; after receiving the feedback, the NFC flow control frame group module generates an NFC flow control frame, and feeds it back to the flow control module of the FPGA that sends the data frame; the flow control module of the FPGA that sends the data frame controls the flow of the data frame sent by itself.

[0080] The lossless flow control module is integrated into the cross-chip channel and uses the NFC flow control function to dynamically adjust the flow size of the sender to achieve the purpose of lossless flow control of data. Its architecture is as follows Fig.12 As shown, the lossless control process of two data frames is as follows Fig.13 As shown. When any FIFO of the traffic aggregation module at the receiving end reaches the waterline (depth 512, waterline value 317, 2 to 3 giant frame lengths are reserved), the FIFO waterline monitoring module of the receiving end aggregation module sends a framing signal to the NFC flow control frame framing module. The NFC flow control frame framing module groups a flow control start frame according to the flow control information given by the FIFO waterline monitoring module of the end aggregation module. The flow control start frame goes to the sending end of another FPGA through the cross-chip channel. The sending end suspends the traffic transmission of the congested cross-chip channel according to the information in the NFC flow control frame. When the FIFO that reaches the waterline at the receiving end drops below the waterline, the FIFO waterline monitoring module of the receiving end aggregation module sends a framing signal to the NFC flow control frame framing module. The NFC flow control frame framing module groups a flow control stop frame according to the flow control information given by the FIFO waterline monitoring module of the end aggregation module. The flow control stop frame goes to the sending end of another FPGA through the cross-chip channel. The sending end starts the traffic transmission of the corresponding cross-chip channel according to the information in the NFC flow control frame. Through the inter-chip lossless flow control module, the inter-chip cross-chip traffic load size is dynamically adjusted to achieve lossless transmission of multiple inter-chip channels.

[0081] The present invention provides a method for load balancing and acceleration of multiple cross-chip channels of a lossless switch, including: a crossbar node traffic distribution module distributes data to nodes based on a source port mode, each packet reassembly module reassembles data according to a predetermined byte interval; an asynchronous clock arbitration module performs asynchronous arbitration on reassembled data frames; a multi-channel balanced shunting module distributes reassembled data frames evenly to each cross-chip channel in a pipeline mode, and then receives reassembled data frames from other FPGAs; a multi-channel traffic aggregation module aggregates data frames using a pipeline mode; each packet reassembly module decomposition and re-allocates the aggregated data frames to the corresponding switching node. The present invention can effectively improve the data transmission efficiency and performance of cross-chip channels, ensure that data flows efficiently and evenly between different FPGAs, thereby improving the stability and reliability of the entire communication network.

[0082] See also Figure 1 In practical applications, the present invention adopts a 12*12 crossbar architecture, in which 8 rows and 8 columns are used for data frame exchange within the switch chip, and 4 rows and 4 columns are used for cross-chip traffic exchange, that is, 4 cross-chip channels are used, and the data flow crosses from FPGA1 to FPGA2.

[0083] See also Figure 2 When cross-chip traffic needs to enter the crossbar architecture, it will first enter the crossbar node traffic distribution module. This module distributes traffic based on the source port number to improve the arbitration speed of cross-chip bus traffic. For details, see Figure 6 When there is data in the crossbar cross-chip switching node, the asynchronous clock arbitration module will allow the node to output data, but at this time the data will not go directly to the asynchronous clock arbitration module, but first go to the packet reassembly module (each vertical column of cross-chip switching nodes corresponds to an asynchronous clock arbitration module). In the packet reassembly module, multiple shorter data packets will be reassembled into a compromise length (1518-3000 bytes), and the reassembled long frame will then enter the asynchronous clock arbitration module, and then go to the multi-channel balancing and diversion module.

[0084] The role of the packet reassembly module is to solve the problem that short frames seriously affect the cross-chip exchange rate during the cross-chip process. Figure 6 The function of the asynchronous clock arbitration module is to increase the processing rate of each node. The impact of the two on the cross-chip rate and the acceleration efficiency can be seen in Formula 1.

[0085] See also Figure 7 When the data flow from the asynchronous clock arbitration module enters the multi-channel balancing and distribution module, the module will evenly distribute the data flow of each bus to the four cross-chip channels to achieve the purpose of load balancing.

[0086] See also Figure 8, when the traffic enters the transmission channel balancing and diversion module, the traffic of each bus will be stored in the corresponding FIFO for cache. Assuming that the cross-chip bus 1 data aggregation FIFO has data at this time, the pipeline is started. At this time, the first-level pipeline, that is, channel 1 arbitration will arbitrate to the above FIFO, and the first frame will be taken out from this FIFO; after the first-level pipeline is completed, the second-level pipeline is started, that is, channel 2 arbitration will still arbitrate to the above FIFO, and the second frame will be taken out from this FIFO; after the second-level pipeline is completed, the third-level pipeline is started, that is, channel 3 arbitration will still arbitrate to the above FIFO, and the third frame will be taken out from this FIFO; after the third-level pipeline is completed, the fourth-level pipeline is started, that is, channel 4 arbitration will still arbitrate to the above FIFO, and the fourth frame will be taken out from this FIFO; different pipelines are independent of each other, and they can be started when the current pipeline is idle. The purpose of this is: traditional non-pipeline arbitration can only give the data in a certain FIFO to a certain cross-chip channel at the same time, and another frame of data in the FIFO can be given to another cross-chip channel only after the transmission is completed, that is, only one of the four channels can transmit data at the same time, which is extremely inefficient. Pipeline arbitration can enable four channels to transmit data simultaneously without causing frame disorder. For details on the pipeline process of the sending channel, see Figure 8 .

[0087] After the data frame comes out of the channel arbitration, it will enter the cross-chip channel and pass through the existing Aurora IP core to the cross-chip receiving channel of another FPGA.

[0088] See Fig.10 After the cross-chip channel receives the cross-chip data frame, it enters the traffic aggregation module for aggregation, and the data of each cross-chip channel is cached in the corresponding cross-chip channel data aggregation FIFO. When all four FIFOs have at least one frame, the bus arbitration module starts the pipeline. When the first-level pipeline is started, the source bus information in the TAG header field of the first frame of the cross-chip channel 1 data aggregation FIFO is judged. If it is a data frame heading to bus 1, a frame is taken out of the cross-chip channel 1 data aggregation FIFO and sent to bus 1. Then the second, third, and fourth-level pipelines are started, and a frame is taken out from the cross-chip channel 2, 3, and 4 data aggregation FIFOs and sent to bus 1 respectively.

[0089] See Fig.11 In order to improve the receiving efficiency, the receiving end also uses a pipeline architecture. When the four FIFOs have data, the TAG header of the first frame of the FIFO of channel 1 is used to determine the bus number to which the first frame of the FIFOs of channels 1-4 goes. That is, all four FIFOs have data to start the pipeline. The first-level pipeline starts from the first frame of the FIFO area of ​​channel 1, determines the destination bus number of the frame, and sends the frame to the bus. The second, third, and fourth-level pipelines take one frame from the FIFOs of channels 2, 3, and 4 respectively, and converge them to the bus.

[0090] See Fig.12 . When data frames are transmitted across slices, the sending end cannot sense whether the load of the receiving end exceeds the receiving capacity of the receiving end. If the receiving end is congested, the sending end still sends data frames, which will cause data frame loss. In order to perform lossless exchange across slices, the present invention adds a lossless flow control module, and uses the NFC flow control function to dynamically adjust the flow size of the sending end to achieve the purpose of data lossless flow control. The flow control principle is that the FIFO waterline monitoring module of the receiving end aggregation module will monitor the four FIFOs in the receiving end traffic aggregation module. When the receiving channel FIFO is about to be full, the NFC flow control frame framing module will be enabled to send a flow control start frame to the sending end, suspend the sending channel corresponding to the sending end, and stop the data frame transmission. When the FIFO is able to receive, the FIFO waterline monitoring module of the receiving end aggregation module will enable the NFC flow control frame framing module, send a flow control stop frame to the sending end, and open the sending channel corresponding to the sending end, so as to achieve the purpose of losslessness. See the detailed control flow. Fig.13 .

[0091] It is worth noting that the terms "first" and "second" in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0092] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components or steps.

[0093] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for load balancing and accelerating multiple cross-chip channels of a lossless switch, characterized in that: Applied to each FPGA, the FPGA includes a crossbar node traffic distribution module, an n-packet reassembly module, an asynchronous clock arbitration module, a multi-channel balancing and shunting module, a multi-channel traffic aggregation module and a switching node. The method for load balancing and acceleration of multiple cross-chip channels of a lossless switch includes: A crossbar node traffic distribution module distributes data frames to two switch nodes in each column of the switch nodes based on source ports, and sends the data frames of the two switch nodes to corresponding packet reassembly modules; Each packet reassembly module reassembles the input data frame according to the predetermined byte interval to obtain two reassembled data frames, and sends them to the asynchronous clock arbitration module; The asynchronous clock arbitration module performs asynchronous arbitration on the two reassembled data frames of each packet reassembly module to distinguish the reassembled data frames sent first and later to obtain an arbitration result; and sends the arbitration result to the multi-channel balancing and diversion module; The multi-channel balanced distribution module evenly distributes all reassembled data frames to each cross-chip channel in a pipeline manner, and sends them to other FPGAs through the corresponding cross-chip channels; and receives the reassembled data frames sent by other FPGAs through the cross-chip channels; The multi-channel traffic aggregation module selects data from the received reassembled data frames for aggregation using a pipeline mode, and then sends them to the corresponding packet reassembly module; Each packet reassembly module decompresses and reassembles the aggregated data frames and distributes them to the corresponding switching nodes.

2. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 1, characterized in that: The switching nodes include common switching nodes and cross-chip switching nodes; The crossbar node traffic distribution module distributes data frames to the two cross-chip switching nodes in each column of the switching nodes based on the source port, and sends the data frames of the two cross-chip switching nodes to the corresponding packet reassembly module; wherein the cross-chip switching nodes are divided into 4 columns, and the number of cross-chip switching nodes to which the data frames are distributed in each column based on the source port is the same.

3. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 1, characterized in that: Each packet reassembly module reassembles the short data frames into long data frames according to the 1518-3000 byte range, obtains two reassembled data frames, and sends them to the asynchronous clock arbitration module; among which, the short data frame is a data frame with less than 1518 bytes, and the long data frame is a data frame with more than 1518 bytes.

4. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 1, characterized in that: The asynchronous clock arbitration module performs asynchronous arbitration on the two reassembled data frames of each packet reassembly module to distinguish the reassembled data frames sent first and later to obtain an arbitration result, and stores the reassembled data frames output by the arbitration module into the corresponding FIFO according to the arbitration result and sends the arbitration result to the multi-channel balancing and diversion module.

5. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 4, characterized in that: The number of columns of the cross-chip switching node is 4; the number of the packet reassembly module, the cross-chip channel and the FIFO is 4.

6. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 5, characterized in that: The channel balancing and diversion module includes four channel arbitration modules. When at least one of the four FIFOs has data, the four channel arbitration modules take data from the FIFOs in a pipeline manner and evenly distribute and send them to corresponding cross-chip channels in the order of the first to the last FIFO with data.

7. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 6, characterized in that: The four channel arbitration modules adopt a pipeline method to take data from the FIFOs and evenly distribute and send data to the corresponding cross-chip channels in the order of the first to the last FIFO with data, including: In the order of 1 to 4, the 4 channel arbitration modules select their corresponding FIFO from the FIFO with data; Each channel arbitration module takes data frames from the FIFO in a pipeline manner, and different channel arbitration modules start the same level of pipeline at different times.

8. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 6, characterized in that: The pipeline method of taking data frames from FIFO includes: The first stage pipeline starts: The first stage pipeline takes out one frame of data from its corresponding FIFO and sends it to the first cross-chip channel; The second-stage pipeline starts: depending on whether the corresponding FIFO is empty, it continues to take out a frame of data from the FIFO or sends an idle frame to the second cross-chip channel; The third-level pipeline starts: depending on whether the corresponding FIFO is empty, it continues to take out a frame of data from the FIFO or sends an idle frame to the third cross-chip channel; The fourth-level pipeline starts: depending on whether the corresponding FIFO is empty, it continues to take out a frame of data from the FIFO or sends an idle frame to the fourth cross-chip channel.

9. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 4, characterized in that: Each cross-chip channel is equipped with a flow control module, a FIFO waterline monitoring module and an NFC flow control frame group module; The FIFO waterline monitoring module monitors the flow of data frames received by itself, and if it exceeds its own accommodation range, it feeds back to the NFC flow control frame group module; After receiving the feedback, the NFC flow control frame group module generates an NFC flow control frame and feeds it back to the flow control module of the FPGA that sends the data frame; The flow control module of the FPGA that sends the data frames controls the flow of the data frames sent by itself.

10. The method for load balancing and accelerating multiple cross-chip channels of a lossless switch according to claim 4, characterized in that: The multi-channel traffic convergence module is used to: Start the first-level pipeline: determine the frame header of the first data frame of the first cross-chip channel from the received reorganized data frame, and extract the frame header information from the frame header to the corresponding cross-chip bus; According to the frame header information, the first data frame of the first cross-chip channel is aggregated to the corresponding cross-chip bus; Start the second-level pipeline: according to the frame header information of the first-level pipeline, aggregate the first data frame of the second cross-chip channel to the corresponding cross-chip bus; Start the third-level pipeline: according to the frame header information of the first-level pipeline, aggregate the first data frame of the third cross-chip channel to the corresponding cross-chip bus; Start the fourth-level pipeline: according to the frame header information of the first-level pipeline, aggregate the first data frame of the fourth cross-chip channel to the corresponding cross-chip bus.

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