Memory, manufacturing method thereof, read-write method and electronic equipment

Abstract

The invention provides a memory, a manufacturing method thereof, a read-write method and electronic equipment. The memory comprises a substrate and a memory unit, wherein the memory unit comprises a read transistor and a write transistor which are sequentially arranged along a direction far away from the substrate; the reading transistor comprises a first grid electrode, a first channel surrounding the side wall of the first grid electrode, and a first source / drain electrode and a second source / drain electrode which are respectively connected with the first channel; the write transistor comprises a second channel, a second grid electrode surrounding the side wall of the second channel, and a third source / drain electrode and a fourth source / drain electrode which are respectively connected with the second channel; wherein the first gate of the read transistor is connected with the third source / drain of the write transistor. According to the device architecture, electric leakage of the write transistor can be reduced, the retention time is prolonged, and the reading rate of the read transistor is increased.

Description

Technical Field

[0001] The present application relates to but is not limited to semiconductor technology, and in particular to a memory and a manufacturing method thereof, a reading and writing method, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] In one aspect, an exemplary embodiment of the present application provides a memory including a substrate and a memory cell, the memory cell including a read transistor and a write transistor sequentially arranged in a direction away from the substrate;

[0006] The read transistor includes a first gate, a first channel surrounding a sidewall of the first gate, and a first source / drain and a second source / drain respectively connected to the first channel;

[0007] The write transistor includes a second channel, a second gate surrounding a sidewall of the second channel, and a third source / drain and a fourth source / drain respectively connected to the second channel;

[0008] The first gate of the read transistor is connected to the third source / drain of the write transistor.

[0009] In an exemplary embodiment, the first source / drain and the second source / drain surround a sidewall of the first gate, and the first source / drain, the first channel, and the second source / drain are sequentially arranged in a direction away from the substrate.

[0010] In an exemplary embodiment, the second channel is hollow cylindrical and extends in a direction away from the substrate, and the third source / drain and the fourth source / drain are sequentially arranged in the direction away from the substrate.

[0011] In an exemplary embodiment, the first gate and the third source / drain are an integrated structure.

[0012] In an exemplary embodiment, the third source / drain includes a first portion located inside the hollow cylinder of the second channel and a second portion located outside the hollow cylinder of the second channel, and both the first portion and the second portion are in contact with the second channel.

[0013] In an exemplary embodiment, the read transistor further includes a first gate insulating layer surrounding a sidewall of the first gate and located between the first gate and the first source / drain, the first channel, and the second source / drain sequentially arranged in a direction away from the substrate.

[0014] In an exemplary embodiment, the write transistor further includes a second gate insulating layer surrounding a sidewall of the second channel and between the second channel and the second gate.

[0015] In an exemplary embodiment, a size of the second channel and the second gate insulating layer in a direction perpendicular to the substrate is greater than or equal to a size of the second gate in a direction perpendicular to the substrate.

[0016] In an exemplary embodiment, the first channel includes N-type or P-type doped single crystal silicon; and the second channel includes an oxide semiconductor material.

[0017] In an exemplary embodiment, the first source / drain and the second source / drain each include N-type doped single crystalline silicon, and the first channel includes P-type doped single crystalline silicon.

[0018] In an exemplary embodiment, the second channel includes indium gallium zinc oxide, and the third source / drain and the fourth source / drain include metal.

[0019] In an exemplary embodiment, it also includes a first through-hole structure, a second through-hole structure and a third through-hole structure, the first gate insulating layer and the first gate are located in the first through-hole structure; the second gate is located in the second through-hole structure; the third through-hole structure is located in the second gate, and the second gate insulating layer and the second channel are located in the third through-hole structure.

[0020] In an exemplary embodiment, the storage unit also includes a capacitor, a first electrode of the capacitor is the first gate of the read transistor, a dielectric layer of the capacitor is part of the first gate insulating layer, and a second electrode of the capacitor is arranged on a side of the first gate insulating layer away from the write transistor.

[0021] In an exemplary embodiment, the second gate of the write transistor is also the back gate of the read transistor, and the opening and closing of the corresponding read transistor is controlled by controlling the voltage of the second gate of the write transistor.

[0022] In an exemplary embodiment, the first source / drain of the read transistor is connected to a read bit line, and the second source / drain is connected to a read word line, or the first source / drain of the read transistor is connected to a read word line, and the second source / drain is connected to a read bit line; the second gate of the write transistor is connected to a write word line, and the fourth source / drain is connected to a write bit line.

[0023] On the other hand, an exemplary embodiment of the present application provides a method for reading and writing the above-mentioned memory, comprising:

[0024] When the memory is written, a start voltage is applied to the write word line, the write transistor is turned on, and the storage information is sequentially written into the storage node SN through the write bit line and the write transistor;

[0025] When the memory is read, a negative voltage is applied to the write word line of the memory cell that is not read, thereby increasing the threshold voltage of the read transistor, and then the voltage of the read word line and the read bit line is adjusted higher relative to their respective original voltages, so that the memory cell cannot be read;

[0026] The voltage of the write word line of the memory cell to be read is kept unchanged so that the threshold voltage of the read transistor remains unchanged, the read word line is adjusted higher relative to its original voltage and the read bit line is adjusted lower relative to its original voltage, or the read bit line is adjusted higher relative to its original voltage and the read word line is adjusted lower relative to its original voltage, so that a voltage difference is generated between the read word line and the read bit line, and the selected memory cell is read.

[0027] In another aspect, an exemplary embodiment of the present application provides a method for manufacturing a memory, comprising the following steps:

[0028] forming a first source / drain material layer, a first channel material layer, and a second source / drain material layer of a read transistor having different positions in a direction away from the substrate;

[0029] forming a first through-hole structure penetrating the first source / drain material layer, the first channel material layer, and the second source / drain material layer;

[0030] forming a first gate of the read transistor within the first via structure;

[0031] forming a third source / drain of a write transistor, so that the third source / drain material layer of the write transistor is connected to the first gate of the read transistor;

[0032] forming a second through-hole structure;

[0033] forming a second gate in the second through-hole structure;

[0034] forming a third through-hole structure in the second gate;

[0035] forming a second channel of the write transistor in the third via structure; and

[0036] A fourth source / drain of the write transistor is formed.

[0037] In an exemplary embodiment, forming the first gate of the read transistor includes:

[0038] depositing an insulating layer on the first source / drain material layer;

[0039] forming a through hole in the insulating layer, filling the through hole with silicon and doping to form the first channel;

[0040] forming a first drain on the first channel;

[0041] forming a first through-hole structure;

[0042] A dielectric layer film and a conductive film are deposited in the first through-hole structure to form a first gate insulating layer and a first gate.

[0043] In an exemplary embodiment, the step of forming the third source / drain of the write transistor further includes making the third source / drain of the write transistor and the first gate of the read transistor an integrated structure.

[0044] On the other hand, an exemplary embodiment of the present application provides an electronic device including the above-mentioned memory.

[0045] In an exemplary embodiment, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.

[0046] The channel layer of the write transistor of the present application adopts IGZO wide tight band semiconductor material, which can reduce the leakage of the write transistor and increase the retention time; and IGZO is a low temperature process, compatible with the back end of line (BEOL) process, and does not affect silicon devices.

[0047] The channel layer of the read transistor of the present application is made of doped silicon, which has high silicon mobility, fast reading speed, and is compatible with peripheral processes. When making the silicon read transistor, the peripheral circuit can be manufactured at the same time.

[0048] The two transistors of the present application can adopt a three-dimensional vertical structure to save area.

[0049] The semiconductor device of the present application can uniquely select the data to be read, thereby suppressing the inevitable current sharing problem in the 2T0C device.

[0050] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0052] Figure 1A A three-dimensional schematic diagram of a memory provided for an exemplary embodiment of the present application;

[0053] Figure 1B For along Figure 1A A schematic diagram of a vertical section taken along section line AA';

[0054] Figure 1C A vertical cross-sectional schematic diagram of another memory provided for an exemplary embodiment of the present application, taken along a plane perpendicular to a substrate;

[0055] Figure 2 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, taken along a plane perpendicular to a substrate;

[0056] Figure 3 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, taken along a plane perpendicular to a substrate;

[0057] Figure 4 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, taken along a plane perpendicular to a substrate;

[0058] Figure 5 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided for an exemplary embodiment of the present application, taken along a plane perpendicular to a substrate; and

[0059] Figure 6 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, the intermediate product being cut along a plane perpendicular to a substrate. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0061] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present application. Therefore, the present application should not be interpreted as being limited to the contents recorded in the following embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0062] The proportions of the drawings in this application can be used as a reference in the actual process, but are not limited to this. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic diagrams of the structure, and one embodiment of this application is not limited to the shapes or values ​​shown in the drawings.

[0063] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the situation.

[0064] In this specification, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0065] In the description of the present application, ordinal numbers such as "first" and "second" are provided to avoid confusion among constituent elements rather than to limit the quantity.

[0066] In this specification, "film" and "layer" may be interchanged. For example, "metal layer" may be replaced with "metal film" in some cases.

[0067] In the description of this application, a transistor refers to a component including at least three terminals: a gate, a drain, and a source. The transistor has a channel layer between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel layer, and the source. In this application, the channel layer refers to the area where the current mainly flows. In this application, the terms "metal oxide semiconductor channel", "channel layer", and "semiconductor layer" are interchangeable.

[0068] The development of integrated circuit technology requires continuous upgrading. Traditional capacitive 1T1C DRAM has problems such as limited storage capacitor capacity and increased transistor off-state current.

[0069] Therefore, an exemplary embodiment of the present application provides a memory, including a substrate and a memory cell, the memory cell including a read transistor and a write transistor arranged in sequence along a direction away from the substrate; the read transistor includes a first gate, a first channel surrounding the sidewall of the first gate, and a first source / drain and a second source / drain respectively connected to the first channel; the write transistor includes a second channel, a second gate surrounding the sidewall of the second channel, and a third source / drain and a fourth source / drain respectively connected to the second channel; wherein the first gate of the read transistor is connected to the third source / drain of the write transistor.

[0070] In an exemplary embodiment, the second channel is hollow cylindrical and extends in a direction away from the substrate, and the third source / drain and the fourth source / drain are sequentially arranged in the direction away from the substrate.

[0071] In an exemplary embodiment, the first channel includes N-type or P-type doped single crystal silicon; and the second channel includes an oxide semiconductor material.

[0072] As used in this application, the term "an integrated structure" may refer to the fact that there is no obvious boundary interface such as a fault or gap between A and B in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B are formed into a film layer using the same material and are simultaneously formed into a structure having a connection relationship through the same patterning process.

[0073] Figure 1A A three-dimensional schematic diagram of a memory provided for an exemplary embodiment of the present application; Figure 1B For along Figure 1A A schematic diagram of a vertical section taken along the section line AA' in FIG. Figure 1A and Figure 1BAs shown, a memory cell may include a substrate 1 and a memory cell, wherein the memory cell includes a read transistor 100 and a write transistor 200 sequentially arranged in a direction away from the substrate. The read transistor 100 may include a first gate 150, a first channel 120 surrounding the sidewall of the first gate 150, and a first source / drain 110 and a second source / drain 130 respectively connected to the first channel 120. The write transistor 200 may include a second channel 220, a second gate 250 surrounding the sidewall of the second channel 220, and a third source / drain 210 and a fourth source / drain 230 respectively connected to the second channel 220.

[0074] The read transistor 100 may further include a first gate insulating layer 140 surrounding a sidewall of the first gate 150 and located between the first gate 150 and the vertically stacked first source / drain 110, the first channel 120, and the second source / drain 130. The write transistor 200 may further include a second gate insulating layer 240 surrounding a sidewall of the second channel 220 and located between the second channel 220 and the second gate 250.

[0075] In the present application, surrounding can be understood as partially or completely surrounding the first gate 150 or the second channel 220. In some embodiments, surrounding can be completely surrounding as a whole, and the cross-section of the channel after surrounding can be a closed ring, and the ring shape is adapted to the outer contour shape of the cross-section of the first gate 150 or the second channel 220. Exemplarily, the cross-section of the first gate 150 or the second channel 220 is, for example, a circular, rectangular, elliptical, or other structure. The interception direction of the cross section is intercepted along a direction parallel to the substrate 1. In an exemplary embodiment, surrounding can be partially surrounding, and the cross-section after surrounding is not closed, such as a ring with an opening.

[0076] like Figure 1B As shown, the first gate 150 of the read transistor 100 may be connected to the third source / drain 210 of the write transistor 200, or the first gate 150 may be an integrated structure with the third source / drain 210. Therefore, the present application obtains a capacitor-free memory, such as a 2T0C DRAM memory, by interconnecting the gate of the read transistor with the source or drain of the write transistor.

[0077] refer to Figure 1B The third source / drain 210 may include a first portion 211 located inside the hollow tube of the second channel 220 and a second portion 212 located outside the hollow tube of the second channel, and both the first portion 211 and the second portion 212 are in contact with the second channel 220 .

[0078] Continue to refer Figure 1A and Figure 1B The first channel 120 surrounds the sidewall of the first gate 150 and is located between the first source / drain 110 and the second source / drain 130. The second channel 220 is surrounded by the second gate 250, and the end of the second channel 220 close to the substrate 1 contacts the third source / drain 210, while the end away from the substrate 1 contacts the fourth source / drain 230.

[0079] Although the first source / drain and the second source / drain and the third source / drain and the fourth source / drain references are used herein to indicate two separate and different source / drains, it is not intended that the source / drain referred to as the "first" source / drain, or the "second" source / drain and the "third" source / drain and the "fourth" source / drain have a unique meaning.

[0080] In an exemplary embodiment, the first source / drain and the second source / drain are independent of each other. In an exemplary embodiment, one of the first source / drain and the second source / drain is a source of a transistor, and the other is a drain of the transistor. Similarly, the third source / drain and the fourth source / drain are independent of each other, and one of the third source / drain and the fourth source / drain is a source of a transistor, and the other is a drain of the transistor.

[0081] In an exemplary embodiment, the first source / drain 110 and the second source / drain 130 may both include N-type doped single crystal silicon or polycrystalline silicon, and the annular first channel 120 may include P-type doped single crystal silicon or polycrystalline silicon. Compared with a junctionless device, the read transistor of the present application may adopt an NPN or PNP inversion mode, which can increase the on-state current I on .

[0082] Therefore, the read transistor of the present application can be a ring channel structure, which has a simpler manufacturing process than the ring gate structure; in addition, compared with the device using oxide channel materials such as IGZO, the ring channel of the read transistor of the present application is made of single crystal silicon or polycrystalline silicon, has a fast response speed, and can increase the on-state current I on , improve reading speed.

[0083] Continue to refer Figure 1B The read transistor 100 may include a first through-hole structure K1, and the first gate insulating layer 140 and the first gate 150 are located in the first through-hole structure K1. The write transistor 200 may include a second through-hole structure K2 and a third through-hole structure K3, and the second gate 250 is located in the second through-hole structure K2; the third through-hole structure K3 is located in the second gate 250, and the second gate insulating layer 240 and the second channel 220 are located in the third through-hole structure K3.

[0084] In an exemplary embodiment, the dimensions of the second channel 220 and the second gate insulating layer 240 in the vertical direction are greater than the dimension of the second gate 250 in the vertical direction.

[0085] like Figure 1A As shown, the first source / drain 110 of the read transistor can be connected to the read bit line 160, the second source / drain 130 can be connected to the read word line 170, or the second source / drain 130 of the read transistor is connected to the read bit line 160, the first source / drain 110 can be connected to the read word line 170; the second gate 250 of the write transistor can be connected to the write word line 270, and the fourth source / drain 230 can be connected to the write bit line 260.

[0086] In the exemplary embodiment of the present application, there is only one insulating layer (not shown in the figure) between the second gate 250 of the write transistor and the first channel 120 of the read transistor, so the second gate 250 of the write transistor also serves as the back gate of the read transistor. The second gate 250 can form a capacitor with the storage node SN to affect the offset of the threshold of the read transistor, and then the voltage of the second gate 250 of the write transistor can be controlled to control the reading of the corresponding read transistor, thereby suppressing the current sharing problem of the 2T0C device.

[0087] In an exemplary embodiment, the second channel 220 of the write transistor 200 may include an oxide semiconductor material, such as indium gallium zinc oxide (IGZO).

[0088] When the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thereby ensuring the low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, which can be adjusted according to actual conditions.

[0089] IGZO has a large bandgap width Eg and low leakage current, generally in e -20The IGZO process is low-temperature, compatible with BEOL, and does not affect transistor devices made of silicon. In addition, the second gate of the write transistor is a ring-gate structure, which has strong gate control and low leakage.

[0090] like Figure 1C As shown, the memory of the present application may further include a first capacitor 300. The first capacitor 300 may include a first electrode 310, a dielectric layer 320, and a second electrode 330. The first electrode 310 may be electrically connected to the storage node SN, and the first gate insulating layer of the read transistor may function as the dielectric layer 320.

[0091] At this time, the first gate 150 (also serving as the first electrode 310 of the first capacitor 300) is closer to the substrate than the first source / drain 110 in a direction perpendicular to the substrate to prevent the second electrode 330 from being short-circuited with the first source / drain 110; the second electrode 330 is disposed in the substrate; by disposing the first capacitor 300, the voltage holding capability of the storage node SN can be enhanced. In some exemplary embodiments, see Figure 1B The memory may further include a second capacitor and a third capacitor, wherein the first electrode of the second capacitor is the first gate 150, and the second electrode of the second capacitor is the first source / drain 110; the first electrode of the third capacitor is the first gate 150, and the second electrode of the third capacitor is the second source / drain 130; that is, the second capacitor and the third capacitor share the first gate 150 as their first electrodes respectively. By providing the second and third capacitors, the voltage holding capability of the storage node SN may also be enhanced.

[0092] In some exemplary embodiments, the present application further provides a method for reading a memory, comprising:

[0093] When the memory is written, a start voltage is applied to the write word line, the write transistor is turned on, and the storage information is sequentially written into the storage node SN through the write bit line and the write transistor;

[0094] When the memory is read, a negative voltage is applied to the write word line of the memory cell that is not read, thereby increasing the threshold voltage of the read transistor, and then the voltage of the read word line and the read bit line is adjusted higher relative to their respective original voltages, and the memory cell cannot be read (there is no voltage difference between the two, no current flows, and no current leakage occurs);

[0095] The voltage of the write word line of the memory cell to be read is kept unchanged so that the threshold voltage of the read transistor remains unchanged, the read word line is adjusted higher relative to its original voltage, the read bit line is adjusted lower relative to its original voltage, or the read bit line is adjusted higher relative to its original voltage and the read word line is adjusted lower relative to its original voltage, so that a voltage difference is generated between the read word line and the read bit line (there is a voltage difference between the two, so that current flows), and the selected memory cell is read.

[0096] By adopting such a reading operation method, the present application can uniquely select the data to be read, thereby suppressing the problem of current sharing.

[0097] The technical solution of the present application is further explained below through the manufacturing process of the memory of the exemplary embodiment of the present application. The "patterning process" mentioned in the exemplary embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in the relevant technology. The "photolithography process" mentioned in the exemplary embodiment includes coating of film layers, mask exposure and development, which are mature manufacturing processes in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of the exemplary embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0098] In an exemplary embodiment, a DRAM memory is taken as an example to describe the method for manufacturing the memory of the present application.

[0099] In an exemplary embodiment, a method for manufacturing a memory may include the following steps:

[0100] S100: forming a source / drain material layer and a channel material layer of a read transistor.

[0101] Exemplary steps may include: depositing an insulating material film on the substrate 1 to form a first insulating layer 10; depositing a Si layer on the first insulating layer 10 and performing N-type doping to form a first source / drain material layer (read word line RWL) 110' of the read transistor 100; then depositing an insulating material film on the first source / drain material layer 110' to form a second insulating layer 20; forming a through hole penetrating the second insulating layer 20 in the middle of the second insulating layer 20 by etching; filling Si into the through hole and performing P-type doping to form a first channel material layer 120'; depositing a Si layer on the first channel material layer 120' and performing N-type doping to form a second source / drain material layer (read bit line RBL) 130' of the read transistor 100, as shown in FIG. Figure 2 shown. Figure 2 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, the intermediate product being cut along a plane perpendicular to a substrate.

[0102] In an exemplary embodiment, each insulating layer film may be deposited by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition (ALD), or the like.

[0103] In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of any one or more non-conductive materials selected from silicon oxide, silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN). In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of an oxide insulating material, such as silicon dioxide (e.g., SiO2), which is convenient for large-area deposition.

[0104] In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of the same or different insulating materials.

[0105] In an exemplary embodiment, the doping concentration of the first source / drain material layer 110' and the second source / drain material layer 130' is different from the doping concentration of the first channel material layer 120'. In other exemplary embodiments, the first channel material layer 120' may also be N-type doped, that is, the doping type of the first source material layer 110', the first channel material layer 120' and the second source / drain material layer 130' is the same.

[0106] In an exemplary embodiment, silicide may be formed on the first source / drain material layer 110 ′ and the second source / drain material layer 130 ′ to serve as connection wires.

[0107] S200: forming a first gate material layer of a read transistor.

[0108] Exemplary steps may include: forming a first through-hole structure K1 in the structure formed in the aforementioned step by etching, the first through-hole structure K1 passing through the second source / drain material layer 130', the first channel material layer 120' and the first source / drain material layer 110', and terminating at a side of the first source / drain material layer 110' away from the first channel material layer 120'; depositing a dielectric layer film and a conductive film in the first through-hole structure K1 to form a first gate insulating material layer 140' covering the sidewall and bottom of the first through-hole structure K1 and a first gate material layer 150' (i.e., a storage node SN of the read transistor) covering the first gate insulating material layer 140'; then removing excess film layers by photolithography and etching, i.e., forming a read transistor 100 having a ring channel structure, such as Figure 3 shown. Figure 3 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, the intermediate product being cut along a plane perpendicular to a substrate.

[0109] In an exemplary embodiment, the first gate insulating material layer 140' may be a dielectric layer with a high dielectric constant, i.e., a dielectric layer with K≥3.9. The dielectric layer with a high dielectric constant may be used as a gate oxide. The first gate insulating material layer 140' may be any one or more of silicon dioxide (SiO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

[0110] In an exemplary embodiment, the first gate material layer 150 ′ may be made of P-type amorphous silicon, metal tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride.

[0111] In an exemplary embodiment, each thin film layer may be deposited using an atomic layer deposition method.

[0112] In an exemplary embodiment, the orthographic projection of the first through-hole structure K1 on a plane parallel to the substrate may be in a square, rectangle, circle, ellipse or the like.

[0113] S300: forming a second gate material layer of a write transistor.

[0114] Exemplary steps may include: depositing an insulating material film on the structure formed in the previous steps to form a third insulating layer 30; forming a groove T in the third insulating layer 30 by etching, and depositing a metal material film in the groove T to form a third source / drain material layer 210' of the write transistor; continuing to deposit a fourth insulating layer 40 on the third insulating layer 30; forming a second through-hole structure K2 in the fourth insulating layer 40 by etching, the orthographic projection of the second through-hole structure K2 on the substrate 1 being larger than the orthographic projection of the groove T on the substrate 1; depositing a metal material film in the second through-hole structure K2 to form a second gate material layer (write word line) 250' of the write transistor, such as Figure 4 shown. Figure 4 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, the intermediate product being cut along a plane perpendicular to a substrate.

[0115] In an exemplary embodiment, the second gate material layer 250 ′ may be made of P-type amorphous silicon, metal tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride.

[0116] S400: forming a second channel material layer of a write transistor.

[0117] Exemplary steps may include: forming a third through-hole structure K3 in the second gate material layer 250' by etching; depositing a high dielectric constant material film on the bottom and sidewalls of the third through-hole structure K3 by an ALD process and etching away the high dielectric constant material film at the bottom of the third through-hole structure K3, thereby forming a second gate insulating material layer 240'; then depositing a semiconductor material film on the sidewalls of the second gate insulating material layer 240' by an ALD process to form a second channel material layer 220', such as Figure 5 shown. Figure 5 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, the intermediate product being cut along a plane perpendicular to a substrate.

[0118] In an exemplary embodiment, the second channel material layer 220' may be made of a metal oxide semiconductor material. In an exemplary embodiment, the metal oxide semiconductor material may be an amorphous or polycrystalline metal oxide semiconductor material, and the metal oxide semiconductor material has a slow corrosion rate in a weakly acidic or weakly alkaline solution. In an exemplary embodiment, the metal oxide semiconductor material may be an oxide of In, an oxide of Ga, an oxide of Zn, an oxide of Sn, etc. These metal oxide materials such as indium gallium zinc oxide (IGZO) may be used as channel materials.

[0119] S500: forming a fourth source / drain material layer of the write transistor.

[0120] The specific steps may include: continuing to fill the third through-hole structure K3 with an insulating layer, and making the upper surface of the structure flush by a chemical mechanical polishing (CMP) process; continuing to deposit a fifth insulating layer 50 on the fourth insulating layer 40; forming a fourth through-hole structure K4 in the fifth insulating layer 50 by etching; filling the fourth through-hole structure K4 with metal to form a fourth source / drain material layer 230', thereby forming a write transistor 200, such as Figure 6 shown. Figure 6 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, the intermediate product being cut along a plane perpendicular to a substrate.

[0121] In an exemplary embodiment, the orthographic projections of the second through hole structure K2 , the third through hole structure K3 , the fourth through hole structure K4 and the groove T on a plane parallel to the substrate may be in the shape of a square, a rectangle, a circle, an ellipse or the like.

[0122] The exemplary embodiment of the present application also provides a method for manufacturing a memory, comprising the following steps:

[0123] forming a first source / drain material layer, a first channel material layer, and a second source / drain material layer of a read transistor having different positions in a direction away from the substrate;

[0124] forming a first through-hole structure penetrating the first source / drain material layer, the first channel material layer, and the second source / drain material layer;

[0125] forming a first gate of the read transistor within the first via structure;

[0126] forming a third source / drain of a write transistor, so that the third source / drain material layer of the write transistor is connected to the first gate of the read transistor;

[0127] forming a second through-hole structure;

[0128] forming a second gate in the second through-hole structure;

[0129] forming a third through-hole structure in the second gate;

[0130] forming a second channel of the write transistor in the third via structure; and

[0131] A fourth source / drain of the write transistor is formed.

[0132] In an exemplary embodiment, forming the first gate of the read transistor includes:

[0133] forming a first source / drain;

[0134] depositing an insulating layer on the first source / drain material layer;

[0135] forming a through hole in the insulating layer, filling the through hole with silicon and doping to form the first channel;

[0136] forming a second source / drain on the first channel;

[0137] forming a first through-hole structure;

[0138] A dielectric layer film and a conductive film are deposited in the first through-hole structure to form a first gate insulating layer and a first gate.

[0139] In an exemplary embodiment, the step of forming the third source / drain of the write transistor further includes making the third source / drain of the write transistor and the first gate of the read transistor an integrated structure.

[0140] An exemplary embodiment of the present application further provides an electronic device, comprising the memory provided by the exemplary embodiment of the present application as above.

[0141] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, etc.

[0142] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A memory, characterized in that: A method for manufacturing a semiconductor device comprising a substrate and a memory cell, wherein the memory cell comprises a read transistor and a write transistor arranged in sequence in a direction away from the substrate; The read transistor includes a first gate, a first channel surrounding a sidewall of the first gate, and a first source / drain and a second source / drain respectively connected to the first channel; The write transistor includes a second channel, a second gate surrounding a sidewall of the second channel, and a third source / drain and a fourth source / drain respectively connected to the second channel; The first gate of the read transistor is connected to the third source / drain of the write transistor.

2. The memory according to claim 1, characterized in that: The first source / drain and the second source / drain surround the sidewall of the first gate, and the first source / drain, the first channel and the second source / drain are arranged in sequence in a direction away from the substrate.

3. The memory according to claim 1, characterized in that: The second channel is in a hollow cylindrical shape and extends in a direction away from the substrate. The third source / drain and the fourth source / drain are sequentially arranged in the direction away from the substrate.

4. The memory according to claim 1, characterized in that: The first gate and the third source / drain are an integrated structure.

5. The memory according to claim 1, characterized in that: The third source / drain includes a first portion located inside the hollow tube of the second channel and a second portion located outside the hollow tube of the second channel, and both the first portion and the second portion are in contact with the second channel.

6. The memory according to claim 1, characterized in that: The read transistor further includes a first gate insulating layer surrounding a side wall of the first gate and located between the first gate and the first source / drain, the first channel, and the second source / drain sequentially arranged in a direction away from the substrate.

7. The memory according to claim 1, characterized in that: The write transistor further includes a second gate insulating layer surrounding a sidewall of the second channel and between the second channel and the second gate.

8. The memory according to claim 7, characterized in that: The dimensions of the second channel and the second gate insulating layer in a direction perpendicular to the substrate are greater than or equal to the dimension of the second gate in a direction perpendicular to the substrate.

9. The memory according to claim 1, characterized in that: The first channel includes N-type or P-type doped single crystal silicon; the second channel includes an oxide semiconductor material.

10. The memory according to claim 9, characterized in that: The first source / drain and the second source / drain both include N-type doped single crystal silicon, and the first channel includes P-type doped single crystal silicon.

11. The memory according to claim 9, characterized in that: The second channel includes indium gallium zinc oxide, and the third source / drain and the fourth source / drain include metal.

12. The memory according to claim 1, characterized in that: It also includes a first through-hole structure, a second through-hole structure and a third through-hole structure, wherein the first gate insulating layer and the first gate are located in the first through-hole structure; the second gate is located in the second through-hole structure; the third through-hole structure is located in the second gate, and the second gate insulating layer and the second channel are located in the third through-hole structure.

13. The memory according to claim 1, characterized in that: The memory cell further includes a first capacitor, a first electrode of the first capacitor being the first gate of the read transistor, a dielectric layer of the first capacitor being a portion of the first gate insulating layer, and a second electrode of the first capacitor being disposed on a side of the first gate insulating layer away from the write transistor.

14. The memory according to claim 1, characterized in that: The second gate of the write transistor is also the back gate of the read transistor, and the opening and closing of the corresponding read transistor is controlled by controlling the voltage of the second gate of the write transistor.

15. The memory according to claim 1, characterized in that: The first source / drain of the read transistor is connected to a read bit line, and the second source / drain is connected to a read word line or the first source / drain of the read transistor is connected to a read word line, and the second source / drain is connected to a read bit line; The second gate of the write transistor is connected to a write word line, and the fourth source / drain is connected to a write bit line.

16. A method for reading and writing a memory according to any one of claims 1 to 15, characterized in that: include: When the memory is written, a start voltage is applied to the write word line, the write transistor is turned on, and the storage information is sequentially written into the storage node SN through the write bit line and the write transistor; When the memory is read, a negative voltage is applied to the write word line of the memory cell that is not read, thereby increasing the threshold voltage of the read transistor, and then the voltage of the read word line and the read bit line is adjusted higher relative to their respective original voltages, so that the memory cell cannot be read; The voltage of the write word line of the memory cell to be read is kept unchanged so that the threshold voltage of the read transistor remains unchanged, the read word line is adjusted higher relative to its original voltage and the read bit line is adjusted lower relative to its original voltage, or the read bit line is adjusted higher relative to its original voltage and the read word line is adjusted lower relative to its original voltage, so that a voltage difference is generated between the read word line and the read bit line, and the selected memory cell is read.

17. A method for manufacturing a memory, characterized in that: The steps include: forming a first source / drain material layer, a first channel material layer, and a second source / drain material layer of a read transistor having different positions in a direction away from the substrate; forming a first through-hole structure penetrating the first source / drain material layer, the first channel material layer, and the second source / drain material layer; forming a first gate of the read transistor within the first via structure; forming a third source / drain of a write transistor, so that the third source / drain material layer of the write transistor is connected to the first gate of the read transistor; forming a second through-hole structure; forming a second gate in the second through-hole structure; forming a third through-hole structure in the second gate; forming a second channel of the write transistor in the third through-hole structure; as well as A fourth source / drain of the write transistor is formed.

18. The manufacturing method according to claim 17, characterized in that: Forming the first gate of the read transistor includes: depositing an insulating layer on the first source / drain material layer; forming a through hole in the insulating layer, filling the through hole with silicon and doping to form the first channel; forming a first drain on the first channel; forming a first through-hole structure; A dielectric layer film and a conductive film are deposited in the first through-hole structure to form a first gate insulating layer and a first gate.

19. The manufacturing method according to claim 17, characterized in that: The step of forming the third source / drain of the write transistor also includes making the third source / drain of the write transistor and the first gate of the read transistor an integrated structure.

20. An electronic device, characterized in that: Comprising a memory according to any one of claims 1-15.

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