Memory and manufacturing method thereof, read / write method, and electronic device

Abstract

The application provides a memory and a manufacturing method, a read-write method and an electronic device thereof. The memory comprises a substrate and a memory cell, wherein the memory cell comprises a read transistor and a write transistor arranged in sequence in a direction away from the substrate; the read transistor comprises a first gate, a first channel surrounding a sidewall of the first gate, and a first source / drain and a second source / drain connected with the first channel respectively; the write transistor comprises a second channel, a second gate surrounding a sidewall of the second channel, and a third source / drain and a fourth source / drain connected with the second channel respectively; and the first gate of the read transistor is connected with the third source / drain of the write transistor. The device architecture can reduce the leakage of the write transistor, increase the retention time, and accelerate the read rate of the read transistor.

Description

Technical Field

[0001] This application relates to, but is not limited to, semiconductor technology, and in particular to a memory and its manufacturing method, reading and writing method, and electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, making it possible for even the slightest differences in the manufacturing process to affect device performance.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] In one aspect, an exemplary embodiment of this application provides a memory including a substrate and a memory cell, the memory cell including a read transistor and a write transistor arranged sequentially in a direction away from the substrate;

[0006] The read transistor includes a first gate, a first channel surrounding the sidewall of the first gate, and a first source / drain and a second source / drain respectively connected to the first channel;

[0007] The write transistor includes a second channel, a second gate surrounding the sidewalls of the second channel, and a third source / drain and a fourth source / drain respectively connected to the second channel;

[0008] The first gate of the read transistor is connected to the third source / drain of the write transistor.

[0009] In an exemplary embodiment, the first source / drain and the second source / drain surround the sidewall of the first gate, and the first source / drain, the first channel, and the second source / drain are arranged sequentially in a direction away from the substrate.

[0010] In an exemplary embodiment, the second channel is a hollow cylindrical shape and extends in a direction away from the substrate, and the third source / drain and the fourth source / drain are arranged sequentially in a direction away from the substrate.

[0011] In an exemplary embodiment, the first gate and the third source / drain are an integral structure.

[0012] In an exemplary embodiment, the third source / drain includes a first portion located inside the hollow cylinder of the second channel and a second portion located outside the hollow cylinder of the second channel, both the first portion and the second portion being in contact with the second channel.

[0013] In an exemplary embodiment, the read transistor further includes a first gate insulating layer surrounding the sidewall of the first gate and located between the first gate and the first source / drain, the first channel, and the second source / drain sequentially disposed in a direction away from the substrate.

[0014] In an exemplary embodiment, the write transistor further includes a second gate insulating layer surrounding the sidewalls of the second channel and located between the second channel and the second gate.

[0015] In an exemplary embodiment, the dimensions of the second channel and the second gate insulating layer in the direction perpendicular to the substrate are greater than or equal to the dimensions of the second gate in the direction perpendicular to the substrate.

[0016] In an exemplary embodiment, the first channel comprises N-type or P-type doped monocrystalline silicon; the second channel comprises an oxide semiconductor material.

[0017] In an exemplary embodiment, both the first source / drain and the second source / drain comprise N-type doped monocrystalline silicon, and the first channel comprises P-type doped monocrystalline silicon.

[0018] In an exemplary embodiment, the second channel comprises indium gallium zinc oxide, and the third and fourth source / drain electrodes comprise metals.

[0019] In an exemplary embodiment, the system further includes a first via structure, a second via structure, and a third via structure, wherein the first gate insulating layer and the first gate are located within the first via structure; the second gate is located within the second via structure; and the third via structure is located within the second gate, wherein the second gate insulating layer and the second channel are located within the third via structure.

[0020] In an exemplary embodiment, the memory cell further includes a capacitor, the first electrode of which is the first gate of the read transistor, the dielectric layer of which is part of the first gate insulating layer, and the second electrode of which is disposed on the side of the first gate insulating layer away from the write transistor.

[0021] In an exemplary embodiment, the second gate of the write transistor is also the back gate of the read transistor, and the opening and closing of the corresponding read transistor is controlled by controlling the voltage of the second gate of the write transistor.

[0022] In an exemplary embodiment, the first source / drain of the read transistor is connected to the read bit line, and the second source / drain is connected to the read word line, or the first source / drain of the read transistor is connected to the read word line, and the second source / drain is connected to the read bit line; the second gate of the write transistor is connected to the write word line, and the fourth source / drain is connected to the write bit line.

[0023] On the other hand, an exemplary embodiment of this application provides a method for reading and writing the above-described memory, comprising:

[0024] When writing to the memory, an enable voltage is applied to the write word line to enable the write transistor, and the stored information is written to the memory node SN by passing through the write bit line and the write transistor in sequence.

[0025] When the memory is read, a negative voltage is applied to the write word line of the memory cell that is not read, thereby increasing the threshold voltage of the read transistor. Then, the voltage of the read word line and the read bit line is increased relative to their original voltage, making it impossible to read the memory cell.

[0026] The voltage of the write word line of the memory cell to be read remains constant, thereby keeping the threshold voltage of the read transistor constant. The read word line is increased relative to its original voltage while the read bit line is decreased relative to its original voltage, or the read bit line is increased relative to its original voltage while the read word line is decreased relative to its original voltage, so as to create a voltage difference between the read word line and the read bit line, and thus read the selected memory cell.

[0027] In another aspect, an exemplary embodiment of this application provides a method for manufacturing a memory, comprising the following steps:

[0028] A first source / drain material layer, a first channel material layer, and a second source / drain material layer are formed on read transistors at different positions along the direction away from the substrate;

[0029] A first via structure is formed that penetrates the first source / drain material layer, the first channel material layer, and the second source / drain material layer;

[0030] The first gate of the read transistor is formed within the first through-hole structure;

[0031] A third source / drain is formed in the write transistor, and the third source / drain material layer of the write transistor is connected to the first gate of the read transistor;

[0032] Forming a second through-hole structure;

[0033] A second gate is formed within the second through-hole structure;

[0034] A third through-hole structure is formed within the second gate;

[0035] The second channel of the write transistor is formed in the third via structure; and

[0036] The fourth source / drain of the write transistor is formed.

[0037] In an exemplary embodiment, the first gate forming the read transistor includes:

[0038] An insulating layer is deposited on the first source / drain material layer;

[0039] A via is formed in the insulating layer, and silicon is filled into the via and doped to form the first channel;

[0040] A first drain electrode is formed on the first channel;

[0041] Forming the first through-hole structure;

[0042] A dielectric thin film and a conductive thin film are deposited within the first via structure to form a first gate insulating layer and a first gate.

[0043] In an exemplary embodiment, the step of forming the third source / drain of the write transistor further includes making the third source / drain of the write transistor and the first gate of the read transistor an integral structure.

[0044] In another aspect, an exemplary embodiment of this application provides an electronic device including the aforementioned memory.

[0045] In exemplary embodiments, the aforementioned electronic devices include storage devices, smartphones, computers, tablets, artificial intelligence devices, wearable devices, or power banks.

[0046] The channel layer of the write transistor in this application uses IGZO wide-band semiconductor material, which can reduce the leakage current of the write transistor and increase the hold time; moreover, IGZO is a low-temperature process, which is compatible with back-end of line (BEOL) process and does not affect silicon devices.

[0047] The channel layer of the read transistor in this application is made of doped silicon, which has high silicon mobility, fast read speed, and is compatible with peripheral processes. When making the silicon read transistor, the peripheral circuit can be manufactured at the same time.

[0048] The two transistors in this application can be arranged in a three-dimensional vertical structure, saving area.

[0049] The semiconductor device of this application can uniquely select the data to be read, suppressing the unavoidable current sharing problem in 2T0C devices.

[0050] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0051] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0052] Figure 1A A perspective view of a memory provided for an exemplary embodiment of this application;

[0053] Figure 1B For along Figure 1A A schematic diagram of the vertical section intercepted by section line AA' in the diagram;

[0054] Figure 1C A schematic diagram of a vertical cross-section taken along a plane perpendicular to the substrate, for an exemplary embodiment of this application;

[0055] Figure 2 A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a memory according to an exemplary embodiment of this application, taken along a plane perpendicular to the substrate.

[0056] Figure 3 A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a memory according to an exemplary embodiment of this application, taken along a plane perpendicular to the substrate.

[0057] Figure 4 A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a memory according to an exemplary embodiment of this application, taken along a plane perpendicular to the substrate.

[0058] Figure 5 A schematic diagram of a vertical cross-section taken along a plane perpendicular to the substrate, representing an intermediate step in a method for manufacturing a memory according to an exemplary embodiment of this application; and

[0059] Figure 6 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a memory according to an exemplary embodiment of this application, taken along a plane perpendicular to the substrate. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0061] The embodiments described herein can be implemented in many different forms. Those skilled in the art will readily understand that the implementation methods and content can be varied in many ways without departing from the spirit and scope of this application. Therefore, this application should not be construed as limited to the contents described in the following embodiments. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0062] The scale of the figures in this application can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The figures described in this application are only schematic diagrams of the structure, and the approach of this application is not limited to the shapes or values ​​shown in the figures.

[0063] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to those described in the specification and may be appropriately replaced as needed.

[0064] In this specification, unless otherwise expressly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0065] In the description of this application, ordinal numbers such as "first" and "second" are used to avoid confusion of constituent elements, rather than to limit the quantity.

[0066] In this specification, "film" and "layer" may be interchanged. For example, "metal layer" may sometimes be replaced with "metal film".

[0067] In this application's description, a transistor refers to a device comprising at least three terminals: a gate, a drain, and a source. A transistor has a channel layer between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel layer, and the source. In this application, the channel layer refers to the region through which current primarily flows. In this application, the terms "metal-oxide-semiconductor channel," "channel layer," and "semiconductor layer" are used interchangeably.

[0068] The development of integrated circuit technology requires continuous upgrading. Traditional capacitor-type 1T1C DRAM has problems such as limited storage capacitor capacity and increased transistor off-state current.

[0069] Therefore, an exemplary embodiment of this application provides a memory including a substrate and a memory cell, the memory cell including a read transistor and a write transistor arranged sequentially in a direction away from the substrate; the read transistor includes a first gate, a first channel surrounding a sidewall of the first gate, and a first source / drain and a second source / drain respectively connected to the first channel; the write transistor includes a second channel, a second gate surrounding a sidewall of the second channel, and a third source / drain and a fourth source / drain respectively connected to the second channel; wherein the first gate of the read transistor is connected to the third source / drain of the write transistor.

[0070] In an exemplary embodiment, the second channel is a hollow cylindrical shape and extends in a direction away from the substrate, and the third source / drain and the fourth source / drain are arranged sequentially in a direction away from the substrate.

[0071] In an exemplary embodiment, the first channel comprises N-type or P-type doped monocrystalline silicon; the second channel comprises an oxide semiconductor material.

[0072] As used in this application, the term "monolithic structure" can refer to a structure in which A and B have no obvious boundary interface such as discontinuities or gaps in their microstructure. Generally, a monolithic structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material to create a single membrane layer and simultaneously formed into a structure with interconnected relationships through the same patterning process.

[0073] Figure 1A A perspective view of a memory provided for an exemplary embodiment of this application; Figure 1B For along Figure 1A A schematic diagram of the vertical section intercepted by section line AA' in the diagram. (See diagram below.) Figure 1A and Figure 1BAs shown, the memory cell may include a substrate 1 and a memory cell. The memory cell includes a read transistor 100 and a write transistor 200 sequentially arranged in a direction away from the substrate. The read transistor 100 may include a first gate 150, a first channel 120 surrounding the sidewall of the first gate 150, and a first source / drain 110 and a second source / drain 130 respectively connected to the first channel 120. The write transistor 200 may include a second channel 220, a second gate 250 surrounding the sidewall of the second channel 220, and a third source / drain 210 and a fourth source / drain 230 respectively connected to the second channel 220.

[0074] The read transistor 100 may further include a first gate insulating layer 140 surrounding the sidewall of the first gate 150 and located between the first gate 150 and the vertically stacked first source / drain 110, first channel 120, and second source / drain 130. The write transistor 200 may further include a second gate insulating layer 240 surrounding the sidewall of the second channel 220 and located between the second channel 220 and the second gate 250.

[0075] In this application, "surrounding" can be understood as partially or completely surrounding the first gate 150 or the second channel 220. In some embodiments, the surrounding can be a complete surround, and the cross-section of the channel after surrounding can be a closed ring, with the ring shape conforming to the outer contour shape of the cross-section of the first gate 150 or the second channel 220. For example, the cross-section of the first gate 150 or the second channel 220 may be a circular, rectangular, elliptical, or other similar structure. The cross-section is cut along a direction parallel to the substrate 1. In exemplary embodiments, the surrounding can be a partial surround, and the cross-section after surrounding is not closed, such as a ring with an opening.

[0076] like Figure 1B As shown, the first gate 150 of the read transistor 100 can be connected to the third source / drain 210 of the write transistor 200, or in other words, the first gate 150 and the third source / drain 210 can be an integral structure. Therefore, by interconnecting the gate of the read transistor with the source or drain of the write transistor, this application obtains a capacitor-free memory, such as a 2TOC DRAM memory.

[0077] refer to Figure 1B The third source / drain 210 may include a first portion 211 located inside the hollow cylinder of the second channel 220 and a second portion 212 located outside the hollow cylinder of the second channel, both the first portion 211 and the second portion 212 being in contact with the second channel 220.

[0078] Continue to refer to Figure 1A and Figure 1B The first channel 120 surrounds the sidewall of the first gate 150 and is located between the first source / drain 110 and the second source / drain 130. The second channel 220 is surrounded by the second gate 250, and the end of the second channel 220 near the substrate 1 contacts the third source / drain 210, while the end away from the substrate 1 contacts the fourth source / drain 230.

[0079] Although this paper uses the references of first source / drain and second source / drain, as well as third source / drain and fourth source / drain, to identify two separate and distinct sources / drains, it is not intended that the source / drain referred to as "first" source / drain, or "second" source / drain, or "third" source / drain and "fourth" source / drain have a single meaning.

[0080] In an exemplary embodiment, the first source / drain and the second source / drain are independent of each other. In an exemplary embodiment, one of the first source / drain and the second source / drain is the source of a transistor, and the other is the drain of a transistor. Similarly, the third source / drain and the fourth source / drain are independent of each other, and one of the third source / drain and the fourth source / drain is the source of a transistor, and the other is the drain of a transistor.

[0081] In an exemplary embodiment, both the first source / drain 110 and the second source / drain 130 may comprise N-type doped monocrystalline silicon or polycrystalline silicon, and the annular first channel 120 may comprise P-type doped monocrystalline silicon or polycrystalline silicon. Compared to junctionless devices, the read transistor of this application can employ NPN or PNP inversion mode, which can increase the on-state current I. on .

[0082] Therefore, the read transistor of this application can have a ring channel structure, which is simpler to manufacture than the ring gate structure. Furthermore, compared to devices using oxide channel materials such as IGZO, the ring channel of the read transistor of this application is made of monocrystalline silicon or polycrystalline silicon, resulting in faster response speed and increased on-state current I. on This improves reading speed.

[0083] Continue to refer to Figure 1B The read transistor 100 may include a first via structure K1, with the first gate insulating layer 140 and the first gate 150 located within the first via structure K1. The write transistor 200 may include a second via structure K2 and a third via structure K3, with the second gate 250 located within the second via structure K2; the third via structure K3 is located within the second gate 250, and the second gate insulating layer 240 and the second channel 220 are located within the third via structure K3.

[0084] In an exemplary embodiment, the dimensions of the second channel 220 and the second gate insulating layer 240 in the vertical direction are larger than the dimensions of the second gate 250 in the vertical direction.

[0085] like Figure 1A As shown, the first source / drain 110 of the read transistor can be connected to the read bit line 160, and the second source / drain 130 can be connected to the read word line 170, or the second source / drain 130 of the read transistor is connected to the read bit line 160, and the first source / drain 110 can be connected to the read word line 170; the second gate 250 of the write transistor can be connected to the write word line 270, and the fourth source / drain 230 can be connected to the write bit line 260.

[0086] In an exemplary embodiment of this application, only one insulating layer (not shown in the figure) exists between the second gate 250 of the write transistor and the first channel 120 of the read transistor. Therefore, the second gate 250 of the write transistor also serves as the back gate of the read transistor. The second gate 250 can form a capacitance with the storage node SN to affect the threshold offset of the read transistor. Consequently, by controlling the voltage of the second gate 250 of the write transistor, the reading of the corresponding read transistor can be controlled, thereby suppressing the current sharing problem of the 2TOC device.

[0087] In an exemplary embodiment, the second channel 220 of the write transistor 200 may include an oxide semiconductor material, such as indium gallium zinc oxide (IGZO).

[0088] When the metal oxide material is IGZO, the transistor leakage current is relatively small (leakage current less than or equal to 10). -15 A), thus ensuring a low refresh rate for the dynamic memory. It should be noted that the metal oxide material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the transistor leakage current meets the requirements. This can be adjusted according to the actual situation.

[0089] IGZO has a large bandgap (Eg) and low leakage current, typically within the range of e. -20The order of magnitude increases the hold time, thus eliminating the need for a 64ms refresh; moreover, IGZO is a low-temperature process, compatible with BEOL, and does not affect transistor devices made of silicon. Furthermore, the write transistor's second gate is a ring-gate structure, providing strong gate control and low leakage current.

[0090] like Figure 1C As shown, the memory of this application may further include a first capacitor 300. The first capacitor 300 may include a first electrode 310, a dielectric layer 320, and a second electrode 330. The first electrode 310 may be electrically connected to the memory node SN, and the first gate insulating layer of the read transistor may serve as the dielectric layer 320.

[0091] At this time, the first gate 150 (also serving as the first electrode 310 of the first capacitor 300) is closer to the substrate relative to the first source / drain 110 in a direction perpendicular to the substrate, to avoid short-circuiting the second electrode 330 with the first source / drain 110; the second electrode 330 is disposed in the substrate; by providing the first capacitor 300, the voltage holding capability of the memory node SN can be enhanced. See also some exemplary embodiments. Figure 1B The memory may also include a second capacitor and a third capacitor. The first electrode of the second capacitor is a first gate 150, and the second electrode of the second capacitor is a first source / drain 110. The first electrode of the third capacitor is a first gate 150, and the second electrode of the third capacitor is a second source / drain 130. That is, the second capacitor and the third capacitor share the first gate 150 as their respective first electrodes. By setting the second and third capacitors, the voltage holding capability of the memory node SN can also be enhanced.

[0092] In some exemplary embodiments, this application also provides a method for reading a memory, including:

[0093] When writing to the memory, an enable voltage is applied to the write word line to enable the write transistor, and the stored information is written to the memory node SN by passing through the write bit line and the write transistor in sequence.

[0094] When the memory is read, a negative voltage is applied to the write word line of the memory cell that is not read, thereby increasing the threshold voltage of the read transistor. Then, the voltage of the read word line and the read bit line is increased relative to their original voltage, so that the memory cell cannot be read (there is no voltage difference between the two, no current flows through, and no current leakage will occur).

[0095] The voltage of the write word line of the memory cell to be read is kept constant, thereby keeping the threshold voltage of the read transistor constant. The read word line is increased relative to its original voltage, and the read bit line is decreased relative to its original voltage, or the read bit line is increased relative to its original voltage and the read word line is decreased relative to its original voltage, so that a voltage difference is generated between the read word line and the read bit line (there is a voltage difference between the two, so current flows through), and the selected memory cell is read.

[0096] This application employs such a reading operation method to uniquely select the data to be read, thereby suppressing the problem of current sharing.

[0097] The technical solution of this application is further illustrated below through the manufacturing process of a memory according to an exemplary embodiment of this application. The "patterning process" mentioned in this exemplary embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this exemplary embodiment includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this exemplary embodiment, it should be understood that a "thin film" refers to a thin film made by depositing or coating a certain material on a substrate. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0098] In an exemplary embodiment, the manufacturing method of the memory of this application is described below using DRAM memory as an example.

[0099] In an exemplary embodiment, the method of manufacturing the memory may include the following steps:

[0100] S100: The source / drain material layer and channel material layer that form the read transistor.

[0101] Exemplary steps may include: depositing an insulating material thin film on a substrate 1 to form a first insulating layer 10; depositing a Si layer on the first insulating layer 10 and performing N-type doping to form a first source / drain material layer (read word line RWL) 110' of a read transistor 100; then depositing an insulating material thin film on the first source / drain material layer 110' to form a second insulating layer 20; forming a via penetrating the second insulating layer 20 by etching; filling the via with Si and performing P-type doping to form a first channel material layer 120'; depositing a Si layer on the first channel material layer 120' and performing N-type doping to form a second source / drain material layer (read bit line RBL) 130' of the read transistor 100, as shown below. Figure 2 As shown. Figure 2 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a memory according to an exemplary embodiment of this application, taken along a plane perpendicular to the substrate.

[0102] In an exemplary embodiment, the insulating thin film can be deposited using methods such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, and atomic layer deposition (ALD).

[0103] In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of any one or more non-conductive materials selected from silicon oxide, silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN). In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of oxide insulating materials, such as silicon dioxide (e.g., SiO2), which facilitates large-area deposition.

[0104] In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of the same or different insulating materials.

[0105] In an exemplary embodiment, the doping concentrations of the first source / drain material layer 110' and the second source / drain material layer 130' are different from the doping concentration of the first channel material layer 120'. In other exemplary embodiments, the first channel material layer 120' may also be N-type doped, meaning that the doping types of the first source material layer 110', the first channel material layer 120', and the second source / drain material layer 130' are the same.

[0106] In an exemplary embodiment, silicides can be fabricated on the first source / drain material layer 110' and the second source / drain material layer 130' to serve as connecting wires.

[0107] S200: The first gate material layer forming the read transistor.

[0108] Exemplary steps may include: forming a first via structure K1 by etching in the structure formed in the aforementioned steps, the first via structure K1 passing through the second source / drain material layer 130', the first channel material layer 120', and the first source / drain material layer 110', and terminating on the side of the first source / drain material layer 110' away from the first channel material layer 120'; depositing a dielectric thin film and a conductive thin film in the first via structure K1 to form a first gate insulating material layer 140' covering the sidewalls and bottom of the first via structure K1 and a first gate material layer 150' covering the first gate insulating layer 140' (i.e., the memory node SN of the read transistor); then removing excess film layers by photolithography etching, i.e., forming a read transistor 100 with a ring channel structure, such as... Figure 3 As shown. Figure 3 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a memory according to an exemplary embodiment of this application, taken along a plane perpendicular to the substrate.

[0109] In an exemplary embodiment, the first gate insulating material layer 140' may be a dielectric layer with a high dielectric constant, i.e., a dielectric layer with K ≥ 3.9. The high dielectric constant dielectric layer may serve as a gate oxide. The first gate insulating material layer 140' may be any one or more of silicon dioxide (SiO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

[0110] In an exemplary embodiment, the first gate material layer 150' may be made of P-type amorphous silicon, tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride.

[0111] In an exemplary embodiment, the deposition of each thin film layer may employ atomic layer deposition.

[0112] In an exemplary embodiment, the orthographic projection of the first through-hole structure K1 onto a plane parallel to the substrate can be square, rectangular, circular, elliptical, or other shapes.

[0113] S300: The second gate material layer forming the write transistor.

[0114] Exemplary steps may include: depositing an insulating material thin film on the structure formed in the preceding steps to form a third insulating layer 30; forming a groove T in the third insulating layer 30 by etching, and depositing a metal material thin film in the groove T to form a third source / drain material layer 210' of the write transistor; continuing to deposit a fourth insulating layer 40 on the third insulating layer 30; forming a second via structure K2 in the fourth insulating layer 40 by etching, wherein the orthographic projection of the second via structure K2 on the substrate 1 is greater than the orthographic projection of the groove T on the substrate 1; depositing a metal material thin film in the second via structure K2 to form a second gate material layer (write word line) 250' of the write transistor, such as... Figure 4 As shown. Figure 4 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a memory according to an exemplary embodiment of this application, taken along a plane perpendicular to the substrate.

[0115] In an exemplary embodiment, the second gate material layer 250' may be made of P-type amorphous silicon, tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride.

[0116] S400: The second channel material layer forming the write transistor.

[0117] Exemplary steps may include: forming a third via structure K3 by etching in the second gate material layer 250'; depositing a high-dielectric-constant material film on the bottom and sidewalls of the third via structure K3 using an ALD process and etching away the high-dielectric-constant material film at the bottom of the third via structure K3, thereby forming a second gate insulating material layer 240'; and then depositing a semiconductor material film on the sidewalls of the second gate insulating material layer 240' using an ALD process to form a second channel material layer 220', such as... Figure 5 As shown. Figure 5 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a memory according to an exemplary embodiment of this application, taken along a plane perpendicular to the substrate.

[0118] In an exemplary embodiment, the second channel material layer 220' can be a metal oxide semiconductor material. In an exemplary embodiment, the metal oxide semiconductor material can be an amorphous or polycrystalline metal oxide semiconductor material, and this metal oxide semiconductor material has a slow etching rate in weakly acidic or weakly alkaline solutions. In an exemplary embodiment, the metal oxide semiconductor material can be oxides of In, Ga, Zn, and Sn, etc. These metal oxide materials, such as indium gallium zinc oxide (IGZO), can be used as channel materials.

[0119] S500: The fourth source / drain material layer forming the write transistor.

[0120] Specific steps may include: continuing to fill the third via structure K3 with an insulating layer and making the upper surface of the structure flush using a chemical mechanical polishing (CMP) process; continuing to deposit a fifth insulating layer 50 on the fourth insulating layer 40; forming a fourth via structure K4 by etching within the fifth insulating layer 50; filling the fourth via structure K4 with metal to form a fourth source / drain material layer 230', thereby forming a write transistor 200, as shown below. Figure 6 As shown. Figure 6 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a method for manufacturing a memory according to an exemplary embodiment of this application, taken along a plane perpendicular to the substrate.

[0121] In an exemplary embodiment, the orthographic projection of the second through-hole structure K2, the third through-hole structure K3, the fourth through-hole structure K4, and the groove T onto a plane parallel to the substrate can be square, rectangular, circular, elliptical, or other shapes.

[0122] An exemplary embodiment of this application also provides a method for manufacturing a memory, comprising the following steps:

[0123] A first source / drain material layer, a first channel material layer, and a second source / drain material layer are formed on read transistors at different positions along the direction away from the substrate;

[0124] A first via structure is formed that penetrates the first source / drain material layer, the first channel material layer, and the second source / drain material layer;

[0125] The first gate of the read transistor is formed within the first through-hole structure;

[0126] A third source / drain is formed in the write transistor, and the third source / drain material layer of the write transistor is connected to the first gate of the read transistor;

[0127] Forming a second through-hole structure;

[0128] A second gate is formed within the second through-hole structure;

[0129] A third through-hole structure is formed within the second gate;

[0130] The second channel of the write transistor is formed in the third via structure; and

[0131] The fourth source / drain of the write transistor is formed.

[0132] In an exemplary embodiment, the first gate forming the read transistor includes:

[0133] Form the first source / drain;

[0134] An insulating layer is deposited on the first source / drain material layer;

[0135] A via is formed in the insulating layer, and silicon is filled into the via and doped to form the first channel;

[0136] A second source / drain is formed on the first channel;

[0137] Forming the first through-hole structure;

[0138] A dielectric thin film and a conductive thin film are deposited within the first via structure to form a first gate insulating layer and a first gate.

[0139] In an exemplary embodiment, the step of forming the third source / drain of the write transistor further includes making the third source / drain of the write transistor and the first gate of the read transistor an integral structure.

[0140] Exemplary embodiments of this application also provide an electronic device, including the memory provided in the exemplary embodiments of this application above.

[0141] In exemplary embodiments, electronic devices may include storage devices, smartphones, computers, tablets, artificial intelligence devices, wearable devices, or power banks, etc.

[0142] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A memory, characterized in that, The storage unit includes a substrate and a memory cell, wherein the memory cell includes a read transistor and a write transistor arranged sequentially in a direction away from the substrate. The read transistor includes a first gate, a first channel surrounding the sidewall of the first gate, and a first source / drain and a second source / drain respectively connected to the first channel; The write transistor includes a hollow cylindrical second channel, a second gate surrounding the sidewall of the second channel, and a third source / drain and a fourth source / drain respectively connected to the second channel; The first gate of the read transistor is connected to the third source / drain of the write transistor; The second gate of the write transistor serves as the back gate of the read transistor.

2. The memory according to claim 1, characterized in that, The first source / drain and the second source / drain surround the sidewall of the first gate, and the first source / drain, the first channel and the second source / drain are arranged sequentially in a direction away from the substrate.

3. The memory according to claim 1, characterized in that, The second channel extends in a direction away from the substrate, and the third source / drain and the fourth source / drain are arranged sequentially in a direction away from the substrate.

4. The memory according to claim 1, characterized in that, The first gate and the third source / drain are an integral structure.

5. The memory according to claim 1, characterized in that, The third source / drain includes a first portion located inside the hollow cylinder of the second channel and a second portion located outside the hollow cylinder of the second channel, both of which are in contact with the second channel.

6. The memory according to claim 1, characterized in that, The read transistor further includes a first gate insulating layer surrounding the sidewall of the first gate and a first source / drain, a first channel, and a second source / drain sequentially disposed in a direction away from the substrate. The first gate insulating layer is also located between the first gate and the first source / drain, between the first gate and the first channel, and between the first gate and the second source / drain.

7. The memory according to claim 1, characterized in that, The write transistor further includes a second gate insulating layer that surrounds the sidewalls of the second channel and is located between the second channel and the second gate.

8. The memory according to claim 7, characterized in that, The dimensions of the second channel and the second gate insulating layer in the direction perpendicular to the substrate are greater than or equal to the dimensions of the second gate in the direction perpendicular to the substrate.

9. The memory according to claim 1, characterized in that, The first channel comprises N-type or P-type doped single-crystal silicon; the second channel comprises an oxide semiconductor material.

10. The memory according to claim 9, characterized in that, Both the first source / drain and the second source / drain consist of N-type doped monocrystalline silicon, and the first channel consists of P-type doped monocrystalline silicon.

11. The memory according to claim 9, characterized in that, The second channel comprises indium gallium zinc oxide, and the third and fourth source / drain electrodes comprise metals.

12. The memory according to claim 1, characterized in that, It also includes a first through-hole structure, a second through-hole structure, and a third through-hole structure, wherein the first gate insulating layer and the first gate are located within the first through-hole structure; the second gate is located within the second through-hole structure; the third through-hole structure is located within the second gate, and the second gate insulating layer and the second channel are located within the third through-hole structure.

13. The memory according to claim 1, characterized in that, The storage cell further includes a first capacitor, the first electrode of which is the first gate of the read transistor, the dielectric layer of which is part of the first gate insulating layer, and the second electrode of which is disposed on the side of the first gate insulating layer away from the write transistor.

14. The memory according to claim 1, characterized in that, The opening and closing of the corresponding read transistor is controlled by controlling the voltage of the second gate of the write transistor.

15. The memory according to claim 1, characterized in that, The first source / drain of the read transistor is connected to the read bit line, and the second source / drain is connected to the read word line; or the first source / drain of the read transistor is connected to the read word line, and the second source / drain is connected to the read bit line. The second gate of the write transistor is connected to the write word line, and the fourth source / drain is connected to the write bit line.

16. A method for reading and writing a memory according to any one of claims 1-15, characterized in that, include: When writing to the memory, an enable voltage is applied to the write word line to enable the write transistor, and the stored information is written to the memory node SN by passing through the write bit line and the write transistor in sequence. When the memory is read, a negative voltage is applied to the write word line of the memory cell that is not read, thereby increasing the threshold voltage of the read transistor. Then, the voltage of the read word line and the read bit line is increased relative to their original voltage, making it impossible to read the memory cell. The voltage of the write word line of the memory cell to be read remains constant, thereby keeping the threshold voltage of the read transistor constant. The read word line is increased relative to its original voltage while the read bit line is decreased relative to its original voltage, or the read bit line is increased relative to its original voltage while the read word line is decreased relative to its original voltage, so as to create a voltage difference between the read word line and the read bit line, and thus read the selected memory cell.

17. A method for manufacturing a memory, characterized in that, Includes the following steps: A first source / drain material layer, a first channel material layer, and a second source / drain material layer are formed on read transistors at different positions along the direction away from the substrate; A first via structure is formed that penetrates the first source / drain material layer, the first channel material layer, and the second source / drain material layer; The first gate of the read transistor is formed within the first through-hole structure; A third source / drain is formed in the write transistor, and the third source / drain material layer of the write transistor is connected to the first gate of the read transistor; Forming a second through-hole structure; A second gate is formed within the second through-hole structure; A third through-hole structure is formed within the second gate; The second channel of the write transistor is formed in the third via structure; as well as The fourth source / drain of the write transistor is formed.

18. The manufacturing method according to claim 17, characterized in that, The first gate forming the read transistor includes: An insulating layer is deposited on the first source / drain material layer; A via is formed in the insulating layer, and silicon is filled into the via and doped to form the first channel; A first drain electrode is formed on the first channel; Forming the first through-hole structure; A dielectric thin film and a conductive thin film are deposited within the first via structure to form a first gate insulating layer and a first gate.

19. The manufacturing method according to claim 17, characterized in that, The step of forming the third source / drain of the write transistor further includes making the third source / drain of the write transistor and the first gate of the read transistor an integral structure.

20. An electronic device, characterized in that, Includes the memory according to any one of claims 1-15.

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