Semiconductor memory device

Abstract

A semiconductor memory device includes: a conductive line extending in a first direction; channel regions spaced apart from each other in the first direction over the conductive line and each electrically connected to the conductive line; a rear gate electrode spaced apart from the conductive line in a third direction and extending in a second direction between a first channel region and a second channel region selected from the channel regions; a pair of word lines spaced apart from each other in the first direction and between a second channel region and a third channel region selected from the channel regions; and epitaxial direct contact plugs extending in the third direction between the channel regions and the conductive line and each including a contact surface contacting one of the channel regions, a protruding contact portion at least partially surrounded by the conductive line, and a vertical contact portion between the contact surface and the protruding contact portion.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0139877 filed on October 18, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Embodiments of the inventive concept relate to a semiconductor memory device, and more particularly, to a semiconductor memory device including a vertical channel transistor. Background Art

[0003] As integrated circuit devices are rapidly scaled down, semiconductor memory devices may be required to provide high operating speeds and improved operating precision. Therefore, research has been conducted to provide semiconductor memory devices having a structure capable of improving performance and reliability thereof. Summary of the invention

[0004] An embodiment of the inventive concept provides a semiconductor memory device configured to mitigate or prevent thermal damage to a unit device through a contact structure, which contact structure can be formed through a low-temperature process during a manufacturing process of a semiconductor memory device including a vertical channel transistor, the semiconductor memory device having a structure that exhibits improved electrical characteristics due to the relatively large contact area provided by the contact structure.

[0005] According to one aspect of the inventive concept, a semiconductor memory device is provided, the semiconductor memory device comprising: a conductive line extending longitudinally in a first direction; a plurality of channel regions arranged above the conductive line and spaced apart from each other in the first direction, each of the plurality of channel regions being configured to be electrically connected to the conductive line; a back gate electrode spaced apart from the conductive line in a third direction and extending in a second direction between a first channel region and a second channel region, the first channel region and the second channel region being selected from the plurality of channel regions and being adjacent to each other, the first direction, the second direction and the third direction being perpendicular to each other; a pair of word lines spaced apart from each other in the first direction and arranged between a second channel region and a third channel region, the second channel region and the third channel region being selected from the plurality of channel regions and being adjacent to each other; and a plurality of epitaxial direct contact plugs extending in a third direction between the plurality of channel regions and the conductive line, each of the plurality of epitaxial direct contact plugs comprising: a contact surface contacting one of the plurality of channel regions, a protruding contact portion at least partially surrounded by the conductive line, and a vertical contact portion extending in the third direction between the contact surface and the protruding contact portion.

[0006] According to another aspect of the inventive concept, a semiconductor memory device is provided, the semiconductor memory device comprising: a conductive line extending longitudinally in a first direction; a plurality of channel regions arranged to be spaced apart from each other in the first direction and spaced apart from the conductive line in a third direction; a plurality of contact plugs spaced apart from the conductive line in the third direction, wherein the plurality of channel regions are located between the plurality of contact plugs and the conductive line; a back gate electrode spaced apart from the conductive line in the third direction and extending longitudinally in a second direction between a first channel region and a second channel region, the first channel region and the second channel region being selected from the plurality of channel regions and adjacent to each other, the first direction, the second direction and the third direction being perpendicular to each other; and a back gate dielectric film, A gate dielectric film is arranged between the word line and the second channel region and contacts each of the word line and the second channel region; a word line is spaced apart from the back gate electrode in a first direction, wherein the second channel region is located between the word line and the back gate electrode; a gate dielectric film is arranged between the word line and the second channel region and contacts each of the word line and the second channel region; and an epitaxial direct contact plug extends in a third direction between the first channel region and the conductive line, the epitaxial direct contact plug comprising: a contact surface contacting the second channel region, a protruding contact portion at least partially surrounded by the conductive line, and a sidewall, the sidewall extending in the third direction between the contact surface and the protruding contact portion and contacts each of the back gate dielectric film and the gate dielectric film.

[0007] According to another aspect of the inventive concept, a semiconductor memory device is provided, the semiconductor memory device comprising: a plurality of conductive lines extending longitudinally in a first direction and spaced apart from each other in a second direction; a plurality of contact plugs spaced apart from the plurality of conductive lines in a third direction, the first direction, the second direction and the third direction being perpendicular to each other; a plurality of channel regions arranged between the plurality of conductive lines and the plurality of contact plugs, the plurality of channel regions each having one end spaced apart from the plurality of conductive lines in the third direction and another end connected to one contact plug selected from the plurality of contact plugs; a plurality of back gate electrodes spaced apart from each other in the first direction and extending longitudinally in the second direction between the plurality of conductive lines and the plurality of contact plugs; a plurality of back gate dielectric films spaced apart from each other in the first direction and spaced apart from each other in the second direction; The invention relates to a method of manufacturing a plurality of epitaxial direct contact plugs, wherein the plurality of epitaxial direct contact plugs are connected to the plurality of conductive wires and contact plugs respectively, wherein the plurality of conductive wire ... BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a plan layout diagram showing some components of a semiconductor memory device according to some embodiments; Figure 2 It is along Figure 1 The line X1-X1' intercepts Figure 1 A cross-sectional view of a semiconductor memory device; Figure 3 yes Figure 2 An enlarged cross-sectional view of area EX1.

[0009] Figures 4 to 10 are cross-sectional views each showing a semiconductor memory device according to some embodiments; FIG. 11A to FIG. 28B are diagrams respectively illustrating a process sequence of a method for manufacturing a semiconductor memory device according to some embodiments, specifically, Fig.11A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.19A, Fig.22A , Fig.23A and Fig.28A are plan layout diagrams each showing some components of a semiconductor memory device according to a process sequence to illustrate an example operation of a method of manufacturing a semiconductor memory device, Fig. 11B , Fig.12 , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18 , Fig.19B , Fig. 20 , Fig.21 , Fig. 22B , Fig. 23B , Fig.24 , Fig.25 , Fig.26 , Fig. 27 and Fig.28B are shown according to the process sequence and along Figure 1 A cross-sectional view of a portion of the semiconductor memory device corresponding to a cross section taken along line X1 - X1 ′ in FIG. Fig.29 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to some embodiments. DETAILED DESCRIPTION

[0010] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout the specification, the same components are represented by the same reference numerals, and their repeated descriptions are omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It is noted that, although not specifically described, the aspects described with respect to one embodiment can be combined in different embodiments. That is, all embodiments and / or features of any embodiment can be combined in any manner and / or combination.

[0011] It should be understood that although terms such as "first", "second", "third", etc. are used herein to describe various components, these components are not limited by these terms. Unless otherwise explicitly stated, these terms are only used to distinguish one component from another component, and it is understood that the first component can be referred to as the second component or the third component, and vice versa. For example, without departing from the scope of the inventive concept, the first channel region can be referred to as the second channel region or the third channel region, and similarly, the second channel region or the third channel region can be referred to as the first channel region. Although the first channel region, the second channel region, and the third channel region are all channel regions, the first channel region, the second channel region, and the third channel region are not the same channel region.

[0012] As used herein, the terms horizontal and vertical refer to the orientation of the semiconductor device as shown in the drawings. For example, the X direction and the Y direction in the drawings refer to the horizontal direction, and the Z direction in the drawings refers to the vertical direction.

[0013] Figure 1 is a plan layout diagram showing some components of the semiconductor memory device 100 according to some embodiments. Figure 2 The semiconductor memory device 100 is Figure 1 A cross-sectional view taken along the line X1-X1', Figure 3 yes Figure 2 An enlarged cross-sectional view of area EX1.

[0014] Reference Figures 1 to 3 , the semiconductor memory device 100 may include a plurality of conductive lines BL extending longitudinally in a first horizontal direction (X direction) and repeatedly configured in an arrangement spaced apart from each other in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction). In the semiconductor memory device 100, each of the plurality of conductive lines BL may form a bit line.

[0015] A plurality of channel regions CHL may be arranged above each of the plurality of conductive lines BL, and a plurality of contact plugs 130 may be arranged on the plurality of channel regions CHL, respectively. The plurality of channel regions CHL may be repeatedly arranged between the plurality of conductive lines BL and the plurality of contact plugs 130, and may be spaced apart from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction). Each of the plurality of channel regions CHL may have one end spaced apart from the plurality of conductive lines BL in a vertical direction (Z direction) and the other end electrically connected to one contact plug 130 selected from the plurality of contact plugs 130. Each of the plurality of channel regions CHL may be physically spaced apart from the conductive lines BL, and may be in contact with one contact plug 130.

[0016] Each of the plurality of conductive lines BL may include metal, conductive metal nitride, doped polysilicon, or a combination thereof. For example, each of the plurality of conductive lines BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, RuTiN, or a combination thereof.

[0017] The plurality of contact plugs 130 may be spaced apart from the plurality of conductive lines BL in a vertical direction (Z direction), wherein the plurality of channel regions CHL are located between the plurality of contact plugs 130 and the plurality of conductive lines BL. The plurality of contact plugs 130 may be arranged in a matrix and spaced apart from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The plurality of contact plugs 130 may be electrically connected to the plurality of channel regions CHL in a one-to-one correspondence with the plurality of channel regions CHL, respectively.

[0018] Each of the plurality of contact plugs 130 may include a metal, a conductive metal nitride, a metal silicide, doped polysilicon, or a combination thereof. For example, each of the plurality of contact plugs 130 may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, doped polysilicon, or a combination thereof. In some embodiments, as Figure 2 As shown in , each of the plurality of contact plugs 130 may include a first conductive pattern 132, a second conductive pattern 134, and a third conductive pattern 136, which are sequentially stacked on each of the plurality of channel regions CHL in the order stated. For example, although the first conductive pattern 132 may include doped polysilicon, the second conductive pattern 134 may include metal silicide, and the third conductive pattern 136 may include metal, embodiments of the inventive concept are not limited thereto.

[0019] like Figure 1 As shown in , the plurality of channel regions CHL may include a first group of channel regions CHL and a second group of channel regions CHL, the first group of channel regions CHL being arranged in a line in a first horizontal direction (X direction) and being spaced apart from each other in the first horizontal direction (X direction), and the second group of channel regions CHL being arranged in a line in a second horizontal direction (Y direction) and being spaced apart from each other in the second horizontal direction (Y direction). Each of the plurality of contact plugs 130 may be arranged on one channel region CHL selected from the plurality of channel regions CHL. Each of the plurality of contact plugs 130 may pass through an interlayer dielectric 138 to contact one selected channel region CHL. The interlayer dielectric 138 may include a silicon oxide film, a silicon nitride film, or a combination thereof.

[0020] In some embodiments, each of the plurality of channel regions CHL may include silicon (e.g., single crystal silicon, polycrystalline silicon, or amorphous silicon). In some embodiments, each of the plurality of channel regions CHL may include one or more materials (such as, for example, Ge, SiGe, SiC, GaAs, InAs, and / or InP). In some embodiments, the channel region CHL may include a conductive region (e.g., a well doped with impurities or a structure doped with impurities).

[0021] A plurality of back gate (also referred to as “back gate”) electrodes BG and a plurality of word lines WL may be arranged above each of the plurality of wires BL. The plurality of back gate electrodes BG and the plurality of word lines WL may each extend longitudinally in the second horizontal direction (Y direction) between the plurality of wires BL and the plurality of contact plugs 130. The plurality of back gate electrodes BG may be spaced apart from each other in the first horizontal direction (X direction), and the plurality of word lines WL may be spaced apart from each other in the first horizontal direction (X direction).

[0022] Among the plurality of back gate electrodes BG and the plurality of word lines WL arranged in a line in the first horizontal direction (X direction) above one conductive line BL, one back gate electrode BG and a pair of word lines WL may be arranged alternately, and one back gate electrode BG may be spaced apart from the pair of word lines WL, with one channel region CHL located between the one back gate electrode BG and the pair of word lines WL. That is, the plurality of word lines WL may be arranged such that a pair of adjacent word lines WL is arranged between each of the plurality of back gate electrodes BG.

[0023] Each of the plurality of back gate electrodes BG may include a metal, a conductive metal nitride, doped polysilicon, or a combination thereof. For example, each of the plurality of back gate electrodes BG may include, but is not limited to, Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, doped polysilicon, or a combination thereof. Each of the plurality of word lines WL may include, but is not limited to, a metal, a conductive metal nitride, or a combination thereof. For example, each of the plurality of word lines WL may include, but is not limited to, Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, or a combination thereof.

[0024] Each of the plurality of back gate electrodes BG may extend longitudinally in the second horizontal direction (Y direction) between two channel regions CHL adjacent to each other in the first horizontal direction (X direction). Each of the plurality of back gate electrodes BG may be spaced apart from each of the conductive line BL and the plurality of contact plugs 130 in the vertical direction (Z direction).

[0025] The semiconductor memory device 100 may include a plurality of back gate dielectric films 152, each of which is on a plurality of back gate electrodes BG and at least partially covers the plurality of back gate electrodes BG. Each of the plurality of back gate dielectric films 152 may be arranged between one back gate electrode BG and one channel region CHL. Each of the plurality of back gate dielectric films 152 may contact the back gate electrode BG and the channel region CHL adjacent thereto. Each of the plurality of back gate dielectric films 152 may include one end contacting the conductive line BL and the other end contacting the contact plug 130.

[0026] In a region between a pair of adjacent channel regions CHL, a first capping insulating pattern 158 may be disposed between the back gate electrode BG and the plurality of contact plugs 130. In a region between a pair of adjacent channel regions CHL, a second capping insulating pattern 160B may be disposed between the back gate electrode BG and the conductive line BL. The first capping insulating pattern 158, the back gate electrode BG, and the second capping insulating pattern 160B may be disposed to at least partially overlap each other in a vertical direction (Z direction).

[0027] Each of the first overlying insulating pattern 158 and the second overlying insulating pattern 160B may include a silicon oxide film, a silicon nitride film, or a combination thereof. In some embodiments, the first overlying insulating pattern 158 and the second overlying insulating pattern 160B may include materials different from each other. For example, the first overlying insulating pattern 158 may include a silicon oxide film, and the second overlying insulating pattern 160B may include a silicon nitride film. In some embodiments, the first overlying insulating pattern 158 and the second overlying insulating pattern 160B may include the same material. For example, the first overlying insulating pattern 158 and the second overlying insulating pattern 160B may include the same material selected from a silicon oxide film and a silicon nitride film.

[0028] Each of the plurality of word lines WL may be spaced apart from the conductive line BL and each of the plurality of contact plugs 130 in the vertical direction (Z direction). In the first horizontal direction (X direction), a pair of word lines WL may be arranged between each of the plurality of back gate electrodes BG. A pair of word lines WL may be spaced apart from adjacent back gate electrodes BG in the first horizontal direction (X direction), and one channel region CHL is located between the pair of word lines WL and the back gate electrode BG.

[0029] like Figure 2 and Figure 3 As shown in , a plurality of epitaxial direct contact plugs DC may be respectively arranged between the conductive line BL and the plurality of channel regions CHL. Each of the plurality of epitaxial direct contact plugs DC may extend in a vertical direction (Z direction) between the conductive line BL and one channel region CHL selected from the plurality of channel regions CHL. Each of the plurality of epitaxial direct contact plugs DC may include a contact surface DCC contacting one channel region CHL among the plurality of channel regions CHL, a protruding contact portion DCP at least partially surrounded by the conductive line BL, and a vertical contact portion DCV extending in a vertical direction (Z direction) between the contact surface DCC and the protruding contact portion DCP.

[0030] In some embodiments, each of the plurality of epitaxial direct contact plugs DC may include a semiconductor film doped with a dopant. The dopant may include an N-type dopant or a P-type dopant. The dopant may include, but is not limited to, P, B, and / or As. For example, each of the plurality of epitaxial direct contact plugs DC may include a silicon film doped with a dopant (or a doped silicon film).

[0031] like Figure 3As shown in , a vertical height LVC1 of an end portion CE1 of each of the plurality of channel regions CHL closest to the conductive line BL may be spaced apart from a vertical height LVB1 of a surface of the conductive line BL closest to the back gate electrode BG in the vertical direction (Z direction). That is, an end portion CE1 of each of the plurality of channel regions CHL closest to the conductive line BL may be spaced apart from a surface of the conductive line BL closest to the back gate electrode BG in the vertical direction (Z direction).

[0032] The plurality of back gate electrodes BG and the plurality of word lines WL may each have an end surface facing the wire BL and closest to the wire BL, and the vertical height of the end surface of each of the plurality of back gate electrodes BG and the plurality of word lines WL may be spaced apart from the vertical height LVB1 of the surface of the wire BL closest to the back gate electrode BG in the vertical direction (Z direction). That is, the end surface of each of the plurality of back gate electrodes BG and the plurality of word lines WL closest to the wire BL may be spaced apart from the surface of the wire BL closest to the back gate electrode BG in the vertical direction (Z direction).

[0033] A vertical distance between the plurality of contact plugs 130 and a surface of the back gate electrode BG closest to the plurality of contact plugs 130 may be greater than a vertical distance between the plurality of contact plugs 130 and a surface of the word line WL closest to the plurality of contact plugs 130. A vertical distance L1 between a vertical height LV1 of a portion of the back gate electrode BG farthest from the conductive line BL in the vertical direction (Z direction) and a vertical height LV2 of a portion of the plurality of contact plugs 130 closest to the conductive line BL in the vertical direction (Z direction) may be greater than a vertical distance L2 between a vertical height LV3 of an end of the word line WL farthest from the conductive line BL and the above-mentioned vertical height LV2. In the vertical direction (Z direction), a length of the first capping insulating pattern 158 may be greater than a length of the first gap-filling insulating pattern 126.

[0034] The isolation insulating pattern 124 may be arranged between a pair of word lines WL, which are arranged between a pair of adjacent channel regions CHL. The first gap filling insulating pattern 126 may be arranged between the pair of word lines WL and a plurality of contact plugs 130, and a pair of second gap filling insulating patterns 160A may be arranged between the pair of word lines WL and the conductive line BL, respectively. The word line WL, the first gap filling insulating pattern 126, and the second gap filling insulating pattern 160A may be arranged between a pair of adjacent channel regions CHL to at least partially overlap each other in the vertical direction (Z direction). The pair of word lines WL may be spaced apart from the plurality of contact plugs 130 in the vertical direction (Z direction), and the first gap filling insulating pattern 126 is located between the pair of word lines WL and the plurality of contact plugs 130. The word line WL may be spaced apart from the conductive line BL, and the second gap filling insulating pattern 160A is located between the word line WL and the conductive line BL. In the vertical direction (Z direction), the length of the second gap-filling insulating pattern 160A may be equal to or similar to that of the second capping insulating pattern 160B. The second gap-filling insulating pattern 160A and the second capping insulating pattern 160B may constitute a gap-filling structure 160 contacting the conductive line BL.

[0035] Each of the isolation insulating pattern 124, the first gap-filling insulating pattern 126, and the second gap-filling insulating pattern 160A may include a silicon oxide film, a silicon nitride film, or a combination thereof. In some embodiments, the isolation insulating pattern 124, the first gap-filling insulating pattern 126, and the second gap-filling insulating pattern 160A may include materials that are the same or similar to each other, respectively. In some embodiments, at least one of the isolation insulating pattern 124, the first gap-filling insulating pattern 126, and the second gap-filling insulating pattern 160A may include a material different from the other. For example, each of the isolation insulating pattern 124, the first gap-filling insulating pattern 126, and the second gap-filling insulating pattern 160A may include, but is not limited to, a silicon nitride film.

[0036] The gate dielectric film 120 may be disposed between each of the plurality of word lines WL and the channel region CHL adjacent thereto. A pair of gate dielectric films 120 may be disposed between a pair of adjacent channel regions CHL, and a pair of word lines WL may be disposed between the pair of gate dielectric films 120. Each of the pair of gate dielectric films 120 may include one end contacting the conductive line BL and the other end contacting one contact plug 130 selected from the plurality of contact plugs 130.

[0037] One sidewall of the vertical contact portion DCV of each of the plurality of epitaxial direct contact plugs DC in the first horizontal direction (X direction) may contact the back gate dielectric film 152, and the other sidewall of the vertical contact portion DCV of each of the plurality of epitaxial direct contact plugs DC in the first horizontal direction (X direction) may contact the gate dielectric film 120. The width of the vertical contact portion DCV of each of the plurality of epitaxial direct contact plugs DC in the first horizontal direction (X direction) may be defined by the back gate dielectric film 152 and the gate dielectric film 120. The protruding contact portion DCP of each of the plurality of epitaxial direct contact plugs DC may protrude further toward the conductive line BL than the back gate dielectric film 152 and the gate dielectric film 120.

[0038] In some embodiments, at least a portion of the protruding contact portion DCP of each of the plurality of epitaxial direct contact plugs DC may have a width in the first horizontal direction (X direction) smaller than a width of the vertical contact portion DCV of each of the plurality of epitaxial direct contact plugs DC in the first horizontal direction (X direction).

[0039] The metal silicide film 164 may be disposed between each of the plurality of epitaxial direct contact plugs DC (eg, the protruding contact portion DCP of each of the plurality of epitaxial direct contact plugs DC) and the conductive line BL. The metal silicide film 164 may include, but is not limited to, TiSi, WSi, TaSi, CoSi, NiSi, or a combination thereof.

[0040] In some embodiments, each of the gate dielectric film 120 and the back gate dielectric film 152 may include a silicon oxide film, a high-K film, or a combination thereof. The high-K film refers to a film having a higher dielectric constant than that of the silicon oxide film. In some embodiments, each of the gate dielectric film 120 and the back gate dielectric film 152 may include one or more materials (such as, for example, silicon oxide, hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanate (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO) and / or lead scandium tantalum oxide (PbScTaO)). The plurality of back gate electrodes BG, the plurality of word lines WL, the plurality of channel regions CHL, the plurality of back gate dielectric films 152 , and the plurality of gate dielectric films 120 arranged between the plurality of conductive lines BL and the plurality of contact plugs 130 may form a plurality of vertical channel transistors.

[0041] like Figure 1 and Figure 2 As shown in , the capacitor structure 140 may be arranged on the plurality of contact plugs 130 and the interlayer dielectric 138. The capacitor structure 140 may include a plurality of lower electrodes 142, a capacitor dielectric film 144 conformally on a surface of each of the plurality of lower electrodes 142 and at least partially covering a surface of each of the plurality of lower electrodes 142, and an upper electrode 146 on the plurality of lower electrodes 142 and at least partially covering the plurality of lower electrodes 142, the capacitor dielectric film 144 being located between the upper electrode 146 and the plurality of lower electrodes 142. Each of the plurality of lower electrodes 142 may be connected to the channel region CHL via one contact plug 130 selected from the plurality of contact plugs 130. The third conductive pattern 136 of each of the plurality of contact plugs 130 may serve as a landing pad contacting one of the lower electrodes 142 selected from the plurality of lower electrodes 142.

[0042] Reference Figures 1 to 3 The described semiconductor memory device 100 includes a plurality of epitaxial direct contact plugs DC, which are contact structures that can be formed by a relatively low temperature process (e.g., a process performed at a temperature selected from a range of room temperature to about 480° C.) during a process of manufacturing the semiconductor memory device 100. Therefore, according to an embodiment of the inventive concept, thermal damage to a unit device in the semiconductor memory device 100 can be reduced or prevented, and a semiconductor memory device 100 having a structure with improved reliability can be provided. In addition, according to an embodiment of the inventive concept, each of the plurality of epitaxial direct contact plugs DC includes a protruding contact portion DCP at least partially surrounded by a conductive line BL. Therefore, each of the plurality of epitaxial direct contact plugs DC can have an increased contact area that can be electrically connected to the conductive line BL via a metal silicide film 164. In this way, the protruding contact portion DCP of each of the plurality of epitaxial direct contact plugs DC can provide a relatively large contact area, thereby providing a semiconductor memory device 100 having a structure with improved electrical characteristics.

[0043] Figure 4 is a cross-sectional view illustrating a semiconductor memory device 200 according to some embodiments. Figure 4 The semiconductor memory device 200 is shown in FIG. Figure 2 The enlarged cross-sectional configuration of the portion corresponding to the region EX1. Figure 4 In, with Figures 1 to 3 The same reference numerals respectively denote the same components, and repeated descriptions thereof are omitted here.

[0044] Reference Figure 4 , the semiconductor memory device 200 has the same Figure 1 and Figure 3 The semiconductor memory device 100 is described with substantially the same configuration. However, the semiconductor memory device 200 may include a back gate electrode BG2 and a first capping insulating pattern 258 .

[0045] The back gate electrode BG2 and the first capping insulating pattern 258 may have the same Figure 1 and Figure 3 The back gate electrode BG2 and the first capping insulating pattern 158 are described to have substantially the same configuration. However, a first vertical distance L21 from the vertical height of the plurality of contact plugs 130 to the back gate electrode BG2 may be equal to or similar to a second vertical distance L22 from the vertical height of the plurality of contact plugs 130 to the word line WL. In the vertical direction (Z direction), the length of the first capping insulating pattern 258 may be equal to or similar to the length of the first gap-filling insulating pattern 126.

[0046] Figure 5 is a cross-sectional view illustrating a semiconductor memory device 300 according to some embodiments. Figure 5 The semiconductor memory device 300 is shown Figure 2 The enlarged cross-sectional configuration of the portion corresponding to the region EX1. Figure 5 In, with Figures 1 to 3 The same reference numerals respectively denote the same components, and repeated descriptions thereof are omitted here.

[0047] Reference Figure 5 , the semiconductor memory device 300 has the same Figure 1 and Figure 3 However, the semiconductor memory device 300 may further include a spacer insulating pattern 324 between the word line WL and the isolation insulating pattern 124. In the first horizontal direction (X direction), the width of the spacer insulating pattern 324 may be smaller than the width of the isolation insulating pattern 124.

[0048] In some embodiments, the spacer insulating pattern 324 and the isolation insulating pattern 124 may include the same material. In some embodiments, the spacer insulating pattern 324 and the isolation insulating pattern 124 may include materials different from each other. In some embodiments, each of the spacer insulating pattern 324 and the isolation insulating pattern 124 may include one or more materials (such as, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and / or silicon boron nitride (SiBN), but embodiments of the inventive concept are not limited to the above materials.

[0049] Figure 6 is a cross-sectional view illustrating a semiconductor memory device 400 according to some embodiments. Figure 6The semiconductor memory device 400 is shown Figure 2 The enlarged cross-sectional configuration of the portion corresponding to the region EX1. Figure 6 In, with Figures 1 to 3 The same reference numerals respectively denote the same components, and repeated descriptions thereof are omitted here.

[0050] Reference Figure 6 , the semiconductor memory device 400 has the same Figure 1 and Figure 3 The semiconductor memory device 400 has substantially the same configuration as the semiconductor memory device 100 described above. However, the semiconductor memory device 400 includes a plurality of epitaxial direct contact plugs DC4 instead of a plurality of epitaxial direct contact plugs DC. The plurality of epitaxial direct contact plugs DC4 have the same configuration as the semiconductor memory device 100 described above. Figure 1 and Figure 3 The described multiple epitaxial direct contact plugs DC have basically the same configuration. However, each of the multiple epitaxial direct contact plugs DC4 includes a protruding contact portion DCP4 protruding toward the wire BL. The protruding contact portion DCP4 may have a facet (facet, or called end face, facet) F4 grown in the crystal direction of the semiconductor film constituting the epitaxial direct contact plug DC4, and the protruding contact portion DCP4 may have a cross-sectional shape that may be approximately triangular. The facet F4 of the protruding contact portion DCP4 may include an inclined surface inclined relative to each of the first horizontal direction (X direction) and the vertical direction (Z direction). The width of at least a portion of the protruding contact portion DCP4 of each of the multiple epitaxial direct contact plugs DC4 in the first horizontal direction (X direction) may be smaller than the width of the vertical contact portion DCV4 of each of the multiple epitaxial direct contact plugs DC4 in the first horizontal direction (X direction).

[0051] The metal silicide film 464 may be disposed between the protruding contact portion DCP4 of each of the plurality of epitaxial direct contact plugs DC4 and the conductive line BL. Figure 2 and Figure 3 The configuration of the metal silicide film 164 described is basically the same.

[0052] Figure 7 is a cross-sectional view illustrating a semiconductor memory device 500 according to some embodiments. Figure 7 The semiconductor memory device 500 is shown Figure 2 The enlarged cross-sectional configuration of the portion corresponding to the region EX1. Figure 7 In, with Figures 1 to 3 The same reference numerals respectively denote the same components, and repeated descriptions thereof are omitted here.

[0053] Reference Figure 7 , the semiconductor memory device 500 has the same Figure 1 and Figure 3 The semiconductor memory device 500 has substantially the same configuration as the semiconductor memory device 100 described above. However, the semiconductor memory device 500 includes a plurality of epitaxial direct contact plugs DC5 instead of a plurality of epitaxial direct contact plugs DC. The plurality of epitaxial direct contact plugs DC5 have the same configuration as the semiconductor memory device 100 described above. Figure 1 and Figure 3 The multiple epitaxial direct contact plugs DC5 described have substantially the same configuration. However, each of the multiple epitaxial direct contact plugs DC5 includes a protruding contact portion DCP5 protruding toward the wire BL. The protruding contact portion DCP5 may have a facet F5 grown in the crystal direction of the semiconductor film constituting the epitaxial direct contact plug DC5, and may have a cross-sectional shape that may be approximately quadrilateral. The facet F5 of the protruding contact portion DCP5 may include an inclined surface inclined relative to each of the first horizontal direction (X direction) and the vertical direction (Z direction). The width of a portion of the protruding contact portion DCP5 of each of the multiple epitaxial direct contact plugs DC5 in the first horizontal direction (X direction) may be greater than the width of the vertical contact portion DCV5 of each of the multiple epitaxial direct contact plugs DC5 in the first horizontal direction (X direction). The width of another portion of the protruding contact portion DCP5 of each of the multiple epitaxial direct contact plugs DC5 in the first horizontal direction (X direction) may be less than the width of the vertical contact portion DCV5 of each of the multiple epitaxial direct contact plugs DC5 in the first horizontal direction (X direction).

[0054] The metal silicide film 564 may be disposed between the protruding contact portion DCP5 of each of the plurality of epitaxial direct contact plugs DC5 and the conductive line BL. Figure 2 and Figure 3 The configuration of the metal silicide film 164 described is basically the same.

[0055] Figure 8 is a cross-sectional view illustrating a semiconductor memory device 600 according to some embodiments. Figure 8 The semiconductor memory device 600 is shown Figure 2 The enlarged cross-sectional configuration of the portion corresponding to the region EX1. Figure 8 In, with Figures 1 to 3 The same reference numerals respectively denote the same components, and repeated descriptions thereof are omitted here.

[0056] Reference Figure 8 , the semiconductor memory device 600 has a Figure 1 and Figure 3The semiconductor memory device 600 has substantially the same configuration as the semiconductor memory device 100 described above. However, the semiconductor memory device 600 includes a plurality of epitaxial direct contact plugs DC6 instead of a plurality of epitaxial direct contact plugs DC. The plurality of epitaxial direct contact plugs DC6 have the same configuration as the semiconductor memory device 100 described above. Figure 1 and Figure 3 The multiple epitaxial direct contact plugs DC described have substantially the same configuration. However, each of the multiple epitaxial direct contact plugs DC6 includes a protruding contact portion DCP6 protruding toward the wire BL. The protruding contact portion DCP6 may have a facet F6 grown in the crystal direction of the semiconductor film constituting the epitaxial direct contact plug DC6, and may have a cross-sectional shape that may be approximately octagonal. The facet F6 of the protruding contact portion DCP6 may include an inclined surface inclined relative to each of the first horizontal direction (X direction) and the vertical direction (Z direction). The width of a portion of the protruding contact portion DCP6 of each of the multiple epitaxial direct contact plugs DC6 in the first horizontal direction (X direction) may be greater than the width of the vertical contact portion DCV6 of each of the multiple epitaxial direct contact plugs DC6 in the first horizontal direction (X direction). The width of another portion of the protruding contact portion DCP6 of each of the multiple epitaxial direct contact plugs DC6 in the first horizontal direction (X direction) may be less than the width of the vertical contact portion DCV6 of each of the multiple epitaxial direct contact plugs DC6 in the first horizontal direction (X direction).

[0057] The metal silicide film 664 may be disposed between the protruding contact portion DCP6 of each of the plurality of epitaxial direct contact plugs DC6 and the conductive line BL. Figure 2 and Figure 3 The configuration of the metal silicide film 164 described is basically the same.

[0058] Fig. 9 is a cross-sectional view illustrating a semiconductor memory device 700 according to some embodiments. Fig. 9 The semiconductor memory device 700 is shown Figure 2 The enlarged cross-sectional configuration of the portion corresponding to the region EX1. Fig. 9 In, with Figures 1 to 3 The same reference numerals respectively denote the same components, and repeated descriptions thereof are omitted here.

[0059] Reference Fig. 9 , the semiconductor memory device 700 has the same Figure 1 and Figure 3 The semiconductor memory device 700 has substantially the same configuration as the semiconductor memory device 100 described above. However, the semiconductor memory device 700 includes a plurality of epitaxial direct contact plugs DC7 instead of a plurality of epitaxial direct contact plugs DC. The plurality of epitaxial direct contact plugs DC7 have the same configuration as the semiconductor memory device 100 described above. Figure 1and Figure 3 The described multiple epitaxial direct contact plugs DC7 have basically the same configuration. However, each of the multiple epitaxial direct contact plugs DC7 includes a protruding contact portion DCP7 protruding toward the conductive line BL. The protruding contact portion DCP7 may have a cross-sectional shape that may be approximately circular. The width of a portion of the protruding contact portion DCP7 of each of the multiple epitaxial direct contact plugs DC7 in the first horizontal direction (X direction) may be greater than the width of the vertical contact portion DCV7 of each of the multiple epitaxial direct contact plugs DC7 in the first horizontal direction (X direction). The width of another portion of the protruding contact portion DCP7 of each of the multiple epitaxial direct contact plugs DC7 in the first horizontal direction (X direction) may be less than the width of the vertical contact portion DCV7 of each of the multiple epitaxial direct contact plugs DC7 in the first horizontal direction (X direction).

[0060] The metal silicide film 764 may be disposed between the protruding contact portion DCP7 of each of the plurality of epitaxial direct contact plugs DC7 and the conductive line BL. Figure 2 and Figure 3 The configuration of the metal silicide film 164 described is basically the same.

[0061] Fig.10 is a cross-sectional view illustrating a semiconductor memory device 800 according to some embodiments. Fig.10 The semiconductor memory device 800 is shown Figure 2 The enlarged cross-sectional configuration of the portion corresponding to the region EX1. Fig.10 In, with Figures 1 to 3 The same reference numerals respectively denote the same components, and repeated descriptions thereof are omitted here.

[0062] Reference Fig.10 , the semiconductor memory device 800 has the same Figure 1 and Figure 3 The semiconductor memory device 800 is described as having substantially the same configuration as the semiconductor memory device 100. However, the semiconductor memory device 800 includes a channel region CHL8 instead of the channel region CHL, and includes a plurality of epitaxial direct contact plugs DC8 instead of the plurality of epitaxial direct contact plugs DC.

[0063] The channel region CHL8 may have a shape that protrudes further toward the conductive line BL than the back gate electrode BG and the word line WL. The plurality of epitaxial direct contact plugs DC8 have the same Figure 1 and Figure 3The multiple epitaxial direct contact plugs DC8 described have substantially the same configuration. However, each of the multiple epitaxial direct contact plugs DC8 may include a contact surface DCC8 in contact with the channel region CHL8, a protruding contact portion DCP8 surrounded by the conductive line BL, and a vertical contact portion DCV8 extending in a vertical direction (Z direction) between the contact surface DCC8 and the protruding contact portion DCP8. The contact surface DCC8 of the epitaxial direct contact plug DC8 may be closer to the conductive line BL than the back gate electrode BG and the word line WL.

[0064] Reference Figures 4 to 10 The described semiconductor memory devices 200, 300, 400, 500, 600, 700, and 800 include a plurality of epitaxial direct contact plugs DC, DC4, DC5, DC6, DC7, and DC8, respectively, which are contact structures that can be formed by a relatively low temperature process (e.g., a process performed at a temperature selected from a range of room temperature to about 480° C.) during a process of manufacturing each of the semiconductor memory devices 200, 300, 400, 500, 600, 700, and 800. Therefore, according to an embodiment of the inventive concept, thermal damage to a unit device in each of the semiconductor memory devices 200, 300, 400, 500, 600, 700, and 800 can be reduced or prevented, and semiconductor memory devices 200, 300, 400, 500, 600, 700, and 800 each having a structure with improved reliability can be provided. In addition, according to an embodiment of the inventive concept, a plurality of epitaxial direct contact plugs DC, DC4, DC5, DC6, DC7, and DC8 include protruding contact portions DCP, DCP4, DCP5, DCP6, DCP7, and DCP8, respectively, which are at least partially surrounded by the conductive line BL. Therefore, each epitaxial direct contact plug DC, DC4, DC5, DC6, DC7, or DC8 may have an increased contact area that may be electrically connected to the conductive line BL via the metal silicide film 164, 464, 564, 664, or 764. In this way, since the protruding contact portion DCP, DCP4, DCP5, DCP6, DCP7, or DCP8 of each epitaxial direct contact plug DC, DC4, DC5, DC6, DC7, or DC8 provides a relatively large contact area, semiconductor memory devices 200, 300, 400, 500, 600, 700, and 800 each having a structure with improved electrical characteristics may be provided. Next, a method for manufacturing a semiconductor memory device according to some embodiments is described by way of specific examples.

[0065] FIG. 11A to FIG. 28B are diagrams respectively illustrating a process sequence of a method for manufacturing a semiconductor memory device according to some embodiments. Specifically, Fig.11A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.19A , Fig.22A , Fig.23A and Fig.28A are plan layout diagrams each showing some components of a semiconductor memory device according to a process sequence to describe an example method of manufacturing a semiconductor memory device. Fig. 11B , Fig.12 , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18 , Fig.19B , Fig. 20 , Fig.21 , Fig. 22B , Fig. 23B , Fig.24 , Fig.25 , Fig.26 , Fig. 27 and Fig.28B are shown according to the process sequence and along Figure 1 A cross-sectional view of a portion of a semiconductor memory device corresponding to a cross-sectional view taken along line X1-X1' in FIG. Fig. 11B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.19B , Fig. 22B , Fig. 23B and Fig.28B Along the Fig.11A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.19A , Fig.22A , Fig.23A and Fig.28A A cross-sectional view taken along the line X1-X1'. FIG. 11A to FIG. 28B Description Made in Figures 1 to 3 An example of a method of a semiconductor memory device 100 is shown in FIG. FIG. 11A to FIG. 28B In, with Figures 1 to 3 The same reference numerals respectively denote the same components, and repeated descriptions thereof are omitted here.

[0066] Reference Fig.11A and Fig. 11B , a substrate structure including a substrate 102 , a gap-filling insulating layer 104 , and an active layer 106 may be prepared.

[0067] The substrate structure may include a silicon-on-insulator (SOI) substrate. The substrate 102 may include a silicon substrate. The gap-filling insulating layer 104 may include a silicon oxide film. The active layer 106 may include one or more materials (such as, for example, Ge, SiGe, SiC, GaAs, InAs and / or InP). In some embodiments, the active layer 106 may include an impurity-doped well or an impurity-doped structure.

[0068] The mask pattern MP1 may be formed on the active layer 106 of the base structure. The mask pattern MP1 may include a silicon nitride film. In some embodiments, an oxide film may be disposed between the active layer 106 and the mask pattern MP1.

[0069] A plurality of first trenches T1 may be formed by etching portions of the substrate structure using the mask pattern MP1 as an etching mask. The plurality of first trenches T1 may be formed to pass through the active layer 106 and the gap-filling insulating layer 104 in a vertical direction (Z direction) and to extend longitudinally in a second horizontal direction (Y direction).

[0070] Reference Fig.12 ,exist Fig.11A and Fig. 11B In the resulting product, a back gate dielectric film 152 and a back gate conductive layer BGL may be formed, the back gate dielectric film 152 conformally at least partially covers the inner walls of the plurality of first trenches T1 and the surface of each mask pattern MP1, and the back gate conductive layer BGL is arranged on the back gate dielectric film 152 to at least partially fill the plurality of first trenches T1. The constituent material of the back gate conductive layer BGL may be substantially the same as the constituent material of the above-mentioned back gate electrode BG.

[0071] Reference Fig.13A and Fig. 13B ,exist Fig.12 In the resulting product, the back gate conductive layer BGL can be etched back to form a plurality of back gate electrodes BG in the plurality of first trenches T1, respectively, and then the upper space of each of the plurality of first trenches T1 is at least partially filled with the first capping insulating pattern 158, and then the resulting product can be planarized to at least partially expose the upper surface of the mask pattern MP1.

[0072] Reference Fig.14A and Fig. 14B , can be obtained from Fig.13A and Fig. 13B The mask pattern MP1 is removed from the resultant product, thereby at least partially exposing the active layer 106 around the plurality of first capping insulating patterns 158 and the plurality of back gate dielectric films 152 .

[0073] Reference Fig.15A and Fig. 15B, a plurality of spacer layers SPL may be formed on a portion of each of the plurality of first capping insulating patterns 158 and the plurality of back gate dielectric films 152 and a portion of the active layer 106 surrounding each of the plurality of first capping insulating patterns 158 and the plurality of back gate dielectric films 152, and may at least partially cover a portion of each of the plurality of first capping insulating patterns 158 and the plurality of back gate dielectric films 152 and a portion of the active layer 106 surrounding each of the plurality of first capping insulating patterns 158 and the plurality of back gate dielectric films 152. Each of the plurality of spacer layers SPL may include a silicon oxide film. The plurality of spacer layers SPL may include a first group of spacer layers SPL and a second group of spacer layers SPL, the first group of spacer layers SPL being arranged in a line in a first horizontal direction (X direction) and being spaced apart from each other in the first horizontal direction (X direction), and the second group of spacer layers SPL being arranged in a line in a second horizontal direction (Y direction) and being spaced apart from each other in the second horizontal direction (Y direction).

[0074] Reference Fig.16A and Fig. 16B , the plurality of spacer layers SPL may be etched back to form a plurality of spacers SP, the plurality of spacers SP respectively at least partially covering both sidewalls of each of the plurality of structures in the first horizontal direction (X direction), each of the plurality of structures including the first capping insulating pattern 158 and the back gate dielectric film 152. Portions of the upper surface of the active layer 106 adjacent to each of the plurality of structures may be at least partially covered by the plurality of spacers SP, respectively.

[0075] Reference Fig.17A and Fig. 17B , the active layer 106 may be etched using the plurality of first capping insulating patterns 158, the plurality of back gate dielectric films 152, and the plurality of spacers SP as etching masks, thereby forming a plurality of second trenches T2. Therefore, portions of the active layer 106 respectively located under the plurality of spacers SP may be respectively retained as a plurality of channel regions CHL. Due to over-etching during the process of etching the active layer 106, the gap-filling insulating layer 104 may be partially etched, and therefore, a plurality of recessed regions 104R may be formed in the upper surface of the gap-filling insulating layer 104 and may be respectively electrically connected to the plurality of second trenches T2.

[0076] Reference Fig.18 , the gate dielectric film 120 may be formed to conformally at least partially cover Fig.17A and Fig. 17BThe resulting product is then formed into a conductive layer to conformally at least partially cover the gate dielectric film 120, and then a portion of the conductive layer in each recessed region 104R of the gap-filling insulating layer 104 may be etched, thereby dividing the conductive layer into a plurality of preliminary word lines PWL. Next, an isolation insulating pattern 124 may be formed to at least partially fill the space above each of the plurality of preliminary word lines PWL. The isolation insulating pattern 124 may be formed to at least partially fill each space between the plurality of preliminary word lines PWL and at least partially cover the upper surface of each of the plurality of preliminary word lines PWL. The constituent material of the conductive layer may be the same as the constituent material of the above-mentioned word lines WL.

[0077] Reference Fig.19A and Fig.19B ,exist Fig.18 In the resulting product, each of the plurality of preliminary word lines PWL may be partially exposed by etching back the isolation insulating pattern 124 so that an upper portion of the isolation insulating pattern 124 is removed, and each of the exposed plurality of preliminary word lines PWL may be etched to form a plurality of word lines WL.

[0078] Reference Fig. 20 , the first gap-filling insulating film 126L may be formed to at least partially cover Fig.19A and Fig.19B The constituent material of the first gap-filling insulating film 126L may be the same as the constituent material of the first gap-filling insulating pattern 126 described above.

[0079] Reference Fig.21 , the exposed upper surface of the first gap-filling insulating film 126L may be Fig. 20 The resulting product is subjected to a planarization process, thereby exposing the plurality of channel regions CHL, and forming a first gap-filling insulating pattern 126 from the first gap-filling insulating film 126L. After exposing the plurality of channel regions CHL, the Fig. 20 The height of the top of each of the first capping insulating pattern 158, the plurality of back gate dielectric films 152, and the gate dielectric film 120 in a resulting product of .

[0080] Reference Fig.22A and Fig. 22B ,exist Fig.21 In the resulting product, a plurality of contact plugs 130 may be formed on the plurality of channel regions CHL, respectively, and an interlayer dielectric 138 may be formed to at least partially fill each space between the plurality of contact plugs 130 .

[0081] Reference Fig.23A and Fig. 23B , the capacitor structure 140 may be formed at Fig.22A and 22BThe resultant product may be connected to the plurality of contact plugs 130 .

[0082] Reference Fig.24 , by Fig.23A and Fig. 23B The resulting product is inverted, and the substrate 102 can be facing upward in the vertical direction (Z direction), so that Fig.23A and Fig. 23B The directions in which the upper and lower portions of the resulting product face in the vertical direction (Z direction) are respectively changed to be opposite to each other, and a grinding process and a wet etching process may be sequentially performed on the substrate 102 in the stated order from the exposed backside surface of the substrate 102 so that the gap-filling insulating layer 104 is at least partially exposed.

[0083] Reference Fig.25 ,exist Fig.24 In the resulting product, a plurality of spaces may be prepared by removing a portion of each of the plurality of back gate electrodes BG and the plurality of word lines WL that are at least partially exposed, and a plurality of second gap-filling insulating patterns 160A and a plurality of second capping insulating patterns 160B may be formed to at least partially fill the plurality of spaces. The plurality of second gap-filling insulating patterns 160A and the plurality of second capping insulating patterns 160B may form a gap-filling structure 160.

[0084] Reference Fig.26 ,exist Fig.25 In the resulting product, a portion of each of the exposed plurality of channel regions CHL may be removed by an etch-back process, thereby preparing a plurality of contact spaces CT.

[0085] Reference Fig. 27 ,exist Fig.26 In the resulting product, an epitaxial growth process may be performed on the plurality of channel regions CHL exposed through the plurality of contact spaces CT, thereby forming a plurality of epitaxial direct contact plugs DC. During the formation of the plurality of epitaxial direct contact plugs DC, an impurity doping process may be performed through an in-situ doping process, thereby forming a plurality of epitaxial direct contact plugs DC each including a doped semiconductor film. By controlling various process conditions while performing the epitaxial growth process, a semiconductor device having Figure 2 and Figure 3 The epitaxial direct contact plug DC of the shape shown in FIG. Figure 6 The epitaxial direct contact plug DC4 of the shape shown in FIG. Figure 7 The epitaxial direct contact plug DC5 of the shape shown in FIG. Figure 8 The epitaxial direct contact plug DC6 of the shape shown in FIG. Fig. 9 The epitaxial direct contact plug DC7 of the shape shown in FIG. 1 or epitaxial direct contact plugs of various shapes modified and changed therefrom without departing from the scope of the inventive concept.

[0086] The epitaxial growth process for forming the plurality of epitaxial direct contact plugs DC may be performed at a relatively low process temperature selected from room temperature to about 480° C. Therefore, other components are not thermally damaged during the formation of the plurality of epitaxial direct contact plugs DC.

[0087] Reference Fig.28A and Fig.28B ,exist Fig. 27 In the resulting product, the metal silicide film 164 and the conductive line BL may be formed to at least partially cover the surface of each of the exposed plurality of epitaxial direct contact plugs DC, thereby manufacturing Figures 1 to 3 A semiconductor memory device 100 is shown in FIG.

[0088] Fig.29 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to some embodiments. Fig.29 Shows the manufacturing process and along Figure 1 The cross-section taken along the line X1-X1' corresponds to the cross-sectional configuration of a portion of the semiconductor memory device. Fig.29 Description Manufacturing Figure 5 An example of a method of a semiconductor memory device 300 is shown in FIG. Fig.29 In, with Figures 1 to 28B The same reference numerals respectively denote the same components, and repeated descriptions thereof are omitted here.

[0089] Reference Fig.29 , you can execute the reference FIG. 11A to FIG. 18 However, in accordance with reference Fig.18 After forming a conductive layer to conformally at least partially cover the gate dielectric film 120 by the process described above, and before etching a portion of the conductive layer in the recessed region 104R of the gap-fill insulating layer 104, the conductive layer may be formed as shown in FIG. Fig.29 As shown in FIG. 1 , a spacer insulating pattern 324 is formed to at least partially cover a sidewall of the conductive layer, and the conductive layer may be etched by using the spacer insulating pattern 324 as an etch mask, thereby dividing the conductive layer into a plurality of preliminary word lines PWL.

[0090] Next, while the spacer insulating pattern 324 remains on the sidewall of each of the plurality of preliminary word lines PWL, a reference FIG. 19A to FIG. 28B Described process, thereby manufacturing Figure 5 A semiconductor memory device 300 is shown in FIG.

[0091] So far, although reference has been made to FIG. 11A to FIG. 29 Describes the manufacturing Figures 1 to 3 and Figure 5The examples of the methods of the semiconductor memory devices 100 and 300 are shown in FIG. 1 , but those skilled in the art will appreciate that the present invention can be described in detail by referring to the references without departing from the spirit and scope of the inventive concept. FIG. 11A to FIG. 29 Various modifications and changes can be made to the examples described to produce Figures 1 to 3 and Figure 5 The semiconductor memory devices 100 and 300 shown in FIG. 1 are modified and changed semiconductor memory devices of various structures.

[0092] While embodiments of the inventive concepts have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device, comprising: A conductor extending longitudinally in a first direction; a plurality of channel regions arranged above the conductive line and spaced apart from each other in a first direction, each of the plurality of channel regions being configured to be electrically connected to the conductive line; a back gate electrode spaced apart from the conductive line in a third direction and extending in a second direction between a first channel region and a second channel region, the first channel region and the second channel region being selected from the plurality of channel regions and adjacent to each other, the first direction, the second direction, and the third direction being perpendicular to each other; a pair of word lines spaced apart from each other in a first direction and arranged between a second channel region and a third channel region, the second channel region and the third channel region being selected from the plurality of channel regions and adjacent to each other; as well as A plurality of epitaxial direct contact plugs are extended in a third direction between the plurality of channel regions and the conductive lines, each of the plurality of epitaxial direct contact plugs comprising: a contact surface contacting one of the plurality of channel regions, a protruding contact portion at least partially surrounded by the conductive lines, and a vertical contact portion extending in the third direction between the contact surface and the protruding contact portion.

2. The semiconductor memory device according to claim 1, wherein Each of the plurality of epitaxial direct contact plugs includes a semiconductor film doped with a dopant.

3. The semiconductor memory device according to claim 1, wherein: A height of an end of each of the plurality of channel regions closest to the conductive line is separated from a height of a surface of the conductive line closest to the back gate electrode in the third direction.

4. The semiconductor memory device according to claim 1, wherein: Each of the pair of word lines and the back gate electrode has an end surface facing the conductive line and closest to the conductive line, and A height of the end surface of each of the pair of word lines and the back gate electrode is spaced apart from a height of a surface of the conductive line closest to the back gate electrode in the third direction.

5. The semiconductor memory device according to claim 1, further comprising: a back gate dielectric film, between the second channel region and the back gate electrode; as well as a gate dielectric film between a first word line closer to the second channel region in the pair of word lines and the second channel region, wherein each of the back gate dielectric film and the gate dielectric film is in contact with the conductive line, and The width of the vertical contact portion of each of the plurality of epitaxial direct contact plugs in the first direction is defined by the back gate dielectric film and the gate dielectric film.

6. The semiconductor memory device according to claim 1, further comprising: a back gate dielectric film, between the second channel region and the back gate electrode; as well as a gate dielectric film between a first word line closer to the second channel region in the pair of word lines and the second channel region, The first sidewall of the vertical contact portion of each of the plurality of epitaxial direct contact plugs in the first direction contacts the back gate dielectric film, and the second sidewall of the vertical contact portion of each of the plurality of epitaxial direct contact plugs in the first direction contacts the gate dielectric film.

7. The semiconductor memory device according to claim 1, further comprising: A plurality of metal silicide films are respectively arranged between the plurality of epitaxial direct contact plugs and the conductive lines.

8. The semiconductor memory device according to claim 1, wherein: Each of the plurality of epitaxial direct contact plugs includes a semiconductor film, and wherein the protruding contact portion of each of the plurality of epitaxial direct contact plugs has a facet grown in a crystal direction of the semiconductor film.

9. The semiconductor memory device according to claim 1, wherein: Each of the plurality of epitaxial direct contact plugs includes a semiconductor film, and Wherein, the protruding contact portion of each of the plurality of epitaxial direct contact plugs includes an inclined surface inclined with respect to each of the first direction and the third direction.

10. The semiconductor memory device according to claim 1, wherein In each of the plurality of epitaxial direct contact plugs, a width of at least a portion of the protruding contact portion in the first direction is smaller than a width of the vertical contact portion in the first direction.

11. The semiconductor memory device according to claim 1, wherein: In each of the plurality of epitaxial direct contact plugs, a width of at least a portion of the protruding contact portion in the first direction is greater than a width of the vertical contact portion in the first direction.

12. The semiconductor memory device according to any one of claims 1 to 11, further comprising: a plurality of contact plugs spaced apart from the conductive line in a third direction, wherein the plurality of channel regions are located between the plurality of contact plugs and the conductive line, and each of the plurality of contact plugs contacts one channel region selected from the plurality of channel regions, The back gate electrode has a first end surface facing the plurality of contact plugs and a second end surface facing the wires, and The distance between the surface of the back gate electrode closest to the contact plugs and the contact plugs in the third direction is greater than the distance between the surface of the pair of word lines closest to the contact plugs and the contact plugs in the third direction.

13. A semiconductor memory device, comprising: A conductor extending longitudinally in a first direction; a plurality of channel regions arranged to be spaced apart from each other in a first direction and spaced apart from the conductive line in a third direction; a plurality of contact plugs spaced apart from the conductive lines in a third direction, wherein the plurality of channel regions are located between the plurality of contact plugs and the conductive lines; a back gate electrode spaced apart from the conductive line in the third direction and extending longitudinally in the second direction between a first channel region and a second channel region, the first channel region and the second channel region being selected from the plurality of channel regions and adjacent to each other, the first direction, the second direction, and the third direction being perpendicular to each other; a back gate dielectric film disposed between the back gate electrode and the second channel region and contacting each of the back gate electrode and the second channel region; a word line spaced apart from the back gate electrode in a first direction, wherein the second channel region is located between the word line and the back gate electrode; a gate dielectric film disposed between the word line and the second channel region and contacting each of the word line and the second channel region; and An epitaxial direct contact plug extends in a third direction between the first channel region and the conductive line, the epitaxial direct contact plug comprising: a contact surface contacting the first channel region, a protruding contact portion at least partially surrounded by the conductive line, and a sidewall extending in the third direction between the contact surface and the protruding contact portion and contacting each of the back gate dielectric film and the gate dielectric film.

14. The semiconductor memory device according to claim 13, wherein: The epitaxial direct contact plug includes a silicon film doped with a dopant.

15. The semiconductor memory device according to claim 13, wherein: Each of the back gate electrode and the word line has an end surface facing the conductive line and closest to the conductive line, and The end surfaces of the back gate electrode and each of the word lines are spaced apart in height from a height of a surface of the conductive line closest to the back gate electrode in the third direction.

16. The semiconductor memory device according to claim 13, wherein: Each of the back gate dielectric film and the gate dielectric film is in contact with the conductive line, and Among them, the epitaxial direct contact plug protrudes further toward the conductive line than the back gate dielectric film and the gate dielectric film.

17. The semiconductor memory device according to claim 13, further comprising: Metal silicide film, between the epitaxial direct contact plug and the conductive line.

18. The semiconductor memory device according to claim 13, wherein: The epitaxial direct contact plug includes a doped silicon film, and Therein, the protruding contact portion of the epitaxial direct contact plug has a facet grown in the crystal direction of the doped silicon film.

19. The semiconductor memory device according to claim 13, wherein: The epitaxial direct contact plug includes a doped silicon film, and Wherein, the protruding contact portion of the epitaxial direct contact plug includes an inclined surface inclined with respect to each of the first direction and the third direction.

20. A semiconductor memory device, comprising: a plurality of conductive lines extending longitudinally in a first direction and spaced apart from one another in a second direction; a plurality of contact plugs spaced apart from the plurality of conductive lines in a third direction, the first direction, the second direction, and the third direction being perpendicular to each other; a plurality of channel regions arranged between the plurality of conductive lines and the plurality of contact plugs, the plurality of channel regions each having one end spaced apart from the plurality of conductive lines in a third direction and another end connected to one contact plug selected from the plurality of contact plugs; a plurality of back gate electrodes spaced apart from each other in the first direction and extending longitudinally in the second direction between the plurality of conductive lines and the plurality of contact plugs; A plurality of back-gate dielectric films, respectively contacting the plurality of back-gate electrodes; a plurality of word lines extending longitudinally in a second direction between the plurality of conductive lines and the plurality of contact plugs; A plurality of gate dielectric films respectively contacting the plurality of word lines; as well as A plurality of epitaxial direct contact plugs extend in a third direction between the plurality of channel regions and the plurality of conductive lines, each of the plurality of epitaxial direct contact plugs comprising: a contact surface contacting one channel region selected from the plurality of channel regions, a protruding contact portion at least partially surrounded by one conductive line selected from the plurality of conductive lines, and a sidewall extending in the third direction between the contact surface and the protruding contact portion and contacting each of one back gate dielectric film selected from the plurality of back gate dielectric films and one gate dielectric film selected from the plurality of gate dielectric films.

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