Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes: a plurality of trenches including a plurality of first trenches in a substrate and a plurality of second trenches between respective ones of the plurality of first trenches; and a plurality of device isolation layers. A first height in the vertical direction of the lowermost surface of the direct contact of the semiconductor memory device may be higher than a second height in the vertical direction of the lowermost surface of the buried contact of the semiconductor memory device with respect to the lower surface of the substrate.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor memory device. Background Art

[0002] With the rapid development of the electronics industry and user needs, electronic devices have become smaller and lighter. Therefore, semiconductor devices with high integration are required for use in electronic devices, and thus the design rules for components of semiconductor devices have been reduced. As a result, the complexity of the manufacturing process for ensuring the connection reliability between conductive patterns constituting semiconductor devices has gradually increased.

[0003] As the integration degree of semiconductor devices gradually increases, a semiconductor device structure having a buried cell array transistor (BCAT) having a structure in which a plurality of word lines are buried in a substrate has been proposed. Summary of the invention

[0004] The inventive concept provides a semiconductor memory device having improved reliability in control of a gate electrode.

[0005] According to aspects of the inventive concept, a semiconductor memory device is provided, the semiconductor memory device comprising: a plurality of trenches, including a plurality of first trenches in a substrate and a plurality of second trenches between corresponding first trenches in the plurality of first trenches; a plurality of device isolation layers, including first device isolation layers and second device isolation layers respectively in the plurality of first trenches and third device isolation layers respectively in the plurality of second trenches; a plurality of active regions defined by the plurality of device isolation layers; word lines on the plurality of active regions; a plurality of direct contacts electrically connecting the word lines to the plurality of active regions; a plurality of buried contacts between corresponding direct contacts in the plurality of direct contacts; and a plurality of fins, corresponding direct contacts in the plurality of direct contacts and the plurality of fins. between corresponding buried contacts in the buried contacts, wherein corresponding widths of the plurality of first trenches in the first direction and the second direction are greater than corresponding widths of the plurality of second trenches in the first direction and the second direction, wherein the first direction and the second direction are parallel to the lower surface of the substrate, wherein the second direction is perpendicular to the first direction, wherein corresponding depths of the plurality of first trenches in the vertical direction are greater than corresponding depths of the plurality of second trenches in the vertical direction, wherein the vertical direction is perpendicular to the lower surface of the substrate, wherein the vertical direction is perpendicular to the first direction and the second direction, and wherein relative to the lower surface of the substrate, corresponding first heights of lowermost surfaces of the plurality of direct contacts in the vertical direction are higher than corresponding second heights of lowermost surfaces of the plurality of buried contacts in the vertical direction.

[0006] According to aspects of the inventive concept, a semiconductor memory device is provided, comprising: a plurality of grooves, including a plurality of first grooves in a substrate and a plurality of second grooves between corresponding first grooves in the plurality of first grooves; a plurality of device isolation layers, including first device isolation layers and second device isolation layers respectively in the plurality of first grooves and third device isolation layers respectively in the plurality of second grooves; a plurality of active areas, defined by the plurality of device isolation layers; word lines, on the plurality of active areas; a plurality of direct contacts, electrically connecting the word lines to the plurality of active areas; and a plurality of buried contacts, between corresponding direct contacts in the plurality of direct contacts, wherein in a plan view: the plurality of active areas extend diagonally relative to a first direction and a second direction perpendicular to the first direction, each of the plurality of active areas comprises longitudinal sides opposite to each other and lateral sides opposite to each other, at least portions of the longitudinal sides respectively comprising protrusions protruding outward in the direction in which the lateral sides extend.

[0007] According to aspects of the inventive concept, there is provided a semiconductor memory device, the semiconductor memory device comprising: a plurality of trenches, including a plurality of first trenches in a substrate and a plurality of second trenches between corresponding first trenches in the plurality of first trenches; a plurality of device isolation layers, including first device isolation layers and second device isolation layers respectively in the plurality of first trenches and third device isolation layers respectively in the plurality of second trenches; a plurality of active regions defined by the plurality of device isolation layers; word lines on the plurality of active regions; a plurality of direct contacts electrically connecting the word lines to the plurality of active regions; a plurality of buried contacts between corresponding direct contacts in the plurality of direct contacts; a plurality of fins, corresponding direct contacts in the plurality of direct contacts and between corresponding buried contacts of the plurality of buried contacts; and a word line lower layer, on a lowermost surface of the word line and between the word line and the plurality of fins, wherein corresponding widths of the plurality of first trenches in a first direction and a second direction are greater than corresponding widths of the plurality of second trenches in the first direction and the second direction, wherein the first direction and the second direction are parallel to a lower surface of the substrate, wherein the second direction is perpendicular to the first direction, wherein corresponding depths of the plurality of first trenches in a vertical direction are greater than corresponding depths of the plurality of second trenches in a vertical direction, wherein the vertical direction is perpendicular to the lower surface of the substrate, wherein the vertical direction is perpendicular to the first direction and the second direction, wherein when a minimum spacing between adjacent conductive lines included in the semiconductor memory device is F, a minimum spacing in the first direction between central axes of a pair of adjacent fins among the plurality of fins is greater than 2F and less than 4F, spacings in the first direction between central axes of adjacent fins among the plurality of fins are different from each other, at least one of the plurality of fins extends in a vertical direction from a first point to a second point, the first point being equal to 1 / 2 of a sum of a first height of a lowermost surface of one of the plurality of direct contacts and a second height of a lowermost surface of one of the plurality of buried contacts, the second point being equal to a level of an uppermost surface of the substrate, the first height and the second height being taken in a vertical direction relative to a lower surface of the substrate, at least portions of outer surfaces of the plurality of fins respectively having a rounded shape, and the plurality of fins The upper surfaces in the vertical direction respectively include vertices of the rounded shape, the wordline lower layer includes an insulating material, at least a portion of the wordline lower layer has a rounded shape surrounding the plurality of fins, at least another portion of the wordline lower layer has a flat shape in the first direction and the second direction, first portions of the wordline lower layer are respectively on the plurality of fins, second portions of the wordline lower layer are respectively on the first device isolation layer, third portions of the wordline lower layer are respectively on the third device isolation layer, respective third heights of the first portions of the wordline lower layer in the vertical direction are equal to each other relative to the lower surface of the substrate, respective fourth heights of the second portions of the wordline lower layer in the vertical direction are different from respective fifth heights of the third portions of the wordline lower layer in the vertical direction relative to the lower surface of the substrate,The respective widths of the second portion of the word line lower layer in the first direction and the second direction are equal to the respective widths of the plurality of first trenches in the first direction and the second direction, the respective widths of the third portion of the word line lower layer in the first direction and the second direction are equal to the respective widths of the plurality of second trenches in the first direction and the second direction, the second portion of the word line lower layer is in contact with the plurality of first trenches, respectively, the third portion of the word line lower layer is in contact with the plurality of second trenches, respectively, the plurality of device isolation layers have a tapered shape so that the respective widths of the plurality of device isolation layers in each of the first direction and the second direction become narrower as the distance from the lower surface of the substrate in the vertical direction decreases, the plurality of device isolation layers include silicon oxide, silicon nitride, or a combination thereof, at least one of the first device isolation layers and at least one of the second device isolation layers include materials different from each other, the second device isolation layers are respectively inside the first device isolation layers, and relative to the lower surface of the substrate, a first height of a lowermost surface of the one of the plurality of direct contacts is higher than a second height of a lowermost surface of the one of the plurality of buried contacts. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B are diagrams showing sequential processes of a method of manufacturing a semiconductor memory device according to some embodiments;

[0010] Fig. 6A is a layout diagram showing main components of a semiconductor memory device according to some embodiments;

[0011] Figure 6B is a cross-sectional view showing a semiconductor memory device according to some embodiments;

[0012] Figure 7 is a block diagram illustrating an example configuration of a semiconductor device according to some embodiments;

[0013] Figure 8 is a plan view showing an arrangement configuration of a semiconductor memory device according to some embodiments;

[0014] Fig. 9 is a block diagram illustrating a system including a semiconductor memory device according to some embodiments; and

[0015] Fig.10 is a block diagram illustrating a memory card including a semiconductor memory device according to some embodiments. DETAILED DESCRIPTION

[0016] The embodiments described herein may have various modifications and various forms, and therefore, some embodiments will be shown in the drawings and described in detail. However, this is not intended to limit the embodiments to the specific disclosed forms. In addition, the embodiments described below are merely illustrative, and various modifications may be made from these embodiments.

[0017] All examples or illustrative terms are used only to describe the inventive concept in detail, and thus the scope of the inventive concept shall not be limited by these examples or illustrative terms unless limited by the claims.

[0018] Hereinafter, unless otherwise specified, a horizontal direction is described as a first direction X and a second direction Y perpendicular to the first direction X, and a vertical direction is described as a perpendicular direction Z perpendicular to the first direction X and the second direction Y.

[0019] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B are diagrams illustrating sequential processes of a method of manufacturing a semiconductor memory device according to some embodiments.

[0020] Specifically, Figure 1A , Figure 2A , Figure 3A , Figure 4A and Figure 5A are plan views showing sequential processes of a method of manufacturing an integrated circuit device. Figure 1B , Figure 2B , Figure 3B , Figure 4B and Figure 5B are along the Figure 1A , Figure 2A , Figure 3A , Figure 4A and Figure 5A A cross-sectional view taken at a position corresponding to line II'.

[0021] Reference Figure 1A and Figure 1B On the substrate 2, the first member 111 and the second member 113 can be formed by a photolithography process, and a groove T can be formed (see Figure 3B). A trench T may be formed therein (see Figure 3B ) is formed in the region of the substrate 2. The first layer 115 may be formed to surround the side surfaces and / or upper surfaces of the first and second members 111 and 113 and the substrate 2 in which the trench T is to be formed (see Figure 3B ) area. It will be understood that "element A surrounds element B" (or similar language) as used herein means that element A is at least partially around element B, but does not necessarily mean that element A completely surrounds element B. The first member 111 can be attached (i.e., connected) to the upper surface of the substrate 2, and the second member 113 can be attached (i.e., connected) to the upper surface of the first member 111 in the vertical direction Z. As used herein, "element A is connected to element B" (or similar language) means that element A is physically and / or electrically connected to element B. The first member 111 and the second member 113 may include a plurality of strips extending diagonally relative to the first direction X and the second direction Y. In other words, the first member 111 and the second member 113 may extend in a third direction having a specific tilt angle α (i.e., a specific angle α) relative to the second direction Y. The specific tilt angle α can be formed in the range of about 20 degrees to about 40 degrees, but is not limited thereto. For example, the first direction X and the second direction Y may be parallel to the lower surface of the substrate 2, and the vertical direction Z may be perpendicular to the lower surface of the substrate 2.

[0022] The first member 111 and the second member 113 may include an insulating material, and the first member 111 and the second member 113 may include different materials. For example, the first member 111 and the second member 113 may include SiN, SiO, SiON, SiOC, metal oxide, or a combination thereof.

[0023] The first layer 115 on at least a portion of the side surface of the first member 111, at least a portion of the upper surface of the second member 113, and at least a portion of the upper surface of the substrate 2 (e.g., covering at least a portion of the side surface of the first member 111, at least a portion of the upper surface of the second member 113, and at least a portion of the upper surface of the substrate 2) can protect the substrate 2 from external foreign matter, etc. In addition, the first layer 115 can be used as an etching stop layer in an etching process for different types of material layers in subsequent processes. Figure 3B ) may be formed in the substrate 2 to penetrate the first layer 115 (ie, extend into the first layer 115).

[0024] In some embodiments, the substrate 2 may be a semiconductor wafer. In some embodiments, the substrate 2 may include silicon (Si). In some other embodiments, the substrate 2 may include a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the substrate 2 may have a silicon-on-insulator (SOI) structure. For example, the substrate 2 may include a buried oxide (BOX) layer. In some embodiments, the substrate 2 may include a conductive region such as an impurity-doped well or an impurity-doped structure. In addition, the substrate 2 may have various device isolation structures such as a shallow trench isolation (STI) structure.

[0025] A plurality of individual devices of various types may be formed on the substrate 2. The plurality of individual devices may include various microelectronic devices, such as metal oxide semiconductor field effect transistors (MOSFETs), system large scale integration (LSI), image sensors (such as complementary metal oxide semiconductor (CMOS) imaging sensors (CIS)), micro electromechanical systems (MEMS), active elements, passive elements, etc.

[0026] Reference Figure 2A and Figure 2B , the second layer 117 may be formed to surround at least a portion of the first member 111 and at least a portion of the second member 113. The second layer 117 may not be formed in the substrate 2 to form a groove T (see Figure 3B ) region. In the second layer 117, the active region ACT (see Fig. 6A ) portion, a load difference may occur so that the second layer 117 has different widths between the major axes and between the minor axes. Fig. 6A ) in a plan view, a direct contact DC can be formed in the region between the long axes (see Fig. 6A ), and a buried contact BC may be formed in the region between the short axes (see Fig. 6A ). In other words, Figure 2A As shown in the plan view of FIG. 1 , the second layer 117 can be formed to form a wide direct contact DC between the long axes of the substrate 2 (see FIG. 1 ). Fig. 6A ) in the region of the substrate 2 will form a narrow buried contact BC between the short axes (see Fig. 6A ) is wider in the region. By forming the second layer 117 to have different widths (e.g., Figure 2B In the first direction X), direct contact DC (see Fig. 6A ) can be formed to be relatively narrow.

[0027] By forming the second layer 117 to have different widths according to the regions of the substrate 2, the trench T (see Figure 3B) can be formed to have different widths and depths. In other words, due to the difference in the width of the second layer 117, the amount of gas used for etching can be adjusted differently. The amount of gas is as follows Figure 2B As shown by the arrows in the figure. Due to the difference in the amount of gas introduced into each area, the groove T (see Figure 3B ) can be formed to have different widths and depths for each region. The gas used in the etching process can be mixed with chlorine (Cl 2 ) and oxygen (O 2 As a result, a plurality of first trenches T1 (see Figure 3B ) may have a width in the first direction X and in the second direction Y perpendicular to the first direction X greater than that of the plurality of second trenches T2 (see Figure 3B ) in the first direction X and the second direction Y, and the plurality of first trenches T1 (see Figure 3B ) in a vertical direction Z perpendicular to the first direction X and the second direction Y (ie, a depth) may be greater than the length of the plurality of second trenches T2 (see Figure 3B ) in the vertical direction Z (i.e., depth).

[0028] After forming the second layer 117 to be uniform just before etching, an additional layer may be deposited by sputtering, which facilitates the formation of the second layer 117 so that direct contact DC in a wide area (see Fig. 6A ) and a buried contact BC in a relatively narrow area (see Fig. 6A ) have different widths, so that direct contact DC will be formed therein (see Fig. 6A ) and buried contact BC (see Fig. 6A ) of the groove T (see Figure 3B ) can be formed to have different widths and depths. Figure 2A The planar shapes of the first member 111, the second member 113 and the second layer 117 may correspond to the active area ACT (see Fig. 6A )’s plane shape.

[0029] Reference Figure 3A and Figure 3B , the semiconductor memory device may include a plurality of trenches T provided in a substrate 2 .

[0030] The plurality of trenches T may include a plurality of first trenches T1 provided in the substrate 2 and a plurality of second trenches T2 provided between the first trenches in the plurality of first trenches T1. The first trench T1 and the second trench T2 may have different widths and depths from each other. Due to the nature of the dry etching process, the widths of the first trench T1 and the second trench T2 may narrow toward their lower portions. Therefore, the sidewalls of the first trench T1 and the sidewalls of the second trench T2 may not be vertical and may have a slightly inclined tapered shape. The first trench T1 may be formed to be deeper than the second trench T2, and the first trench T1 may be formed to be wider than the second trench T2. The plurality of trenches T may be formed to isolate devices.

[0031] Reference Figure 3A In a plan view, the active area ACT may be formed into an island shape having a relatively long shape, the island shape having a short axis and a long axis, and at least a portion of the long axis of the active area ACT may have a protrusion further protruding in the direction of the short axis. For example, in a plan view, the long axis of each active area ACT may be taken in a third direction, and the short axis of each active area ACT may be taken in a horizontal direction perpendicular to the third direction. That is, the long axis of each active area ACT corresponds to the longest length of each active area ACT (for example, in the third direction), and the short axis of each active area ACT corresponds to the shortest length of each active area ACT (for example, in a horizontal direction perpendicular to the third direction). As used herein, "long axis direction" refers to the direction taken along the long axis of the active area ACT, and "short axis direction" refers to the direction taken along the short axis of the active area ACT. A protrusion may be formed for each long axis of the active area ACT (i.e., for each side of the active area ACT extending in the long axis direction), and the protrusions may be positioned spaced apart from each other and may be formed in facing (i.e., opposite) directions. Reference will be made to Fig. 6A The distance between the protrusions and the distance between the long axes are described in detail. In a plan view, the protrusions may be formed to have a distance from the second layer 117 (see Figure 2A ) are substantially the same shape.

[0032] Reference Figure 4A and Figure 4B , the plurality of trenches T may be filled with an insulating material to form a plurality of device isolation layers DIL.

[0033] The device isolation layer DIL may include a first device isolation layer DIL_1, a second device isolation layer DIL_2, and a third device isolation layer DIL_3. Although the first device isolation layer DIL_1, the second device isolation layer DIL_2, and the third device isolation layer DIL_3 are shown as being formed simultaneously, the third device isolation layer DIL_3 may be formed after the first device isolation layer DIL_1 and the second device isolation layer DIL_2 are formed. In some other embodiments, the first device isolation layer DIL_1 and the second device isolation layer DIL_2 may be formed sequentially after the third device isolation layer DIL_3 is formed. The second device isolation layer DIL_2 may be formed in the first device isolation layer DIL_1. For example, the second device isolation layer DIL_2 may be inside the first device isolation layer DIL_1.

[0034] The plurality of device isolation layers DIL may be formed depending on the trench T (see Figure 3B ) and have different structures. For example, the device isolation layer DIL may have a first structure including a single insulating layer (such as a third device isolation layer DIL_3). In addition, the device isolation layer DIL may have a second structure (i.e., a multilayer structure) including a first device isolation layer DIL_1 and a second device isolation layer DIL_2. The first device isolation layer DIL_1 and the second device isolation layer DIL_2 may be provided in the first trench T1 (see Figure 3B ). The third device isolation layer DIL_3 may be provided in the second trench T2 (see Figure 3B ). The first device isolation layer DIL_1 and the second device isolation layer DIL_2 may include materials different from each other. For example, the first device isolation layer DIL_1 may include an oxide layer, and the second device isolation layer DIL_2 may include a nitride layer. However, the configuration of the device isolation layer DIL is not limited thereto. For example, as described above, the device isolation layer DIL may include a single layer (which includes one type of insulating layer, such as the third device isolation layer DIL_3) and / or a multilayer (which includes a combination of at least two types of insulating layers).

[0035] The plurality of device isolation layers DIL may be formed to have a tapered shape in which a width in each of the first direction X and the second direction Y becomes narrower toward a lower portion thereof in the vertical direction Z. For example, the respective widths of the plurality of device isolation layers DIL in each of the first direction X and the second direction Y may become narrower as a distance from the lower surface of the substrate 2 in the vertical direction Z decreases.

[0036] Here, the uppermost surface of the device isolation layer DIL may be formed at a level substantially the same as that of the uppermost surface of the substrate 2, and may then be etched to a level lower than that of the uppermost surface of the substrate 2. As used herein, the term "level" refers to a height from the lower surface of the substrate 2 in the vertical direction Z. In other words, "level" (or similar language) as used herein refers to a height taken in the vertical direction Z relative to the lower surface of the substrate 2. It will be understood that "level" as used herein may also be referred to as "height". The level of the upper surface of the first device isolation layer DIL_1 after etching may be formed to be higher than the level of the upper surface of the third device isolation layer DIL_3. Specifically, a first trench T1 (see FIG. 1 ) in which the first device isolation layer DIL_1 and the second device isolation layer DIL_2 are provided. Figure 3B ) may be formed to have a width greater than that of the second trench T2 (see Figure 3B ) width. By supplying similar amounts of etching gas to the upper surface of the first device isolation layer DIL_1 and the upper surface of the third device isolation layer DIL_3, the etching amount per unit area of ​​the third device isolation layer DIL_3 may be greater than the etching amount per unit area of ​​the first device isolation layer DIL_1. Therefore, the uppermost surface of the third device isolation layer DIL_3 may be formed to be lower than the uppermost surface of the first device isolation layer DIL_1. By forming the uppermost surface of the third device isolation layer DIL_3 to be lower than the uppermost surface of the first device isolation layer DIL_1, the buried contact level LV_BC (see Figure 6B ) can be formed below the direct contact level LV_DC (see Figure 6B ). This will refer to Figure 6B Described in more detail. Although the uppermost surface of the first device isolation layer DIL_1 and the uppermost surface of the third device isolation layer DIL_3 are shown to have a flat shape (each formed at a uniform height in the vertical direction Z), the first device isolation layer DIL_1 and the third device isolation layer DIL_3 are not limited thereto, and the heights of their uppermost surfaces may not be formed to be uniform due to the nature of the dry etching process.

[0037] A plurality of active regions ACT may be defined on the substrate 2 by the device isolation layer DIL. Referring to the cross-sectional view of the active region ACT, a plurality of fins 100 (see FIG. Figure 6B ) may be formed in the upper portion of the active area ACT, and in the process of etching the substrate 2, the plurality of fins 100 (see Figure 6B ) may be formed to have a rounded shape at least in part of an outer peripheral surface thereof.

[0038] Reference Figure 5A and Figure 5BThe word line layer WLa may be formed to surround the upper surfaces of the plurality of device isolation layers DIL and at least a portion of the upper surface of the active area ACT formed on the substrate 2. The word line layer WLa may be formed in the first trench T1 (see Figure 3B ) inner wall and second groove T2 (see Figure 3B ) on the inner wall (for example, the first trench T1 (see Figure 3B ) inner wall and second groove T2 (see Figure 3B ) inner wall). The word line layer WLa may be formed to have a thickness of about to about The wordline lower layer WLa may include silicon oxide. For example, the wordline lower layer WLa may include tetraethyl orthosilicate (TEOS), high density plasma (HDP) silicon oxide, or borophosphosilicate glass (BPSG).

[0039] The word line lower layer WLa may include an insulating material, and at least a portion of the word line lower layer WLa may have a surrounding fin 100 (see Figure 6B ), at least a portion of the wordline lower layer WLa may have a flat shape in the first direction X and the second direction Y (for example, on the first device isolation layer DIL_1 and / or the third device isolation layer DIL_3). The levels of the uppermost surfaces of the wordline lower layers WLa may be formed to be the same as each other, but the levels of the lower surfaces of the wordline lower layers WLa may be formed to be different from each other. For example, the first portions of the wordline lower layers WLa may be respectively located on the plurality of fins 100 (see Figure 6B ), the second part of the word line lower layer WLa can be respectively on the first device isolation layer DIL_1, and the third part of the word line lower layer WLa can be respectively on the third device isolation layer DIL_3. Relative to the lower surface of the substrate 2, the corresponding height of the first part of the word line lower layer WLa in the vertical direction Z (for example Figure 6B The corresponding heights of the second portion of the word line lower layer WLa in the vertical direction Z (eg, Figure 6B The horizontal LV_DC in the word line layer WLa may be the same as the corresponding height of the third portion of the word line layer WLa in the vertical direction Z (eg Figure 6B In addition, the width of the lower surface of the word line layer WLa in the first direction X and the second direction Y can be formed to be equal to the width of the trench T (see Figure 3B ) has the same width in the first direction X and the second direction Y, and the trench T contacts the lower surface of the word line lower layer WLa. For example, the corresponding widths of the second portion of the word line lower layer WLa in the first direction X and the second direction Y may be equal to the plurality of first trenches T1 (see Figure 3B) in the first direction X and the second direction Y, the corresponding widths of the third portion of the word line lower layer WLa in the first direction X and the second direction Y may be equal to the plurality of second trenches T2 (see Figure 3B ) in the first direction X and the second direction Y. The second portion of the word line layer WLa may be respectively adjacent to the plurality of first trenches T1 (see Figure 3B ), the third portion of the word line layer WLa can be respectively in contact with the plurality of second trenches T2 (see Figure 3B )touch.

[0040] Fig. 6A is a layout diagram showing main components of a semiconductor memory device 1 according to some embodiments. Figure 6B is a cross-sectional view showing a semiconductor memory device 1 according to some embodiments. Specifically, Figure 6B is along the line corresponding to Fig. 6A A cross-sectional view taken along line II'.

[0041] Reference Fig. 6A and Figure 6B , the semiconductor memory device 1 may be a dynamic random access memory (DRAM) device. The semiconductor memory device 1 may include a plurality of unit devices (i.e., a plurality of unit cells or memory cells) arranged in an array. Here, each unit device may have a 1T1C structure including one transistor and one capacitor.

[0042] The semiconductor memory device 1 may include: a plurality of trenches T (see Figure 3B ), including a plurality of first trenches T1 provided in the substrate 2 (see Figure 3B ) and provided in the plurality of first trenches T1 (see Figure 3B ) between the corresponding first trenches in the plurality of second trenches T2 (see Figure 3B ); a plurality of device isolation layers DIL, including a plurality of first trenches T1 (see Figure 3B ) and the first device isolation layer DIL_1 and the second device isolation layer DIL_2 provided in the plurality of second trenches T2 (see Figure 3B) in a third device isolation layer DIL_3; a plurality of active areas ACT defined by the plurality of device isolation layers DIL; a word line WL formed on one side of the plurality of active areas ACT in a vertical direction Z; a plurality of direct contacts DC electrically connecting the word line WL to the plurality of active areas ACT; a plurality of buried contacts BC located between corresponding direct contacts in the plurality of direct contacts DC; and a plurality of fins 100 located between corresponding direct contacts in the plurality of direct contacts DC and corresponding buried contacts in the plurality of buried contacts BC. For example, a corresponding one of the plurality of fins 100 may be between a corresponding one of the plurality of direct contacts DC and a corresponding one of the plurality of buried contacts BC.

[0043] The level LV_DC of the lowermost surface of the formation region of the direct contact DC can be formed to be higher than the level LV_BC of the lowermost surface of the formation region of the buried contact BC, and therefore, the region of the buried contact BC can be formed to be deeper than the region of the direct contact DC. As a result, the distance between the fins 100 can be widened, and therefore, when the minimum spacing between adjacent conductive lines is F (feature size), an inter-fin distance D_100 greater than 2F and less than 4F can be formed. For example, the inter-fin distance D_100 can be the minimum spacing (i.e., the minimum distance) between the central axes of an adjacent pair of fins 100 in the first direction X. That is, the inter-fin distance D_100 can be the minimum center-to-center distance between an adjacent pair of fins 100 in the first direction X. For example, the central axis of each fin 100 refers to an imaginary line passing through the center of each fin 100. In addition, due to the multiple grooves T (see Figure 3B ) have different widths in the first direction X and the second direction Y, so the intervals between the central axes of the plurality of fins 100 in the first direction X may be different. That is, since the first trench T1 (see Figure 3B ) has a width in the first direction X and the second direction Y different from that of the second trench T2 (see Figure 3B ) in the first direction X and the second direction Y, so the intervals between the central axes of the plurality of fins 100 in the first direction X may be different from each other. For example, there is a second trench T2 (see Figure 3B ) in the first direction X may be greater than the spacing between the central axes of adjacent fins 100 having the first trench T1 therebetween (see Figure 3B) in the first direction X is shorter. In other words, the spacing between the central axes of adjacent fins in the plurality of fins 100 in the first direction X may be different from each other. As used herein, "F" refers to the characteristic size of the semiconductor memory device 1. The characteristic size may refer to the minimum distance between components within the semiconductor memory device 1, and thus may be described as the minimum spacing (i.e., the minimum distance) between adjacent conductive lines included in the semiconductor memory device 1. The characteristic size is typically measured in nanometers (nm) and may be used to represent the smallest element in a unit device (i.e., a unit cell or a memory cell) of the semiconductor memory device 1.

[0044] The plurality of fins 100 may be formed from a point equal to 1 / 2 of the sum of the level LV_DC of the lowermost surface of the direct contact DC and the level LV_BC of the lowermost surface of the buried contact BC to the level LV_100 of the uppermost surface of the substrate 2, and at least a portion of the outer peripheral surface of the plurality of fins 100 may have a rounded shape, and the peak points of the plurality of fins 100 in the vertical direction Z may be formed as vertices of the rounded shape. For example, the plurality of fins 100 may extend from a first point to a second point in the vertical direction Z. The first point may be equal to 1 / 2 of the sum of the level LV_DC (i.e., height LV_DC) of the lowermost surface of the direct contact DC in the vertical direction Z and the level LV_BC (i.e., height LV_BC) of the lowermost surface of the buried contact BC in the vertical direction Z. The second point may be equal to the level of the uppermost surface of the substrate 2 in the vertical direction Z (i.e., may be equal to the level LV_100). For example, at least a portion of the outer surfaces of the plurality of fins 100 may have rounded shapes, respectively, and the upper surfaces of the plurality of fins 100 in the vertical direction Z may include vertices of the rounded shapes, respectively. As used herein, the term "vertex" refers to a corresponding point on a rounded shape at which the rounded shape makes its greatest turn (e.g., a turning point). In other words, the vertex of each rounded shape may be the point at which the rounded shape has its tightest bend. For example, Figure 6B As shown, each fin 100 includes an upper surface having a rounded shape, and each rounded shape has an apex at which it makes a maximum turn. For example, the apex of each rounded shape may correspond to a center point of the upper surface of each fin 100 .

[0045] When the buried contact BC is formed to be relatively deep, the margin for filling metal near the buried contact BC can be increased, and when the fin height H_100 increases, the control of the gate can be facilitated, and therefore, the characteristics of the gate can be improved, and the defects of the gate can be reduced. Although omitted in the drawings, a channel layer can be formed. In some embodiments, the channel layer may include a semiconductor material. For example, the channel layer may include single crystal silicon or polycrystalline silicon. In some other embodiments, the channel layer may include an oxide semiconductor material. The channel layer may include at least one of a binary or ternary oxide semiconductor material containing a first metal element, a ternary oxide semiconductor material containing a first metal element and a second metal element different from each other, and a quaternary oxide semiconductor material containing a first metal element, a second metal element, and a third metal element different from each other. The binary or ternary oxide semiconductor material may be one of, for example, ZnO (zinc oxide, ZnxO), GaO (gallium oxide, GaxO), SnO (tin oxide, SnxO), ZnON (zinc oxynitride, ZnxOyN), IZO (indium zinc oxide, InxZnyO), GZO (gallium zinc oxide, GaxZnyO), TZO (tin zinc oxide, SnxZnyO) and TGO (tin gallium oxide, SnxGayO), but is not limited thereto. The quaternary oxide semiconductor material may be, for example, IGZO (indium gallium zinc oxide, InxGayZnzO), IGSO (indium gallium silicon oxide, InxGaySizO), ITZO (indium tin zinc oxide, InxSnyZnzO), IGTO (indium gallium tin oxide, InxGaySnzO), ZZTO (zirconium zinc tin oxide, ZrxZnySnzO), HIZO (hafnium indium zinc oxide, HfxInyZnzO), GZTO (gallium zinc tin oxide, GaxZnySnzO), AZTO (aluminum zinc tin oxide, AlxZnySnzO), YGZO (ytterbium gallium zinc oxide, YbxGayZnzO) and IAZO (indium aluminum zinc oxide) One of, but not limited to. In some embodiments, the channel layer may include a crystalline oxide semiconductor material or an amorphous oxide semiconductor material. When the channel layer includes a crystalline oxide semiconductor material, the channel layer may have the crystallinity of at least one of a single crystal, a polycrystalline, a spinel, and a c-axis oriented crystal (CAAC). In some embodiments, the channel layer may be formed by stacking at least two layers including a first layer including a crystalline oxide semiconductor material and a second layer including an amorphous oxide semiconductor material. For example, the channel layer may be formed by sequentially stacking a first layer including a crystalline oxide semiconductor material, a second layer including an amorphous oxide semiconductor material, and a third layer including a crystalline oxide semiconductor material.

[0046] The word line WL may be formed on the upper surface of the word line lower layer WLa in the vertical direction Z. For example, the word line lower layer WLa may be on the lowermost surface of the word line WL and between the word line WL and the plurality of fins 100. The word line WL may include a conductive material. For example, the word line WL may include at least one of a metal, a semiconductor, and an alloy. The metal may include, for example, aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), etc. The semiconductor may include, for example, a group IV semiconductor material, a group III-V semiconductor material, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, etc. However, the embodiment is not limited thereto. A plurality of word lines WL may be formed to have the same length in the vertical direction Z. In some other embodiments, the lengths of the plurality of word lines WL in the vertical direction Z may be different from each other, but are not limited thereto. In some embodiments, after the word line WL is formed, a source / drain region may be formed at the upper surface of the plurality of active regions ACT by implanting impurity ions into the substrate 2 from the opposite side of the word line WL. In some other embodiments, an impurity ion implantation process for forming source / drain regions may be performed before forming the plurality of word lines WL. Although the word lines WL are shown as a single layer, the word lines WL may include a first word line layer and a second word line layer arranged on an upper surface of the first word line layer in a vertical direction Z, and the first word line layer and the second word line layer may include different materials from each other and are not limited to the shapes, thicknesses, etc. shown in the drawings.

[0047] In addition, although not shown in the drawings, in some embodiments, the semiconductor memory device 1 may include a plurality of bit lines spaced apart from the word line WL. Each of the plurality of bit lines may include polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the bit line may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, WSi, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto. In some other embodiments, the bit line may include a two-dimensional semiconductor material. The two-dimensional semiconductor material may include, for example, graphene, carbon nanotubes, or a combination thereof. The bit line may include a single layer or multiple layers containing the above-mentioned conductive material.

[0048] In addition, although not shown in the drawings, in some embodiments, the semiconductor memory device 1 may include a gate electrode spaced apart from the word line WL. The gate electrode may include a first conductive pattern, a second conductive pattern arranged on the lower surface of the first conductive pattern, and a third conductive pattern arranged on the lower surface of the second conductive pattern. The first conductive pattern, the second conductive pattern, and the third conductive pattern may include materials different from each other, and the thicknesses of the respective conductive patterns may be different from each other. In addition, a gate dielectric layer may be formed around the gate electrode. The gate dielectric layer may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, and at least one of a high-k dielectric layer having a dielectric constant higher than that of silicon oxide. For example, the gate dielectric layer may have a dielectric constant of about 10 to about 25. In some embodiments, the gate dielectric layer may include at least one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the gate dielectric layer may include HfO 2 、Al 2 O 3 、HfAlO 3 、 2 O 3 or TiO 2 .

[0049] In addition, although not shown in the drawings, a landing pad may be formed in the semiconductor memory device 1. Specifically, the landing pad may be formed by sequentially forming a conductive barrier layer and a conductive layer. A plurality of conductive landing pads connected to the plurality of buried contacts BC may be formed in the space between each pair of conductive lines including a plurality of bit lines in the cell array region. The method of forming the landing pad may be performed by chemical vapor deposition (CVD), but is not limited thereto. In addition, in the process of forming the landing pad, a conductive layer may be formed on the upper surface of the direct contact plug in the core / peripheral region. Each conductive barrier layer may have a Ti / TiN stacked structure. The conductive layer may include doped polysilicon, a metal, a metal silicide, a conductive metal nitride, or a combination thereof.

[0050] In the plan view, Fig. 6AAs shown, the plurality of active areas ACT may extend diagonally relative to the first direction X and the second direction Y perpendicular to the first direction X to form an island shape. That is, the plurality of active areas ACT may extend in the third direction to have an island shape. The active area ACT may have a longitudinal side and a lateral side that intersect (i.e., connect) each other, the longitudinal sides may face each other (i.e., opposite), and the lateral sides may face each other (i.e., opposite). For example, the longitudinal side may extend perpendicular to the lateral side. The longitudinal side is the longer side of each active area ACT in the plan view and extends in the third direction. The lateral side is the shorter side of each active area ACT in the plan view and extends in a horizontal direction perpendicular to the third direction. At least part of the longitudinal side of the active area ACT may have a protrusion protruding in the direction in which the lateral side extends, respectively. In other words, at least a part of each longitudinal side may include a protrusion protruding outward in the direction in which the lateral side extends. The formation position of the direct contact DC may be the formation position of the device isolation layer between the active areas ACT in the long axis direction, and the formation position of the buried contact BC may be the formation position of the device isolation layer between the active areas ACT in the short axis direction. That is, each direct contact DC may be between adjacent active regions in the active region ACT in the long axis direction (i.e., the third direction), and each buried contact BC may be between adjacent active regions in the active region ACT in the short axis direction (i.e., the horizontal direction perpendicular to the third direction). The device isolation layer between adjacent active regions in the active region ACT in the long axis direction may be the first device isolation layer DIL_1. Although there is no Fig. 6A However, the device isolation layer between adjacent active regions in the active region ACT in the short axis direction may be a third device isolation layer DIL_3 (see Figure 6BDIL_3 in ). One of the protrusions may be formed on each of the longitudinal sides of the active area ACT facing each other (i.e., opposite), and the protrusion may protrude toward the formation position of the direct contact DC. In a plan view, a pair of active areas ACT adjacent to each other in the short axis direction (direct contact DC therebetween) may be referred to as a first active area and a second active area. The first active area may have a first longitudinal side and a first lateral side, and the second active area may have a second longitudinal side and a second lateral side. The first protrusion may be formed on the first longitudinal side, the second protrusion may be formed on the second longitudinal side, and the direct contact DC may be formed between the first protrusion and the second protrusion. The first distance D1 (which is the shortest (i.e., minimum) distance between the first protrusion and the second protrusion) may be less than the second distance D2 (which is the distance between the first longitudinal side and the second longitudinal side on the corresponding portion where the protrusion does not exist). The protrusions may not be formed on the same axis on the longitudinal sides of the active area ACT facing each other (i.e., opposite), and each of the plurality of active areas ACT may be formed to have an asymmetric shape with respect to the long axis of the active area ACT as the central axis. That is, the protrusions on the corresponding longitudinal sides of each active area ACT may be spaced apart from each other in the long axis direction (i.e., the third direction), and therefore, in a plan view, each of the plurality of active areas ACT may have an asymmetric shape. For example, the corresponding longitudinal sides of each active area ACT may be asymmetric to each other along the long axis direction. In other words, the protrusions on the corresponding longitudinal sides of each active area ACT may be offset from each other in the short axis direction (i.e., the horizontal direction perpendicular to the third direction) (i.e., may not be directly opposite to each other). As used herein, "element A and element B are offset from each other in the X direction" (or similar language) means that element A and element B are not aligned with each other along the X direction. In addition, the lateral sides and protrusions of the active area ACT may be formed to have a rounded shape, but are not limited thereto.

[0051] Figure 7 is a block diagram illustrating an example configuration of a semiconductor memory device 1 according to some embodiments.

[0052] Reference Figure 7 , the semiconductor memory device 1 may include a first region 22 and a second region 24. The first region 22 may be a memory cell region of a DRAM device, and the second region 24 may be a peripheral circuit region of the DRAM device. The first region 22 may include a memory cell array 22A. The second region 24 may include a row decoder 52, a sense amplifier 54, a column decoder 56, a self-refresh control circuit 58, a command decoder 60, a mode register set / extended mode register set (MRS / EMRS) circuit 62, an address buffer 64, and a data input / output circuit 66.

[0053] Figure 8is a plan view showing an arrangement configuration of a semiconductor memory device 1 according to some embodiments.

[0054] Reference Figure 8 , the semiconductor memory device 1 may include a plurality of first regions 22 . Each of the plurality of first regions 22 may be surrounded by a second region 24 .

[0055] Each of the plurality of first regions 22 may be a cell array region MCA of a DRAM device, and the second region 24 may be a region where a peripheral circuit of the DRAM device is formed and may include a core region.

[0056] The second region 24 may include a sub-word line driver block SWD, a sense amplifier block S / A, and a junction block CJT. A plurality of bit line sense amplifiers may be arranged in the sense amplifier block S / A. The junction block CJT may be arranged at a point where the sub-word line driver block SWD intersects with the sense amplifier block S / A. A power driver and a ground driver for driving the bit line sense amplifier may be alternately arranged in the junction block CJT. Peripheral circuits such as inverter chains and input / output circuits may be further formed in the second region 24.

[0057] Fig. 9 is a block diagram illustrating a system 1000 including a semiconductor memory device according to some embodiments.

[0058] Reference Fig. 9 , system 1000 may include a controller 1010, an input / output device 1020, a storage device 1030, and an interface 1040. System 1000 may be a mobile system or a system for sending or receiving information. In some embodiments, the mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card. Controller 1010 may control the execution program in system 1000, and may include a microprocessor, a digital signal processor, a microcontroller, or a device similar thereto. Input / output device 1020 may be used to input or output data of system 1000. System 1000 may be connected to an external device (e.g., a personal computer or a network) by using input / output device 1020, and may exchange data with the external device. Input / output device 1020 may be, for example, a keypad, a keyboard, or a display.

[0059] The storage device 1030 may store codes and / or data for the operation of the controller 1010, or may store data processed by the controller 1010. The storage device 1030 may include a semiconductor device. For example, the storage device 1030 may include the above-mentioned Figures 1A to 8 A semiconductor memory device 1 is described.

[0060] The interface 1040 may be a data transmission path between the system 1000 and other external devices. The controller 1010, the input / output device 1020, the storage device 1030, and the interface 1040 may communicate with each other via a bus 1050. The system 1000 may be used for a mobile phone, an MP3 player, a navigation device, a portable multimedia player (PMP), a solid state disk (SSD), and / or a home appliance.

[0061] Fig.10 is a block diagram illustrating a memory card 1100 including a semiconductor memory device according to some embodiments.

[0062] Reference Fig.10 , the memory card 1100 may include a storage device 1110 and a memory controller 1120 .

[0063] The storage device 1110 may store data. In some embodiments, the storage device 1110 may have a non-volatile characteristic that allows the stored data to be retained even when power is interrupted. The storage device 1110 may include a semiconductor device. For example, the storage device 1110 may include the semiconductor device described above. Figures 1A to 8 A semiconductor memory device 1 is described.

[0064] The memory controller 1120 may read data stored in the storage device 1110, or may store data of the storage device 1110 in response to a read / write request from the host 1130. The memory controller 1120 may include a semiconductor device. For example, the memory controller 1120 may include the above reference Figures 1A to 8 A semiconductor memory device 1 is described.

[0065] As used herein, it will be understood that the terms "comprises," "comprising," "having" and any other variations thereof specify the presence of stated features, steps, operations, elements, parts and / or groups, but do not preclude the presence or addition of one or more other features, steps, operations, elements, parts and / or groups thereof.

[0066] While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

[0067] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0137974 filed in the Korean Intellectual Property Office on October 16, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: a plurality of trenches including a plurality of first trenches in the substrate and a plurality of second trenches between corresponding first trenches in the plurality of first trenches; A plurality of device isolation layers, including first device isolation layers and second device isolation layers respectively in the plurality of first trenches and third device isolation layers respectively in the plurality of second trenches; a plurality of active regions defined by the plurality of device isolation layers; word lines on the plurality of active regions; a plurality of direct contacts electrically connecting the word lines to the plurality of active regions; a plurality of buried contacts between corresponding direct contacts of the plurality of direct contacts; as well as a plurality of fins between corresponding direct contacts of the plurality of direct contacts and corresponding buried contacts of the plurality of buried contacts, wherein respective widths of the plurality of first grooves in a first direction and a second direction are greater than respective widths of the plurality of second grooves in the first direction and the second direction, wherein the first direction and the second direction are parallel to the lower surface of the substrate, and wherein the second direction is perpendicular to the first direction, wherein respective depths of the plurality of first grooves in a vertical direction are greater than respective depths of the plurality of second grooves in the vertical direction, wherein the vertical direction is perpendicular to the lower surface of the substrate, wherein the vertical direction is perpendicular to the first direction and the second direction, and Wherein, relative to the lower surface of the substrate, respective first heights of the lowermost surfaces of the plurality of direct contacts in the vertical direction are higher than respective second heights of the lowermost surfaces of the plurality of buried contacts in the vertical direction.

2. The semiconductor memory device according to claim 1, wherein: When a minimum interval between adjacent conductive lines included in the semiconductor memory device is F, a minimum interval between central axes of an adjacent pair of fins among the plurality of fins in the first direction is greater than 2F and less than 4F. 3 . The semiconductor memory device according to claim 2 , wherein intervals between central axes of adjacent fins among the plurality of fins in the first direction are different from each other.

4. The semiconductor memory device according to claim 1 , wherein at least one of the plurality of fins extends in the vertical direction from a first point equal to 1 / 2 of the sum of the first height and the second height to a second point equal to the level of the uppermost surface of the substrate, and At least parts of outer surfaces of the plurality of fins have rounded shapes, respectively, and upper surfaces of the plurality of fins in the vertical direction include vertices of the rounded shapes, respectively. 5 . The semiconductor memory device of claim 1 , further comprising a word line lower layer on a lowermost surface of the word line and between the word line and the plurality of fins.

6. The semiconductor memory device according to claim 5, wherein the word line lower layer comprises an insulating material, wherein at least a first portion of the wordline lower layer has a rounded shape surrounding the plurality of fins, and At least a second portion of the wordline lower layer has a flat shape in the first direction and the second direction.

7. The semiconductor memory device according to claim 5, wherein the first portion of the lower layer under the word line is respectively on the plurality of fins, the second portion of the lower layer under the word line is respectively on the first device isolation layer, and the third portion of the lower layer under the word line is respectively on the third device isolation layer, wherein respective third heights of the first portions of the wordline lower layer in the vertical direction are equal to each other relative to the lower surface of the substrate, and Wherein, relative to the lower surface of the substrate, a corresponding fourth height of the second portion of the lower layer under the word line in the vertical direction is different from a corresponding fifth height of the third portion of the lower layer under the word line in the vertical direction.

8. The semiconductor memory device according to claim 7, wherein the respective widths of the second portion of the word line lower layer in the first direction and the second direction are equal to the respective widths of the plurality of first trenches in the first direction and the second direction, wherein the respective widths of the third portion of the word line layer in the first direction and the second direction are equal to the respective widths of the plurality of second trenches in the first direction and the second direction, and The second portions of the lower layer of the word line are in contact with the plurality of first trenches, respectively, and the third portions of the lower layer of the word line are in contact with the plurality of second trenches, respectively.

9. The semiconductor memory device according to claim 1, wherein the plurality of device isolation layers have a tapered shape so that the respective widths of the plurality of device isolation layers in each of the first direction and the second direction become narrower as the distance from the lower surface of the substrate in the vertical direction decreases.

10. The semiconductor memory device according to claim 8, wherein the plurality of device isolation layers comprise silicon oxide, silicon nitride or a combination thereof, wherein at least one of the first device isolation layers and at least one of the second device isolation layers include materials different from each other, and The second device isolation layers are respectively inside the first device isolation layers.

11. A semiconductor memory device, comprising: a plurality of trenches including a plurality of first trenches in the substrate and a plurality of second trenches between corresponding first trenches in the plurality of first trenches; A plurality of device isolation layers, including first device isolation layers and second device isolation layers respectively in the plurality of first trenches and third device isolation layers respectively in the plurality of second trenches; a plurality of active regions defined by the plurality of device isolation layers; word lines on the plurality of active regions; a plurality of direct contacts electrically connecting the word lines to the plurality of active regions; as well as a plurality of buried contacts between corresponding direct contacts of the plurality of direct contacts, Among them, in the plan view: The plurality of active regions extend diagonally relative to a first direction and a second direction perpendicular to the first direction, Each of the plurality of active regions includes longitudinal sides opposite to each other and lateral sides opposite to each other, and At least parts of the longitudinal sides respectively include protrusions protruding outward in the direction in which the lateral sides extend.

12. The semiconductor memory device according to claim 11, wherein: In the said plan view: The plurality of direct contacts are between corresponding active regions in the plurality of active regions in the direction of the long axes of the plurality of active regions, and The plurality of buried contacts are between corresponding active regions among the plurality of active regions in a short axis direction of the plurality of active regions.

13. The semiconductor memory device according to claim 12, wherein: In the said plan view: The first device isolation layer is between the corresponding active regions in the plurality of active regions in the long axis direction, and The third device isolation layer is between the corresponding active regions among the plurality of active regions in the short-axis direction.

14. The semiconductor memory device according to claim 12, wherein: In the plan view, the protrusion protrudes toward a corresponding direct contact of the plurality of direct contacts.

15. The semiconductor memory device according to claim 11, wherein In said plan view, each of said longitudinal sides comprises one of said protrusions.

16. The semiconductor memory device according to claim 11, wherein In the plan view, a first active region and a second active region of the plurality of active regions are adjacent to each other, and Wherein, in the plan view: The first active region includes a first longitudinal side of the longitudinal sides and a first lateral side of the lateral sides, The second active region includes a second longitudinal side of the longitudinal sides and a second lateral side of the lateral sides, The first of the longitudinal sides comprises a first of the protrusions, the second of the longitudinal sides comprises a second of the protrusions, and The shortest distance between the first one of the protrusions and the second one of the protrusions is smaller than a distance between corresponding portions of the first one of the longitudinal sides and the second one of the longitudinal sides where the protrusions are not present.

17. The semiconductor memory device according to claim 11, wherein: In the plan view, each of the plurality of active regions has an asymmetrical shape.

18. The semiconductor memory device according to claim 11, wherein In the plan view, the lateral sides and the protrusions have a rounded shape.

19. A semiconductor memory device comprising: a plurality of trenches including a plurality of first trenches in the substrate and a plurality of second trenches between corresponding first trenches in the plurality of first trenches; A plurality of device isolation layers, including first device isolation layers and second device isolation layers respectively in the plurality of first trenches and third device isolation layers respectively in the plurality of second trenches; a plurality of active regions defined by the plurality of device isolation layers; word lines on the plurality of active regions; a plurality of direct contacts electrically connecting the word lines to the plurality of active regions; a plurality of buried contacts between corresponding direct contacts of the plurality of direct contacts; a plurality of fins between corresponding ones of the plurality of direct contacts and corresponding ones of the plurality of buried contacts; as well as a lower layer below the word line, on a lowermost surface of the word line and between the word line and the plurality of fins, wherein respective widths of the plurality of first grooves in a first direction and a second direction are greater than respective widths of the plurality of second grooves in the first direction and the second direction, wherein the first direction and the second direction are parallel to the lower surface of the substrate, and wherein the second direction is perpendicular to the first direction, wherein respective depths of the plurality of first grooves in a vertical direction are greater than respective depths of the plurality of second grooves in the vertical direction, wherein the vertical direction is perpendicular to the lower surface of the substrate, wherein the vertical direction is perpendicular to the first direction and the second direction, Wherein, when the minimum interval between adjacent conductive lines included in the semiconductor memory device is F: The minimum interval between the central axes of a pair of adjacent fins in the plurality of fins in the first direction is greater than 2F and less than 4F, The intervals between the central axes of adjacent fins in the plurality of fins in the first direction are different from each other, At least one of the plurality of fins extends in the vertical direction from a first point to a second point, the first point being equal to 1 / 2 of a sum of a first height of a lowermost surface of one of the plurality of direct contacts and a second height of a lowermost surface of one of the plurality of buried contacts, the second point being equal to a level of an uppermost surface of the substrate, the first height and the second height being taken in the vertical direction relative to the lower surface of the substrate, At least parts of outer surfaces of the plurality of fins have rounded shapes, respectively, and upper surfaces of the plurality of fins in the vertical direction respectively include vertices of the rounded shapes, The wordline layer comprises an insulating material, At least a portion of the wordline lower layer has a rounded shape surrounding the plurality of fins, At least another portion of the wordline layer has a flat shape in the first direction and the second direction, The first part of the lower layer under the word line is respectively on the plurality of fins, the second part of the lower layer under the word line is respectively on the first device isolation layer, and the third part of the lower layer under the word line is respectively on the third device isolation layer. Relative to the lower surface of the substrate, respective third heights of the first portions of the lower layer of the word line in the vertical direction are equal to each other, relative to the lower surface of the substrate, a corresponding fourth height of the second portion of the lower layer under the word line in the vertical direction is different from a corresponding fifth height of the third portion of the lower layer under the word line in the vertical direction, The respective widths of the second portion of the word line layer in the first direction and the second direction are equal to the respective widths of the plurality of first trenches in the first direction and the second direction, The respective widths of the third portion of the word line layer in the first direction and the second direction are equal to the respective widths of the plurality of second trenches in the first direction and the second direction, The second portions of the lower layer under the word line are respectively in contact with the plurality of first trenches, and the third portions of the lower layer under the word line are respectively in contact with the plurality of second trenches. the plurality of device isolation layers having a tapered shape such that respective widths of the plurality of device isolation layers in each of the first direction and the second direction become narrower as a distance from the lower surface of the substrate in the vertical direction decreases, The plurality of device isolation layers include silicon oxide, silicon nitride or a combination thereof, At least one of the first device isolation layers and at least one of the second device isolation layers include materials different from each other, The second device isolation layers are respectively inside the first device isolation layers, and Relative to the lower surface of the substrate, the first height of the lowermost surface of the one of the plurality of direct contacts is higher than the second height of the lowermost surface of the one of the plurality of buried contacts.

20. The semiconductor memory device according to claim 19, wherein In floor plan: The plurality of active regions extend diagonally relative to the first direction and the second direction, Each of the plurality of active areas comprises longitudinal sides opposite to each other and lateral sides opposite to each other, At least parts of the longitudinal sides respectively include protrusions protruding outward in the direction in which the transverse sides extend, the protrusion protrudes toward a corresponding direct contact among the plurality of direct contacts, each of said longitudinal sides comprises one of said protrusions, The plurality of direct contacts are between corresponding active regions in the plurality of active regions in the direction of the long axes of the plurality of active regions, The plurality of buried contacts are between corresponding active regions among the plurality of active regions in a direction of a short axis of the plurality of active regions, The first device isolation layer is between the corresponding active regions among the plurality of active regions in the long axis direction, The third device isolation layer is between the corresponding active regions among the plurality of active regions in the short axis direction, Each of the plurality of active regions has an asymmetric shape, and The lateral sides and the protrusions have a rounded shape.

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