Reverse conducting insulated gate bipolar transistor, forming method thereof, chip and vehicle

Abstract

The invention provides a reverse conducting insulated gate bipolar transistor, a forming method thereof, a chip and a vehicle. The reverse conducting insulated gate bipolar transistor comprises a substrate, a first collector doped region and a second collector doped region which are located in the substrate, and a first short circuit doped region located in the substrate. The substrate comprises a first surface and a second surface which are opposite in the first direction, the second surface exposes the first collector doped region and the second collector doped region, the second collector doped region comprises a first region and a second region, and the second region is in contact with the side, away from the second surface, of the first region. The second surface further exposes the first short-circuit doped region, the first short-circuit doped region is located between the first collector doped region and the first region, and the second region is in contact with the side, away from the second surface, of the first short-circuit doped region. Therefore, electrons need to bypass the second region to reach the first short-circuit doping region, a short-circuit resistance region is formed above the second region, the short-circuit resistance of the short-circuit resistance region is increased, and the phenomenon of voltage rebound is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a reverse conducting insulated gate bipolar transistor and a method for forming the same, a chip and a vehicle. Background Art

[0002] The reverse conducting insulated gate bipolar transistor (RC-IGBT) is a new type of insulated gate bipolar transistor (IGBT) device with high integration, which integrates the fast recovery diode (FRD) and the insulated gate bipolar transistor on the same chip. Compared with the traditional insulated gate bipolar transistor device, the reverse conducting insulated gate bipolar transistor improves the device power density, reduces the chip area, manufacturing cost and packaging cost, and improves the reliability of the insulated gate bipolar transistor.

[0003] However, due to the existence of short-circuit doping regions in the reverse-conducting insulated gate bipolar transistor, the device switches from unipolar mode to bipolar mode at the initial start-up, resulting in a voltage rebound phenomenon, which is not conducive to the parallel connection of the device and its use under low temperature conditions. Summary of the invention

[0004] The purpose of the present application is to provide a reverse conducting insulated gate bipolar transistor and a method for forming the same, in order to improve the voltage rebound phenomenon.

[0005] An embodiment of the present application provides a reverse-conducting insulated gate bipolar transistor, comprising: a substrate, the substrate comprising a first surface and a second surface opposite to each other along a first direction; a first collector doping region and a second collector doping region located in the substrate, the second surface exposing the first collector doping region and the second collector doping region, the second collector doping region comprising a first region and a second region, the second region contacting a side of the first region away from the second surface; a first short-circuit doping region located in the substrate, the second surface exposing the first short-circuit doping region, the first short-circuit doping region being located between the first collector doping region and the first region, and the second region contacting a side of the first short-circuit doping region away from the second surface.

[0006] In some embodiments, a maximum dimension of the second region along a second direction is greater than a maximum dimension of the first region along the second direction, and the second direction is parallel to the second surface.

[0007] In some embodiments, a maximum dimension of the second collector doping region along the first direction is greater than a maximum dimension of the first collector doping region along the first direction.

[0008] In some embodiments, a maximum dimension of the first region along the first direction is greater than a maximum dimension of the first collector doping region along the first direction.

[0009] In some embodiments, the reverse conducting insulated gate bipolar transistor further includes a third collector doping region exposed on the second surface, and the third collector doping region and the first collector doping region are respectively located on two sides of the first region.

[0010] In some embodiments, the substrate further includes a second short circuit doping region exposed on the second surface, the second short circuit doping region is located between the third collector doping region and the first region, and the second region contacts a side of the second short circuit doping region away from the second surface.

[0011] In some embodiments, the orthographic projections of the first short-circuit doped region and the second short-circuit doped region on the second surface are both located within the orthographic projection of the second region on the second surface.

[0012] In some embodiments, the second region includes a third surface away from the second surface, and the second region includes a first protruding region protruding relative to the third surface.

[0013] In some embodiments, the second region includes a fourth surface away from the first surface, and the second region includes a second protruding region protruding relative to the fourth surface.

[0014] In some embodiments, the first collector doping region includes a fifth surface away from the second surface, and the first collector doping region includes a third protruding region protruding relative to the fifth surface.

[0015] In some embodiments, the third raised areas are arranged alternately with the second raised areas.

[0016] In some embodiments, the first short-circuit doping region includes a first sub-short-circuit doping region and a second sub-short-circuit doping region, and the first sub-short-circuit doping region is located between the first collector doping region and the first region; the second sub-short-circuit doping region is in contact with a side of the first sub-short-circuit doping region away from the second surface, and the second sub-short-circuit doping region is connected between the first collector doping region and the second region.

[0017] In some embodiments, a size of the second sub-short circuit doping region along a second direction is greater than a size of the first sub-short circuit doping region along the second direction, and the second direction is parallel to the second surface.

[0018] In some embodiments, a cross-sectional shape of the second region in a direction perpendicular to the second surface is rectangular, square, or elliptical.

[0019] In some embodiments, the first collector doping region, the first region, and the second region have the same conductivity type, and the conductivity type of the first collector doping region is opposite to the conductivity type of the first short-circuit doping region.

[0020] In some embodiments, the substrate includes a well region, a carrier storage region, a drift region, and a buffer region stacked in sequence along the first direction, and a surface of the well region away from the carrier storage region is the first surface.

[0021] In some embodiments, the first collector doping region, the second region, the first region, and the first short circuit doping region are all located in the buffer region.

[0022] An embodiment of the present application also provides a method for forming a reverse-conducting insulated gate bipolar transistor, comprising: providing an initial substrate, the initial substrate comprising a first surface and a second surface opposite to each other along a first direction; performing ion implantation on one side of the second surface to form a second region; performing ion implantation on one side of the second surface to form a first region, the first region and the second region forming a first collector doping region, and the second region contacting a side of the first region away from the second surface; performing ion implantation on one side of the second surface to form a first short-circuit doping region, the first short-circuit doping region being adjacent to the first region, and the second region contacting a side of the first short-circuit doping region away from the second surface; performing ion implantation on one side of the second surface to form a first collector doping region, the first short-circuit doping region being located between the first collector doping region and the first region.

[0023] In some embodiments, the method of performing ion implantation on one side of the second surface to form the second region includes: using a photolithography process to form a first patterned layer on the second surface, the first patterned layer exposing a portion of the second surface; using the first patterned layer as a mask, performing a first ion implantation on the initial substrate to form the second region.

[0024] In some embodiments, the method of performing ion implantation on one side of the second surface to form a second region also includes: using a photolithography process to form a second patterned layer on the second surface, the second patterned layer includes a plurality of openings corresponding to the second region; using the second patterned layer as a mask, performing a second ion implantation on the initial substrate to form a doped region intersecting the second region; using a photolithography process to form a third patterned layer on the second surface, the openings of the third patterned layer corresponding to portions of the doped regions on both sides of the first region; using the third patterned layer as a mask, performing inversion ion implantation on portions of the doped regions to invert portions of the doped regions close to the second surface to form a first raised region and a second raised region located on both sides of the second region.

[0025] In some embodiments, the method of performing ion implantation on one side of the second surface to form the first region includes: using a photolithography process to form a fourth patterned layer on the second surface, wherein the fourth patterned layer exposes the first region; using the fourth patterned layer as a mask, performing ion implantation on a portion of the doped region below and an initial substrate between the doped regions to form the first region.

[0026] In some embodiments, the method of performing ion implantation on one side of the second surface to form a first short-circuit doping region includes: performing inversion ion implantation on both sides of the first region along a second direction to shrink the first region along the second direction and form a first short-circuit doping region and a second short-circuit doping region located on both sides of the shrunk first region, and the second direction is parallel to the second surface.

[0027] In some embodiments, the method of performing ion implantation on one side of the second surface to form a first collector doping region includes: performing a first ion implantation on a portion of the initial substrate on a side of the first short-circuit doping region away from the first region to form a first collector doping region; performing a second ion implantation on a portion of the initial substrate corresponding to the first collector doping region to form a third raised region located on a side of the first collector doping region away from the second surface.

[0028] In some embodiments, it also includes:

[0029] A collector layer is formed on the second surface of the initial substrate, wherein the collector layer is connected to the first collector doping region, the first region and the first short circuit doping region.

[0030] In some embodiments, it also includes:

[0031] Before forming the second region, ion implantation is performed on the second surface to form a buffer zone, and the first collector doping zone, the second zone, the first zone and the first short-circuit doping zone are all formed in the buffer zone; the conductivity types of the first collector doping zone, the first zone and the second zone are opposite to the conductivity type of the buffer zone, and the conductivity type of the first short-circuit doping zone is the same as the conductivity type of the buffer zone.

[0032] In some embodiments, it also includes: performing ion implantation on the first surface to form a well region, a carrier storage region, and a drift region stacked in sequence along the first direction, wherein the surface of the well region away from the carrier storage region is the first surface; the conductivity type of the carrier storage region is the same as the conductivity type of the drift region, and the conductivity type of the well region is opposite to the conductivity type of the carrier storage region.

[0033] An embodiment of the present application also provides a chip, comprising the reverse conducting insulated gate bipolar transistor described in any of the above embodiments.

[0034] An embodiment of the present application also provides a vehicle, comprising the chip as described above.

[0035] The present application provides a reverse-conducting insulated gate bipolar transistor and a method for forming the same, wherein the second collector doping region is divided into a first region and a second region, wherein the second region contacts the side of the first region away from the second surface, that is, the second region is introduced into the substrate. Since the second region contacts the side of the first short-circuit doping region away from the second surface, that is, the second region covers the side of the first short-circuit doping region away from the second surface, electrons need to bypass the second region to reach the first short-circuit doping region, thus forming a short-circuit resistance region above the second region, increasing the resistance of the short-circuit resistance region, thereby improving the voltage rebound phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0037] Figure 1 is a schematic structural diagram of a reverse-conducting insulated gate bipolar transistor provided in some embodiments of the present application;

[0038] Figure 2 is a schematic structural diagram of a reverse-conducting insulated gate bipolar transistor provided in some embodiments of the present application;

[0039] Figure 3 is a schematic structural diagram of a reverse-conducting insulated gate bipolar transistor provided in some embodiments of the present application;

[0040] Figure 4is a schematic structural diagram of a reverse-conducting insulated gate bipolar transistor provided in some embodiments of the present application;

[0041] Figure 5 is a schematic structural diagram of a reverse-conducting insulated gate bipolar transistor provided in some embodiments of the present application;

[0042] Figure 6 is a schematic structural diagram of a reverse-conducting insulated gate bipolar transistor provided in some embodiments of the present application;

[0043] Figure 7 is a schematic flow chart of a method for forming a reverse conducting insulated gate bipolar transistor provided in some embodiments of the present application;

[0044] Figure 8 to Figure 17 It is a schematic structural diagram of a reverse conducting insulated gate bipolar transistor during the formation process provided in some embodiments of the present application. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0046] Due to the existence of short-circuit doping regions in the reverse-conducting insulated gate bipolar transistor, the device switches from unipolar mode to bipolar mode at the initial start-up, resulting in a voltage rebound phenomenon, which is not conducive to the parallel connection of the device and its use under low temperature conditions.

[0047] Based on the above situation, an embodiment of the present application provides a reverse-conducting insulated gate bipolar transistor, comprising a substrate, a first collector doping region and a second collector doping region located in the substrate, and a first short-circuit doping region located in the substrate. The substrate comprises a first surface and a second surface opposite to each other along a first direction, the second surface exposes the first collector doping region and the second collector doping region, the second collector doping region comprises a first region and a second region, the second region contacts a side of the first region away from the second surface. The second surface also exposes the first short-circuit doping region, the first short-circuit doping region is located between the first collector doping region and the first region, and the second region contacts a side of the first short-circuit doping region away from the second surface.

[0048] In the embodiment of the present application, the second collector doping region is divided into a first region and a second region, and the second region contacts the side of the first region away from the second surface, that is, the second region is introduced inside the substrate. Since the second region contacts the side of the first short-circuit doping region away from the second surface, that is, the second region covers the side of the first short-circuit doping region away from the second surface, electrons need to bypass the second region to reach the first short-circuit doping region, so a short-circuit resistance region is formed above the second region, increasing the short-circuit resistance of the short-circuit resistance region, thereby improving the voltage rebound phenomenon.

[0049] In one embodiment, the method of suppressing voltage rebound can also be achieved by increasing the ratio of the collector doping area to the short-circuit doping area, but this will cause uneven distribution of the reverse conduction current of the device. In addition, the voltage rebound phenomenon can also be suppressed by etching grooves on the back of the chip and filling them with insulating materials to increase the short-circuit resistance, but this process method is not easy to implement, which is mainly limited by the thickness of the chip. After the front structure of the cell is made, the etching process on the back of the chip will increase the risk of warping and fragmentation, which is difficult.

[0050] In the embodiment of the present application, since the ratio of the collector doping region (including the first collector doping region and the second collector doping region) and the first short-circuit doping region at the second surface is not increased, the second collector doping region is divided into the first region and the second region, and the second region is introduced inside the substrate, thereby achieving the purpose of suppressing voltage rebound while solving the problem of uneven distribution of reverse conduction current of the device. In addition, the embodiment of the present application does not need to etch the back of the chip, but introduces the second collector doping region into the substrate to increase the short-circuit resistance of the device structure, thereby improving the voltage rebound phenomenon, reducing the risk of chip warping and fragmentation, and reducing the process difficulty.

[0051] The specific structure of the reverse conducting insulated gate bipolar transistor is described in detail below with reference to the accompanying drawings.

[0052] See also Figure 1 , Figure 1 It is a schematic diagram of the structure of a reverse conducting insulated gate bipolar transistor provided in some embodiments of the present application.

[0053] The reverse conducting insulated gate bipolar transistor 100 includes a substrate 10, a first collector doping region 1 and a second collector doping region 2 located in the substrate 10, and a first short-circuit doping region 3 located in the substrate 10. The substrate 10 includes a first surface 101 and a second surface 102 opposite to each other along a first direction X, and the second surface 102 exposes the first collector doping region 1 and the second collector doping region 2. The second collector doping region 2 includes a first region 21 and a second region 22, and the second region 22 contacts a side of the first region 21 away from the second surface 102. The second surface 102 also exposes the first short-circuit doping region 3, and the first short-circuit doping region 3 is located between the first collector doping region 1 and the first region 21, and the second region 22 contacts a side of the first short-circuit doping region 3 away from the second surface 102.

[0054] In some embodiments, the first collector doping region 1, the first region 21, and the second region 22 have the same conductivity type, and the conductivity type of the first collector doping region 1 is opposite to the conductivity type of the first short-circuit doping region 3. For example, when the conductivity types of the first collector doping region 1, the first region 21, and the second region 22 are all P-type, the conductivity type of the first short-circuit doping region 3 is N-type; when the conductivity types of the first collector doping region 1, the first region 21, and the second region 22 are all N-type, the conductivity type of the first short-circuit doping region 3 is P-type.

[0055] It should be noted that the doped element types of the P-type doping region can be boron (B) and boron fluoride (BF2), and the doped element types of the N-type doping region can be phosphorus (P), arsenic (As) and hydrogen (H), and there are no specific restrictions on both.

[0056] In some embodiments, the substrate 10 includes a well region 3, a carrier storage region 4, a drift region 5, and a buffer region 6 stacked in sequence along the first direction X, and the surface of the well region 3 away from the carrier storage region 4 is the first surface 101. The first collector doping region 1, the second region 22, the first region 21, and the first short-circuit doping region 3 are all located in the buffer region 6. An electron channel can be formed in the well region 3, the carrier storage region 4 can enhance the conductivity modulation effect of the device, and the buffer region 6 can enhance the voltage resistance. Among them, the carrier storage region 4 can block holes coming from below and gather holes at the position of the carrier storage region 4, thereby attracting electrons from the emission region 7 to play a conductivity modulation role.

[0057] The conductivity type of the well region 3 may be the same as that of the first collector doping region 1 , and the conductivity types of the carrier storage region 4 , the drift region 5 and the buffer region 6 are opposite to that of the first collector doping region 1 , that is, the same as that of the first short-circuit doping region 3 .

[0058] For example, the conductivity type of the well region 3 is P type, the conductivity types of the carrier storage region 4, the drift region 5, the buffer region 6 and the first short circuit doping region 3 are all N type, and the conductivity types of the first collector doping region 1, the second region 22 and the first region 21 are all P type.

[0059] The reverse conducting insulated gate bipolar transistor 100 may further include a gate structure 20, an emitter region 7, an ohmic contact region (not shown) and an emitter electrode layer 30. The gate structure 20 penetrates a portion of the substrate 10 from the first surface 101, the emitter region 7 is located in the substrate 10 and connected to the side wall of the gate structure 20, the ohmic contact region is located in the substrate 10 and connected to the emitter region 7, and the emitter electrode layer 30 is connected to the ohmic contact region on the first surface 101 through a contact structure (not shown). Among them, the conductivity type of the emitter region 7 is opposite to the conductivity type of the ohmic contact region and the well region 3, for example, the conductivity type of the ohmic contact region and the well region 3 are both P-type. Specifically, the ohmic contact region can be a P-type heavily doped region, thereby reducing the contact resistance.

[0060] The reverse conducting insulated gate bipolar transistor 100 may further include a collector layer 40 , and the collector layer 40 is located on the second surface 102 .

[0061] The reverse-conducting insulated gate bipolar transistor 100 has a conversion process from unipolar to bipolar conduction mode. When the gate structure 20 is turned on, the area near the side wall of the trench gate 20 in the well region 3 is inverted to form an electron channel, and the electrons migrate to the collector layer 40 under the drive of the electric field. Due to the built-in electric field of the PN junction formed by the collector doping region (including the first collector doping region 1 and the second collector doping region 2) and the buffer region 6, the electrons are more inclined to flow into the collector layer 40 through the first short-circuit doping region 3 at the beginning of the device opening. When the current is small, the electrons all flow into the collector layer 40 through the first short-circuit doping region 3; as the current increases, the voltage drop generated by the electronic current on the buffer region 6 gradually increases. When it increases to the turn-on voltage of the PN junction, the device is in a critical state of switching from unipolar to bipolar. At this time, the electrons injected into the collector doping region begin to become active, and a large amount of hole current is injected into the buffer region 6 and the drift region 5, resulting in the generation of conductivity modulation, and the device enters the bipolar working mode.

[0062] like Figure 1As shown, at the initial stage of device startup, that is, when the device is in a unipolar state, the current flow path is: emitter region 7—well region 3—carrier storage region 4—drift region 5—buffer region 6—bypassing the second region 22 above the first short-circuit doping region 3 to the first short-circuit doping region 3—collector layer 40. The portion of the buffer region 6 above the second region 22 is called the short-circuit resistance region. Due to the presence of the second collector doping region 2 in the substrate 10, electrons need to bypass the second region 22 to reach the first short-circuit doping region 3. Therefore, the second region 22 greatly prolongs the flow path of the electron current and increases the short-circuit resistance, thereby suppressing the voltage rebound phenomenon of the reverse conducting insulated gate bipolar transistor 100.

[0063] As the short-circuit resistance increases, the voltage drop caused by the lateral flow of the electron current in the short-circuit resistance area increases. When the potential difference between the second area 22 and the short-circuit resistance area is greater than the built-in potential of the two, the PN junction is turned on, and the holes in the second collector doping area 2 begin to be injected into the drift area 5, and the second collector doping area 2 realizes the unipolar to bipolar conduction mode. Thereafter, as the voltage of the collector layer 40 increases, when the potential difference between the first collector doping area 1 and the buffer area 6 above it is greater than the built-in potential of the two, the PN junction is turned on, and the first collector doping area 1 enters the bipolar mode. Therefore, compared with the first collector doping area 1, the second collector doping area 2 will enter the bipolar mode first. In other words, the second collector doping area 2 accelerates the conduction mode of the reverse-conducting insulated gate bipolar transistor 100 from unipolar to bipolar.

[0064] In some embodiments, the maximum dimension of the second collector doping region 2 along the first direction X is greater than the maximum dimension of the first collector doping region 1 along the first direction X. In this way, the distance from the collector doping region (mainly the second collector doping region 2) to the emitter region 7 is shortened, the on-resistance is reduced, and thus the on-voltage drop of the device is reduced, which greatly reduces the turn-on loss of the device.

[0065] It should be noted that the size of the second collector doping region 2 along the first direction X refers to the thickness of the second collector doping region 2 in the longitudinal direction. When the second collector doping region 2 has multiple different sizes along the first direction X, that is, the thickness of the second collector doping region 2 at different positions is different, the maximum size of the second collector doping region 2 along the first direction X refers to the largest size among the multiple different sizes. Similarly, the maximum size of the first collector doping region 1 along the first direction X can be understood as the maximum thickness of the first collector doping region 1 in the longitudinal direction.

[0066] In some embodiments, the maximum dimension of the first region 21 along the first direction X is greater than the maximum dimension of the first collector doping region 1 along the first direction X. When the maximum thickness of the first region 21 is greater than the maximum thickness of the first collector doping region 1, the maximum thickness of the second collector doping region 2 is greater than the maximum thickness of the first collector doping region 1, thereby facilitating shortening the distance from the second collector doping region 2 to the emitter region 7.

[0067] In some embodiments, the maximum size of the second region 22 along the second direction Y is greater than the maximum size of the first region 21 along the second direction Y, and the second direction Y is parallel to the second surface 102. In this way, the size of the second region 22 in the second direction Y is larger, and the path for electrons to flow in the lateral direction (i.e., the second direction Y) is larger, which is conducive to increasing the short-circuit resistance of the short-circuit resistance region.

[0068] The size of the second collector doping region 2 along the first direction X and the size of the second region 22 along the second direction Y can be adjusted according to the magnitude of the snap-back voltage. The greater the concentration of doped ions in the buffer region 6, the smaller the resistance and the smaller the on-resistance. However, in order to suppress the snap-back voltage, the resistance of the short-circuit resistance region in the buffer region 6 needs to be increased. Therefore, the concentration of doped ions in the buffer region 6 can be adjusted according to the compromise between the snap-back voltage and the on-voltage drop.

[0069] In some embodiments, the reverse conducting insulated gate bipolar transistor 100 further includes a third collector doping region 8 exposed on the second surface 102 , and the third collector doping region 8 and the first collector doping region 1 are respectively located on two sides of the first region 21 .

[0070] The substrate 10 may further include a second short-circuit doping region 9 exposed at the second surface 102, the second short-circuit doping region 9 is located between the third collector doping region 8 and the first region 21, and the second region 22 covers a side of the second short-circuit doping region 9 away from the second surface 102. The second short-circuit doping region 9 may separate the third collector doping region 8 and the first region 21.

[0071] Since the second region 22 also covers the side of the second short-circuit doped region 9 away from the second surface 102 , electrons can bypass the second region 22 and flow to the second short-circuit doped region 9 , thereby accelerating the conduction mode of the reverse conducting insulated gate bipolar transistor 100 from unipolar to bipolar.

[0072] In some embodiments, Figure 1As shown, the size of the third collector doping region 8 along the first direction X may be equal to the size of the first collector doping region 1 along the first direction X. The size of the first short-circuit doping region 3 along the first direction X may be equal to the size of the second short-circuit doping region 9 along the first direction X, and both are equal to the size of the first region 21 along the first direction X. Then, the sizes of the first short-circuit doping region 3 and the second short-circuit doping region 9 along the first direction X may both be greater than the size of the third collector doping region 8 along the first direction X or the size of the first collector doping region 1 along the first direction X.

[0073] In some embodiments, the orthographic projections of the first short-circuit doped region 3 and the second short-circuit doped region 9 on the second surface 102 are both located within the orthographic projection of the second region 22 on the second surface 102, which is beneficial to increase the electron flow path.

[0074] Specifically, Figure 1 As shown, the distance from the left side of the first short-circuit doping region 3 to the right side of the second short-circuit doping region 9 is smaller than the size of the second region 22 in the second direction Y, thereby facilitating increasing the flow path for electrons to reach the first short-circuit doping region 3 and the second short-circuit doping region 9 .

[0075] In some embodiments, the cross-sectional shape of the second region 22 in a direction perpendicular to the second surface 102 is rectangular, square, or elliptical.

[0076] See also Figure 2 , Figure 2 1 is a schematic diagram of the structure of a reverse-conducting insulated gate bipolar transistor provided in some embodiments of the present application. For ease of understanding and brief description, the same reference numerals are used for the same structures as in the above embodiments, and the same structures are not described in detail. Only the different structures are described in detail in this embodiment.

[0077] The embodiments of the present application Figure 1 The difference between the embodiment and the embodiment is that the cross-sectional shape of the second region 22a in the second collector doping region 2a in the direction perpendicular to the second surface 102 is elliptical.

[0078] See also Figure 3 , Figure 3 1 is a schematic diagram of the structure of a reverse-conducting insulated gate bipolar transistor provided in some embodiments of the present application. For ease of understanding and brief description, the same reference numerals are used for the same structures as in the above embodiments, and the same structures are not described in detail. Only the different structures are described in detail in this embodiment.

[0079] The embodiments of the present application Figure 1The difference between the embodiment is that the first short-circuit doping region 3a includes a first sub-short-circuit doping region 31 and a second sub-short-circuit doping region 32, and the first sub-short-circuit doping region 31 is located between the first collector doping region 1 and the first region 21. The second sub-short-circuit doping region 32 is in contact with the side of the first sub-short-circuit doping region 31 away from the second surface 102, and the second sub-short-circuit doping region 32 is connected between the first collector doping region 1 and the second region 22, so the second sub-short-circuit doping region 32 covers part of the side of the first collector doping region 1 away from the second surface 102.

[0080] In some embodiments, the size of the second sub-short-circuit doping region 32 along the second direction Y is greater than the size of the first sub-short-circuit doping region 31 along the second direction Y. The cross-sectional shape of the second short-circuit doping region 9 may also be the same as the cross-sectional shape of the first short-circuit doping region 3a, so the sizes of the first short-circuit doping region 3a and the second short-circuit doping region 9 along the second direction Y can be adjusted. Since the first short-circuit doping region 3a and the second short-circuit doping region 9 serve as cathodes of the fast recovery diode device, the electrical characteristics required by the fast recovery diode device can be achieved by adjusting the lengths of the first short-circuit doping region 3a and the second short-circuit doping region 9 in the second direction Y.

[0081] See also Figure 4 , Figure 4 1 is a schematic diagram of the structure of a reverse-conducting insulated gate bipolar transistor provided in some embodiments of the present application. For ease of understanding and brief description, the same reference numerals are used for the same structures as in the above embodiments, and the same structures are not described in detail. Only the different structures are described in detail in this embodiment.

[0082] The embodiments of the present application Figure 1 The difference between the embodiment is that the second region 22b in the second collector doping region 2b includes a third surface 221 away from the second surface 102, and the second region 22b includes a first protruding region 222 protruding relative to the third surface 221. The first protruding region 222 can further extend the electron current flow path, thereby increasing the short-circuit resistance.

[0083] In some embodiments, the second region 22b includes a fourth surface 223 away from the first surface 101, and the second region 22b includes a second protruding region 224 protruding relative to the fourth surface 223. The second protruding region 224 can further extend the electron current flow path, thereby increasing the short-circuit resistance.

[0084] In some embodiments, the first collector doping region 1a includes a fifth surface 11 away from the second surface 102, and the first collector doping region 1a includes a third protruding region 111 protruding relative to the fifth surface 11. The third protruding region 111 can also further extend the electron current flow path, thereby increasing the short-circuit resistance.

[0085] The width and number of the first raised area 222 , the second raised area 224 and the third raised area 111 , as well as the concentration of doped ions in each raised area, can be adjusted according to the effect of suppressing the rebound voltage.

[0086] In some embodiments, the first raised area 222 , the second raised area 224 , and the third raised area 111 may exist at the same time, or only two of them may exist, or only one of them may exist.

[0087] like Figure 4 As shown, the first convex area 222, the second convex area 224 and the third convex area 111 exist at the same time, and the third convex area 111 and the second convex area 224 are arranged alternately along the second direction Y. Therefore, the second area 22b and the first collector doping area 1a are interlaced in a comb-tooth shape, which has a stronger effect of suppressing the voltage rebound phenomenon, and has the characteristics of lower conduction voltage drop and turn-on loss.

[0088] See also Figure 5 , Figure 5 1 is a schematic diagram of the structure of a reverse conducting insulated gate bipolar transistor provided in some embodiments of the present application, wherein only the first collector doping region 1 a includes a third protruding region 111 protruding relative to the fifth surface 11 .

[0089] See also Figure 6 , Figure 6 1 is a schematic diagram of the structure of a reverse-conducting insulated gate bipolar transistor provided in some embodiments of the present application. For ease of understanding and brief description, the same reference numerals are used for the same structures as in the above embodiments, and the same structures are not described in detail. Only the different structures are described in detail in the present embodiment.

[0090] The embodiments of the present application Figure 4The difference between the embodiment in the embodiment is that the first short-circuit doping region 3a includes a first sub-short-circuit doping region 31 and a second sub-short-circuit doping region 32, and the first sub-short-circuit doping region 31 is located between the first collector doping region 1a and the first region 21. The second sub-short-circuit doping region 32 is in contact with the side of the first sub-short-circuit doping region 31 away from the second surface 102, and the second sub-short-circuit doping region 32 is connected between the first collector doping region 1a and the second region 22. The size of the second sub-short-circuit doping region 32 along the second direction Y is greater than the size of the first sub-short-circuit doping region 31 along the second direction Y, and the second direction Y is parallel to the second surface 102. That is, Figure 6 The embodiment is Figure 4 Example and Figure 3 Combination of embodiments.

[0091] See also Figure 7 , Figure 7 The figure is a schematic flow chart of a method for forming a reverse conducting insulated gate bipolar transistor provided in some embodiments of the present application. The method for forming a reverse conducting insulated gate bipolar transistor comprises the following steps S1 to S5.

[0092] Step S1: providing an initial substrate, wherein the initial substrate comprises a first surface and a second surface opposite to each other along a first direction.

[0093] Step S2: performing ion implantation on one side of the second surface to form a second region.

[0094] Step S3: performing ion implantation on one side of the second surface to form a first region, the first region and the second region forming a first collector doping region, and the second region contacts a side of the first region away from the second surface.

[0095] Step S4: performing ion implantation on one side of the second surface to form a first short-circuit doped region, wherein the first short-circuit doped region is adjacent to the first region, and the second region is in contact with a side of the first short-circuit doped region away from the second surface.

[0096] Step S5: performing ion implantation on one side of the second surface to form a first collector doping region, wherein the first short circuit doping region is located between the first collector doping region and the first region.

[0097] In the method for forming a reverse-conducting insulated gate bipolar transistor provided in an embodiment of the present application, a second collector doping region is formed by ion implantation, and the second collector doping region is divided into a first region and a second region, and the second region contacts the side of the first region away from the second surface, that is, the second region is introduced into the substrate. Since the second region contacts the side of the first short-circuit doping region away from the second surface, that is, the second region covers the side of the first short-circuit doping region away from the second surface, electrons need to bypass the second region to reach the first short-circuit doping region, so a short-circuit resistance region is formed above the second region, and the short-circuit resistance of the short-circuit resistance region is increased, thereby improving the voltage rebound phenomenon.

[0098] The method for forming the reverse conducting insulated gate bipolar transistor is described in detail below with reference to the accompanying drawings.

[0099] See also Figure 8 to Figure 17 , Figure 8 to Figure 17 It is a schematic structural diagram of a reverse conducting insulated gate bipolar transistor during the formation process provided in some embodiments of the present application.

[0100] Step S1: Provide an initial substrate 10a, wherein the initial substrate 10a includes a first surface 101 and a second surface 102 opposite to each other along a first direction X. Figure 8 .

[0101] The material of the initial substrate 10 a may include at least one of Si, SiC, GaAs or GaN, and the initial substrate 10 a may have lightly doped ions of the first conductivity type (for subsequent formation of a drift region).

[0102] like Figure 8 As shown, the method for forming the reverse conducting insulated gate bipolar transistor may further include: performing ion implantation on the first surface 101 to form a well region 3, a carrier storage region 4, and a drift region 5 stacked in sequence along the first direction X, wherein the surface of the well region 3 away from the carrier storage region 4 is the first surface 101. The conductivity type of the carrier storage region 4 is the same as that of the drift region 5, and the conductivity type of the well region 3 is opposite to that of the carrier storage region 4.

[0103] Specifically, the first conductive type ion doping and high temperature well driving process can be performed on the first surface 101 of the initial substrate 10a to form a first conductive type carrier storage region 4 in the initial substrate 10a, and the undoped portion of the initial substrate 10a away from the first surface 101 forms the drift region 5. If the first conductive type lightly doped initial substrate 10a is selected, the undoped portion of the initial substrate 10a away from the first surface 101 can form the drift region 5 of the first conductive type.

[0104] Specifically, the first surface 101 of the initial substrate 10a may be doped with ions of the second conductivity type to form a well region 3 located on the side of the carrier storage region 4 away from the first surface 101, that is, the carrier storage region 4 is located between the well region 3 and the drift region 5. The junction depth of the well region 3 may be 1 um to 3 um, for example, 1 um, 2 um or 3 um.

[0105] The second conductivity type is opposite to the first conductivity type. When the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type.

[0106] The method for forming the reverse-conducting insulated gate bipolar transistor may further include: forming an emitter region 7 by ion implantation; forming a trench penetrating the well region 3, the carrier storage region 4 and the portion of the drift region 5; forming a gate structure 20 in the trench, wherein the emitter region 7 is located on the sidewall of the gate structure 20; and forming a dielectric layer 50 covering the gate structure 20 on the first surface 101. The material of the dielectric layer 50 may include phosphosilicate glass or other insulating materials.

[0107] In some embodiments, the formation process of the emitter region 7, the well region 3 and the carrier storage region 4 can be prepared before or after the trenches.

[0108] Specifically, an insulating layer 201 is first formed on the inner walls of the trenches, and then a conductive layer 202 is formed on the surface of the insulating layer 201 to form the gate structure 20 .

[0109] The formation process of the insulating layer 201 can be: first, a sacrificial oxide layer is grown on the inner wall of each groove by high-temperature oxidation; the sacrificial oxide layer is etched away by a wet method, thereby removing the damaged layer inside the groove and exposing the initial substrate 10a material with better quality, which can reduce the crystal defects and impurities on the inner wall of the groove; and a layer of oxide layer is grown on the inner wall of each groove area by high-temperature oxidation to form the insulating layer 201. This process can form an insulating layer 201 with better density.

[0110] The formation process of the conductive layer 202 may be: firstly depositing polysilicon doped with first conductivity type ions, and then removing the polysilicon on the first surface 101 to form the conductive layer 202 in the trench.

[0111] In some embodiments, the depth of the trench may be 2um to 8um, such as 2um, 5um or 8um. The insulating layer material includes at least one of SiO2, HfO2, Al2O3, Si3N4, and the insulating layer may also include other high-k (dielectric constant) dielectric materials.

[0112] In some embodiments, the width (ie, distance) between adjacent trenches and the number of trenches can be adjusted according to the channel current density, and the doping concentration of the well region 3 can be adjusted according to the threshold value required by the device.

[0113] In some embodiments, the reverse conducting insulated gate bipolar transistor may also be a planar reverse conducting insulated gate bipolar transistor, that is, the gate structure 20 is formed on the first surface 101 .

[0114] The method for forming the reverse conducting insulated gate bipolar transistor may further include: etching the dielectric layer 50 to form a contact hole, and implanting high-concentration second conductive type ions through the contact hole to form a heavily doped ohmic contact region, wherein the ohmic contact region is in contact with the emitter region 7 .

[0115] The method for forming the reverse conducting insulated gate bipolar transistor may further include: forming an emitter electrode layer 30 on the surface of the dielectric layer 50 and the first surface 101 of the fast recovery diode region 1102. The material of the emitter electrode layer 30 may include aluminum / silicon alloy or aluminum / silicon / copper alloy.

[0116] Step S2: performing ion implantation on one side of the second surface 102 to form a second region 22 .

[0117] In some embodiments, see Figure 9-10 .

[0118] See also Fig. 9 , flip the initial substrate 10a, and thin the second surface 102 of the initial substrate 10a to a desired thickness.

[0119] The method for forming the reverse conducting insulated gate bipolar transistor may further include: before forming the second region 22, performing ion implantation on the second surface 102 to form a buffer region 6, wherein the first collector doping region 1, the second region 22, the first region 21 and the first short circuit doping region 3 are all formed in the buffer region 6. After forming the buffer region 6, the initial substrate 10a forms the substrate 10.

[0120] In some embodiments, the conductivity types of the first collector doping region 1 , the first region 21 , and the second region 22 are opposite to the conductivity type of the buffer region 6 , and the conductivity type of the first short-circuit doping region 3 is the same as the conductivity type of the buffer region 6 .

[0121] In some embodiments, the buffer region 6 can also be prepared before the ion implantation process of the first surface 101. Alternatively, a double-layer epitaxial material having both the drift region 5 and the buffer region 6 can be selected as the initial substrate 10a for the process start, which can replace the ion implantation process using the buffer region 6 described above.

[0122] See also Fig.10 A first patterned layer 61 is formed on the second surface 102 by a photolithography process, wherein the first patterned layer 61 exposes a portion of the second surface 102; and the first patterned layer 61 is used as a mask to perform a first ion implantation on the initial substrate 10a to form the second region 22. The cross-sectional shape of the second region 22 is a rectangle.

[0123] In some embodiments, see Figures 9 to 12 , the method for forming the second region 22b may further include the following steps.

[0124] See also Fig.11 A second patterned layer 62 is formed on the second surface 102 by photolithography, wherein the second patterned layer 62 includes a plurality of openings corresponding to the second region 22. Using the second patterned layer 62 as a mask, a second ion implantation is performed on the initial substrate 10a to form a doped region 220 intersecting the second region 22.

[0125] See also Fig.12 , a third patterned layer 63 is formed on the second surface 102 by a photolithography process, and the openings of the third patterned layer 63 correspond to the parts of the doped regions 220 on both sides of the first region 21. Using the third patterned layer 63 as a mask, inversion ion implantation is performed on parts of the doped regions 220, and the parts of the doped regions 220 close to the second surface 102 are inverted to form the first raised regions 222 and the second raised regions 224 on both sides of the second region 22, thereby forming the second region 22b including the first raised regions 222 and the second raised regions 224.

[0126] Step S3: Perform ion implantation on one side of the second surface 102 to form a first region 21, wherein the first region 21 and the second region 22b form a first collector doping region 1, and the second region 22b contacts the side of the first region 21 away from the second surface 102. Fig.13 .

[0127] A fourth patterned layer 64 is formed on the second surface 102 by a photolithography process, and the fourth patterned layer 64 exposes the first region 21; using the fourth patterned layer 64 as a mask, ion implantation is performed on the lower portion of the doped region 220 and the initial substrate 10a between the doped regions 220 to form the first region 21. The first region 21 and the second region 22b constitute a second collector doped region.

[0128] Step S4: Perform ion implantation on one side of the second surface 102 to form a first short-circuit doped region 3, wherein the first short-circuit doped region 3 is adjacent to the first region 21, and the second region 22b is in contact with a side of the first short-circuit doped region 3 away from the second surface 102. Fig.14 .

[0129] Inversion ion implantation is performed on both sides of the first region 21 along the second direction Y to shrink the first region 21 along the second direction Y and form a first short-circuit doping region 3 and a second short-circuit doping region 9 located on both sides of the shrunk first region 21. The second direction Y is parallel to the second surface 102.

[0130] Step S5: Perform ion implantation on one side of the second surface 102 to form a first collector doping region 1, wherein the first short circuit doping region 3 is located between the first collector doping region 1 and the first region 21. Fig.15 .

[0131] A first ion implantation is performed on a portion of the initial substrate 10 a at a side of the first short-circuit doping region 3 away from the first region 21 to form a first collector doping region 1 .

[0132] In some embodiments, the third collector doping region 8 may be formed together with the first collector doping region 1 , and the third collector doping region 8 and the first collector doping region 1 are respectively located on both sides of the first region 21 .

[0133] In some embodiments, see Figures 15-16 .

[0134] See also Fig.16 , a second ion implantation is performed on a portion of the initial substrate 10a corresponding to the first collector doping region 1 to form a third raised region 111 located on a side of the first collector doping region 1 away from the second surface 102 , thereby forming a first collector doping region 1a including the third raised region 111 .

[0135] See also Fig.17 The method for forming the reverse conducting insulated gate bipolar transistor may further include: forming a collector layer 40 on the second surface 102 of the initial substrate 10a, wherein the collector layer 40 is connected to the first collector doping region 1a, the first region 21 and the first short-circuit doping region 3.

[0136] An embodiment of the present application also provides a chip, which includes the reverse conducting insulated gate bipolar transistor in any of the above embodiments. The chip has all the beneficial effects of the above reverse conducting insulated gate bipolar transistor, which will not be described in detail in the present application.

[0137] An embodiment of the present application also provides a vehicle, which includes the chip in any of the above embodiments. The vehicle has all the beneficial effects of the above chips, which will not be described in detail in this application.

[0138] The vehicle may be a fuel vehicle, a plug-in hybrid vehicle or a new energy vehicle, etc., and this application does not make any specific limitation on this.

[0139] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0140] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0141] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0142] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A reverse conducting insulated gate bipolar transistor (100), characterized in that: include: A substrate (10), the substrate (10) comprising a first surface (101) and a second surface (102) opposite to each other along a first direction (X); A first collector doping region (1) and a second collector doping region (2) located in the substrate (10), the second surface (102) exposing the first collector doping region (1) and the second collector doping region (2), the second collector doping region (2) comprising a first region (21) and a second region (22), the second region (22) being in contact with a side of the first region (21) away from the second surface (102); A first short-circuit doping region (3) is located in the substrate (10), the second surface (102) exposes the first short-circuit doping region (3), the first short-circuit doping region (3) is located between the first collector doping region (1) and the first region (21), and the second region (22) is in contact with a side of the first short-circuit doping region (3) away from the second surface (102).

2. The reverse conducting insulated gate bipolar transistor (100) according to claim 1, characterized in that: The maximum dimension of the second area (22) along the second direction (Y) is greater than the maximum dimension of the first area (21) along the second direction (Y), and the second direction (Y) is parallel to the second surface (102).

3. The reverse conducting insulated gate bipolar transistor (100) according to claim 1, characterized in that: The maximum size of the second collector doping region (2) along the first direction (X) is greater than the maximum size of the first collector doping region (1) along the first direction (X).

4. The reverse conducting insulated gate bipolar transistor (100) according to claim 3, characterized in that: The maximum dimension of the first region (21) along the first direction (X) is greater than the maximum dimension of the first collector doping region (1) along the first direction (X).

5. The reverse conducting insulated gate bipolar transistor (100) according to claim 1, characterized in that: The reverse-conducting insulated gate bipolar transistor (100) further comprises a third collector doping region (8) exposed on the second surface (102), wherein the third collector doping region (8) and the first collector doping region (1) are respectively located on two sides of the first region (21).

6. The reverse conducting insulated gate bipolar transistor (100) according to claim 5, characterized in that: The substrate (10) further comprises a second short-circuit doping region (9) exposed on the second surface (102), the second short-circuit doping region (9) being located between the third collector doping region (8) and the first region (21), and the second region (22) being in contact with a side of the second short-circuit doping region (9) away from the second surface (102).

7. The reverse conducting insulated gate bipolar transistor (100) according to claim 5, characterized in that: The orthographic projections of the first short-circuit doped region (3) and the second short-circuit doped region (9) on the second surface (102) are both located within the orthographic projection of the second region (22) on the second surface (102).

8. The reverse conducting insulated gate bipolar transistor (100) according to claim 1, characterized in that: The second area (22) includes a third surface (221) on a side away from the second surface (102), and the second area (22) includes a first protruding area (222) protruding relative to the third surface (221).

9. The reverse conducting insulated gate bipolar transistor (100) according to claim 1, characterized in that: The second area (22) includes a fourth surface (223) on a side away from the first surface (101), and the second area (22) includes a second protruding area (224) protruding relative to the fourth surface (223).

10. The reverse conducting insulated gate bipolar transistor (100) according to claim 1 or 8, characterized in that: The first collector doping region (1) comprises a fifth surface (11) away from the second surface (102), and the first collector doping region (1) comprises a third protruding region (111) protruding relative to the fifth surface (11).

11. The reverse conducting insulated gate bipolar transistor (100) according to claim 10, characterized in that: The third raised areas (111) and the second raised areas (224) are arranged alternately.

12. The reverse conducting insulated gate bipolar transistor (100) according to claim 1, characterized in that: The first short-circuit doping region (3) comprises a first sub-short-circuit doping region (31) and a second sub-short-circuit doping region (32), and the first sub-short-circuit doping region (31) is located between the first collector doping region (1) and the first region (21); The second sub-short circuit doping region (32) is in contact with a side of the first sub-short circuit doping region (31) away from the second surface (102), and the second sub-short circuit doping region (32) is connected between the first collector doping region (1) and the second region (22).

13. The reverse conducting insulated gate bipolar transistor (100) according to claim 12, characterized in that: The size of the second sub-short-circuit doped region (32) along the second direction (Y) is greater than the size of the first sub-short-circuit doped region (31) along the second direction (Y), and the second direction (Y) is parallel to the second surface (102).

14. The reverse conducting insulated gate bipolar transistor (100) according to claim 1, characterized in that: The cross-sectional shape of the second area (22) in a direction perpendicular to the second surface (102) is rectangular, square or elliptical.

15. The reverse conducting insulated gate bipolar transistor (100) according to claim 1, characterized in that: The first collector doping region (1), the first region (21) and the second region (22) have the same conductivity type, and the conductivity type of the first collector doping region (1) is opposite to the conductivity type of the first short-circuit doping region (3).

16. The reverse conducting insulated gate bipolar transistor (100) according to claim 1, characterized in that: The substrate (10) comprises a well region (3), a carrier storage region (4), a drift region (5), and a buffer region (6) stacked in sequence along the first direction (X); a surface of the well region (3) away from the carrier storage region (4) is the first surface (101).

17. The reverse conducting insulated gate bipolar transistor (100) according to claim 16, characterized in that: The first collector doping region (1), the second region (22), the first region (21) and the first short-circuit doping region (3) are all located in the buffer region (6).

18. A method for forming a reverse conducting insulated gate bipolar transistor, characterized in that: include: Providing an initial substrate (10a), wherein the initial substrate (10a) comprises a first surface (101) and a second surface (102) opposite to each other along a first direction (X); Performing ion implantation on one side of the second surface (102) to form a second region (22); Ion implantation is performed on one side of the second surface (102) to form a first region (21), the first region (21) and the second region (22) forming a first collector doping region (1), and the second region (22) is in contact with a side of the first region (21) away from the second surface (102); Ion implantation is performed on one side of the second surface (102) to form a first short-circuit doped region (3), wherein the first short-circuit doped region (3) is adjacent to the first region (21), and the second region (22) is in contact with a side of the first short-circuit doped region (3) away from the second surface (102); Ion implantation is performed on one side of the second surface (102) to form a first collector doping region (1), and the first short-circuit doping region (3) is located between the first collector doping region (1) and the first region (21).

19. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 18, wherein: The method of forming the second region (22) by ion implantation on one side of the second surface (102) comprises: forming a first patterned layer (61) on the second surface (102) by using a photolithography process, wherein the first patterned layer (61) exposes a portion of the second surface (102); Using the first patterned layer (61) as a mask, a first ion implantation is performed on the initial substrate (10a) to form the second region (22).

20. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 19, wherein: The method of performing ion implantation on one side of the second surface (102) to form the second region (22) further comprises: forming a second patterned layer (62) on the second surface (102) by using a photolithography process, wherein the second patterned layer (62) comprises a plurality of openings corresponding to the second area (22); Using the second patterned layer (62) as a mask, a second ion implantation is performed on the initial substrate (10a) to form a doped region intersecting with the second region (22); Using a photolithography process to form a third patterned layer (63) on the second surface (102), the openings of the third patterned layer (63) corresponding to parts of the doped regions on both sides of the first region (21); Using the third patterned layer (63) as a mask, inversion ion implantation is performed on part of the doped region to invert the portion of the doped region close to the second surface (102) to form a first raised region (222) and a second raised region (224) located on both sides of the second region (22).

21. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 20, wherein: The method of forming the first region (21) by ion implantation on one side of the second surface (102) comprises: forming a fourth patterned layer (64) on the second surface (102) by using a photolithography process, wherein the fourth patterned layer (64) exposes the first area (21); Using the fourth patterned layer (64) as a mask, ion implantation is performed on a portion of the doped region below and the initial substrate (10a) between the doped regions to form the first region (21).

22. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 18, wherein: The method of performing ion implantation on one side of the second surface (102) to form a first short-circuit doping region (3) comprises: Inverse ion implantation is performed on both sides of the first region (21) along a second direction (Y) to shrink the first region (21) along the second direction (Y) and form a first short-circuit doping region (3) and a second short-circuit doping region (9) located on both sides of the shrunken first region (21), wherein the second direction (Y) is parallel to the second surface (102).

23. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 18, wherein: The method of performing ion implantation on one side of the second surface (102) to form a first collector doping region (1) comprises: Performing a first ion implantation on a portion of the initial substrate (10a) on a side of the first short-circuit doping region (3) away from the first region (21) to form a first collector doping region (1); A second ion implantation is performed on a portion of the initial substrate (10a) corresponding to the first collector doping region (1) to form a third raised region (111) located on a side of the first collector doping region (1) away from the second surface (102).

24. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 18, wherein: Also includes: A collector layer (40) is formed on the second surface (102) of the initial substrate (10a), and the collector layer (40) is connected to the first collector doping region (1), the first region (21) and the first short-circuit doping region (3).

25. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 18, wherein: Also includes: Before forming the second region (22), ion implantation is performed on the second surface (102) to form a buffer region (6), wherein the first collector doping region (1), the second region (22), the first region (21) and the first short-circuit doping region (3) are all formed in the buffer region (6); The conductivity types of the first collector doping region (1), the first region (21) and the second region (22) are opposite to the conductivity type of the buffer region (6), and the conductivity type of the first short-circuit doping region (3) is the same as the conductivity type of the buffer region (6).

26. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 18, wherein: Also includes: Ion implantation is performed on the first surface (101) to form a well region (3), a carrier storage region (4) and a drift region (5) stacked in sequence along the first direction (X), wherein the surface of the well region (3) away from the carrier storage region (4) is the first surface (101); The conductivity type of the carrier storage region (4) is the same as the conductivity type of the drift region (5), and the conductivity type of the well region (3) is opposite to the conductivity type of the carrier storage region (4).

27. A chip, characterized in that: It comprises the reverse conducting insulated gate bipolar transistor according to any one of claims 1 to 17.

28. A vehicle, characterized in that: Comprising the chip as claimed in claim 27.

Images