Groove type MOSFET device structure and preparation method thereof

Abstract

The invention provides a trench type MOSFET device structure and a preparation method thereof, in the trench type MOSFET device structure or the prepared trench type MOSFET device structure, a gate conductive structure comprises a plurality of gate polycrystalline silicon layers, and the doping types of two adjacent gate polycrystalline silicon layers are different, so that at least one PN junction is formed in the gate conductive structure; at least one gate junction capacitor is arranged in the gate conductive structure, and the gate junction capacitors are connected in series with an intrinsic capacitor (namely an intrinsic gate-drain capacitor) of the device, so that the total gate-drain capacitance of the device is reduced, the gate-drain charge is reduced, the dynamic loss of the device is reduced, and meanwhile, the characteristic on-resistance of the device is not improved. That is to say, according to the trench type MOSFET device structure and the preparation method thereof, the compromise relation between the gate leakage charge and the characteristic on-resistance is optimized, and the electrical performance of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors and relates to a trench MOSFET device structure and a preparation method thereof. Background Art

[0002] In the field of medium and low voltage power devices, trench metal-oxide-semiconductor field effect transistors (MOSFETs) have a characteristic on-resistance R sp With the advantages of low switching speed, fast switching speed, high cell density and low drive current, it is widely used in fields such as motor drive, power management, synchronous rectification, energy storage control, etc. In recent years, with the development of technology and industry, the requirements for MOSFET dynamic parameters in mid-to-high-end fields such as communications and industrial control are getting higher and higher. Among the dynamic parameters of MOSFET, gate-drain charge Q gd The most important. Gate-drain charge Q gd The smaller the MOSFET is, the faster the switching speed is and the smaller the dynamic loss is. The traditional trench MOSFET has a large overlap area between the gate and the drift region because its trench is embedded in the epitaxial layer, thus increasing the gate-drain capacitance C. gd Larger, and C gd Reflects the gate-drain charge Q gd The gate-drain charge Q of the trench MOSFET is gd It is generally large, which results in large dynamic losses when the device is switched, limiting its practical application.

[0003] Therefore, how to provide a new trench MOSFET device structure and its preparation method to reduce the gate-drain capacitance, thereby reducing the gate-drain charge, reducing dynamic loss, and improving the electrical performance of the device has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0004] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a trench MOSFET device structure and a preparation method thereof, which is used to solve the problem that the existing trench MOSFET has large dynamic losses during device switching due to large gate-drain charges, which limits its practical application.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a trench MOSFET device structure, comprising the following steps:

[0007] Providing a substrate, forming a gate trench in the substrate, the substrate comprising a base layer and an epitaxial layer located on the base layer, the gate trench opening from a top surface of the epitaxial layer and extending downward but not penetrating the epitaxial layer;

[0008] forming a gate dielectric layer, wherein the gate dielectric layer conformally covers the inner wall of the gate trench but does not completely fill the gate trench;

[0009] forming a gate conductive structure in the gate trench, the gate conductive structure comprising a first gate polysilicon layer of a first conductivity type and a second gate polysilicon layer of a second conductivity type, wherein the first gate polysilicon layer conformally covers the surface of the gate dielectric layer and does not completely fill the gate trench, and the second gate polysilicon layer fills the space enclosed by the first gate polysilicon layer, and the second conductivity type is opposite to the first conductivity type;

[0010] forming a base region of the second conductivity type in the epitaxial layer on both sides of the gate trench, and forming a source region of the first conductivity type on the upper surface layer of the base region;

[0011] An interlayer dielectric layer is formed on the epitaxial layer, and a conductive via, a front metal layer and a back metal layer are formed. The conductive via penetrates the interlayer dielectric layer and extends into the source region and the base region to be electrically connected to the source region and the base region. The front metal layer is located on the interlayer dielectric layer and is electrically connected to the conductive via. The back metal layer is located on a side of the substrate layer away from the epitaxial layer.

[0012] Optionally, the second gate polysilicon layer completely fills the space surrounded by the first gate polysilicon layer.

[0013] Optionally, forming a gate conductive structure in the gate trench includes the following steps:

[0014] depositing a first polysilicon layer, wherein the first polysilicon layer fills the gate trench and extends to a surface outside the gate trench;

[0015] performing ion implantation to introduce first conductivity type impurities into the first polysilicon layer;

[0016] depositing a second polysilicon layer, wherein the second polysilicon layer fills the gate trench and extends to a surface of the first polysilicon layer outside the gate trench;

[0017] performing ion implantation to introduce second conductivity type impurities into the second polysilicon layer;

[0018] Chemical mechanical polishing is performed to remove the first polysilicon layer and the second polysilicon layer outside the gate trench, wherein the portion of the first polysilicon layer located in the gate trench constitutes the first gate polysilicon layer, and the portion of the second polysilicon layer located in the gate trench constitutes the second gate polysilicon layer.

[0019] Optionally, in a direction from the epitaxial layer to the substrate layer, the thickness of the second gate polysilicon layer is T1, and the thickness of the first gate polysilicon layer is T2, wherein the range of T1 / T2 is 1 / 3 to 3 / 1.

[0020] Optionally, the doping concentration range of the first gate polysilicon layer is 1e13 cm -3 ~1e17 cm -3 The doping concentration of the second gate polysilicon layer is in the range of 1e13 cm -3 ~1e17 cm -3 .

[0021] Optionally, the second gate polysilicon layer does not fill the space enclosed by the first gate polysilicon layer, and the gate conductive structure further includes a third gate polysilicon layer of the first conductivity type, and the third gate polysilicon layer fills the space enclosed by the second gate polysilicon layer.

[0022] Optionally, forming a gate conductive structure in the gate trench includes the following steps:

[0023] depositing a first polysilicon layer, wherein the first polysilicon layer fills the gate trench and extends to a surface outside the gate trench;

[0024] performing ion implantation to introduce first conductivity type impurities into the first polysilicon layer;

[0025] depositing a second polysilicon layer, wherein the second polysilicon layer fills the gate trench and extends to a surface of the first polysilicon layer outside the gate trench;

[0026] performing ion implantation to introduce second conductivity type impurities into the second polysilicon layer;

[0027] depositing a third polysilicon layer, wherein the third polysilicon layer fills the gate trench and extends to a surface of the second polysilicon layer outside the gate trench;

[0028] performing ion implantation to introduce first conductivity type impurities into the third polysilicon layer;

[0029] Chemical mechanical polishing is performed to remove the first polysilicon layer, the second polysilicon layer and the third polysilicon layer outside the gate trench, wherein the portion of the first polysilicon layer located in the gate trench constitutes the first gate polysilicon layer, the portion of the second polysilicon layer located in the gate trench constitutes the second gate polysilicon layer, and the portion of the third polysilicon layer located in the gate trench constitutes the third gate polysilicon layer.

[0030] Optionally, in the direction of the epitaxial layer pointing to the substrate layer, the thickness of the third gate polysilicon layer is T3, the thickness of the second gate polysilicon layer is T4, and the thickness of the first gate polysilicon layer is T5, wherein the range of T3 / T4 is 1 / 3 to 3 / 1, and the range of T4 / T5 is 1 / 3 to 3 / 1.

[0031] Optionally, the doping concentration range of the first gate polysilicon layer is 1e13 cm -3 ~1e17 cm -3 The doping concentration of the second gate polysilicon layer is in the range of 1e13 cm -3 ~1e17 cm -3 The doping concentration range of the third gate polysilicon layer is 1e13 cm -3 ~1e17 cm -3 .

[0032] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.

[0033] The present invention also provides a trench MOSFET device structure, comprising:

[0034] A substrate, comprising a substrate layer and an epitaxial layer located on the substrate layer;

[0035] a gate trench opening from a top surface of the epitaxial layer and extending downward but not penetrating the epitaxial layer;

[0036] a gate dielectric layer conformally covering an inner wall of the gate trench and not completely filling the gate trench;

[0037] a gate conductive structure, located in the gate trench and comprising a first gate polysilicon layer of a first conductivity type and a second gate polysilicon layer of a second conductivity type, wherein the first gate polysilicon layer conformally covers the surface of the gate dielectric layer and does not completely fill the gate trench, and the second gate polysilicon layer fills the space enclosed by the first gate polysilicon layer, and the second conductivity type is opposite to the first conductivity type;

[0038] A base region of the second conductivity type is located in the epitaxial layer on both sides of the gate trench;

[0039] A source region of a first conductivity type, located on an upper surface layer of the base region;

[0040] an interlayer dielectric layer, located on the epitaxial layer;

[0041] a conductive via penetrating the interlayer dielectric layer and extending into the source region and the base region to be electrically connected to the source region and the base region;

[0042] a front metal layer, located on the interlayer dielectric layer and electrically connected to the conductive through hole;

[0043] The back metal layer is located on a side of the substrate layer away from the epitaxial layer.

[0044] Optionally, the second gate polysilicon layer completely fills the space surrounded by the first gate polysilicon layer.

[0045] Optionally, the second gate polysilicon layer does not fill the space enclosed by the first gate polysilicon layer, and the gate conductive structure further includes a third gate polysilicon layer of the first conductivity type, and the third gate polysilicon layer fills the space enclosed by the second gate polysilicon layer.

[0046] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.

[0047] As described above, in the trench MOSFET device structure and preparation method of the present invention, the gate conductive structure includes multiple gate polysilicon layers, wherein the doping types of two adjacent gate polysilicon layers are different, thereby forming at least one PN junction within the gate conductive structure, so that the gate conductive structure has at least one gate junction capacitor within the gate conductive structure. This gate junction capacitor or capacitors are connected in series with the inherent capacitance of the device (i.e., the intrinsic gate-drain capacitance), so that the total gate-drain capacitance of the device is reduced, the gate-drain charge is reduced, and thus the dynamic loss of the device is reduced without increasing the characteristic on-resistance of the device. In other words, the trench MOSFET device structure and preparation method of the present invention optimize the trade-off relationship between gate-drain charge and characteristic on-resistance, which helps to improve the electrical performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 Shown is a schematic cross-sectional view of a trench MOSFET device.

[0049] Figure 2 Shown is a process flow chart of a method for preparing a trench MOSFET device structure according to the present invention.

[0050] Figure 3 It is a schematic diagram showing the structure obtained after forming a gate trench in a substrate according to the method for preparing a trench MOSFET device structure of the present invention.

[0051] Figure 4 It is a schematic diagram showing the structure obtained after forming the gate dielectric layer according to the method for preparing the trench MOSFET device structure of the present invention.

[0052] Figure 5 Schematic diagram showing a structure obtained after depositing a first polysilicon layer of a predetermined thickness in one embodiment of a method for fabricating a trench MOSFET device structure of the present invention.

[0053] Figure 6 Schematic diagram showing a structure obtained after depositing a second polysilicon layer of a predetermined thickness in one embodiment of a method for fabricating a trench MOSFET device structure of the present invention.

[0054] Figure 7 Schematic diagram showing a structure obtained after removing the first polysilicon layer and the second polysilicon layer outside the gate trench in one embodiment of the method for fabricating a trench MOSFET device structure of the present invention.

[0055] Figure 8 It is a schematic diagram showing a structure obtained after depositing a first polysilicon layer of a predetermined thickness in another embodiment of the method for preparing a trench MOSFET device structure of the present invention.

[0056] Figure 9 It is a schematic diagram showing a structure obtained after depositing a second polysilicon layer of a predetermined thickness in another embodiment of the method for preparing a trench MOSFET device structure of the present invention.

[0057] Figure 10 It is a schematic diagram showing a structure obtained after depositing a third polysilicon layer of a predetermined thickness in another embodiment of the method for preparing a trench MOSFET device structure of the present invention.

[0058] Figure 11 A schematic diagram showing a structure obtained after removing the first polysilicon layer, the second polysilicon layer, and the third polysilicon layer outside the gate trench in another embodiment of the method for fabricating a trench MOSFET device structure of the present invention.

[0059] Figure 12 Shown as Figure 7 Schematic diagram of the structure obtained after the source region is formed in the preamble structure shown.

[0060] Figure 13 Shown as Figure 11 Schematic diagram of the structure obtained after the source region is formed in the preamble structure shown.

[0061] Figure 14 Displayed based on Figure 12 The schematic diagram of the structure obtained after the back metal layer is formed on the previous structure is shown.

[0062] Figure 15 Displayed based on Figure 13 The schematic diagram of the structure obtained after the back metal layer is formed on the previous structure is shown.

[0063] Figure 16 Display as Figure 14 Schematic diagram of capacitors in series in the structure shown.

[0064] Figure 17 Display as Figure 15 Schematic diagram of capacitors in series in the structure shown.

[0065] Description of Reference Numerals

[0066] 101 drain metal layer

[0067] 102 first conductive type heavily doped substrate layer

[0068] 103 first conductivity type epitaxial layer

[0069] 104 gate trench

[0070] 105 trench oxide layer

[0071] 106 gate polysilicon layer

[0072] 107 base area

[0073] 108 Source Area

[0074] 109 contact holes

[0075] 110 source metal layer

[0076] Steps S1 to S5

[0077] 201 Gate Trench

[0078] 202 substrate layer

[0079] 203 epitaxial layer

[0080] 204 gate dielectric layer

[0081] 205 first gate polysilicon layer

[0082] 205a first polysilicon layer

[0083] 206 second gate polysilicon layer

[0084] 206a second polysilicon layer

[0085] 207 third gate polysilicon layer

[0086] 207a third polysilicon layer

[0087] 208 base area

[0088] 209 Source Area

[0089] 210 interlayer dielectric layer

[0090] 211 conductive vias

[0091] 212 front metal layer

[0092] 213 back metal layer DETAILED DESCRIPTION

[0093] See also Figure 1 , which shows a cross-sectional schematic diagram of a trench MOSFET device, including a drain metal layer 101, an N-type heavily doped substrate layer 102, a first conductive type epitaxial layer 103, a gate trench 104, a trench oxide layer 105, a first conductive type heavily doped gate polysilicon layer 106, a second conductive type base region 107, a first conductive type heavily doped source region 108, a contact hole 109 and a source metal layer 110, wherein the first conductive type is N-type or P-type, and the second conductive type is opposite to the first conductive type. Figure 1 The structure shown converts the leakage current into a completely bottom-up vertical current by embedding the trench in the epitaxial layer, eliminating the lateral conduction of leakage current in the planar vertical double diffused metal oxide semiconductor field effect transistor (VDMOS), further reducing the characteristic on-resistance (Rsp) and the device conduction loss. However, the gate of this trench MOSFET has a large overlap area with the drift region, resulting in a large gate-drain charge (Q gd ) is large, resulting in high dynamic losses, which imposes many limitations on its practical application. After extensive analysis and research, the inventors of this application have proposed an improved trench MOSFET device structure and preparation method, which can achieve the technical effect of reducing gate-drain capacitance and gate-drain charge, thereby reducing dynamic losses and improving device electrical performance.

[0094] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0095] It should be emphasized that the term "include / comprising" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0096] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0097] For example, when describing the embodiments of the present invention, schematic diagrams illustrating device structures may be partially enlarged for ease of explanation. These schematic diagrams are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0098] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0099] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0100] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0101] The present invention provides a method for preparing a trench MOSFET device structure. Figure 2 , shown as a process flow diagram of the method, comprising the following steps:

[0102] S1: providing a substrate, forming a gate trench in the substrate, wherein the substrate includes a base layer and an epitaxial layer located on the base layer, wherein the gate trench opens from a top surface of the epitaxial layer and extends downward but does not penetrate the epitaxial layer;

[0103] S2: forming a gate dielectric layer, wherein the gate dielectric layer conformally covers the inner wall of the gate trench but does not completely fill the gate trench;

[0104] S3: forming a gate conductive structure in the gate trench, the gate conductive structure comprising a first gate polysilicon layer of a first conductivity type and a second gate polysilicon layer of a second conductivity type, the first gate polysilicon layer conformally covering a surface of the gate dielectric layer and not completely filling the gate trench, the second gate polysilicon layer filling a space enclosed by the first gate polysilicon layer, and the second conductivity type being opposite to the first conductivity type;

[0105] S4: forming a base region of the second conductivity type in the epitaxial layer on both sides of the gate trench, and forming a source region of the first conductivity type on an upper surface layer of the base region;

[0106] S5: forming an interlayer dielectric layer on the epitaxial layer, and forming a conductive via, a front metal layer and a back metal layer, wherein the conductive via penetrates the interlayer dielectric layer and extends into the source region and the base region to be electrically connected to the source region and the base region, the front metal layer is located on the interlayer dielectric layer and is electrically connected to the conductive via, and the back metal layer is located on a side of the substrate layer away from the epitaxial layer.

[0107] The above steps will be described in detail below with reference to the structural diagram.

[0108] First see Figure 3 , perform step S1: provide a substrate, and use semiconductor processes such as photolithography and etching to form a gate trench 201 in the substrate, wherein the substrate includes a substrate layer 202 and an epitaxial layer 203 located on the substrate layer 202, and the gate trench 201 opens from the top surface of the epitaxial layer 203 and extends downward, but does not penetrate the epitaxial layer 203.

[0109] As an example, the substrate layer 202 may be a silicon substrate, a silicon carbide substrate, or other suitable semiconductor substrate. The substrate layer 202 may be doped with the second conductivity type or the first conductivity type. The specific doping type and doping concentration may be selected based on the desired electrical parameters and are not specifically limited herein.

[0110] As an example, the epitaxial layer 203 is formed on the surface of the substrate layer 202 by epitaxial growth, and its lattice structure is the same as that of the substrate layer 202, but the resistivity and thickness may be different. The epitaxial layer 203 can use the same material as the substrate layer 202 (homoepitaxial growth) or a different material from the substrate layer 202 (heteroepitaxial growth).

[0111] Specifically, the gate trench 201 may be formed by at least one of dry etching and wet etching. The specific depth of the gate trench 201 may be set according to the required electrical parameters, which is not specifically limited in the present invention.

[0112] See also Figure 4 , performing the step S2: forming a gate dielectric layer 204 , wherein the gate dielectric layer 204 conformally covers the inner wall of the gate trench 201 but does not completely fill the gate trench 201 .

[0113] As an example, the gate dielectric layer 204 is a silicon oxide layer, which can be formed by thermal oxidation or other suitable processes.

[0114] As an example, before the gate dielectric layer 204 is formed, the surface of the epitaxial layer 203 outside the gate trench 201 may already have a silicon oxide protective layer or other film layer. If the gate dielectric layer 204 is formed by thermal oxidation, the surface of the epitaxial layer 203 outside the gate trench 201 may also be oxidized, or the silicon oxide protective layer on the surface of the epitaxial layer 203 outside the gate trench 201 may be thickened.

[0115] See also Figures 5 to 11 , perform the step S3: forming a gate conductive structure in the gate trench 201, the gate conductive structure including a first gate polysilicon layer 205 of a first conductive type and a second gate polysilicon layer 206 of a second conductive type, the first gate polysilicon layer 205 conformally covering the surface of the gate dielectric layer 204 and not filling the gate trench 201, the second gate polysilicon layer 206 filling the space enclosed by the first gate polysilicon layer 205, and the second conductive type is opposite to the first conductive type.

[0116] In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

[0117] Specifically, the purpose of this step is to form a gate conductive structure having multiple gate polysilicon layers, wherein the doping types of two adjacent gate polysilicon layers are different, thereby forming at least one PN junction inside the gate conductive structure, so that the gate conductive structure has at least one gate junction capacitance C GJ , and the trench MOSFET device structure itself has an inherent capacitance, that is, the intrinsic gate-drain capacitance C between the gate and the drain GD0 , gate junction capacitance C GJ and the intrinsic gate-drain capacitance C GD0 series, making the total gate-drain capacitance of the device C gd becomes smaller, the gate-drain charge Q gd Reducing the device's dynamic loss will not increase the device's characteristic on-resistance R sp That is, the gate conductive structure with multiple gate polysilicon layers optimizes the gate-drain charge Q gd and characteristic on-resistance Rsp The trade-off relationship between them helps to improve the electrical performance of the device.

[0118] Specifically, in some embodiments, this step forms a gate conductive structure having a double-layer gate polysilicon layer. In this embodiment, the second gate polysilicon layer 206 completely fills the space enclosed by the first gate polysilicon layer 205, so that the gate conductive structure includes two inner and outer gate polysilicon layers. In other embodiments, this step may also form a gate conductive structure having three gate polysilicon layers. In this embodiment, the second gate polysilicon layer 206 does not completely fill the space enclosed by the first gate polysilicon layer 205. The gate conductive structure further includes a third gate polysilicon layer 207 of the first conductivity type. The third gate polysilicon layer 207 fills the space enclosed by the second gate polysilicon layer 206, so that the gate conductive structure includes three inner, middle and outer gate polysilicon layers.

[0119] The following will be combined Figures 5 to 7 A process for forming a gate conductive structure having a double-layer gate polysilicon layer is described in detail, including the following steps:

[0120] (1) Figure 5 As shown, a first polysilicon layer 205 a with a preset thickness is deposited, and the first polysilicon layer 205 a fills the gate trench 201 and extends to the surface outside the gate trench 201 .

[0121] (2) Ion implantation is performed to introduce first conductive type impurities, such as N-type impurities, into the first polysilicon layer 205a.

[0122] (3) Figure 6 As shown, a second polysilicon layer 206 a with a preset thickness is deposited. The second polysilicon layer 206 a fills the gate trench 201 and extends to the surface of the first polysilicon layer 205 a outside the gate trench 201 .

[0123] (4) Ion implantation is performed to introduce second conductivity type impurities, such as P-type impurities, into the second polysilicon layer 206a.

[0124] (5) Figure 7 As shown, chemical mechanical polishing is performed to remove the first polysilicon layer 205a and the second polysilicon layer 206a outside the gate trench 201. The portion of the first polysilicon layer 205a located in the gate trench 201 constitutes the first gate polysilicon layer 205, and the portion of the second polysilicon layer 206a located in the gate trench 201 constitutes the second gate polysilicon layer 206.

[0125] In some embodiments, after chemical mechanical polishing is performed to remove the first polysilicon layer 205 a and the second polysilicon layer 206 a outside the gate trench 201 , the polysilicon layer in the gate trench 201 may be etched back to a desired depth as needed.

[0126] Specifically, the specific thickness of the first gate polysilicon layer 205, the specific thickness of the second gate polysilicon layer 206, the specific doping concentration of the first gate polysilicon layer 205 and the specific doping concentration of the second gate polysilicon layer 206 can be set according to the required device performance parameters.

[0127] As an example, in the direction from the epitaxial layer 203 to the substrate layer 201 , the thickness of the second gate polysilicon layer 206 is T1 , and the thickness of the first gate polysilicon layer 205 is T2 , wherein the range of T1 / T2 is 1 / 3 to 3 / 1.

[0128] As an example, the doping concentration range of the first gate polysilicon layer 205 is 1e13 cm -3 ~1e17 cm -3 The doping concentration of the second gate polysilicon layer 206 is in the range of 1e13 cm -3 ~1e17 cm -3 .

[0129] The following will be combined Figures 8 to 11 A process for forming a gate conductive structure having three gate polysilicon layers is described in detail. The process is similar to the process for forming a gate conductive structure having two gate polysilicon layers. The main difference is that in the process for forming the gate conductive structure having three gate polysilicon layers, the gate polysilicon deposition and ion implantation are performed three times, while in the process for forming the gate conductive structure having two gate polysilicon layers, the gate polysilicon deposition and ion implantation are performed only twice. Specifically, the process for forming the gate conductive structure having three gate polysilicon layers includes the following steps:

[0130] (1) Figure 8 As shown, a first polysilicon layer 205 b of a preset thickness is deposited, and the first polysilicon layer 205 b fills the gate trench 201 and extends to the surface outside the gate trench 201 .

[0131] (2) Ion implantation is performed to introduce first conductive type impurities, such as N-type impurities, into the first polysilicon layer 205 b.

[0132] (3) Figure 9As shown, a second polysilicon layer 206 b of a preset thickness is deposited, and the second polysilicon layer 206 b fills the gate trench 201 and extends to the surface of the first polysilicon layer 205 b outside the gate trench 201 .

[0133] (4) Ion implantation is performed to introduce second conductivity type impurities, such as P-type impurities, into the second polysilicon layer 206 b.

[0134] (5) Figure 10 As shown, a third polysilicon layer 207 b with a preset thickness is deposited. The third polysilicon layer 207 b fills the gate trench 201 and extends to the surface of the second polysilicon layer 206 b outside the gate trench 201 .

[0135] (6) Ion implantation is performed to introduce first conductivity type impurities, such as N-type impurities, into the third polysilicon layer 207 b.

[0136] (7) Figure 11 As shown, chemical mechanical polishing is performed to remove the first polysilicon layer 205b, the second polysilicon layer 206b and the third polysilicon layer 207b outside the gate trench 201. The portion of the first polysilicon layer 205b located in the gate trench 201 constitutes the first gate polysilicon layer 205, the portion of the second polysilicon layer 206b located in the gate trench 201 constitutes the second gate polysilicon layer 206, and the portion of the third polysilicon layer 207b located in the gate trench 201 constitutes the third gate polysilicon layer 207.

[0137] In some embodiments, after chemical mechanical polishing is performed to remove the first polysilicon layer 205a, the second polysilicon layer 206a and the third polysilicon layer 207b outside the gate trench 201, the polysilicon layer in the gate trench 201 may be etched back to a desired depth as needed.

[0138] Specifically, the specific thickness of the first gate polysilicon layer 205, the specific thickness of the second gate polysilicon layer 206, the specific thickness of the third gate polysilicon layer 207, the specific doping concentration of the first gate polysilicon layer 205, the specific doping concentration of the second gate polysilicon layer 206 and the specific doping concentration of the third gate polysilicon layer 207 can be set according to the required device performance parameters.

[0139] As an example, in the direction of the epitaxial layer 203 pointing to the substrate layer 201, the thickness of the third gate polysilicon layer 207 is T3, the thickness of the second gate polysilicon layer 206 is T4, and the thickness of the first gate polysilicon layer 205 is T5, wherein the range of T3 / T4 is 1 / 3 to 3 / 1, and the range of T4 / T5 is 1 / 3 to 3 / 1.

[0140] As an example, the doping concentration range of the first gate polysilicon layer 205 is 1e13 cm -3 ~1e17 cm -3 The doping concentration of the second gate polysilicon layer 206 is in the range of 1e13 cm -3 ~1e17 cm -3 The doping concentration of the third gate polysilicon layer 207 is in the range of 1e13 cm -3 ~1e17 cm -3 .

[0141] See also Figure 12 and Figure 13 , performing step S4: forming a second conductive type base region 208, such as a P-type base region (P-body) in the epitaxial layer 203 on both sides of the gate trench 201, and forming a first conductive type source region 209 on the upper surface of the base region, wherein, Figure 12 Shown as Figure 7 The schematic diagram of the structure obtained after the source region 209 is formed in the preamble structure shown, Figure 13 Shown as Figure 11 FIG. 1 is a schematic diagram of a structure obtained after the source region 209 is formed in the preamble structure.

[0142] As an example, a method of forming the base region 208 and the source region 209 includes ion implantation and annealing.

[0143] See also Figure 14 and Figure 15 , performing step S5: forming an interlayer dielectric layer 210 on the epitaxial layer 203 by chemical vapor deposition, physical vapor deposition or other suitable methods, and forming a conductive via 211, a front metal layer 212 and a back metal layer 213, wherein the conductive via 211 penetrates the interlayer dielectric layer 210 and extends into the source region 209 and the base region 208 to be electrically connected to the source region 209 and the base region 208, the front metal layer 212 is located on the interlayer dielectric layer 210 and is electrically connected to the conductive via 211, and the back metal layer 213 is located on a side of the substrate layer 202 away from the epitaxial layer 203, wherein, Figure 14 Displayed based on Figure 12The schematic diagram of the structure obtained after the back metal layer 213 is formed in the pre-sequence structure shown, Figure 15 Displayed based on Figure 13 The schematic diagram of the structure obtained after the back metal layer 213 is formed in the previous structure is shown.

[0144] As an example, after the front metal layer 212 is formed on the interlayer dielectric layer 210 , the process further includes depositing a passivation layer and etching the passivation layer with a mask to form a metal lead region.

[0145] As an example, before forming the back metal layer 213 , a step of thinning the substrate layer 202 to a preset thickness from the back side of the substrate layer 202 is further included.

[0146] Thus, a trench MOSFET device structure with multiple gate polysilicon layers is prepared.

[0147] For details, please refer to Figure 16 , displayed as Figure 14 Schematic diagram of capacitor series connection of the structure shown, wherein, for a trench MOSFET device structure having a double-layer gate polysilicon layer, the inner gate polysilicon layer (the second gate polysilicon layer 206) of the gate conductive structure is doped with impurities of the second conductive type to form a heavily doped gate polysilicon of the second conductive type, and the outer gate polysilicon layer (the first gate polysilicon layer 205) is doped with impurities of the first conductive type to form a heavily doped gate polysilicon of the first conductive type, and the two form a PN junction in the gate conductive structure portion, so that the gate conductive structure has a gate junction capacitance C GJ , and C GD0 is the intrinsic gate-drain capacitance between the gate and the drain, which is the inherent capacitance of the device, C GJ and C GD0 The series connection, like the parallel connection of resistors, reduces the total gate-drain capacitance C gd The size of the gate-drain charge Qgd is reduced, which reduces the dynamic loss without increasing the characteristic on-resistance R sp , thereby improving the electrical performance of the device.

[0148] It should be pointed out that in the description of this specification, "heavily doped" is a relative concept, wherein the doping concentration of the "heavily doped" film layer is higher than the concentration of the "doped" film layer of the same conductivity type. For example, the doping concentration of the second conductivity type heavily doped gate polysilicon is higher than the doping concentration of the second conductivity type doped base region. In the present invention, there is no specific restriction on the specific doping concentration of each film layer.

[0149] For details, please refer to Figure 17 , displayed as Figure 15Schematic diagram of capacitor series connection of the structure shown, wherein, for a trench MOSFET device structure with three gate polysilicon layers, the innermost gate polysilicon layer (third gate polysilicon layer 207) of the gate conductive structure is doped with first conductivity type impurities, forming a heavily doped gate polysilicon of the first conductivity type, the middle gate polysilicon layer (the second gate polysilicon layer 206) is doped with second conductivity type impurities, forming a heavily doped gate polysilicon of the second conductivity type, and the outermost gate polysilicon layer (the first gate polysilicon layer 205) is doped with first conductivity type impurities, forming a heavily doped gate polysilicon of the first conductivity type. Similar to the trench MOSFET device structure with two gate polysilicon layers, the first gate junction capacitance C is formed inside the gate of the trench MOSFET device structure with three gate polysilicon layers. GJ1 and the second gate junction capacitance C GJ2 , which together with the intrinsic gate-drain capacitance C GD0 connected in series, reducing the total gate-drain capacitance C gd The size of the gate-drain charge Q is reduced gd , reducing dynamic losses without increasing the characteristic on-resistance R sp , thereby improving the electrical performance of the device.

[0150] In the method for preparing the trench MOSFET device structure of the present invention, multiple gate polysilicon layers are formed when preparing the gate conductive structure, wherein the doping types of two adjacent gate polysilicon layers are different, thereby forming at least one PN junction within the gate conductive structure, so that the gate conductive structure has at least one gate junction capacitance. This gate junction capacitance or capacitances are connected in series with the inherent capacitance of the device (i.e., the intrinsic gate-drain capacitance), thereby reducing the total gate-drain capacitance of the device and the gate-drain charge, thereby facilitating the reduction of the dynamic loss of the device without increasing the characteristic on-resistance of the device. In other words, the trench MOSFET device structure of the present invention and its preparation method optimize the trade-off relationship between gate-drain charge and characteristic on-resistance, thereby helping to improve the electrical performance of the device.

[0151] The present invention further provides a trench MOSFET device structure, which can be prepared using the method for preparing the trench MOSFET device structure in the above embodiment, or can be prepared using other suitable methods.

[0152] For details, please refer to Figure 14, which is a schematic structural diagram of the trench MOSFET device structure in an embodiment, includes a substrate, a gate trench 201, a gate dielectric layer 204, a gate conductive structure, a base region 208 of the second conductivity type, a source region 209 of the first conductivity type, an interlayer dielectric layer 210, a conductive via 211, a front metal layer 212, and a back metal layer 213, wherein the substrate includes a substrate layer 202 and an epitaxial layer 203 located on the substrate layer 202, the gate trench 201 opens from the top surface of the epitaxial layer 203 and extends downward, but does not penetrate the epitaxial layer 203, the gate dielectric layer 204 conformally covers the inner wall of the gate trench 201 and does not fill the gate trench 201, the gate conductive structure is located in the gate trench 201 and includes a first gate polysilicon layer 205 of the first conductivity type and a second gate polysilicon layer 206 of the second conductivity type, the second conductivity type being opposite to the first conductivity type, for example, the second The first conductivity type is N-type, the second conductivity type is P-type, the first gate polysilicon layer 205 conformally covers the surface of the gate dielectric layer 204 and does not fill the gate trench 201, the second gate polysilicon layer 206 fills the space enclosed by the first gate polysilicon layer 205, the base region 208 of the second conductivity type is located in the epitaxial layer 203 on both sides of the gate trench 201, the source region 209 of the first conductivity type is located on the upper surface of the base region 208, the interlayer dielectric layer 210 is located on the epitaxial layer 203, the conductive via 211 penetrates the interlayer dielectric layer 210 and extends into the source region 209 and the base region 208 to be electrically connected to the source region 209 and the base region 208, the front metal layer 212 is located on the interlayer dielectric layer 210 and is electrically connected to the conductive via 211, and the back metal layer 213 is located on the side of the substrate layer 202 facing away from the epitaxial layer 203.

[0153] Specifically, in Figure 14 In the illustrated embodiment, the second gate polysilicon layer 206 completely fills the space enclosed by the first gate polysilicon layer 205 , so that the gate conductive structure includes two inner and outer gate polysilicon layers.

[0154] Specifically, in some other embodiments, the second gate polysilicon layer 206 may not fill the space enclosed by the first gate polysilicon layer 205. In this case, the gate conductive structure further includes a third gate polysilicon layer 207 of the first conductivity type, and the third gate polysilicon layer 207 fills the space enclosed by the second gate polysilicon layer 206, so that the gate conductive structure includes three gate polysilicon layers: inner, middle and outer. For example, see Figure 15 , showing a schematic diagram of a trench MOSFET device structure in which a gate conductive structure includes three gate polysilicon layers, inner, middle and outer.

[0155] The trench MOSFET device structure of the present invention introduces one or more gate junction capacitors C into the gate conductive structure. GJ , which is related to the intrinsic gate-drain capacitance C of the device GD0 connected in series, reducing the total gate-drain capacitance C of the device gd , thereby reducing the gate-drain charge Q gd , reducing dynamic losses without increasing the characteristic on-resistance (R sp ) produces degradation, thereby optimizing the gate-drain charge Q gd and characteristic on-resistance R sp The trade-off relationship between them improves the electrical performance of the device.

[0156] In summary, in the trench MOSFET device structure and preparation method of the present invention, the gate conductive structure includes multiple layers of gate polysilicon layers, wherein the doping types of two adjacent gate polysilicon layers are different, thereby forming at least one PN junction inside the gate conductive structure, so that the gate conductive structure has at least one gate junction capacitance inside. This or these gate junction capacitances are connected in series with the inherent capacitance of the device (i.e., intrinsic gate-drain capacitance), so that the total gate-drain capacitance of the device becomes smaller and the gate-drain charge is reduced, thereby helping to reduce the dynamic loss of the device without increasing the characteristic on-resistance of the device. In other words, the trench MOSFET device structure and preparation method of the present invention optimize the trade-off relationship between gate-drain charge and characteristic on-resistance, which helps to improve the electrical performance of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0157] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a trench MOSFET device structure, characterized in that: The following steps are involved: Providing a substrate, forming a gate trench in the substrate, the substrate comprising a substrate layer and an epitaxial layer located on the substrate layer, the gate trench opening from the top surface of the epitaxial layer and extending downward but not penetrating the epitaxial layer; forming a gate dielectric layer, wherein the gate dielectric layer conformally covers the inner wall of the gate trench and does not completely fill the gate trench; forming a gate conductive structure in the gate trench, the gate conductive structure comprising a first gate polysilicon layer of a first conductive type and a second gate polysilicon layer of a second conductive type, the first gate polysilicon layer conformally covers the surface of the gate dielectric layer and does not completely fill the gate trench, the second gate polysilicon layer fills the space enclosed by the first gate polysilicon layer, and the second conductive type is opposite to the first conductive type; forming a base region of the second conductivity type in the epitaxial layer on both sides of the gate trench, and forming a source region of the first conductivity type on the upper surface layer of the base region; An interlayer dielectric layer is formed on the epitaxial layer, and a conductive via, a front metal layer and a back metal layer are formed. The conductive via penetrates the interlayer dielectric layer and extends into the source region and the base region to be electrically connected to the source region and the base region. The front metal layer is located on the interlayer dielectric layer and is electrically connected to the conductive via. The back metal layer is located on a side of the substrate layer away from the epitaxial layer.

2. The method for preparing a trench MOSFET device structure according to claim 1: the second gate polysilicon layer completely fills the space enclosed by the first gate polysilicon layer.

3. The method for preparing a trench MOSFET device structure according to claim 2, characterized in that: Forming a gate conductive structure in the gate trench comprises the following steps: Depositing a first polysilicon layer, wherein the first polysilicon layer fills the gate trench and extends to a surface outside the gate trench; Performing ion implantation to introduce first conductivity type impurities into the first polysilicon layer; Depositing a second polysilicon layer, wherein the second polysilicon layer fills the gate trench and extends to a surface of the first polysilicon layer outside the gate trench; performing ion implantation to introduce second conductivity type impurities into the second polysilicon layer; Chemical mechanical polishing is performed to remove the first polysilicon layer and the second polysilicon layer outside the gate trench, wherein the portion of the first polysilicon layer located in the gate trench constitutes the first gate polysilicon layer, and the portion of the second polysilicon layer located in the gate trench constitutes the second gate polysilicon layer.

4. The method for preparing a trench MOSFET device structure according to claim 2, characterized in that: In the direction from the epitaxial layer to the substrate layer, the thickness of the second gate polysilicon layer is T1, and the thickness of the first gate polysilicon layer is T2, wherein the range of T1 / T2 is 1 / 3 to 3 / 1.

5. The method for preparing a trench MOSFET device structure according to claim 2, characterized in that: The doping concentration range of the first gate polysilicon layer is 1e13 cm -3 ~1e17 cm -3 , the doping concentration range of the second gate polysilicon layer is 1e13 cm -3 ~1e17 cm -3 .

6. The method for preparing a trench MOSFET device structure according to claim 1, characterized in that: The second gate polysilicon layer does not fill up the space surrounded by the first gate polysilicon layer, and the gate conductive structure further includes a third gate polysilicon layer of the first conductive type, and the third gate polysilicon layer fills into the space surrounded by the second gate polysilicon layer.

7. The method for preparing a trench MOSFET device structure according to claim 6, characterized in that: Forming a gate conductive structure in the gate trench comprises the following steps: Depositing a first polysilicon layer, wherein the first polysilicon layer fills the gate trench and extends to a surface outside the gate trench; Performing ion implantation to introduce first conductivity type impurities into the first polysilicon layer; Depositing a second polysilicon layer, wherein the second polysilicon layer fills the gate trench and extends to a surface of the first polysilicon layer outside the gate trench; performing ion implantation to introduce second conductivity type impurities into the second polysilicon layer; Depositing a third polysilicon layer, wherein the third polysilicon layer fills the gate trench and extends to a surface of the second polysilicon layer outside the gate trench; performing ion implantation to introduce first conductivity type impurities into the third polysilicon layer; Chemical mechanical polishing is performed to remove the first polysilicon layer, the second polysilicon layer and the third polysilicon layer outside the gate trench, wherein the portion of the first polysilicon layer located in the gate trench constitutes the first gate polysilicon layer, the portion of the second polysilicon layer located in the gate trench constitutes the second gate polysilicon layer, and the portion of the third polysilicon layer located in the gate trench constitutes the third gate polysilicon layer.

8. The method for preparing a trench MOSFET device structure according to claim 6, characterized in that: In the direction from the epitaxial layer to the substrate layer, the thickness of the third gate polysilicon layer is T3, the thickness of the second gate polysilicon layer is T4, and the thickness of the first gate polysilicon layer is T5, wherein the range of T3 / T4 is 1 / 3 to 3 / 1, and the range of T4 / T5 is 1 / 3 to 3 / 1.

9. The method for preparing a trench MOSFET device structure according to claim 6, characterized in that: The doping concentration range of the first gate polysilicon layer is 1e13 cm -3 ~1e17 cm -3 , the doping concentration range of the second gate polysilicon layer is 1e13 cm -3 ~1e17 cm -3 The doping concentration range of the third gate polysilicon layer is 1e13 cm -3 ~1e17cm -3 .

10. The method for preparing a trench MOSFET device structure according to claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

11. A trench MOSFET device structure, characterized in that: include: A substrate, comprising a substrate layer and an epitaxial layer located on the substrate layer; A gate trench opens from the top surface of the epitaxial layer and extends downward but does not penetrate the epitaxial layer; a gate dielectric layer conformally covering an inner wall of the gate trench and not completely filling the gate trench; a gate conductive structure, located in the gate trench and comprising a first gate polysilicon layer of a first conductivity type and a second gate polysilicon layer of a second conductivity type, wherein the first gate polysilicon layer conformally covers the surface of the gate dielectric layer and does not completely fill the gate trench, and the second gate polysilicon layer fills the space enclosed by the first gate polysilicon layer, and the second conductivity type is opposite to the first conductivity type; A base region of a second conductivity type is located in the epitaxial layer on both sides of the gate trench; A source region of a first conductivity type, located on an upper surface layer of the base region; An interlayer dielectric layer, located on the epitaxial layer; A conductive via, penetrating the interlayer dielectric layer and extending into the source region and the base region to be electrically connected to the source region and the base region; A front metal layer, located on the interlayer dielectric layer and electrically connected to the conductive via; The back metal layer is located on a side of the substrate layer away from the epitaxial layer.

12. The trench MOSFET device structure according to claim 10, characterized in that: The second gate polysilicon layer fills up the space surrounded by the first gate polysilicon layer.

13. The trench MOSFET device structure according to claim 10, characterized in that: The second gate polysilicon layer does not fill up the space surrounded by the first gate polysilicon layer, and the gate conductive structure further includes a third gate polysilicon layer of the first conductive type, and the third gate polysilicon layer fills into the space surrounded by the second gate polysilicon layer.

14. The trench MOSFET device structure according to claim 10, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

Images