Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. A method according to one embodiment of the present disclosure includes forming a stack of channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shaped structure, forming a dummy gate stack over a channel region of the fin-shaped structure, recessing a source / drain region to form a source / drain trench, forming an epitaxial feature in the source / source trench, and forming a source / drain trench over the dummy gate stack. The method includes forming a dummy gate stack in a channel region, removing the dummy gate stack after forming the epitaxial feature, releasing the channel layer as channel members in the channel region, forming a gate structure surrounding each channel member, and performing an ion implantation to increase a dopant concentration of the dopant in the epitaxial feature after forming the gate structures.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to semiconductor devices and methods for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each smaller and more complex than the previous one. During IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. This shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit technology moves toward smaller nodes, multi-gate metal oxide semiconductor field effect transistors (multi-gate MOSFETs or multi-gate devices) are introduced to improve gate control by increasing gate-channel coupling, reducing cutoff current, and reducing short channel effects (SCE). A multi-gate device generally refers to a device having a gate structure or portion thereof disposed on multiple sides of a channel region. Fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. FinFETs have a protruding channel wrapped by a gate on multiple sides (e.g., a gate wraps around the top and sidewalls of a semiconductor material "fin" extending from a substrate). A GAA transistor has a gate structure that can extend around the channel region to provide access to the channel region on all four sides.

[0004] To improve the performance of GAA transistors, much effort has been devoted to developing epitaxial features that strain the channel and reduce resistance. While conventional epitaxial features are generally adequate for their intended purposes, they are not satisfactory in all respects. Summary of the invention

[0005] One embodiment of the present disclosure provides a method for forming a semiconductor device, comprising: forming a stack above a substrate, the stack comprising a plurality of channel layers interlaced with a plurality of sacrificial layers; patterning the stack to form a fin-shaped structure, the fin-shaped structure comprising a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing a gate spacer on the sidewall of the dummy gate stack; recessing the source / drain region to form a source / drain trench exposing the sidewalls of the channel layer and the sacrificial layer; recessing a portion of the sacrificial layer to form a plurality of internal spacer grooves; forming a plurality of internal spacers in the internal spacer grooves; forming an epitaxial component in the source / drain trench; after forming the epitaxial component, removing the dummy gate stack; releasing the channel layer in the channel region to serve as a plurality of channel components; forming a gate structure surrounding each channel component of the channel component; and after forming the gate structure, performing ion implantation to increase the dopant concentration of the dopant in the epitaxial component.

[0006] Another embodiment of the present disclosure provides a method for forming a semiconductor device, comprising: forming a plurality of channel components disposed above a fin-shaped substrate; forming a plurality of internal spacers, the plurality of internal spacers being staggered with the channel components; forming epitaxial components adjacent to the channel components; forming a gate structure surrounding each channel component of the channel components; and after forming the gate structure, increasing the dopant concentration in the epitaxial components.

[0007] Yet another embodiment of the present disclosure provides a semiconductor device, comprising: a plurality of channel components disposed above a substrate; a plurality of internal spacers interlaced with the channel components; a gate structure surrounding each of the channel components; a gate spacer layer disposed on a sidewall of the gate structure; and a source / drain component adjacent to the channel component, wherein the source / source component has a dopant concentration profile having a peak located above a top surface of a second channel component from the top of the channel component. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 A flow chart of a method for forming a semiconductor device according to one or more aspects of the present disclosure is shown.

[0010] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 , Fig.29 and Fig.30 According to one or more aspects of the present disclosure, Figure 1 A partial cross-sectional view of a workpiece during the manufacturing process of the method.

[0011] Fig.31 Phosphorus concentration profiles within different depth ranges in source / drain features according to one or more aspects of the present disclosure are shown. DETAILED DESCRIPTION

[0012] The present invention provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] In addition, when a number or series of numbers is described using "approximately," "approximately," etc., the term is intended to include numbers within a reasonable range, taking into account variations inherent in the manufacturing process as understood by a person of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing components with the number associated with it, the number or range includes a reasonable range including the described number, such as within + / -10% of the described number. For example, a material layer with a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is known to a person of ordinary skill in the art to be + / -15%. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0015] The present disclosure relates generally to multi-gate transistors and methods of fabrication, and more particularly to dopant implantation in source / drain features of GAA transistors.

[0016] The channel region of a GAA transistor can be arranged in a nanowire channel member, a strip channel member, a nanosheet channel member, a nanostructure channel member, a column-shaped channel member or a pillar channel member and / or other suitable channel configurations. Depending on the shape of the channel member, a GAA transistor may also be referred to as a nanowire transistor or a nanosheet transistor. Despite the different shapes, each channel member of a GAA transistor extends between and is coupled to two epitaxial components in two opposing source / drain regions. Epitaxial components are also referred to as source / drain components or source / drain epitaxial components. The source / drain region may refer to the source or drain individually or collectively, depending on the context.

[0017] The source / drain components of a GAA transistor are typically implanted with dopants to provide low resistance. For example, the source / drain components of an n-type field effect transistor (FET) are doped with n-type dopants such as phosphorus (P) or arsenic (As), and the source / drain components of a p-type FET are doped with p-type dopants such as boron (B) or gallium (Ga). Generally, the higher the dopant concentration in the source / drain component, the lower the resistance. However, the amount of dopant to be implanted into the source / drain component must be balanced with other design considerations. For example, in the gate replacement process during the formation of a GAA transistor, phosphorus (P), which is a dopant with high solubility, may diffuse into the area between the channel component and the internal spacer component and cause metal gate extrusion through the area. When metal gate extrusion occurs, device performance deteriorates and yield decreases.

[0018] The present disclosure provides an embodiment of a semiconductor device, wherein an additional dopant implant is performed after a gate replacement process to introduce a high concentration of phosphorus into a source / drain feature, thereby reducing the resistance of the source / drain region. Since a metal gate has been formed after the gate replacement process, the increase in phosphorus concentration in the source / drain feature does not cause metal gate squeezing.

[0019] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 1 is a flow chart illustrating a method 100 of forming a semiconductor device from a workpiece according to an embodiment of the present disclosure. The method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, deleted, or reassigned for other embodiments of the method. For simplicity, not all steps are described in detail. Figures 2 to 30 Describing method 100, these figures are based on Figure 1 1 is a partial cross-sectional view of a workpiece 200 at different manufacturing stages of an embodiment of the method 100. Because the workpiece 200 will be manufactured into a semiconductor device, the workpiece 200 may be referred to as a semiconductor device 200 in this document as the context requires. To avoid, Figures 2 to 30 The X, Y and Z directions are perpendicular to each other. In the present disclosure, unless otherwise specified, the same reference numerals denote the same components.

[0020] refer to Figure 1 and Figure 2 , the method 100 includes a block 102, in which a stack 204 of alternating semiconductor layers is formed above a workpiece 200. Figure 2As shown, workpiece 200 includes substrate 202. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. According to design requirements known in the art, substrate 202 may include various doping configurations. In embodiments where the semiconductor device is p-type, an n-type doping profile (i.e., an n-type well or n-well) may be formed on substrate 202. In some embodiments, an n-type dopant for forming an n-type well may include phosphorus (P) or arsenide (As). In embodiments where the semiconductor device is n-type, a p-type doping profile (i.e., a p-type well or p-well) may be formed on substrate 202. In some embodiments, a p-type dopant for forming a p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of dopants. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Additionally, the substrate 202 may optionally include an epitaxial layer (epi layer), may be strained to improve performance, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement features.

[0021] In some embodiments, the stack 204 includes a sacrificial layer 206 of a first semiconductor composition interleaved with a channel layer 208 of a second semiconductor composition. The first and second semiconductor compositions may be different. In some embodiments, the sacrificial layer 206 includes silicon germanium (SiGe) and the channel layer 208 includes silicon (Si). It should be noted that Figure 2 As shown, three (3) layers of sacrificial layers 206 and three (3) layers of channel layers 208 are arranged alternately, which is for illustration purposes only and is not intended to limit the specific references in the claims. It is understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the number of channel components required for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 1 and 20.

[0022] In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness between about 3 nm and about 10 nm, and all channel layers 208 may have a substantially uniform second thickness between about 3 nm and about 15 nm. The first thickness and the second thickness may be the same or different. As described in more detail below, the channel layer 208 or a portion thereof may be used as a channel member for a subsequently formed multi-gate device, and the thickness of each channel layer may be selected based on device performance considerations. The sacrificial layer 206 in the channel region may eventually be removed and used to define the vertical distance between adjacent channel regions for a subsequently formed multi-gate device, and the thickness of each sacrificial layer 206 may be selected based on device performance considerations.

[0023] The layers in stack 204 may be deposited using a molecular beam epitaxy (MBE) process, a vapor phase deposition (VPE) process, and / or other suitable epitaxial growth processes. Therefore, stack 204 is also referred to as epitaxial stack 204. As described above, in at least some instances, sacrificial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer, and channel layer 208 includes an epitaxially grown silicon (Si) layer. In some embodiments, sacrificial layer 206 and channel layer 208 are substantially free of dopants, for example, no intentional doping is performed during the epitaxial growth of stack 204. In some embodiments, the top surface of substrate 202 is located in a (100) crystal plane, so each layer of stack 204 has a (100) top surface. In some alternative embodiments, the top surface of the substrate is located in a (110) crystal plane, so each layer of stack 204 has a (110) top surface.

[0024] refer to Figure 1 , Figure 2 and Figure 3 The method 100 includes a block 104 in which a fin structure 212 is formed by patterning the stack 204 and the substrate 202. To pattern the stack 204, a hard mask layer 210 (eg, Figure 2 ) to form an etching mask. The hard mask layer 210 may be a single layer or a multilayer. For example, the hard mask layer 210 may include a pad oxide layer and a pad nitride layer above the pad oxide layer. The fin structure 212 may be patterned from the stack 204 and the substrate 202 using a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., centrifugal dehydration and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. As Figure 3As shown, the etching process at box 104 forms a groove extending through the stack 204 and a portion of the substrate 202. The groove defines a fin structure 212. In some embodiments, a double patterning or multiple patterning process can be used to define a fin structure, for example, a fin structure having a pitch that is smaller than that obtainable using a single, direct lithography process. For example, in one embodiment, a material layer is formed above the substrate and the material layer is patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 212 by etching the top of the stack 204 and the substrate 202. The patterned top of the substrate 202 is also represented as a fin base 212B. The horizontal plane including the interface between the stack 204 and the fin base 212B is represented as plane 202T, which marks the position of the bottom surface of the stack 204 and / or the top surface of the fin base 2120. Depending on the context, fin base 212B may still be considered as the top of substrate 202. Therefore, plane 202T may also be considered as marking the location of the top surface of substrate 202. Figure 3 As shown, the fin-shaped structure 212 including the patterned stack 204 and the fin-shaped base 212B extends vertically along the Z direction and longitudinally along the X direction. In some cases, the width of the fin-shaped structure 212 measured along the Y direction is between about 6 nm and about 80 nm, and the distance between the opposite sidewalls of two adjacent fin-shaped structures 212 measured along the Y direction is between about 6 nm and about 115 nm.

[0025] The isolation component 214 is formed adjacent to the fin structure 212. In some embodiments, the isolation component 214 can be formed in a trench to isolate the fin structure 212 from an adjacent active area. The isolation component 214 may also be referred to as a shallow trench isolation (STI) component 214. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a negative pressure CVD (SACVD) process, a flowable CVD process, a spin coating process, and / or other suitable processes. Then, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled-back by a dry etching process, a wet etching process, and / or a combination thereof to form the STI component 214. After being recessed, the fin structure 212 rises above the STI feature 214. The recessed top surface of the STI feature 214 may be flush with the plane 202T or below the plane 202T.

[0026] refer to Figure 1 , Figure 4 and Figure 5 The method 100 includes block 106 in which a dummy gate stack 220 is formed on the channel region 212C of the fin structure 212 . Figure 5 is along Figure 4 In some embodiments, a gate replacement process (or a gate-last process) is used, wherein the dummy gate stack 220 (such as Figure 4 and Figure 5 ) is used as a placeholder to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are also possible. Figure 5 In some embodiments shown, the dummy gate stack 220 is formed above the fin structure 212, and the fin structure 112 can be divided into a channel region 212C below the dummy gate stack 220 and a source / drain region 212SD not below the dummy gate stack 210. The channel region 212C is adjacent to the source / drain region 212SD. Figure 5 As shown, the channel region 2120C is disposed between two source / drain regions 212SD along the X direction.

[0027] The formation of the dummy gate stack 220 may include depositing and patterning the layers in the dummy gate stack. Figure 4 , a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 can be blanket deposited over the workpiece 200. In some embodiments, the dummy dielectric layer 216 can be formed over the fin structure 212 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, or other suitable process. In some cases, the dummy dielectric layer 216 can include silicon oxide. Thereafter, a dummy electrode layer 218 can be deposited on the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable process. In some cases, the dummy electrode layer 218 can include polysilicon. For patterning purposes, a gate top hard mask layer 222 can be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable process. The gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220, such as Figure 5As shown. For example, the patterning process may include a photolithography process (e.g., photolithography or electron beam lithography), which may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., centrifugal dehydration drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 above the silicon oxide layer 223. As shown Figure 5 As shown, no dummy gate stack 220 is disposed over the source / drain region 212SD of the fin structure 212 .

[0028] refer to Figure 1 and Figure 6 , the method 100 includes a frame 108, wherein a gate spacer layer 226 is deposited on the dummy gate stack 220. In some embodiments, the gate spacer layer 226 is conformally deposited over the workpiece 200, including over the top surface and sidewalls of the dummy gate stack 220. For the convenience of describing a layer having a substantially uniform thickness over various regions, the term "conformal" may be used herein. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may include silicon carbonitride, silicon oxycarbide, silicon carbonitride oxide, or silicon nitride. The gate spacer layer 226 may be deposited over the dummy gate stack 220 using a process such as a CVD process, a negative pressure CVD (SACVD) process, an ALD process, or other suitable process. In one embodiment, the gate spacer layer 226 includes a first layer and a second layer disposed over the first layer. The first layer may include silicon oxynitride, and the second layer may include silicon nitride. In some cases, the thickness of the gate spacer layer 226 measured along the X direction is between about 3 nm and about 8 nm.

[0029] refer to Figure 1 and Figure 7 The method 100 includes a block 110 in which the source / drain region 212SD of the fin structure 212 is recessed to form a source / drain trench 228. In some embodiments, the source / drain region 212SD not covered by the dummy gate stack 220 and the gate spacer 226 is etched by dry etching or a suitable etching process to form the source / source trench 228. For example, the dry etching process may be performed using an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 and / or C 2 F 6 ), chlorine-containing gases (such as Cl 2 , CHCl3 , CCl 4 and / or BCl 3 ), bromine-containing gases (e.g., HBr and / or CHBR3), iodine-containing gases, other suitable gases and / or plasmas and / or combinations thereof. Figure 7 In some embodiments shown, source / drain regions 212SD of fin structure 212 are recessed to expose sidewalls of sacrificial layer 206 and channel layer 208. In some implementations, source / drain trenches 228 extend below stack 204 into substrate 202 (below plane 202T). Figure 7 FIG. 2 shows a cross-sectional view of the workpiece 200 at the source / drain region 212SD observed along the Y direction. Figure 7 As shown, at block 110 , the sacrificial layer 206 and the channel layer 208 in the source / drain region 212SD are removed to expose the substrate 202 .

[0030] refer to Figure 1 , Figure 8 , Fig. 9 and Fig.10 , the method 100 includes block 112, where an internal spacer feature 234 is formed. Although not explicitly shown, the operations at block 112 may include selectively and partially removing the sacrificial layer 206 to form an internal spacer recess 230, depositing an internal spacer material 232 over the workpiece 200, and etching back the internal spacer material 232 to form the internal spacer feature 234 in the internal spacer recess 230. Figure 8 200 ). The sacrificial layer 206 exposed in the substrate 202 (as shown) is selectively and partially recessed to form an inner spacer recess 230, while the gate spacer layer 226, the exposed portion of the substrate 202, and the channel layer 208 are substantially unetched. In embodiments where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon germanium (SiGe), the selective recessing of the sacrificial layer 206 may be performed using a selective wet etching process or a selective dry etching process. The selective and partial recessing of the sacrificial layer 206 may include a SiGe oxidation process followed by removal of the SiGe oxide. In this embodiment, the SiGe oxidation process may include the use of ozone. In some other embodiments, the selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include APM etching (e.g., an ammonia-hydrogen peroxide-water mixture).

[0031] After forming the inner spacer recess 230, an inner spacer material 232 is deposited over the workpiece 200, including over the inner spacer recess 230, such as Fig. 9As shown. The internal spacer material 232 may include a metal oxide, silicon oxide, silicon oxynitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. The metal oxide may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides. Although not explicitly shown, the internal spacer material 232 may be a single layer or multiple layers. In some embodiments, the internal spacer material 232 may be deposited using CVD, PECVD, SACVD, ALD, or other suitable methods. The internal spacer material 232 is deposited into the internal spacer recess 230 and over the sidewalls of the channel layer 208 exposed in the source / drain trench 228. Refer to Fig.10 , the deposited inner spacer material 232 is then etched back to remove the inner spacer material 232 from the sidewalls of the channel layer 208, thereby forming an inner spacer feature 234 in the inner spacer recess 230. At block 112, the inner spacer material 232 may also be removed from the top surface and / or sidewalls of the gate top hard mask layer 222 and the gate spacer layer 226. In some embodiments, the etch back operation performed at block 112 may include using hydrogen fluoride (HF), fluorine gas (F 2 ), hydrogen (H 2 ), ammonia (NH 3 ), nitrogen trifluoride (NF 3 ) or other fluorine-based etchants. Fig.10 As shown, each internal spacer component 234 is in direct contact with the recessed sacrificial layer 206 and is disposed between two adjacent channel layers 208. In some cases, the thickness of each internal spacer component 234 measured along the X direction is between about 3 nm and about 5 nm. In the depicted embodiment, each internal spacer component 234 has a concave sidewall surface facing the corresponding source / drain trench 228 (i.e., curving inwardly toward the corresponding sacrificial layer 206). Alternatively, the sidewall surface can be flat (e.g., substantially vertical) or convex (i.e., curving outwardly toward the corresponding source / drain trench 228). As shown in FIG. Fig.10 As shown, although the selective etching process and etch-back process at box 112 are selective to the sacrificial layer 206 and the internal spacer material 232, the channel layer 208 is moderately etched and has rounded ends. In the depicted embodiment, the source / drain trench 228 extends to a depth D1 (measured from the plane 202T) in the substrate 202, and the depth D1 is between about 3nm and about 115nm. The width of the source / drain trench 228 (e.g., measured between opposite sidewalls of the gate spacer layer 226 on adjacent dummy gate stacks 220 along the X direction) is between about 9nm and about 32nm.

[0032] refer to Figure 1 and Fig.11, method 100 includes block 114, performing a cleaning process 300. Cleaning process 300 may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may use a suitable cleaning solution, such as a solution including a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide, a solution including a mixture of deionized water, hydrochloric acid, and hydrogen peroxide, SPM (sulfuric acid peroxide mixture), and / or hydrofluoric acid for removing oxides. The dry cleaning process may include performing a helium (He) and hydrogen (H2) cleaning process at a temperature of about 250° C. to about 550° C. and a pressure of about 75 mTorr to about 155 mTorr. 2 ) treatment. Hydrogen treatment can convert silicon on the surface into silane (SiH 4 ), the silane can be pumped out and removed. In some embodiments, the cleaning process is configured to selectively remove or trim portions of the channel layer without substantially removing the inner spacer features 234. The cleaning process 300 can remove surface oxides and debris to ensure a clean semiconductor surface, which facilitates the growth of the base epitaxial layer at block 116.

[0033] refer to Figure 1 and Fig.12 , method 100 includes block 116, where a base epitaxial layer 236 is deposited at the bottom of source / drain trench 228. In some embodiments, except for doping conditions (doping elements and / or doping concentrations), base epitaxial layer 236 includes the same material as substrate 202 and channel layer 208, such as silicon (Si). For example, base epitaxial layer 236 is made of undoped silicon, substrate 202 is made of doped silicon, and channel layer 208 is made of undoped or doped silicon. In some embodiments, base epitaxial layer 236 includes the same material as sacrificial layer 206, such as silicon germanium (SiGe), where the germanium (Ge) content is the same or different from each other. In some embodiments, base epitaxial layer 236 includes Si x Ge 1-x, where x is between about 0.1 and 1. The range of germanium content is not trivial. When the germanium content is greater than about 90%, the lattice mismatch between silicon and germanium may cause excessive defects at the interface between the base epitaxial layer 236 and the substrate 202. In other embodiments, the base epitaxial layer 236, the channel layer 208, and the sacrificial layer 206 are made of different semiconductor materials from each other. In various embodiments, the base epitaxial layer 236 is free of dopants, for example, no intentional doping is performed during the epitaxial growth process. In comparison, in one example, the substrate 202 is lightly doped (e.g., n-type dopants in p-type regions for forming PFETs or p-type dopants in n-type regions for forming NFETs), and therefore has a higher doping concentration than the base epitaxial layer 236. The base epitaxial layer 236 without dopants provides a high resistance path from subsequently formed source / drain components to the substrate 202, thereby suppressing leakage current into the substrate 202.

[0034] Suitable epitaxial processes for block 116 include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), selective CVD, and / or other suitable processes. Various deposition parameters may be adjusted to selectively deposit semiconductor material on the exposed semiconductor surfaces in the source / drain trenches 228, such as deposition gas composition, carrier gas composition, deposition gas flow rate, carrier gas flow rate, deposition time, deposition pressure, deposition temperature, source power, RF bias, DC bias, RF bias power, DC bias power, other suitable deposition parameters, or combinations thereof. In some embodiments, when forming the base epitaxial layer 236, the workpiece 200 is exposed to a gas comprising DCS and / or SiH 4 (containing silicon precursor), H 2 (carrier precursor) and HCl (containing etchant precursor). In some embodiments, the selective CVD process achieves a deposition temperature of about 600°C to about 750°C. In some embodiments, the selective CVD process achieves a deposition pressure of about 10 Torr to about 100 Torr. In some embodiments, the selective CVD process is configured as a bottom-up deposition process such that the base epitaxial layer 236 grows from the exposed semiconductor surface at the bottom of the source / drain trench 228, but not from the exposed end of the channel layer 208. In some embodiments, the growth of the base epitaxial layer 236 is time controlled such that the top surface of the base epitaxial layer 235 is approximately the top surface of the fin-shaped base 212B (i.e., above the plane 202T). In some embodiments, the top surface of the base epitaxial layer 236 is between about 1 nm and about 5 nm above the plane 202T. In some alternative embodiments, the top surface of the base epitaxial layer 236 is about 2 nm to about 20 nm below the plane 202T.

[0035] refer to Figure 1 , Fig.13 and Fig.14, the method 100 includes block 118, where a dielectric film 240 is formed in the bottom of the source / drain trench 228 and over the base epitaxial layer 236. Although not explicitly shown, the operation at block 118 may include depositing a dielectric material 238 over the workpiece 200, and etching back the dielectric material 236 to form the dielectric film 240 at the bottom of the source / drain trench 228. Fig.13 As shown, dielectric material 238 is deposited over workpiece 200, including over the sidewalls and bottom surfaces of source / drain trenches 228 and over the sidewalls and top surfaces of dummy gate stack 220. In some embodiments, dielectric material 238 may include a metal oxide or a metal nitride, such as La 2 O 3 、Al 2 O 3 、ZnO、ZrN、Zr 2 Al 3 O 9 、TiO 2 、TaO 2 、ZrO 2 , HfO 2 , Y 2 O 3 , AlON, TaCN, other suitable materials or combinations thereof. In some embodiments, the dielectric material 238 may include silicon oxide, silicon carbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride or a low-k dielectric material. The dielectric material 238 is selected to have a different etch selectivity from the internal spacer component 234, thereby allowing the dielectric material 239 to be etched back without causing etching loss to the internal spacer structure 234. In some embodiments, the dielectric material 238 can be deposited using a directional deposition process (such as PECVD or other suitable methods). The directional deposition process forms a dielectric material 238 having a thicker horizontal portion (e.g., on the bottom surface of the source / drain trench 228 and the top surface of the dummy gate stack 220) and a thinner vertical portion (e.g., on the sidewalls of the dummy gate stack 200 and the fin structure 212).

[0036] refer to Fig.14 , and then etching back the deposited dielectric material 238 to remove thinner vertical portions from the sidewalls of the dummy gate stack 220 and the fin structure 212. In some embodiments, the etching back operation performed at block 118 may include using hydrogen fluoride (HF), fluorine gas (F 2 ), hydrogen (H 2 ), ammonia (NH 3 ), nitrogen trifluoride (NF 3) or other fluorine-based etchants. Due to the loading effect, the thicker horizontal portion at the top of the dummy gate stack 220 can also be removed, while the thicker horizontal portion at the bottom of the source / drain trench 228 is thinned, but still remains as a dielectric film 240 covering the base epitaxial layer 236. In some embodiments, the dielectric film 240 has a thickness of about 2 nm to about 20 nm (measured in the Z direction). In the depicted embodiment, the top surface of the dielectric film 240 is approximately plane 202T, and the dielectric film 240 is in contact with one of the bottommost internal spacers 234.

[0037] refer to Figure 1 and Fig.15 , the method 100 includes a block 120, in which a first epitaxial layer 242 is deposited. The first epitaxial layer 242 can be epitaxially and selectively formed from the exposed sidewalls of the channel layer 208, while the sidewalls of the sacrificial layer 206 are still covered by the internal spacer features 234. Suitable epitaxial processes for block 120 include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process at block 120 can use a gaseous precursor that interacts with the composition of the channel layer 208. In some embodiments, the parameters of the epitaxial growth process at block 120 are selected so that the first epitaxial layer 242 is not epitaxially deposited on the internal spacer features 234. In some embodiments, at the end of the operation at block 120, at least some of the internal spacer features 234 remain exposed. That is, at least some of the internal spacer features 234 are not completely covered by the first epitaxial layer 242.

[0038] In some cases, in a p-type region for forming a p-type transistor, the first epitaxial layer 242 includes silicon germanium (SiGe) and is doped with a p-type dopant, such as boron (B). In some embodiments, the first epitaxial layer 242 includes a germanium (Ge) content between about 10% and about 40% and a silicon (Si) content between about 90% and about 60%. The range of germanium (Ge) content is not insignificant. When the germanium content is greater than about 40%, the lattice mismatch between silicon and germanium may cause excessive defects at the interface between the first epitaxial layer 242 and the channel layer 208, which may cause increased resistance or device failure. When the germanium content is less than about 10%, the channel layer 208 may not be sufficiently strained to improve hole mobility.

[0039] In some cases, in an n-type region for forming an n-type transistor, the first epitaxial layer 242 includes silicon arsenic (SiAs) and is doped with an n-type dopant, such as phosphorus (P). In some embodiments, the first epitaxial layer 242 includes an arsenic (As) content of about 10% to about 40% atomic percent and a silicon (Si) content of about 90% to about 60% atomic percent. The range of arsenic (As) content is not insignificant. When the arsenic content is greater than about 40%, the lattice mismatch between silicon and arsenic may cause excessive defects at the interface between the first epitaxial layer 244A and the channel layer 208, which may cause increased resistance or device failure. When the arsenic content is less than about 10%, the channel layer 208 may not be sufficiently strained to improve carrier mobility.

[0040] refer to Figure 1 and Fig.16 , method 100 includes frame 122, wherein a second epitaxial layer 244 is deposited over the first epitaxial layer 242. The first epitaxial layer 242 and the second epitaxial layer 244 in the source / drain region 212SD are collectively referred to as source / drain components 246. In some embodiments, the second epitaxial layer 244 may be epitaxially and selectively formed from the first epitaxial layer 242. Suitable epitaxial processes for frame 122 include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process at frame 122 may use a gaseous precursor that interacts with the composition of the first epitaxial layer 242. The second epitaxial layer 244 is allowed to overgrow and merge over the internal spacer component 234 and substantially fill the source / drain trench 228. A top surface of the second epitaxial layer 244 may be grown over a top surface of the fin structure 212 (ie, a top surface of the topmost channel layer 208 ) and intersect a sidewall of the gate spacer 226 .

[0041] In some cases, in a p-type region for forming a p-type transistor, second epitaxial layer 244 includes silicon germanium (SiGe) doped with a p-type dopant, such as boron (B). Second epitaxial layer 244 serves as a low resistance layer and includes a greater doping concentration than in first epitaxial layer 242. In some cases, the doping concentration in second epitaxial layer 244 may be about 1.2×10 20 Atom / cm 3 and about 2×10 21 Atom / cm 3 The doping density in the first epitaxial layer 242 may be between about 1×10 18 Atom / cm 3 About 1×10 20 Atom / cm 3 The p-type dopant concentration range is not trivial. When the p-type dopant concentration in the second epitaxial layer 244 is less than about 1.2×1020 Atom / cm 3 When the dopant concentration of the p-type dopant in the second epitaxial layer 244 is greater than about 2×10 21 Atom / cm 3 When the p-type dopant in the lattice gap is formed, it is also possible that excessive defects are caused by the p-type dopant in the lattice gap, which may cause an increase in resistance. The second epitaxial layer 244 can be in-situ doped so that the p-type dopant is substantially uniformly distributed in depth. If the second epitaxial layer 244 is not in-situ doped, an ion implantation process is performed to dope the second epitaxial film 244. The doping concentration in the second epitaxial layer 244 is limited by the solubility of boron (B) in the second epitaxial film 244. Compared with the first epitaxial layer 242, the second epitaxial layer 244 includes a greater germanium content to enhance the strain on the channel layer 208. In some embodiments, the second epitaxial layer 244 includes a germanium content of about 40% to about 70% and a silicon content of about 60% to about 30%. Compared with the second epitaxial layer 244, the base epitaxial layer 236 may include a greater germanium content. In an alternative embodiment, the base epitaxial layer 236 may include a lesser germanium content than the first epitaxial layer 242.

[0042] In some cases, in an n-type region for forming an n-type transistor, the second epitaxial layer 244 includes silicon doped with an n-type dopant, such as phosphorus (P). The second epitaxial layer 244 serves as a low resistance layer and includes a greater doping concentration than in the first epitaxial layer 242. Unlike the p-type region, the doping concentration in the second epitaxial layer 244 in the n-type region is lower than the solubility of phosphorus in the second epitaxial film 244. The second epitaxial layer 244 in the n-type region may be in-situ doped so that the n-type dopant is substantially uniformly distributed over the depth. If the second epitaxial layer 244 is not in-situ doped, an ion implantation process may be performed to dope the second epitaxial film 244. In some cases, the doping concentration in the second epitaxial layer 244 may be between about 2×10 17 Atom / cm 3 and about 5×10 18 Atom / cm 3 The doping density in the first epitaxial layer 242 may be between about 1×10 15 Atom / cm 3 About 1×10 17 Atom / cm 3, which is lower than the corresponding counterpart in the p-type region. This is because the high concentration of phosphorus atoms accelerates the diffusion of phosphorus atoms into the channel region along the boundary between the channel layer 208 and the internal spacer component 234 and reaches the sacrificial layer 206. Since the phosphorus atoms reduce the etching contrast between the channel layer 208 and the sacrificial layer 206, during the gate replacement process of removing the sacrificial layer 206, the portion of the channel layer 208 where the phosphorus atoms are diffused may suffer excessive etching loss, so that a tunnel along the boundary between the channel layer 208 and the internal spacer component 234 may be formed. When a metal gate is formed during the gate replacement process, the metal material from the metal gate may extend into the tunnel, causing a short circuit between the metal gate and the source / drain component, a phenomenon known as "metal gate extrusion". Metal gate extrusion can be prevented by maintaining a relatively low phosphorus concentration in the n-type region. In one embodiment, at the end of the operation at block 122, the source / drain features 246 in the n-type region may even remain substantially undoped or at a relatively low concentration level, unlike the p-type region where the p-type dopant is at an appropriate concentration. As discussed in further detail below, after the gate replacement process, an ion implantation process will be further performed in the n-type region to increase the phosphorus concentration in the source / drain features 246.

[0043] refer to Figure 1 and Fig.17 , the method 100 includes a block 124, in which the workpiece 200 is annealed in an annealing process 400. In some embodiments, the annealing process 400 may include a rapid thermal annealing (RTA) process, a laser spike annealing process, a flash annealing process, or a furnace annealing process. The annealing process 400 may include a peak annealing temperature between about 900° C. and about 1000° C. In these embodiments, the peak annealing temperature may be maintained for a duration measured in seconds or microseconds. Through the annealing process 400, a desired electronic contribution of a p-type dopant (such as silicon germanium (SiGe) or germanium (Ge)) in the semiconductor body may be obtained. The annealing process 400 may generate vacancies that facilitate the movement of the p-type dopant from interstitial sites to substitutional lattice sites and reduce damage or defects in the semiconductor body lattice. Through the annealing process 400, the n-type dopant in the n-type region, although at a relatively low concentration level, is also more uniformly distributed, particularly extending to the bottom of the source / drain feature 246.

[0044] refer to Figure 1 and Fig.18, the method 100 includes a block 126, wherein a contact etch stop layer (CESL) 248 and a first interlayer dielectric (ILD) layer 250 are deposited on the workpiece 200. In some embodiments, the CESL 248 includes silicon nitride, silicon oxynitride, and / or other materials known in the art. The CESL 248 may be formed by an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition processes. A first ILD layer 250 is then deposited over the CESL 248. In some embodiments, the first ILD layer 250 includes a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. The first ILD layer 250 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the first ILD layer 250, the workpiece 200 may be annealed to improve the integrity of the first ILD layer 150. like Fig.18 As shown, the CESL 248 is disposed directly on the top surface of the source / drain feature 246. After the CESL 248 and the first ILD layer 250 are deposited, the workpiece 200 may be planarized by a planarization process to expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process. The exposure of the dummy gate stack 220 allows the removal of the dummy gate stack 200 and the release of the channel layer 208.

[0045] refer to Figure 1 and Fig.19 , the method 100 includes a block 128, in which the dummy gate stack 220 is removed, thereby forming a gate trench 252 above the channel region 212C. Removing the dummy gate stack 220 may include one or more etching processes that are selective to the material of the dummy gate stack 200. For example, the removal of the dummy gate stack 220 may be performed using a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 220. After removing the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 212C are exposed in the gate trench 252.

[0046] refer to Figure 1 and Fig. 20, the method 100 includes a frame 130, wherein the sacrificial layer 206 between the channel layers 208 in the channel region 212C is selectively removed. The selective removal of the sacrificial layer 206 releases the channel layer 208 to form a channel member (also referred to as 208). The selective removal of the sacrificial layer 206 also leaves a space 254 between the channel members 208. The selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching or other selective etching processes. An exemplary selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include APM etching (e.g., ammonia-hydrogen peroxide-water mixture).

[0047] refer to Figure 1 and Fig.21 , method 100 includes frame 132, wherein a gate structure 256 is formed to surround each channel member 208. In some embodiments, the gate structure 256 is formed within the gate trench 252 and is formed in the space 254 left by removing the sacrificial layer 206. In this regard, the gate structure 256 surrounds each channel member 208. The gate structure 256 includes a gate dielectric layer 258 and a gate electrode layer 260 above the gate dielectric layer 258. In some embodiments, although not explicitly shown in the figure, the gate dielectric layer 258 includes an interfacial layer and a high-K gate dielectric film. As used and described herein, a high-K dielectric material includes a dielectric material having a high dielectric constant, for example, a dielectric constant greater than that of thermally oxidized silicon (~3.9). The interfacial layer may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-K gate dielectric layer may include hafnium oxide. Alternatively, the high-K gate dielectric layer may include other high-K dielectric materials, such as titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 5 ), hafnium silicon oxide (HfSiO 4 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO), yttrium oxide (Y 2 O 3 )、SrTiO 3 (STO), BaTiO 3(BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (Hfta O), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-K gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0048] The gate electrode layer 260 of the gate structure 256 may include a single layer or a multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to improve device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy or various combinations of metal silicides. For example, the gate electrode layer 260 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer 260 may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In various embodiments, a CMP process may be performed to remove excess metal, thereby providing a substantially planar top surface of the gate structure 256. The gate structure 256 includes a portion between the channel members 208 in the channel region 212C.

[0049] Still refer to Fig.21 In the depicted embodiment, the gate structure 256 (including the gate dielectric layer 258 and the gate electrode layer 260) is recessed, thereby forming a recess directly above the gate structure 256 and between the opposite portion of the gate spacer layer 226. A gate mask 262 including one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, etc.) is filled in the recess, and a planarization process is then performed to remove excess portions of the dielectric material extending above the first ILD layer 250. A subsequently formed gate contact (not shown) penetrates the gate mask 262 to contact the top surface of the recessed gate electrode layer 260. After the gate structure 256 is recessed, the distance from the top surface of the gate structure 256 to the top surface of the topmost channel member 208 along the Z direction can be measured between about 5 nm and about 50 nm.

[0050] refer to Figure 1 and Fig. 22, the method 100 includes a block 134, wherein a second ILD layer 264 is deposited on the workpiece 200. The second ILD layer 264 can be a single layer or multiple layers. In some embodiments, the second ILD layer 264 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD layer 264 includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG) and / or other suitable dielectric materials. The second ILD layer 264 can be deposited by a PECVD process or other suitable deposition techniques.

[0051] refer to Figure 1 and Fig.23 , the method 100 includes a block 136, wherein a hard mask layer 266 is formed on the second ILD layer 264. The hard mask layer 266 may include SiO, HfSi, SiOC, AlO, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, Si, SiOCN, ZrN, SiCN, or other suitable materials. The thickness of the hard mask layer 266 may be in the range of about 5 nm to about 30 nm. A photolithography patterning and etching process is performed to pattern the hard mask layer 266. In particular, the photolithography process forms a patterned photoresist layer having an opening, and an etching process is applied to transfer the opening to the hard mask layer 266 as an opening 272. The opening 272 is larger than the size of the underlying source / drain feature 246, so that a portion of the gate structure 256 is also directly covered under the opening 272.

[0052] refer to Figure 1 and Fig.24 , the method 100 includes a block 138, in which a selective etching process is performed to extend an opening 272 through the second ILD layer 264 and the first ILD layer 250 to expose the underlying source / drain features 246. At the end of the operation at block 138, the opening 272 is also referred to as a source / drain contact hole 272. The selective etching process may include dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes. In some embodiments, the etching process includes a first selective etching and a second selective etching, the first selective etching being adjusted to be selective to the materials in the second ILD layer 264 and the first ILD layer 250, while not (or minimally) etching the CESL 248, the gate spacer layer 226, and the gate mask 262, and the second selective etching being adjusted to open the CESL 248, while not (or minimally) etching the source / drain features 246.

[0053] refer to Figure 1 and Fig.25 , the method 100 includes a frame 140, wherein a liner 274 is deposited along the sidewalls of the opening 272. The liner 274 is used to protect the gate structure 256 from the diffusion of dopants in a subsequent ion implantation process. The liner 274 can be a single layer or a multilayer. In an example process, at least one metal material is conformally deposited on the workpiece 200 and then anisotropically etched back to expose the source / drain component 246. In one example, the liner 284 is a titanium (Ti) layer. In another example process, at least one dielectric material is deposited on the workpiece 200, and then the deposited dielectric material is anisotropically etched back to expose the source / drain component 246. In some cases, the at least one dielectric material for the liner 284 may include silicon, oxygen, nitrogen, or carbon. For example, the at least one dielectric material may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbide, or silicon oxynitride. After the etch-back process, the thickness of the liner 284 in the X direction may be between about 1 nm and about 15 nm.

[0054] refer to Figure 1 and Fig.26 , the method 100 includes a block 142, wherein a phosphorus ion implantation 500 is performed in the n-type region while covering the p-type region. The phosphorus ion implantation 500 provides a relatively heavy and shallow doping on top of the source / drain feature 246. The pad 284 may also be doped with phosphorus, which may be detected by SIMS (secondary ion mass spectrometry). In some embodiments, phosphorus dimer (P2+) ions are utilized at block 142 to effectively introduce a higher chemical phosphorus concentration and increase a higher amorphous level. In comparison, during the formation of the source / drain feature 246, a conventional phosphorus ion implantation using P+ may be used at block 122. In some embodiments, the phosphorus dimer ion implantation may include cooling the workpiece 200 from room temperature to a temperature of -20°C, or to below -20°C in some other embodiments. Due to the relatively high degree of amorphism (or the lower activation energy required for activation), the phosphorus dimer ion implantation induces more activated phosphorus dopants on the surface at these low temperatures. As a result, the phosphorus dimer ion implantation performed as a low temperature implantation may result in more lateral diffusion than a room temperature implantation. This is because the lower temperature causes the implanted phosphorus atoms to move further laterally relative to the initial penetration point of the strained material top surface. Due to lateral diffusion, the phosphorus concentration at the same depth may be substantially the same even between the first epitaxial layer 242 and the second epitaxial layer 244.

[0055] In some aspects, phosphorus ion implantation 500 uses an implantation energy in the range of about 0.1 KeV to about 10 KeV to implant the dopant species. In some embodiments, the implantation dose is about 1×10 15 Atom / cm 3 About 5×10 15 Atom / cm 2In some embodiments, the phosphorus ion implantation 500 includes a first ion implantation with an implantation energy in the range of about 2 KeV to about 3 KeV and a dose in the range of about 1×10 15 Atom / cm 3 About 5×10 15 Atom / cm 3 The phosphorus atoms in the first ion implantation are mainly driven to the region between the top surface of the first top (topmost) channel member 208 and the top surface of the second top channel member 308 ( Fig.26 The phosphorus atoms in the second ion implantation are mainly driven to the region between the top surface of the second top channel member 208 and the bottom surface of the second top channel member 208 ( Fig.26 In order to fine-tune doping to meet different device performance requirements, the first ion implantation may be performed before or after the second ion implantation. Fig.31 Figure 1 shows an example of phosphorus concentration distribution at different depths. Fig.31 As shown, the peak phosphorus concentration in the region between the AC regions, especially in the region between the AB region a few nm above the B line, may be greater than about 1×10 22 Atom / cm 3 In contrast, the phosphorus concentration in the area below line C is much smaller than the peak. In some embodiments, the graph may have two peaks (denoted by Fig.31 ), the first peak in the AB region corresponds to the first ion implantation, and the second peak in the BC region corresponds to the second ion implantation. The first peak may be higher than the second peak.

[0056] refer to Figure 1 , Fig. 27 and Fig.28 , the method 100 includes a block 144, in which a silicide layer 278 is formed on the source / drain region 212SD. When forming the silicide layer 278, the metal layer 276 can first be conformally deposited on the exposed surface of the workpiece 200, including the exposed portion of the gate mask 262, the liner 274 and the top surface of the source / drain feature 246, such as Fig. 27 As shown. In some embodiments, the metal layer 276 is a titanium nitride (TiN) layer. The thickness of the metal layer 276 in the X direction may be between about 1 nm and about 5 nm. After depositing the metal layer 276, a silicide layer 278 may be formed by reacting the upper portion of the source / drain feature 246 with the metal layer 276, as shown. Fig.28As shown. In some embodiments, the workpiece 200 is subjected to an annealing process, such as rapid thermal annealing (RTA), to cause a silicide reaction where the metal layer 276 and the liner 274 contact the source / drain features 246. The bottom of the liner 274 and the metal layer 276 are converted into a silicide layer 278 containing TiSi. The top of the metal layer 276 can remain on the top surface of the silicide layer 278 as a barrier layer to prevent oxidation of the silicide layer 277. Therefore, the remaining horizontal portion of the metal layer 276 can be thinner than the vertical portion of the metal layer 276.

[0057] refer to Figure 1 , Fig.29 and Fig.30 , the method 100 includes block 146, in which a source / drain contact 282 is formed in the opening 272. When forming the source / drain contact 282, a conductive material 280 may be deposited in the opening 272, such as Fig.29 As shown. Conductive material 280 may include cobalt, tungsten, copper, ruthenium, aluminum, gold, silver, alloys thereof, etc., or combinations thereof, and may be deposited by CVD, ALD, PVD, ECP, or any suitable deposition technique. After depositing conductive material 280, excess conductive material 280 may be removed by using a planarization process (e.g., CMP). The planarization process may remove excess conductive material 280 from above the top surface of first ILD layer 250, while the remaining portion of conductive material 280 serves as source / drain contact 282. Therefore, the top surfaces of source / drain contact 282, first ILD layer 250, and gate mask 262 may be coplanar.

[0058] Still refer to Fig.30, after the operation of frame 146 is completed, a transistor 290, particularly an n-type transistor 290, is substantially formed. The n-type transistor 290 can find applications in various circuits, such as being paired with a p-type transistor in an inverter of a static random access memory (SRAM) cell. Due to the lower resistance and higher strain in the source / drain region, an SRAM cell incorporating an n-type transistor 290 can increase the cell current by 3% and reduce the minimum operating voltage by 20mV. The transistor 290 includes a channel member 208 stacked vertically in the Z direction. Each channel member 208 is wrapped by a gate structure 256. The channel member 208 extends along the X direction or is sandwiched between two source / drain components 246. Each source / drain component 246 includes a first epitaxial layer 242 in contact with the channel member 208 and a second epitaxial layer 244 in contact with the first epitaxial layer 242. The second epitaxial layer 244 is separated from the channel member 208 by the first epitaxial layer 242. Below the source / drain feature 246 is the dielectric film 240 and the base epitaxial layer 236. Compared to a p-type transistor in which the p-type dopant in the source / drain feature is substantially uniformly distributed across the depth, the n-type transistor 280 has a non-uniform n-type dopant distribution across the depth. For example, the top of the source / drain feature 246 has a high phosphorus concentration, which can be located at the top channel member 208 (e.g., the top two channel members 208 or Fig.30 In contrast, the bottom of source / drain feature 246 has a lower phosphorus concentration. Due to the additional phosphorus ion implantation performed after the gate replacement process, the phosphorus concentration in n-type transistor 290 may even be higher than the p-type dopant in the p-type transistor. Since gate structure 256 is formed before the additional phosphorus doping, metal gate extrusion is prevented.

[0059] In one exemplary aspect, the present disclosure relates to a method. The method includes forming a stack above a substrate, the stack including a plurality of channel layers interlaced with a plurality of sacrificial layers, patterning the stack to form a fin-shaped structure, the fin-shaped structure including a channel region and a source / drain region, forming a dummy gate stack on the channel region of the fin-shaped structure, depositing a gate spacer on the sidewalls of the dummy gate stack, recessing the source / drain region to form a source / channel trench exposing the channel layer and the sidewalls of the sacrificial layer, partially recessing the sacrificial layer to form a plurality of internal spacer grooves, forming a plurality of internal spacers in the internal spacer grooves, forming an epitaxial component in the source / drain trench after forming the epitaxial component, removing the dummy gate stack, releasing the channel layer in the channel region as a plurality of channel components, forming a gate structure around each channel component, and after forming the gate structure, performing ion implantation to increase the dopant concentration of the dopant in the epitaxial component. In some embodiments, the dopant is an n-type dopant. In some embodiments, the dopant is phosphorous. In some embodiments, the method further comprises depositing a dielectric layer above the epitaxial component, etching through the dielectric layer to form a hole exposing the top surface of the epitaxial component, and depositing a liner along the sidewall of the hole before performing ion implantation. In some embodiments, the liner is a titanium layer. In some embodiments, the ion implantation uses a phosphorus dimer. In some embodiments, the dopant concentration has a first peak value above the top surface of the top second channel component in the channel component. In some embodiments, the dopant concentration has a second peak value between the top surface and the bottom surface of the top second channel component. In some embodiments, the dopant concentration at the bottom of the epitaxial component is at least one order of magnitude lower than the top of the epitaxial component. In some embodiments, the dopant concentration at the same depth of the epitaxial component is substantially the same.

[0060] In another exemplary aspect, the present disclosure relates to a method. The method includes forming a plurality of channel members disposed on a fin-shaped substrate, forming a plurality of internal spacers that stagger the channel members, forming an epitaxial component adjacent to the channel member, forming a gate structure surrounding each channel member, and after forming the gate structure, increasing a dopant concentration in the epitaxial component. In some embodiments, the increase in dopant concentration includes a phosphorus ion implantation process. In some embodiments, the dopant concentration has a value greater than about 1×10 22 Atom / cm 3 In some embodiments, the peak is located above the bottom surface of the top second channel member in the channel member. In some embodiments, the dopant concentration has another peak at a depth lower than the depth at which the peak is located. In some embodiments, the epitaxial component is substantially undoped before the dopant concentration is increased. In some embodiments, the epitaxial component includes a first epitaxial layer adjacent to the channel member and a second epitaxial layer adjacent to the internal spacer, wherein the first and second epitaxial layers at the same depth of the epitaxial component have substantially the same dopant concentration.

[0061] In another exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device includes a plurality of channel components disposed on a substrate, a plurality of internal spacers interlaced with the channel components, a gate structure surrounding each channel component, a gate spacer layer disposed on a sidewall of the gate structure, and a source / drain component adjacent to the channel component. The source / drain component has a dopant concentration profile with a peak located above a top surface of a second channel component from the top. In some embodiments, the peak is greater than about 1×10 22 Atom / cm 3 In some embodiments, the semiconductor device further comprises a liner disposed on a sidewall of the gate spacer layer. The liner comprises the same dopant as that in the source / drain feature.

[0062] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can be subjected to various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a stack over a substrate, the stack comprising a plurality of channel layers interleaved with a plurality of sacrificial layers; patterning the stack to form a fin-shaped structure, the fin-shaped structure including a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin structure; depositing gate spacers on sidewalls of the dummy gate stack; recessing the source / drain region to form a source / drain trench exposing sidewalls of the channel layer and the sacrificial layer; recessing the sacrificial layer portion to form a plurality of inner spacer grooves; forming a plurality of internal spacers in the internal spacer grooves; forming an epitaxial feature in the source / drain trench; After forming the epitaxial component, removing the dummy gate stack; releasing the channel layer in the channel region to serve as a plurality of channel components; forming a gate structure surrounding each of the channel members; as well as After forming the gate structure, ion implantation is performed to increase the dopant concentration of the dopant in the epitaxial feature.

2. The method according to claim 1, wherein: The dopant is an n-type dopant.

3. The method according to claim 2, wherein: The dopant is phosphorus.

4. The method according to claim 1, further comprising: depositing a dielectric layer over the epitaxial component; etching through the dielectric layer to form a hole exposing a top surface of the epitaxial feature; as well as Prior to performing the ion implantation, a liner is deposited along the sidewalls of the hole.

5. The method according to claim 4, wherein: The liner is a titanium layer.

6. A method of forming a semiconductor device, comprising: forming a plurality of channel members disposed over the fin-shaped substrate; forming a plurality of interior spacers, the plurality of interior spacers being interlaced with the channel member; forming an extension adjacent to the channel member; forming a gate structure surrounding each of the channel members; and After forming the gate structure, a dopant concentration in the epitaxial feature is increased.

7. The method according to claim 6, wherein: The increasing of the dopant concentration includes a phosphorus ion implantation process.

8. A semiconductor device comprising: a plurality of channel members disposed above the substrate; a plurality of internal spacers interlaced with the channel members; a gate structure surrounding each of the channel members; A gate spacer layer, disposed on a sidewall of the gate structure; as well as A source / drain feature adjoins the channel member, wherein the source / drain feature has a dopant concentration profile having a peak located above a top surface of a second channel member from the top of the channel member.

9. The semiconductor device according to claim 8, wherein: The peak is higher than about 1×10 22 Atom / cm 3 .

10. The semiconductor device according to claim 8, further comprising: A liner is disposed on a sidewall of the gate spacer layer, wherein the liner includes the same dopant as that in the source / drain component.

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