Enhanced GaN HEMT with low gate leakage and preparation method thereof

Abstract

The invention relates to an enhanced GaN HEMT (High Electron Mobility Transistor) with low gate leakage and a preparation method thereof. The enhanced GaN HEMT comprises a substrate; the barrier layer is arranged on the upper surface of the substrate; the p-type doped GaN layer is arranged on the upper surface of the barrier layer; the p-type doped GaN layer is provided with a groove which does not penetrate through the bottom of the p-type doped GaN layer; an n-type doped GaN layer is arranged in the groove; the grid electrode is positioned on the upper surface of the n-type doped GaN layer; the source electrode and the drain electrode are located on the upper surface of the barrier layer, and the grid electrode and the drain electrode are located on the two opposite sides of the p-type doped GaN layer respectively. According to the invention, an ultra-thin barrier is combined with a p-GaN gate, so that two-dimensional electron gas below the gate is further exhausted, an enhanced device with higher threshold voltage can be realized, a medium is deposited in an area outside the gate to recover 2DEG of an active area and realize low on-resistance, meanwhile, n-GaN is extended on a groove on p-GaN, and a reverse diode structure is formed when high gate voltage is applied to the gate, so that the performance of the enhanced device is improved. The voltage of the channel layer can be effectively shared, and the gate electric leakage is reduced.

Description

Technical Field

[0001] The present invention relates to the field of transistors, and in particular to an enhanced GaN HEMT (high electron mobility transistor) with low gate leakage and a preparation method thereof, and in particular to an enhanced AlGaN / GaN heterojunction high electron mobility transistor with low gate leakage and a preparation method thereof. Background Art

[0002] AlGaN / GaN heterojunction power electronic devices have the advantages of high operating temperature, high breakdown voltage, high electron mobility, etc., and have great material and system advantages in promoting the miniaturization and intelligence of the next generation of power devices. From the application point of view, the enhancement mode (normally off) power transistor is the core of ensuring the failure safety of power electronic systems. At present, the main way to prepare GaN-based enhancement mode power electronic devices in the industry is p-GaN gate technology, and GaN-based enhancement mode devices based on p-GaN gate have gate reliability problems. Under the forward gate voltage, due to the current flowing through the depletion region of p-GaN or the side wall of the gate metal / p-GaN structure, the p-GaN gate shows time-dependent breakdown, increases the gate leakage, and reduces the gate swing. At the same time, the electric field on the surface of p-GaN is very high, and the surface electric field distribution is uneven, which reduces the reliability of the gate.

[0003] To this end, the present invention is proposed. Summary of the invention

[0004] The main purpose of the present invention is to provide an enhancement-mode GaN HEMT with low gate leakage and a preparation method thereof, which combines an ultra-thin barrier with a p-GaN gate to further deplete the two-dimensional electron gas under the gate, thereby realizing an enhancement-mode device with a higher threshold voltage. At the same time, n-GaN is epitaxially grown in a groove on the p-GaN, and when a high gate voltage is applied to the gate, a reverse diode structure is formed, which can effectively share the voltage of the channel layer and reduce the gate leakage.

[0005] In order to achieve the above objectives, the present invention provides the following technical solutions.

[0006] A first aspect of the present invention provides an enhancement mode GaN HEMT with low gate leakage, comprising:

[0007] substrate;

[0008] and a barrier layer disposed on the upper surface of the substrate;

[0009] and a p-type doped GaN layer disposed on the upper surface of the barrier layer; the p-type doped GaN layer is provided with a groove that does not penetrate the bottom thereof; an n-type doped GaN layer is provided in the groove;

[0010] and a gate located on the upper surface of the n-type doped GaN layer;

[0011] and a source electrode and a drain electrode located on the upper surface of the barrier layer, and the gate electrode and the drain electrode are respectively located on two opposite sides of the p-type doped GaN layer.

[0012] Therefore, the invention combines the ultra-thin barrier with the p-GaN gate to achieve at least the following technical effects:

[0013] 1. Use thin barrier layer / GaN heterojunction to achieve intrinsic depletion of two-dimensional electron gas under the gate;

[0014] 2. The spatial depletion region formed by the contact between the p-GaN gate and the ultra-thin barrier heterojunction is used to further deplete the two-dimensional electron gas under the gate, thereby increasing the threshold of the enhancement-mode GaN-based power device;

[0015] 3. The reverse diode structure formed by combining the p-GaN layer and the n-GaN layer is used to make the PN junction depletion region bear part of the gate voltage, thereby reducing the electric field strength of the channel layer, improving the gate reliability and reducing the gate leakage;

[0016] 4. The gate and n-GaN can also form an electron barrier blocking layer. Under high gate voltage, it prevents electrons injected into p-GaN from the two-dimensional electron gas channel from bombarding the gate metal through the acceleration of the built-in electric field of the reverse-biased pn junction, thereby improving gate reliability and further reducing leakage.

[0017] In summary, the present invention effectively avoids the gate leakage problem under high voltage of p-GaN gate, realizes 2DEG depletion in the natural state, and realizes stable enhancement mode; at the same time, it can share the channel layer voltage when high voltage is applied to the gate, reduce gate leakage, and increase gate swing. It is of great significance to further realize high threshold enhancement mode AlGaN / GaN heterojunction high electron mobility transistor.

[0018] Furthermore, the barrier layer is made of metal nitride, wherein the metal includes at least one of aluminum, gallium and indium.

[0019] Furthermore, the barrier layer includes at least one of an AlN binary alloy, an AlGaN ternary alloy, an AlInN ternary alloy, an InGaN ternary alloy, and an AlInGaN quaternary alloy.

[0020] Furthermore, the thickness of the barrier layer is ≤6 nm.

[0021] Furthermore, the thickness of the p-type doped GaN layer is 20-200 nm.

[0022] Furthermore, the thickness of the n-type doped GaN layer is 15-60 nm.

[0023] The above ultra-thin barrier layer combined with the thickness of the P-GaN layer and the N-GaN layer can significantly reduce gate leakage and increase the threshold.

[0024] Furthermore, it also includes a dielectric layer covering the p-type doped GaN layer and isolating the gate from the source and the drain.

[0025] The main function of the dielectric layer is to restore the 2DEG in the gate outer region of the AlGaN / GaN heterojunction channel to achieve low on-resistance; the dielectric layer may include an aluminum oxide layer or a stack of an aluminum nitride layer and an aluminum oxide layer.

[0026] Furthermore, the length of the gate is greater than the length of the n-type doped GaN layer and less than the length of the p-type doped GaN layer;

[0027] Alternatively, the length of the gate is smaller than the length of the n-type doped GaN layer.

[0028] The above two structures of transistors can increase the operating speed of the device when it is turned on and improve the threshold stability by introducing a Schottky junction at the edge without significantly increasing the gate leakage current.

[0029] Furthermore, it also includes: a buffer layer located between the substrate and the barrier layer, and the buffer layer is preferably gallium nitride.

[0030] Adding a buffer layer can improve the quality of the epitaxial barrier layer and reduce defects.

[0031] The second aspect of the present invention provides a method for preparing the low gate leakage enhancement mode GaN HEMT of the first aspect, comprising:

[0032] forming a barrier layer on the substrate;

[0033] forming a p-type doped GaN layer on the barrier layer;

[0034] Forming a source electrode and a drain electrode on the upper surface of the barrier layer and on opposite sides of the p-type doped GaN layer respectively;

[0035] Performing n-type doping on the shallow layer of the p-type doped GaN layer to form an n-type doped GaN layer; or etching the shallow layer of the p-type doped GaN layer to form a groove, and epitaxially growing an n-type doped GaN layer in the groove;

[0036] A gate is formed on the upper surface of the n-type doped GaN layer.

[0037] Therefore, the present invention can realize the nested stacking of p-type doped GaN layer and n-type doped GaN layer in various ways, and can alleviate the electric field strength at the gate edge.

[0038] Furthermore, before forming the barrier layer, the method further includes: forming a buffer layer on the substrate.

[0039] Adding a buffer layer can improve the quality of the epitaxial barrier layer and reduce defects.

[0040] Compared with the prior art, the present invention achieves the following technical effects: an ultra-thin barrier is combined with a p-GaN gate to further deplete the two-dimensional electron gas under the gate, thereby realizing an enhancement-mode device with a higher threshold voltage; at the same time, n-GaN is epitaxially grown in a groove on the p-GaN, and a reverse diode structure is formed when a high gate voltage is applied to the gate, which can effectively share the voltage of the channel layer and reduce gate leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the following detailed description of the preferred embodiment.The drawings are only for the purpose of illustrating the preferred embodiments and are not to be construed as limiting the invention.

[0042] Figure 1 A schematic diagram of the structure of a high electron mobility transistor provided by the present invention;

[0043] Figure 2 A schematic structural diagram of another high electron mobility transistor provided by the present invention.

[0044] Reference numerals:

[0045] 1-substrate, 2-buffer layer, 3-barrier layer, 4-p-GaN layer, 5-n-GaN layer, 6-gate, 7-source, 8-drain, 9-dielectric layer. DETAILED DESCRIPTION

[0046] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0047] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0048] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0049] In order to solve the problem of poor reliability of GaN-based enhancement-mode devices based on p-GaN gates, the present invention provides an enhancement-mode AlGaN / GaN heterojunction high electron mobility transistor with low gate leakage. Figure 1 and 2 As shown, it includes a substrate 1, which can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide or germanium on insulator, etc., and the corresponding top semiconductor material is silicon, germanium, silicon germanium or gallium arsenide, etc. The substrate 1 can also be a stacked structure of multiple layers of semiconductor materials, such as a stack of silicon layer-silicon germanium layer-silicon layer. A barrier layer 3 is provided on the upper surface of the substrate 1. For a high electron mobility transistor, the barrier layer 3 is usually ultra-thin. In some embodiments, a buffer layer 2 is further provided between the substrate 1 and the barrier layer 3 to reduce the quality defects of the barrier layer 3, and the material composition of the buffer layer 2 is close to that of the barrier layer 3. A p-type doped GaN layer, i.e., a P-GaN layer, is provided on the upper surface of the barrier layer 3. The p-GaN layer 4 is provided with a groove that does not penetrate the bottom thereof; an n-type doped GaN layer, i.e., an n-GaN layer 5 is provided in the groove. and a gate electrode 6 located on the n-type upper surface of the N-GaN layer. In addition, a source electrode 7 and a drain electrode 8 are arranged on the upper surface of the barrier layer 3 and are located on two opposite sides of the p-GaN layer 4, respectively.

[0050] The high electron mobility transistor combines an ultra-thin barrier with a p-GaN gate, which can effectively avoid the gate 6 leakage problem under high voltage of the p-GaN gate, achieve 2DEG (two-dimensional electron gas) depletion in a natural state, and achieve a stable enhancement mode. At the same time, it can share the channel layer voltage when a high voltage is applied to the gate 6, reduce the gate 6 leakage, and increase the gate 6 swing.

[0051] In some embodiments, the barrier layer 3 is made of metal nitride, wherein the metal includes at least one of aluminum, gallium, and indium.

[0052] For example, the barrier layer 3 includes at least one of an AlN binary alloy, an AlGaN ternary alloy, an AlInN ternary alloy, an InGaN ternary alloy, and an AlInGaN quaternary alloy.

[0053] In some embodiments, the thickness of the barrier layer 3 is ≤6 nm.

[0054] In some embodiments, the p-type doped GaN layer has a thickness of 20 to 200 nm.

[0055] In some embodiments, the thickness of the n-type doped GaN layer is 15-60 nm.

[0056] The above ultra-thin barrier layer 3 combined with the thickness of the p-GaN layer 4 and the n-GaN layer 5 can significantly reduce the leakage of the gate 6 and increase the threshold.

[0057] In some embodiments, a dielectric layer 9 covering the p-type doped GaN layer and isolating the gate 6 from the source 7 and the drain 8 is also included, and the dielectric layer 9 includes an aluminum oxide layer or a stack of an aluminum nitride layer and an aluminum oxide layer. When the aluminum nitride layer and the aluminum oxide layer are stacked, the aluminum nitride is located in the lower layer and the aluminum oxide is located in the upper layer, and the two can be stacked alternately multiple times. The above dielectric layer 9 can prevent the deactivation of the doped elements in p-GaN, and the dielectric layer 9 formed by the contact between Al2O3 and p-GaN can block electron injection under high field.

[0058] In some embodiments, Figure 1 As shown, the length of the gate 6 is greater than the length of the n-type doped GaN layer, and less than the length of the p-type doped GaN layer;

[0059] In some embodiments, Figure 2 As shown, the length of the gate 6 is smaller than the length of the n-type doped GaN layer.

[0060] The above two structures of transistors can increase the operating speed of the device when it is turned on and improve the threshold stability by introducing a Schottky junction at the edge without significantly increasing the gate leakage current.

[0061] In some embodiments, the present invention further comprises: a buffer layer 2 located between the substrate 1 and the barrier layer 3 , wherein the buffer layer 2 is preferably gallium nitride.

[0062] Adding the buffer layer 2 can improve the quality of the epitaxial barrier layer 3 and reduce defects.

[0063] In some embodiments, the gate 6 is a metal gate, which forms a Schottky contact with n-GaN to form an electron barrier blocking layer, which prevents electrons injected into p-GaN from the 2DEG channel under high gate voltage, and bombards the gate metal through the acceleration of the built-in electric field of the reverse-biased pn junction, thereby improving the reliability of the gate 6 and further reducing leakage. Metal gates include but are not limited to nickel, titanium and their alloys.

[0064] The present invention also provides a method for preparing the high electron mobility transistor, taking the addition of the buffer layer 2 as an example, the details are as follows.

[0065] Step 1: epitaxially or depositing an unintentionally doped GaN buffer layer 2 on a substrate 1.

[0066] Step 2: Continue to form a barrier layer 3 on the buffer layer 2, such as a thin barrier Al(In,Ga)N layer with a thickness less than 6 nm.

[0067] Step 3: epitaxially grow a p-GaN layer 4 (the thickness may be 20-200 nm) on the barrier layer 3.

[0068] Step 4, etching the p-GaN layer 4 to form a groove, and epitaxially growing the n-GaN layer 5 (the thickness can be 15-60 nm). This step can also be replaced by the following method: using n-type ions such as Si ions to implant on the p-GaN surface, so that the shallow layer of the p-GaN layer 4 is converted into the n-GaN layer 5.

[0069] Step 5, depositing metal to simultaneously form a gate 6 , a source 7 and a drain 8 , wherein the source 7 and the drain 8 are respectively located on the upper surface of the barrier layer 3 and on opposite sides of the p-GaN layer 4 , and the gate 6 is located on the n-GaN layer 5 .

[0070] Step 6: forming a dielectric layer 9 between the epitaxial layer and the source and drain electrodes 8.

[0071] In the above method, the gate electrode 6 , the source electrode 7 and the drain electrode 8 can be deposited with metal at one time to form an n-type ohmic contact, which simplifies the process.

[0072] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. An enhancement-mode GaN HEMT with low gate leakage, characterized in that: include: substrate; and a barrier layer disposed on the upper surface of the substrate; and a p-type doped GaN layer disposed on the upper surface of the barrier layer; the p-type doped GaN layer is provided with a groove that does not penetrate the bottom thereof; an n-type doped GaN layer is provided in the groove; and a gate located on the upper surface of the n-type doped GaN layer; and a source electrode and a drain electrode located on the upper surface of the barrier layer, and the gate electrode and the drain electrode are respectively located on two opposite sides of the p-type doped GaN layer.

2. The low gate leakage enhancement mode GaN HEMT according to claim 1, characterized in that: The barrier layer is made of metal nitride, wherein the metal includes at least one of aluminum, gallium and indium; Preferably, the barrier layer comprises at least one of an AlN binary alloy, an AlGaN ternary alloy, an AlInN ternary alloy, an InGaN ternary alloy, and an AlInGaN quaternary alloy.

3. The low gate leakage enhancement mode GaN HEMT according to claim 1, characterized in that: The thickness of the barrier layer is ≤6 nm.

4. The low gate leakage enhancement mode GaN HEMT according to any one of claims 1 to 3, characterized in that: The thickness of the p-type doped GaN layer is 20-200 nm.

5. The low gate leakage enhancement mode GaN HEMT according to claim 4, characterized in that: The thickness of the n-type doped GaN layer is 15-60 nm.

6. The low gate leakage enhancement mode GaN HEMT according to claim 1, characterized in that: It also includes a dielectric layer covering the p-type doped GaN layer and isolating the gate from the source and the drain, and the dielectric layer includes an aluminum oxide layer or a stack of an aluminum nitride layer and an aluminum oxide layer.

7. The low gate leakage enhancement mode GaN HEMT according to claim 1, characterized in that: The length of the gate is greater than the length of the n-type doped GaN layer and less than the length of the p-type doped GaN layer; Alternatively, the length of the gate is smaller than the length of the n-type doped GaN layer.

8. The low gate leakage enhancement mode GaN HEMT according to claim 2, characterized in that: Also includes: A buffer layer is located between the substrate and the barrier layer, and the buffer layer is preferably gallium nitride.

9. The method for preparing an enhanced-mode GaN HEMT with low gate leakage according to any one of claims 1 to 7, characterized in that: include: forming a barrier layer on the substrate; forming a p-type doped GaN layer on the barrier layer; Forming a source electrode and a drain electrode on the upper surface of the barrier layer and on opposite sides of the p-type doped GaN layer respectively; Performing n-type doping on a shallow layer of the p-type doped GaN layer to form an n-type doped GaN layer; Alternatively, a shallow layer of the p-type doped GaN layer is etched to form a groove, and an n-type doped GaN layer is epitaxially grown in the groove; A gate is formed on the upper surface of the n-type doped GaN layer.

10. The preparation method according to claim 9, characterized in that: Before forming the barrier layer, the method further includes: forming a buffer layer on the substrate.

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