Low-source-drain-resistance high-Al-component barrier GaN heterojunction transistor and preparation method thereof

Abstract

The invention discloses a barrier GaN heterojunction transistor with low source-drain resistance and high Al component and a preparation method thereof, the transistor structurally comprises a substrate, a composite buffer layer, a channel layer, an isolation layer, a barrier layer and a cap layer which are sequentially arranged from bottom to top, source and drain electrodes are arranged at two ends of the surface of the cap layer, and a gate electrode is arranged between the source and drain electrodes. Etching is carried out on a partial region below the source and drain electrodes to form a nano groove array structure, inclined-angle ion implantation activation is carried out, N-type heavy doping is formed near a nano groove, and metal is filled in the nano groove to form the source and drain electrodes. Source and drain electrode metal of the structure is in direct contact with 2DEG, and forms ohmic contact after being annealed together with an N-type heavily doped region, so that the contact resistance is reduced. According to the method, the problem that the resistance value of a source-drain electrode contact resistor prepared by a conventional method of a high-Al-component barrier GaN heterojunction material is large is solved, the output current of a GaN heterojunction high-electron-mobility transistor device is increased, and the preparation process is simple, easy to implement and outstanding in effect.

Description

Technical Field

[0001] The invention relates to a GaN heterojunction transistor with low source-drain resistance and high Al component potential barrier and a preparation method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] As a typical representative of the third generation of semiconductor materials, GaN has shown great application potential in high-power and high-frequency electronic devices due to its outstanding characteristics such as high breakdown electric field, wide bandgap and high electron mobility. In GaN-based heterostructures, due to the generation of high-concentration, high-mobility two-dimensional electron gas (2DEG) at the interface, low on-resistance can be formed, effectively reducing the power loss of the device.

[0003] The transistors with high Al content barrier GaN heterostructures have higher bandgap width and breakdown electric field due to the increase of aluminum content in the barrier layer. The excellent electrical and optical properties of the devices make them widely used in high power, high frequency, high speed, ultraviolet photoelectric, radiation resistance and other fields. These devices have promoted the development of next generation electronic and optoelectronic technologies due to their high efficiency, durability and high temperature performance.

[0004] However, due to the large bandgap width of the barrier layer in GaN heterojunction materials with high Al component barriers (including AlGaN / GaN, AlN / GaN, InAlN / GaN, ScAlN / GaN), when in contact with metal, a high barrier is usually generated, which significantly limits the injection efficiency of carriers. In addition, the Fermi level pinning effect makes it difficult to adjust the interface Fermi level to the edge of the conduction band or valence band, further increasing the contact resistance.

[0005] The industry often uses Ti / Al / Ni / Au metals to be directly deposited on the wafer surface, and then annealed at high temperature to form an ohmic contact. However, after high temperature annealing, the electrode surface is rough and the edges are not sharp enough, which can easily generate spike electric fields that affect the device, and the contact resistance is not low enough. Others use the ohmic front groove etching method to etch away the entire barrier layer in the source electrode and drain electrode area, shorten the distance between the metal and the channel, reduce the barrier, and thus reduce the contact resistance. However, this method not only makes the etching accuracy difficult to control, but also only the metal close to the gate side contacts the channel layer, and the effect of reducing the ohmic contact resistance is limited.

[0006] In order to further reduce the contact resistance, some people have adopted the method of etching nano-patterns in the source electrode and drain electrode areas to form nano-grooves, filling them with metal and annealing to form ohmic contacts. However, the production of nano-patterns in this method relies on electron beam lithography equipment, which has a complex process and high cost. In addition, it is not effective for high Al component barrier GaN heterojunction materials.

[0007] Some people have also tried to perform ion implantation and heavy doping in the source and drain regions to reduce the ohmic contact resistance. However, due to the large band gap width of the high Al component barrier GaN heterojunction material, it is difficult to form heavy doping by ion implantation, resulting in a still large ohmic contact resistance, and the fabricated devices have high source resistance and drain resistance.

[0008] In view of the deficiencies in the prior art, a low source-drain resistance and high Al component barrier GaN heterojunction transistor and a preparation method thereof are invented to improve the above deficiencies. Summary of the invention

[0009] The main purpose of the present invention is to provide a low source-drain resistance high Al component barrier GaN heterojunction transistor and a preparation method thereof.

[0010] The purpose of the present invention can be achieved by adopting the following technical solutions:

[0011] A low source-drain resistance high Al component barrier GaN heterojunction transistor, the transistor structure includes a substrate, a composite buffer layer, a channel layer, an isolation layer, a barrier layer, and a cap layer arranged in sequence from bottom to top, a source electrode and a drain electrode are arranged at both ends of the cap layer surface, and a gate electrode is arranged between the source electrode and the drain electrode. The channel layer, the isolation layer and the barrier layer are III-N materials, the channel layer and the isolation layer form a heterojunction, and the heterojunction interface formed by the channel layer and the isolation layer and the side close to the isolation layer form a two-dimensional electron gas (2DEG) as a conductive channel of the GaN heterojunction transistor. Below the source electrode and the drain electrode, the cap layer, the barrier layer, and part of the channel layer are etched and removed in a part of the area to form a nano-groove array structure, ion implantation is performed at a certain tilt angle to form N-type heavy doping near the nano-groove, and then metal is filled in the nano-groove to form a source electrode and a drain electrode. The source electrode and the drain electrode metal of the structure are directly in contact with the 2DEG, and form an ohmic contact with the surrounding N-type heavily doped area to reduce the contact resistance. The method solves the problem of large contact resistance between source and drain electrodes of high Al component barrier GaN heterojunction materials, improves the performance of high Al component barrier GaN heterojunction high electron mobility transistor devices, and has a simple preparation process, easy implementation, and outstanding effect.

[0012] In one embodiment of the present invention, the substrate material may be one of silicon, silicon carbide, sapphire, diamond, GaN, and AlN, with a thickness of 50-1500 μm;

[0013] In one embodiment of the present invention, the composite buffer layer material is III-N, and the thickness is 500-1500 nm;

[0014] In one embodiment of the present invention, the channel layer 3 is made of GaN and has a thickness of 50-500 nm;

[0015] In one embodiment of the present invention, the isolation layer material is AlN, and the thickness is 0-3 nm;

[0016] In one embodiment of the present invention, the barrier layer material is AlGaN or AlN with a high Al content, and the thickness is 5-30 nm; the cap layer 6 material is GaN or silicon nitride, and the thickness is 0-5 nm.

[0017] In one embodiment of the present invention, the source electrode and the drain electrode are formed by electron beam evaporation or magnetron sputtering process, and the bottom two layers are a metal stack of Ti / Al, or the bottom two layers are a metal stack of Ta / Al, or the bottom two layers are a metal stack of Hf / Al, or the bottom two layers are a metal stack of Mo / Al, or the bottom three layers are a metal stack of Si / Ti / Al, or a Ti / Al / Ni / Au metal stack, and the thickness of the metal stack is 50-500nm.

[0018] In one embodiment of the present invention, the gate electrode is, from bottom to top, Ni and other metals, or Ti and other metals, or TiN and other metals;

[0019] The present invention also provides a method for preparing a low source-drain resistance and high Al component barrier GaN heterojunction transistor, comprising the following steps:

[0020] S1: Select GaN heterogeneous crystal circle, photolithography the device active area, and perform device isolation;

[0021] S2: Photolithography is performed to form the source electrode 9 and the drain electrode 11 regions, and a nano-groove array structure 8 is formed in the source electrode 9 and the drain electrode 11 regions by using an AAO (porous anodic aluminum oxide) material as a mask and a dry etching process;

[0022] S3: ion implantation at a certain tilt angle, annealing activation, and forming an N-type heavily doped region 7 in the III-N material around the nano-groove array structure 8;

[0023] S4: depositing metal to fill the nano-groove array structure 8 to connect the source electrode 9 and the drain electrode 11, and annealing to form the source electrode 9 and the drain electrode 11;

[0024] S5: Photolithography of the gate 10 region, deposition of gate metal, and completion of device preparation.

[0025] In one embodiment of the present invention, device isolation is accomplished by forming a high resistance region using dry etching or ion implantation.

[0026] In one embodiment of the present invention, in step S2, the AAO material is a nanoporous anodized aluminum material having a nanoarray pattern, and the AAO is used as a mask to form nanoarray grooves 8 in the source electrode 9 and drain electrode 11 regions by dry etching. The dry etching process adopts RIE, ICP or ECR dry etching method, and uses a mixed gas including Cl2 or BCl3 for etching, or Cl2 or BCl3 with O2 or Ar gas for auxiliary etching to form a nanogroove array pattern, and the etching depth reaches about the channel layer, about 0-100nm below the 2DEG channel.

[0027] In one embodiment of the present invention, in step S3, ion implantation is performed to activate Si to form an N-type heavily doped region, and the implantation tilt angle is 5-45 degrees.

[0028] In one embodiment of the present invention, in step S4, the nano-grooves are first filled by electron beam evaporation or magnetron sputtering, and then the source and drain metals are deposited by electron beam evaporation or magnetron sputtering. The annealing process is rapid thermal annealing, furnace annealing, or box annealing in a N2 atmosphere, at a temperature of 350-900°C and an annealing time of 10s-6min.

[0029] In one embodiment of the present invention, in step S4, before depositing the source and drain electrode metals, acid washing is performed to eliminate the negative impact of oxides on the ohmic contact.

[0030] In one embodiment of the present invention, in step S4, the gate metal is deposited by electron beam evaporation or magnetron sputtering process, and the metal is a Ti / Al metal stack, or a Ta / Al metal stack, or a Ti / Au metal stack, or a Ni / Au metal stack.

[0031] Beneficial technical effects of the present invention:

[0032] 1. The present invention etches nano-array grooves under the source and drain regions, fills metal to connect the source and drain, and makes the source and drain metal directly contact the channel layer, thereby increasing the contact area between the metal and the channel layer and effectively reducing the resistance of the source electrode and the drain electrode;

[0033] 2. The present invention uses AAO material as an etching mask to etch nano-array grooves. Compared with the conventional method of using electron beam exposure to generate nano-patterns, it simplifies the process preparation process, reduces the process preparation difficulty, and reduces the device preparation cost;

[0034] 3. In the nano-array grooves below the source and drain regions, Si is implanted with ions at a certain tilt angle. After activation, N-type heavy doping is formed in the channel layer near the nano-grooves, so that the source and drain metal sides are in contact with the N-type heavily doped GaN channel layer, solving the problem that the barrier layer with high Al components is difficult to form N-type heavy doping and reducing the ohmic contact resistance;

[0035] 4. The preparation process of the present invention is simple, compatible with existing processes, low in cost, and conducive to large-scale promotion. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Schematic diagram of the GaN heterojunction epitaxial material structure in an embodiment of the present invention

[0037] Figure 2 Schematic diagram of the structure of the GaN heterojunction high electron mobility transistor prepared in the embodiment of the present invention

[0038] Figure 3 The overall process flow chart of the GaN heterojunction high electron mobility transistor prepared by the present invention.

[0039] Figure 4-8 This is a diagram of the manufacturing process of the GaN heterojunction high electron mobility transistor prepared by the present invention.

[0040] Description of the accompanying drawings: 1-substrate layer, 2-composite buffer layer, 3-channel layer, 4-isolation layer, 5-barrier layer, 6-cap layer, 7-ion implantation to form N-type heavily doped region, 8-nano-groove structure, 9-source electrode, 10-gate electrode, 11-drain electrode. DETAILED DESCRIPTION

[0041] In order to make the technical solution of the present invention more clear and specific to those skilled in the art, the present invention is further described in detail below in conjunction with embodiments and drawings, but the implementation manner of the present invention is not limited thereto.

[0042] Please see the attached picture, Figure 1 is a schematic structural diagram of a GaN heterojunction epitaxial material provided by an embodiment of the present invention, Figure 2 It is a schematic diagram of a low source-drain resistance and high Al component barrier GaN heterojunction transistor structure provided by an embodiment of the present invention. The GaN heterojunction epitaxial material provided in this embodiment includes a substrate layer 1, a composite buffer layer 2, a channel layer 3, an isolation layer 4, a barrier layer 5, and a cap layer 6 from bottom to top, wherein the composite buffer layer is composed of AlN, AlGaN with varying aluminum components, and GaN. The channel layer 3 and the barrier layer 5 form a heterojunction structure, and a two-dimensional electron gas with high concentration and high mobility is formed at the interface. The source electrode 9 and the drain electrode 11 are located above the nano-groove structure 8 and the N-type heavily doped region 7, and the gate electrode 10 is located above the cap layer. Figure 2 Schematic diagram of the structure of a GaN heterojunction high electron mobility transistor prepared in an embodiment of the present invention. Figure 3 It is an overall process flow chart of the GaN heterojunction high electron mobility transistor prepared by the present invention. Figure 4-8 This is a diagram of the manufacturing process of the GaN heterojunction high electron mobility transistor prepared by the present invention.

[0043] The material of the substrate layer 1 of the present invention can be silicon, silicon carbide, sapphire, diamond, GaN, AlN, and the thickness is 50-1500 μm. In this example, a silicon substrate with a thickness of 675 μm is selected.

[0044] The composite buffer layer 2 of the present invention, in this embodiment, the materials selected in the composite buffer layer are AlN, AlGaN with varying aluminum components, and GaN in sequence, and the total thickness of the composite buffer layer is 1.5 μm.

[0045] The material of the channel layer 3 of the present invention is GaN, InGa or AlN, which can be selected according to specific performance and cost requirements. In this embodiment, the material of the channel layer 3 is GaN, and the thickness is 300nm.

[0046] The barrier layer 4 of the present invention is located between the channel layer and the barrier layer, and is made of AlN with a thickness of 1 nm. Insertion of the barrier layer can improve the electron density and mobility of the two-dimensional electron gas, which is beneficial to improving the output characteristics of the device.

[0047] The barrier layer 5 of the present invention has a thickness of 5-30 nm, is located on the channel layer 3, and is generally made of AlGaN, InGaN or AlN. The material type can be selected according to cost and performance requirements. In this embodiment, the barrier layer 4 has a thickness of 6 nm and is made of AlN.

[0048] The cap layer 6 of the present invention is located on the barrier layer, and its material is generally GaN or silicon nitride, with a thickness of 0-5 nm. In this embodiment, the cap layer is 3 nm GaN.

[0049] The present invention utilizes a dry etching process and uses AAO material as a mask to form a nano-groove array pattern 8 below the source 9 and drain 11 regions, forms an N-type heavily doped region 7 by oblique ion implantation, fills the source 9 and drain 11 with metal, arranges a Schottky gate 10 on the cap layer, arranges a source electrode 7, and the drain electrode 10 is located on the nano-groove structure 8.

[0050] Reference Figure 3 and Figure 4 The present invention provides a method for preparing a GaN heterojunction transistor with low source-drain resistance and high Al component barrier, comprising the following steps:

[0051] S1: Select GaN heterogeneous crystal circle, photolithography the device active area, and perform device isolation;

[0052] S2: Photolithography is performed to form the source electrode 9 and the drain electrode 11 regions, and a nano-groove array structure 8 is formed in the source electrode 9 and the drain electrode 11 regions by using an AAO (porous anodic aluminum oxide) material as a mask and a dry etching process;

[0053] S3: ion implantation at a certain tilt angle, annealing activation, and forming an N-type heavily doped region 7 in the III-N material around the nano-groove array structure 8;

[0054] S4: depositing metal to fill the nano-groove array structure 8 to connect the source electrode 9 and the drain electrode 11, and annealing to form the source electrode 9 and the drain electrode 11;

[0055] S5: Photolithography of the gate area, deposition of gate metal, and completion of device preparation.

[0056] The following, combined Figure 3 , Figure 4 , several embodiments of preparing the above device are given:

[0057] Embodiment 1:

[0058] A method for preparing a low source-drain resistance and high Al component barrier GaN heterojunction transistor according to this embodiment includes the following steps:

[0059] Step 1, cleaning the GaN heterojunction epitaxial material;

[0060] Specifically, the sample surface was first cleaned with an acid solution to remove oxides and metal particles, then ultrasonically cleaned with an acetone solution for 10 minutes, then ultrasonically cleaned with an isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure N2.

[0061] Step 2: Use photolithography technology to define active areas on the GaN heterojunction epitaxial material, and use ion implantation or ICP dry etching to isolate the device. In this embodiment, ICP dry etching process is used to achieve device isolation.

[0062] Step 3: clean the sample surface and define the source and drain ohmic contact electrode areas by photolithography.

[0063] Specifically, the sample surface was cleaned with BOE solution for 2 minutes, then ultrasonically cleaned with acetone solution for 10 minutes, then ultrasonically cleaned with isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure N2. The sample surface was coated with photoresist, dried on a hot plate, exposed with a photolithography machine, and developed to reveal the ohmic contact areas of the source and drain electrodes.

[0064] Step 4: Using the AAO material as a mask, a nano-groove array is formed by dry etching.

[0065] Specifically, the AAO material is covered on the surface of the source electrode and drain electrode areas, and an ICP dry etching process is used with a Cl2 / BCl3 mixed gas and the AAO material as a mask to etch a nano-pattern. The etching depth reaches the GaN heterojunction channel layer, which is about 10 nm below the 2DEG channel, to form a nano-groove array.

[0066] Step 5, ion implantation of Si at an inclined angle forms an N-type heavily doped region around the nano-groove after activation.

[0067] Specifically, acid pickling is used to remove the negative effects of etching derivatives on the device's ohmic contact and ion implantation, Si is implanted at a 45-degree tilt angle, and a rapid annealing furnace is used to anneal at 1200°C for 30s to activate Si ions to form an N-type heavily doped region around the nano-grooves and repair the damage caused by dry etching.

[0068] Step 6: Fill the nano-groove array with metal and deposit source and drain electrode metals.

[0069] Specifically, the sample was soaked in BOE solution for 30 seconds before metal deposition to remove the influence of oxide on ohmic contact; the nano-groove array structure was first filled with a magnetron sputtering device, and the sputtered metal was Ti / Au, with a metal Ti thickness of 20nm and a metal Au thickness of 30nm. Then, Ti / Al / Ni / Au ohmic metal was deposited using an electron beam evaporation process, with a bottom metal Ti thickness of 20nm, a metal Al thickness of 120nm, a metal Ni thickness of 40nm, and a metal Au thickness of 50nm.

[0070] Step 7: Using a rapid thermal annealing process, annealing in a N2 atmosphere to form an ohmic contact.

[0071] Specifically, in an N2 atmosphere, a rapid thermal annealing process is adopted, and rapid annealing is performed at 850°C for 32s to form an ohmic contact.

[0072] Step 8: Photolithography defines the gate area and deposits gate metal.

[0073] Specifically, the gate metal is deposited by electron beam evaporation or magnetron sputtering. In this embodiment, the gate metal Ni / Au is deposited by electron beam evaporation, and the thickness of the metal Ni is 40 nm and the thickness of the metal Au is 300 nm.

[0074] Embodiment 2:

[0075] A method for preparing a low source-drain resistance and high Al component barrier GaN heterojunction transistor according to this embodiment includes the following steps:

[0076] Step 1, cleaning the GaN heterojunction epitaxial material;

[0077] Specifically, the sample surface was first cleaned with an acid solution to remove oxides and metal particles, then ultrasonically cleaned with an acetone solution for 10 minutes, then ultrasonically cleaned with an isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure N2.

[0078] Step 2: Use photolithography technology to define active regions on GaN heterojunction epitaxial materials, and use ion implantation or ICP dry etching to isolate devices. In this embodiment, Ar ion implantation is used to form high resistance regions for device isolation.

[0079] Step 3: clean the sample surface and define the source and drain ohmic contact electrode areas by photolithography.

[0080] Specifically, the sample surface was cleaned with BOE solution for 2 minutes, then ultrasonically cleaned with acetone solution for 10 minutes, then ultrasonically cleaned with isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure N2. The sample surface was coated with photoresist, dried on a hot plate, exposed with a photolithography machine, and developed to reveal the ohmic contact areas of the source and drain electrodes.

[0081] Step 4: Using the AAO material as a mask, a nano-groove array is formed by dry etching.

[0082] Specifically, the AAO material is covered on the surface of the source electrode and drain electrode areas, and an ICP dry etching process is used with a Cl2 / BCl3 mixed gas and the AAO material as a mask to etch a nano-pattern. The etching depth reaches the GaN heterojunction channel layer, which is about 20nm below the 2DEG channel, to form a nano-groove array.

[0083] Step 5, ion implantation of Si at an inclined angle forms an N-type heavily doped region around the nano-groove after activation.

[0084] Specifically, acid pickling is used to remove the negative effects of etching derivatives on the device's ohmic contact and ion implantation, Si is implanted at a 40-degree tilt angle, and a rapid annealing furnace is used to anneal at 1150°C for 30 seconds to activate Si ions to form an N-type heavily doped region around the nano-grooves and repair the damage caused by dry etching.

[0085] Step 6: Fill the nano-groove array with metal and deposit source and drain electrode metals.

[0086] Specifically, the sample was soaked in BOE solution for 30 seconds before metal deposition to remove the influence of oxide on ohmic contact; the nano-groove array structure was first filled with a magnetron sputtering device, and the sputtered metal was Ti / Au, with a metal Ti of 20nm and a metal Au of 30nm. Then, the Hf / Al / Ni / Au ohmic metal connection nano-groove array metal was deposited using an electron beam evaporation process, with the bottom metal Hf having a thickness of 20nm, the metal Al having a thickness of 120nm, the metal Ni having a thickness of 40nm, and the metal Au having a thickness of 50nm.

[0087] Step 7: Using a rapid thermal annealing process, annealing in a N2 atmosphere to form an ohmic contact.

[0088] Specifically, in an N2 atmosphere, a rapid thermal annealing process is adopted, and rapid annealing is performed at 800°C for 32s to form an ohmic contact.

[0089] Step 8: Photolithography defines the gate area and deposits gate metal.

[0090] Specifically, the gate metal is deposited by electron beam evaporation or magnetron sputtering. In this embodiment, the gate metal Ni / Au is deposited by electron beam evaporation, and the thickness of the metal Ni is 40 nm and the thickness of the metal Au is 300 nm.

[0091] Embodiment three:

[0092] A method for preparing a low source-drain resistance and high Al component barrier GaN heterojunction transistor according to this embodiment includes the following steps:

[0093] Step 1, cleaning the GaN heterojunction epitaxial material;

[0094] Specifically, the sample surface was first cleaned with an acid solution to remove oxides and metal particles, then ultrasonically cleaned with an acetone solution for 10 minutes, then ultrasonically cleaned with an isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure N2.

[0095] Step 2: Use photolithography technology to define active regions on GaN heterojunction epitaxial materials, and use ion implantation or ICP dry etching to isolate devices. In this embodiment, Ar ion implantation is used to form high resistance regions for device isolation.

[0096] Step 3: clean the sample surface and define the source and drain ohmic contact electrode areas by photolithography.

[0097] Specifically, the sample surface was cleaned with BOE solution for 2 minutes, then ultrasonically cleaned with acetone solution for 10 minutes, then ultrasonically cleaned with isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure N2. The sample surface was coated with photoresist, dried on a hot plate, exposed with a photolithography machine, and developed to reveal the ohmic contact areas of the source and drain electrodes.

[0098] Step 4: Using the AAO material as a mask, a nano-groove array is formed by dry etching.

[0099] Specifically, the AAO material is covered on the surface of the source electrode and drain electrode areas, and the ECR dry etching process is adopted with a Cl2 / BCl3 mixed gas and the AAO material as a mask to etch the nano-pattern. The etching depth reaches the GaN heterojunction channel layer, which is about 30nm below the 2DEG channel, to form a nano-groove array.

[0100] Step 5, ion implantation of Si at an inclined angle forms an N-type heavily doped region around the nano-groove after activation.

[0101] Specifically, acid pickling was used to remove the negative effects of etching derivatives on the device's ohmic contact and ion implantation, Si was implanted at a 35-degree tilt angle, and a rapid annealing furnace was used to anneal at 1200°C for 1 min to activate Si ions to form an N-type heavily doped region around the nano-grooves and repair the damage caused by dry etching.

[0102] Step 6: Fill the nano-groove array with metal and deposit source and drain electrode metals.

[0103] Specifically, the sample was soaked in BOE solution for 30 seconds before metal deposition to remove the influence of oxide on ohmic contact; the nano-groove array structure was first filled with a magnetron sputtering device, and the sputtered metal was Ti / Cu, the metal Ti was 20nm, and the metal Cu was 30nm. Then, the Ti / Al / Ti / TiN ohmic metal was deposited to connect the metal of the nano-groove array by electron beam evaporation process, and the bottom metal Ti was 10nm thick, the metal Al was 100nm thick, the metal Ti was 40nm thick, and the metal Ti was 60nm thick.

[0104] Step 7: Using a rapid thermal annealing process, annealing in a N2 atmosphere to form an ohmic contact.

[0105] Specifically, in an N2 atmosphere, a rapid thermal annealing process is adopted, and rapid annealing is performed at 530° C. for 32 seconds to form an ohmic contact.

[0106] Step 8: Photolithography defines the gate area and deposits gate metal.

[0107] Specifically, the gate metal is deposited by electron beam evaporation or magnetron sputtering. In this embodiment, the gate metal Ni / TiN is deposited, the thickness of the electron beam evaporated metal Ni is 40nm, and the thickness of the magnetron sputtered metal TiN is 350nm.

[0108] Embodiment 4:

[0109] A method for preparing a low source-drain resistance and high Al component barrier GaN heterojunction transistor according to this embodiment includes the following steps:

[0110] Step 1, cleaning the GaN heterojunction epitaxial material;

[0111] Specifically, the sample surface was first cleaned with an acid solution to remove oxides and metal particles, then ultrasonically cleaned with an acetone solution for 10 minutes, then ultrasonically cleaned with an isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure N2.

[0112] Step 2: Use photolithography technology to define active areas on the GaN heterojunction epitaxial material, and use ion implantation or ICP dry etching to isolate devices. In this embodiment, ICP dry etching is used to isolate devices.

[0113] Step 3: clean the sample surface and define the source and drain ohmic contact electrode areas by photolithography.

[0114] Specifically, the sample surface was cleaned with BOE solution for 2 minutes, then ultrasonically cleaned with acetone solution for 10 minutes, then ultrasonically cleaned with isopropanol solution for 10 minutes, then cleaned with deionized water for 5 minutes, and finally dried with ultrapure N2. The sample surface was coated with photoresist, dried on a hot plate, exposed with a photolithography machine, and developed to reveal the ohmic contact areas of the source and drain electrodes.

[0115] Step 4: Using the AAO material as a mask, a nano-groove array is formed by dry etching.

[0116] Specifically, the AAO material is covered on the surface of the source electrode and drain electrode areas, and the ECR dry etching process is adopted. A Cl2 / BCl3 mixed gas is used, and the AAO material is used as a mask to etch the nano pattern. The etching depth reaches the GaN heterojunction channel layer, which is about 40nm below the 2DEG channel, to form a nano groove array.

[0117] Step 5, ion implantation of Si at an inclined angle forms an N-type heavily doped region around the nano-groove after activation.

[0118] Specifically, acid pickling was used to remove the negative effects of etching derivatives on the device's ohmic contact and ion implantation, Si was implanted at a 30-degree tilt angle, and a rapid annealing furnace was used to anneal at 1150°C for 1 min to activate Si ions to form an N-type heavily doped region around the nano-grooves and repair the damage caused by dry etching.

[0119] Step 6: Fill the nano-groove array with metal and deposit source and drain electrode metals.

[0120] Specifically, the sample was soaked in BOE solution for 30 seconds before metal deposition to remove the influence of oxide on ohmic contact; the nano-groove array structure was first filled with a magnetron sputtering device, and the sputtered metal was Ti / Cu, with a metal Ti of 20nm and a metal Cu of 30nm. Then, the Ta / Al / TiN ohmic metal connection nano-groove array metal was deposited using an electron beam evaporation process, with a bottom metal Ta thickness of 20nm, a metal Al thickness of 200nm, and a metal TiN thickness of 60nm.

[0121] Step 7: annealing to form an ohmic contact.

[0122] Specifically, in a N2 atmosphere, a rapid thermal annealing process is adopted, and rapid annealing is performed at 570°C for 240s to form an ohmic contact.

[0123] Step 8: Photolithography defines the gate area and deposits gate metal.

[0124] Specifically, the gate metal is deposited by electron beam evaporation or magnetron sputtering. In this embodiment, the gate metal Ni / W is deposited by electron beam evaporation, and the thickness of the metal Ni is 40 nm, and the thickness of the metal W is 300 nm.

[0125] The above description is only a further embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solutions and concepts of the present invention within the scope disclosed by the present invention, which belong to the protection scope of the present invention.

Claims

1. A low source-drain resistance and high Al component barrier GaN heterojunction transistor, characterized in that: The invention comprises a substrate (1), a composite buffer layer (2), a channel layer (3), an isolation layer (4), a barrier layer (5), and a cap layer (6) which are arranged in sequence from bottom to top. A source electrode (9) and a drain electrode (11) are arranged at both ends of the surface of the cap layer (6). A gate electrode (10) is arranged between the source electrode (9) and the drain electrode (11). The channel layer (3), the isolation layer (4), and the barrier layer (5) are made of III-N materials. The channel layer (3) and the isolation layer (4) form a heterojunction. A two-dimensional electron gas (2DEG) is formed at the heterojunction interface formed by the channel layer (3) and the isolation layer (4) and on the side close to the isolation layer (4), which serves as a conductive channel of a GaN heterojunction transistor. The source electrode (9) and drain electrode (11), a cap layer (6), a barrier layer (5), a channel layer (4) and a part of the III-N composite buffer layer (2) are etched and removed in a part of the region to form a nano-groove array (8) structure, ions are implanted at an inclined angle to form an N-type heavily doped region (7) near the nano-groove array (8) structure, and metal is then filled in the nano-groove (8) to form a source electrode (9) and a drain electrode (11). The source electrode (9) and the drain electrode (11) of the structure are in direct contact with the 2DEG through the nano-groove (8), thereby increasing the contact area between the source electrode (9) and the drain electrode (11) and the 2DEG, forming an ohmic contact with the surrounding N-type heavily doped region, and reducing the contact resistance.

2. The low source-drain resistance and high Al content barrier GaN heterojunction transistor according to claim 1, characterized in that: The substrate (1) material can be one of silicon, silicon carbide, sapphire, diamond, GaN, and AlN, with a thickness of 50-1500 μm; the composite buffer layer (2) material is III-N, with a thickness of 500-1500 nm; the channel layer (3) material is GaN, with a thickness of 50-500 nm; the isolation layer (4) material is AlN, with a thickness of 0-3 nm; the barrier layer (5) material is one of AlGaN, AlN, InAlN, and ScAlN with a high Al component, with an Al component of ≥50%, and a thickness of 5-30 nm; the cap layer (6) material is GaN or silicon nitride, with a thickness of 0-5 nm.

3. The low source-drain resistance and high Al content barrier GaN heterojunction transistor according to claim 1, characterized in that: The source electrode (9) and the drain electrode (11) are formed by electron beam evaporation or magnetron sputtering, and the bottom two layers are a metal stack of Ti / Al, or the bottom two layers are a metal stack of Ta / Al, or the bottom two layers are a metal stack of Hf / Al, or the bottom two layers are a metal stack of Mo / Al, or the bottom three layers are a metal stack of Si / Ti / Al, or a metal stack of Ti / Al / Ni / Au, and the thickness of the metal stack is 50-500nm. The gate electrode (10) is, from bottom to top, Ni and other metals, or Ti and other metals, or TiN and other metals.

4. The method for preparing a low source-drain resistance and high Al component barrier GaN heterojunction transistor according to claim 1, characterized in that: The following steps are involved: S1: Select GaN heterogeneous crystal circle, photolithography the device active area, and perform device isolation; S2: Photolithography is performed to form source electrode (9) and drain electrode (11) regions, and a nano-groove array structure (8) is formed in the source electrode (9) and drain electrode (11) regions using an AAO (porous anodic aluminum oxide) material as a mask plate by dry etching process; S3: ion implantation at an inclined angle, annealing activation, and forming an N-type heavily doped region (7) in the III-N material around the nano-groove array structure (8); S4: depositing metal to fill the nano-groove array structure (8) to connect the source electrode (9) and the drain electrode (11), and annealing to form the source electrode (9) and the drain electrode (11); S5: Photolithography of the gate (10) region, deposition of gate metal, and completion of device preparation.

5. The method for preparing a low source-drain resistance and high Al component barrier GaN heterojunction transistor according to claim 4, characterized in that: In the step S1, the device isolation is completed by forming a high resistance region by dry etching or ion implantation.

6. The method for preparing a low source-drain resistance and high Al component barrier GaN heterojunction transistor according to claim 4, characterized in that: In the step S2, the AAO material is a nanoporous anodized aluminum material having a nanoarray pattern thereon. AAO is used as a mask to form nanoarray grooves (8) in the source electrode (9) and drain electrode (11) regions by dry etching. The dry etching process adopts RIE, ICP or ECR dry etching methods, and uses a mixed gas including Cl2 or BCl3 for etching, or Cl2 or BCl3 with O2 or Ar gas for auxiliary etching to form a nanogroove array structure (8). The etching depth reaches approximately the channel layer, approximately 0-50 nm below the channel layer.

7. The method for preparing a low source-drain resistance and high Al component barrier GaN heterojunction transistor according to claim 4, characterized in that: In the step S3, Si is ion-implanted at a certain tilt angle to form an N-type heavily doped region (7) in the III-N material near the nano-groove array (8), and the tilt angle is 5-45 degrees.

8. The method for preparing a low source-drain resistance and high Al component barrier GaN heterojunction transistor according to claim 4, characterized in that: In the step S4, the annealing process is rapid thermal annealing, furnace annealing, or box annealing in a N2 atmosphere, with a temperature of 350-900°C and an annealing time of 10s-6min.

9. The method for preparing a low source-drain resistance and high Al component barrier GaN heterojunction transistor according to claim 4, characterized in that: In the step S5, gate metal is deposited by electron beam evaporation or magnetron sputtering.

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