Double-groove small-size SiC MOSFET device structure and preparation method thereof

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a double-groove small-size SiC MOSFET device structure which comprises a drain electrode, a source electrode and a semiconductor epitaxial layer, the semiconductor epitaxial layer comprises an N substrate layer, an N-type drift layer, a P well layer, a grid electrode, a grid oxide layer, an N well layer and a heavily doped P layer, the grid oxide layer covers the surface of the grid electrode, and the N well layer covers the surface of the N substrate layer. The light emitting diode is characterized in that the section heights of the P well layer and the N well layer are consistent, and the doping height of the P well layer exceeds the doping height of the heavily doped P layer; the section width of the adjacent P well layer and N well layer in a single MOS cell is consistent with the section width of the gate oxide layer. According to the invention, the source electrode ohmic contact region is changed from the transverse direction to the longitudinal direction, so that the cell size occupied by the transverse contact between the source electrode metal and the N + source region is eliminated, the cell size of the device can be greatly reduced, the current density of the device is improved, and the yield of the device with the same performance can be increased by more than 20%.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a double-trench small-size SiC MOSFET device structure and a preparation method thereof. Background Art

[0002] SiC MOSFET devices have the significant advantages of high frequency and low loss, and are widely used in electric vehicles, photovoltaic inverters, charging piles, etc. In order to meet the development needs of high energy efficiency, high power density, and small and lightweight power electronic systems, SiC power devices are developing in the direction of high voltage, high power, high frequency and low loss.

[0003] Compared with the traditional VDMOSFET structure, the U-groove MOSFET structure reduces the interface state density and thus increases the reliability of the device; at the same time, it increases the channel mobility, eliminates the JFET region resistance, and transforms the channel from horizontal to vertical, thereby reducing the cell size. This makes the U-groove MOSFET device structure have a higher current density than the VDMOSFET device structure.

[0004] However, with the continuous development of devices, the existing U-groove MOSFET device structure is no longer sufficient to meet the requirements of cell size reduction. Figure 3 shown.

[0005] Existing patents disclose a silicon carbide dual-trench MOSFET with integrated trench diode (publication number: CN113990923B), a dual-trench SS-SiC MOSFET structure (publication number: CN109768091B), a dual-trench low on-resistance, small gate charge silicon carbide MOSFET device and preparation method (publication number: CN107658340A), etc., all of which are improvements on existing U-trench MOSFET devices from different angles, but all at the expense of cell size. This is not much different from the P+ injection area in a general single U-trench MOSFET, and except for its patent name, it has nothing to do with the three words "double U-trench". Summary of the invention

[0006] The main technical problem solved by the present invention is to provide a double-trench small-size SiC MOSFET device structure and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0007] To solve the above technical problems, according to one aspect of the present invention, more specifically, a double-trench small-size SiCMOSFET device structure includes a drain, a source and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer includes an N substrate layer, an N-type drift layer, a P-well layer, a gate, a gate oxide layer, an N-well layer and a heavily doped P layer, wherein the gate oxide layer covers the surface of the gate, and is characterized in that: the cross-sectional height of the P-well layer is consistent with that of the N-well layer, and the doping height of the P-well layer exceeds the doping height of the heavily doped P layer;

[0008] The cross-sectional widths of two adjacent P-well layers and N-well layers in a single MOS cell are consistent with the cross-sectional width of the gate oxide layer, wherein the ohmic contact regions between the source electrode and the P-well layer and the N-well layer are transformed from the horizontal direction to the vertical direction.

[0009] Furthermore, the heavily doped P layer is formed into a convex shape by injecting excess ions.

[0010] A method for preparing a double-trench small-size SiC MOSFET device structure comprises the following steps:

[0011] S1, SiC substrate selection and epitaxial layer growth, as well as source and drain doping;

[0012] S2, oxidation growth to form a gate oxide layer, and photolithography and patterning;

[0013] S3, gate metallization;

[0014] S4, etching and formation of double groove structure;

[0015] S5, source and drain metallization;

[0016] S6. Electrical performance testing and packaging.

[0017] Furthermore, in the doping of the source and drain in step S, it is necessary to perform doping in the epitaxial layer by ion implantation or diffusion process to form the source and drain regions.

[0018] Furthermore, the etching and formation of the double-groove structure in step S is mainly performed by etching the source and drain regions of the device using a double-groove etching method, and the process requires the use of a dry etching method to control the groove width and depth.

[0019] Furthermore, in the step S, metal material is deposited by metal evaporation and sputtering to form source and drain electrodes.

[0020] Furthermore, in step S, the electrical performance test of the SiC MOSFET device structure includes the turn-on voltage, on-resistance, breakdown voltage of the device, and the total charge required for the SiC MOSFET device to switch from off to on, to determine the electrical performance of the SiC MOSFET device, including:

[0021]

[0022] Where, C represents the electrical performance qualification coefficient of SiC MOSFET devices, V G It represents the minimum gate-source voltage required for the SiCMOSFET device to start conducting. B It represents the maximum voltage value that the device can withstand under the drain-source voltage, R represents the resistance between the source and the drain of the SiC MOSFET device when it is on, and Q represents the total charge required for the SiC MOSFET device to switch from off to on.

[0023] Furthermore, when C ≥ 93%, it indicates that the electrical performance of the detected SiC MOSFET device is excellent;

[0024] When C ≥ 71%, it means that the electrical performance of the tested SiC MOSFET device is qualified;

[0025] When C is less than 71%, it indicates that the electrical performance of the detected SiC MOSFET device is unqualified.

[0026] Beneficial effects:

[0027] 1. The present invention transforms the source ohmic contact area from horizontal to vertical, eliminating the cell size occupied by the source metal in the horizontal contact with the N+ source area, which can greatly reduce the cell size of the device, improve the device current density, and increase the output of devices with the same performance by more than 20%.

[0028] 2. The present invention implants P+ ions at a depth exceeding a certain depth of the gate U groove, which can form an electric field shield for the gate U groove when the device is blocked, thereby preventing the gate from breaking down and improving device reliability.

[0029] 3. The present invention can efficiently and conveniently detect the electrical performance of the SiC MOSFET device by measuring the turn-on voltage, on-resistance, breakdown voltage, and the total charge required for the SiC MOSFET device to switch from off to on. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural schematic diagram of Embodiment 1 of the present invention;

[0031] Figure 2This is a schematic diagram of the structure of Embodiment 2 of the present invention;

[0032] Figure 3 Schematic diagram of existing SiC MOSFET devices;

[0033] Figure 4 It is a comparison diagram between the existing SiC MOSFET device and the embodiment device.

[0034] In the figure: 1, drain; 2, N substrate layer; 3, N-type drift layer; 4, P well layer; 5, gate; 6, gate oxide layer; 7, N well layer; 8, heavily doped P layer; 9, source. DETAILED DESCRIPTION

[0035] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] A method for preparing a double-trench small-size SiC MOSFET device structure comprises the following steps:

[0037] Step 1: SiC substrate selection and epitaxial layer growth, as well as source 9 and drain 1 doping; in the doping of source 9 and drain 1, ion implantation or diffusion process is required to be performed in the epitaxial layer to form source 9 and drain 1 regions.

[0038] Step 2: Oxidation growth to form a gate oxide layer 6, photolithography and patterning, and gate 5 metallization.

[0039] Step three, etching and forming a double-trench structure; the etching and forming of the double-trench structure mainly uses a double-trench etching method to etch and form the source 9 and drain 1 regions of the device, and the process requires the use of a dry etching method to control the trench width and depth.

[0040] Step 4: Metallization of the source 9 and the drain 1: Depositing metal material by metal evaporation and sputtering to form the source 9 and the drain 1 electrodes.

[0041] Step 5: Electrical performance testing and packaging.

[0042] The electrical performance test of SiC MOSFET device structure includes the device's turn-on voltage, on-resistance, breakdown voltage, and the total charge required for the SiC MOSFET device to switch from off to on, to determine the electrical performance of the SiC MOSFET device, including:

[0043]

[0044] Where, C represents the electrical performance qualification coefficient of SiC MOSFET devices, V GIt represents the minimum gate-source voltage required for the SiCMOSFET device to start conducting. B It represents the maximum voltage value that the device can withstand under the drain-source voltage, R represents the resistance between the source 9 and the drain 1 of the SiC MOSFET device when it is on, and Q represents the total charge required for the SiC MOSFET device to switch from off to on.

[0045] When C ≥ 93%, it means that the electrical performance of the tested SiC MOSFET device is excellent;

[0046] When C ≥ 71%, it means that the electrical performance of the tested SiC MOSFET device is qualified;

[0047] When C is less than 71%, it indicates that the electrical performance of the detected SiC MOSFET device is unqualified.

[0048] When device X is tested, it is detected that the minimum gate-source voltage of device X required for the SiC MOSFET device to start conducting is V G =9(V), the maximum voltage that device X can withstand under drain-source voltage is V B =150(V), the resistance between source 9 and drain 1 in the on state is R=28(milliohms), the total charge required for device X from off to on is Q=60(nC), then:

[0049]

[0050] From the above calculation, it can be known that the electrical performance of device X is qualified.

[0051] Example 1

[0052] like Figure 1-2 As shown, according to one aspect of the present invention, a double-trench small-size SiC MOSFET device structure is provided, comprising a drain 1, a source 9 and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises an N substrate layer 2, an N-type drift layer 3, a P-well layer 4, a gate 5, a gate oxide layer 6, an N-well layer 7 and a heavily doped P layer 9, wherein the gate oxide layer 6 covers the surface of the gate 5, the cross-sectional heights of the P-well layer 4 and the N-well layer 7 are consistent, and the doping height of the P-well layer 4 exceeds the doping height of the heavily doped P layer 8; the cross-sectional widths of two adjacent P-well layers 4 and N-well layers 7 in a single MOS cell are consistent with the cross-sectional width of the gate oxide layer 6, wherein the ohmic contact region of the source 9 and the P-well layer 4 and the N-well layer 7 is transformed from the horizontal direction to the vertical direction. By transforming the source ohmic contact region from the horizontal direction to the vertical direction, the cell size occupied by the source metal in the contact with the N+ source region in the horizontal direction is eliminated, which can greatly reduce the cell size of the device, improve the device current density, and increase the yield of devices with the same performance by more than 20%.

[0053] Example 2

[0054] A double-groove small-size SiC MOSFET device structure includes a drain 1, a source 9, and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer includes an N substrate layer 2, an N-type drift layer 3, a P-well layer 4, a gate 5, a gate oxide layer 6, an N-well layer 7, and a heavily doped P layer 9, wherein the gate oxide layer 6 covers the surface of the gate 5, and the heavily doped P layer 8 is formed into a convex shape by injecting excess ions. The P+ type ion implantation depth exceeds a certain depth of the gate U groove to form a convex shape, which can form an electric field shielding for the gate U groove when the device is blocked, prevent the gate from breaking through, and improve the reliability of the device.

[0055] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A double-trench small-size SiC MOSFET device structure, comprising a drain (1), a source (9) and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises an N substrate layer (2), an N-type drift layer (3), a P well layer (4), a gate (5), a gate oxide layer (6), an N well layer (7) and a heavily doped P layer (9), wherein the gate oxide layer (6) covers the surface of the gate (5), and is characterized in that: The cross-sectional heights of the P-well layer (4) and the N-well layer (7) are consistent, and the doping height of the P-well layer (4) exceeds the doping height of the heavily doped P layer (8); The cross-sectional widths of two adjacent P-well layers (4) and N-well layers (7) in a single MOS cell are consistent with the cross-sectional width of a gate oxide layer (6), wherein the ohmic contact region between the source electrode (9) and the P-well layer (4) and N-well layer (7) is transformed from a horizontal direction to a vertical direction.

2. The double-trench small-size SiC MOSFET device structure according to claim 1, characterized in that: The heavily doped P layer (8) is formed into a convex shape by injecting excess ions.

3. A method for preparing a double-trench small-size SiC MOSFET device structure according to claims 1 and 2, characterized in that: The following steps are involved: S1, SiC substrate selection and epitaxial layer growth, as well as source (9) and drain (1) doping; S2, oxidation growth to form a gate oxide layer (6), and photolithography and patterning; S3, gate (5) metallization; S4, etching and formation of double groove structure; S5, source (9) and drain (1) metallization; S6. Electrical performance testing and packaging.

4. The method for preparing a double-trench small-size SiC MOSFET device structure according to claim 3, characterized in that: In the step S1 of doping the source (9) and the drain (1), doping needs to be performed in the epitaxial layer by ion implantation or diffusion process to form the source (9) and drain (1) regions.

5. The method for preparing a double-trench small-size SiC MOSFET device structure according to claim 3, characterized in that: The step S4 is to etch and form the double groove structure, mainly by etching the source (9) and drain (1) regions of the device through the double groove etching method, and the process requires the use of dry etching to control the groove width and depth.

6. The method for preparing a double-trench small-size SiC MOSFET device structure according to claim 3, characterized in that: In the step S5, metal material is deposited by metal evaporation and sputtering to form source (9) and drain (1) electrodes.

7. The method for preparing a double-trench small-size SiC MOSFET device structure according to claim 1, characterized in that: In step S6, the electrical performance test of the SiC MOSFET device structure includes the turn-on voltage, on-resistance, breakdown voltage of the device, and the total charge required for the SiC MOSFET device to switch from off to on, to determine the electrical performance of the SiC MOSFET device, including: Where, C represents the electrical performance qualification coefficient of SiC MOSFET devices, V G The minimum gate-source voltage required for the SiC MOSFET device to start conducting is V B represents the maximum voltage value that the device can withstand under the drain-source voltage, R represents the resistance between the source (9) and the drain (1) of the SiC MOSFET device in the on state, and Q represents the total charge required for the SiC MOSFET device to switch from off to on.

8. The method for preparing a double-trench small-size SiC MOSFET device structure according to claim 7, characterized in that: When C ≥ 93%, it means that the electrical performance of the tested SiC MOSFET device is excellent; When C ≥ 71%, it means that the electrical performance of the tested SiC MOSFET device is qualified; When C is less than 71%, it indicates that the electrical performance of the detected SiC MOSFET device is unqualified.

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