Buried body diode separation gate SiC MOSFET device and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductor power devices, in particular to a buried body diode separation gate SiC MOSFET device and a manufacturing method thereof, a strip-shaped P + type injection region is formed at the top of a silicon carbide first N-type epitaxial layer, and then a second N-type epitaxial layer is grown; forming a P-type injection region, an N + type injection region and a source contact hole which are vertical to the strip-shaped P + type injection region by using a self-alignment process; further forming a gate oxide layer and separating the gate; further forming a high-K dielectric layer; and further forming a source ohmic contact metal and a source metal electrode, and further forming a back drain metal electrode. According to the invention, the on-resistance is reduced, and the anti-short-circuit capability of the device and the through-current capability of the body diode are improved; key layers all use a self-alignment process, so that the registration deviation is reduced; the separation gate improves the reliability of the gate; and due to the rounded grid vertex angle, the problem of electric field concentration is reduced, and the stability of the device in the production and use process is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and in particular to a buried body diode separated gate SiC MOSFET device and a manufacturing method thereof. Background Art

[0002] The breakdown field strength of silicon carbide can reach 3.5 (MV / cm), which is about 10 times that of silicon. Therefore, the thickness of the drift layer required for withstand voltage is reduced, and it has the characteristics of high withstand voltage, low on-resistance, and low on-thermal resistance. The thermal conductivity of silicon carbide can reach 4.0 (W / cm·K), which is about 3 times that of silicon, and is suitable for high temperature conditions. The saturated electron drift rate of silicon carbide can reach 2.0*10 7 (cm / s), about twice that of silicon, enabling high-frequency applications;

[0003] For traditional silicon carbide MOSFET devices, the P+ type injection region is located on the surface of the N-type silicon carbide epitaxial layer, which occupies area. As the cell size decreases, the planar ohmic contact resistance increases, which is not conducive to reducing the on-resistance. The gate oxide at the bottom of the gate that completely crosses the JFET region is a reliability weak point, and the output and input capacitances are large. The top of the gate is pointed, and there is an electric field concentration problem, which reduces the reliability of the device. During the device manufacturing process, different layers are aligned to the zero layer. This design causes registration deviations between layers, increases the size of the device design, wastes device area, and increases the risk of device use. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a buried body diode separated gate SiC MOSFET device and a manufacturing method to solve the problem of insufficient stability of traditional silicon carbide MOSFET.

[0005] Based on the above purpose, the present invention provides a buried body diode split gate SiC MOSFET device and a manufacturing method thereof. In the first aspect, the present invention provides a buried body diode split gate SiC MOSFET device, comprising an N+ type substrate; a first N-type epitaxial layer, which is located above the N+ type substrate; a P+ type injection region, which is located at the top of the first N-type epitaxial layer and is distributed in a strip shape; a second N-type epitaxial layer, which is located above the first N-type epitaxial layer; a P-type injection region, which is located at the top of the second N-type epitaxial layer and is distributed perpendicular to the P+ injection region; an N+ injection region, which is located at the middle position of the top of the P-type injection region; a source contact hole, which is located at the middle position of the N+ injection region and penetrates into the P+ injection region; An N-type injection region, which is located at the bottom and both sides of the P-type injection region; a gate oxide layer, which is located above the P-type injection region and part of the N+ type injection region and part of the N-type injection region; a gate, which is located above the gate oxide layer; a first high-K dielectric layer, which is located on both sides and above the gate; a source ohmic contact metal, which is located in the source contact hole; a source metal electrode, which is located above the source ohmic contact metal, on both sides and above the first high-K dielectric layer; a drain metal electrode, which is located below the N+ type substrate and forms an ohmic contact with the N+ type substrate.

[0006] The present invention is further configured such that the P+ type injection region is located on the top of the first N-type epitaxial layer and is distributed in a strip shape, with a second N-epitaxial layer thereon, which is a buried layer design.

[0007] The present invention is further configured such that the N+ type injection region and the source contact hole are both formed by a self-alignment process, and there is no alignment deviation between the P-type injection region, the N+ type injection region and the source contact hole.

[0008] The present invention is further configured such that the P-type injection region, the N+ type injection region, and the source contact hole are all distributed perpendicularly to the P+ type injection region without any registration deviation.

[0009] The present invention is further configured such that the P+ type injection region adopts a buried layer design, which can increase the electric field shielding capability of the gate, and the buried layer P+ type injection region distributed perpendicular to the P- type injection region and the N+ type injection region can enhance the current carrying capacity of the body diode and enhance the short circuit resistance of the device.

[0010] The present invention is further configured such that the source contact hole acts as a source current channel, vertically penetrates the N+ type injection area and stops in the P+ type injection area, and the side walls and bottom surface of the hole groove increase the ohmic contact area and reduce the ohmic contact resistance, so the size of the source contact hole can be greatly reduced, the channel density is increased, and the on-resistance is reduced.

[0011] The present invention is further configured such that the N-type injection area is fully opened in the active area for general injection, so there is no alignment deviation between the N-type injection area and the P+ type injection area, the P-type injection area, the N+ type injection area, and the source contact hole.

[0012] The present invention is further configured such that the gate oxide layer is formed by high temperature self-oxidation of silicon carbide and is made of oxide.

[0013] The present invention is further configured such that the gate material in the cell is P-doped polysilicon, which can be obtained by depositing P-doped polysilicon or depositing undoped polysilicon and then injecting P; the gate in the cell is a separated gate, which can improve gate oxide reliability, reduce input and Miller capacitance, and improve device switching speed.

[0014] The present invention is further configured such that the gate adopts a gate double mask etching or self-oxidation method to form a dielectric layer, which can make the top of the gate rounded, reduce the electric field concentration problem, improve the reliability of the gate, and provide a guarantee for further thinning of the first high-K dielectric layer.

[0015] The present invention is further configured such that the first high-K dielectric layer is formed by gate high temperature self-oxidation or self-aligned deposition and etching methods, which can ensure that the two sidewalls of the first high-K dielectric layer are of equal thickness and have no alignment deviation with the gate.

[0016] The present invention is further configured such that the top of the first high-K dielectric layer is rounded by a high-temperature reflow method to make its thickness distribution more uniform, thereby reducing the reliability risk caused by the sharp top angle or thin thickness of the dielectric layer.

[0017] In a second aspect, the present invention provides a method for manufacturing a buried body diode split-gate SiC MOSFET device, the method comprising:

[0018] Step 1:

[0019] The P+ type implantation region is formed by implantation, and then the second N- type epitaxial layer is grown.

[0020] Step 2:

[0021] The P-type implantation region is formed by implantation. Then, the N+ type implantation region is formed by implantation through a self-alignment process, and the source contact hole is formed by etching. Then, the N-type implantation region is formed by implantation.

[0022] Step 3:

[0023] The gate oxide layer is formed by high-temperature self-oxidation. Then, the gate is formed by doping polycrystalline, photolithography, and etching. As in Examples 2 and 3, a double mask layer of photoresist + silicon oxide is used. After the photoresist is developed, silicon oxide is etched to the surface of the polysilicon; then the silicon oxide window is enlarged by wet etching; then the polysilicon is etched. The larger silicon oxide mask window can make the top angle of the polysilicon more easily etched and become rounded by the etching atmosphere. After the gate is formed, the gate oxide layer in the source contact hole is removed by photolithography and isotropic etching.

[0024] Step 4:

[0025] The first high-K dielectric layer is formed by high-temperature self-oxidation of the gate. The photoresist can also be removed after the gate is etched, and the silicon oxide mask is retained as the first high-K dielectric layer on the top of the gate; then the high-temperature polysilicon is self-oxidized to form the gate top corner and sidewall dielectric layer; then the dielectric layer top corner is rounded by reflow. The photoresist can also be removed after the gate is etched, and the silicon oxide mask is retained as the first high-K dielectric layer on the top of the gate; then silicon oxide is deposited to form the gate top corner and sidewall dielectric layer; then the dielectric layer top corner is rounded by reflow; and then the excess silicon oxide between the sidewalls of the dielectric layer is etched away.

[0026] Step 5:

[0027] Annealing forms the source ohmic contact metal. Then etching forms the source metal electrode. Then metal evaporation forms the back drain metal electrode.

[0028] Beneficial effects of the present invention: In the buried body diode separated gate SiC MOSFET device of the present invention, the P+ type injection region in the active region adopts a strip buried layer design perpendicular to the channel, which saves the area of ​​the P+ source region and increases the short circuit resistance and the current flow capacity of the body diode of the device; both side walls and the bottom of the three-dimensional source contact hole can form ohmic contacts, which reduces the ohmic contact resistance, is conducive to reducing the cell size, improving the channel density, and reducing the on-resistance; the design of the separated gate reduces the reliability risk of the gate oxide layer under the gate, and can reduce the input and Miller capacitances, and improve the switching speed of the device; in the process of double mask etching and self-oxidation of the gate to form a dielectric layer, the top angle of the gate can be rounded, the problem of electric field concentration is reduced, and the reliability of the device is improved; except for the one-time overlay of the gate to the P-type injection region, the remaining key steps all adopt a self-alignment process, which reduces the inter-layer overlay deviation and improves the stability of the device during production and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 (a) is a schematic diagram of the 3D structure of the device in the present invention;

[0031] Figure 1 (b) is a schematic diagram of the cross-sectional cell structure along line AA' in the present invention;

[0032] Figure 1 (c) is a schematic diagram of the cross-sectional cell structure along line BB' in the present invention;

[0033] Figure 2 It is a schematic structural diagram of an N+ type substrate and a first N- type epitaxial layer in the present invention;

[0034] Figure 3 It is a schematic diagram of the structure of the P+ type injection region in the present invention;

[0035] Figure 4 is a schematic structural diagram of the second N-type epitaxial layer in the present invention;

[0036] Figure 5 It is a schematic diagram of the structure of the P-type injection region in the present invention;

[0037] Figure 6 It is a schematic diagram of the structure of the N+ type implantation region in the present invention;

[0038] Figure 7 is a schematic structural diagram of the source contact hole in the present invention;

[0039] Figure 8 It is a schematic diagram of the structure of the N-type implantation region in the present invention;

[0040] Fig. 9 is a schematic diagram of the structure of the gate oxide layer in the present invention;

[0041] Fig.10 It is a schematic diagram of the structure of the gate in the present invention;

[0042] Fig.11 is a schematic structural diagram of the first high-K dielectric layer in the present invention;

[0043] Fig.12 It is a schematic diagram of the structure of the source ohmic contact metal in the present invention;

[0044] Fig.13 It is a schematic diagram of the structure of the source metal electrode in the present invention;

[0045] Fig.14 It is a schematic diagram of the structure of the drain metal electrode in the present invention;

[0046] In the figure: 1. N+ type substrate; 2. first N- type epitaxial layer; 3. P+ type injection region; 4. second N- type epitaxial layer; 5. P- type injection region; 6. N+ type injection region; 7. source contact hole; 8. N- type injection region; 9. gate oxide layer; 10. gate; 11. first high-K dielectric layer; 12. source ohmic contact metal; 13. source metal electrode; 14. drain metal electrode. DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0048] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0049] Example 1

[0050] Figure 1 (a) Figure 1 (b) with Figure 1(c) shows an embodiment, which comprises: an N+ type substrate 1; a first N-type epitaxial layer 2, which is located above the N+ type substrate; a P+ type injection region 3, which is located at the top of the first N-type epitaxial layer and is distributed in a strip shape; a second N-type epitaxial layer 4, which is located above the first N-type epitaxial layer; a P-type injection region 5, which is located at the top of the second N-type epitaxial layer and is perpendicular to the P+ type injection region; an N+ type injection region 6, which is located at the middle position of the top of the P-type injection region; a source contact hole 7, which is located at the middle position of the N+ type injection region and penetrates into the P+ type injection region; An N-type injection region 8 is located at the bottom and both sides of the P-type injection region; a gate oxide layer 9 is located above the P-type injection region and part of the N+ type injection region and the N-type injection region; a gate electrode 10 is located above the gate oxide layer; a first high-K dielectric layer 11 is located on both sides and above the gate electrode; a source ohmic contact metal 12 is located in the source contact hole; a source metal electrode 13 is located above the source ohmic contact metal and on both sides and above the first high-K dielectric layer; a drain metal electrode 14 is located below the N+ type substrate and forms an ohmic contact with the N+ type substrate.

[0051] exist Figure 2 In the embodiment shown, a first N-type epitaxial layer 2 is grown on an N+ type substrate 1, the substrate thickness is 100-500 um, and the substrate concentration is 1*10 18 -1*10 20 / cm 3 , the epitaxial layer is grown by nitrogen doping, with a thickness of 1-50um and a concentration of 1*10 14 -1*10 19 / cm 3 .

[0052] exist Figure 3 In the embodiment shown, the P+ type injection region 3 is formed by mask deposition, photolithography, etching, injection, and mask removal. The P+ type injection region is arranged in parallel in a strip shape. The mask material is generally an oxide layer. The mask thickness is determined by the type, energy, and dose of the injected element. The spin-coated photoresist is exposed and developed, and the injection area is defined by etching. Al is injected at a high temperature of 200-500°C. The doping concentration of the P+ type injection region is about 1*10 18 -1*10 19 / cm 3 , depth 0.3-0.6um.

[0053] exist Figure 4 In the embodiment shown, the second N-type epitaxial layer 4 is formed by nitrogen doping growth, with a thickness of 0.2-0.4 um and a concentration of 1*10 14 -1*10 19 / cm 3 .

[0054] exist Figure 5 In the embodiment shown, the P-type implantation region 5 is formed by mask deposition, photolithography, etching, and implantation. The mask material is generally an oxide layer. The mask thickness is determined by the type, energy, and dose of the implanted element. The spin-coated photoresist is exposed and developed, and the implantation area is defined by etching. The P-type implantation region is perpendicular to the buried layer P+ type implantation region, and there is no registration deviation. Al is implanted at a high temperature of 200-500°C. The doping concentration of the P-type implantation region is about 5*10 16 -5*10 17 / cm 3 , depth 0.5-1.2um.

[0055] exist Figure 6 In the embodiment shown, the N+ type implantation region 6 is formed by mask deposition, etching, and implantation. The mask material is generally an oxide layer. The area to be implanted is defined by etching. Since the self-alignment process is adopted, there is no registration deviation. N or P is implanted at a high temperature of 200-500°C. The doping concentration of the N+ type implantation region is about 1*10 18 -1*10 19 / cm 3 , depth 0.2-0.4um.

[0056] exist Figure 7 In the embodiment shown, the source contact hole 7 is formed by mask deposition, mask etching, source contact hole etching, and mask removal. The mask material is generally an oxide layer. The area to be etched for the source contact hole is defined by mask etching. Since the self-alignment process is adopted, there is no alignment deviation between the source contact hole and the previously formed P+ type injection area, P- type injection area, and N+ type injection area, and the hole depth is 0.3-0.8um. ​​The source contact hole acts as a source current channel, vertically penetrates the N+ type injection area and stops in the P+ type injection area. The vertically distributed sidewalls and bottom surface increase the ohmic contact area and reduce the ohmic contact resistance. Therefore, the size of the source contact hole can be greatly reduced, and the width can be 0.1-2um, which can reduce the device area, increase the channel density, and reduce the on-resistance.

[0057] In the embodiment shown in FIG8 , the N-type implantation region 8 is formed by mask deposition, photolithography, etching, implantation, and mask removal. The mask material is generally an oxide layer. The mask thickness is determined by the type, energy, and dose of the implanted element. The spin-coated photoresist is exposed and developed, and the implantation area is defined by etching. The active area is fully opened for general implantation, so there is no registration deviation. The doping concentration is about 5*10 15 -2*10 16 / cm 3 , depth 0.5-2um.

[0058] exist Fig. 9In the embodiment shown, the oxide layer 9 is formed by high-temperature self-oxidation of silicon carbide, and the oxidation temperature is generally between 1200-1400°C. After the oxide layer growth is completed, N-doping annealing is performed to reduce the interface state density, improve the carrier mobility, and thereby reduce the channel resistance. The thickness is 10-100nm.

[0059] exist Fig.10 In the implementation method, the gate 10 is formed by P-doped polycrystalline deposition or undoped polycrystalline deposition plus P implantation, photolithography, and etching. The gate thickness is 0.2-1.0um. The gate oxide layer 9 in the source contact hole is further removed by photolithography and isotropic etching. The gate in the cell is a separated gate. The distance between the separated gates is 0.2-1.0um. The separated gate can improve the gate oxide reliability, reduce the input and Miller capacitance, and improve the switching speed of the device.

[0060] exist Fig.11 In the implementation method, the first high-K dielectric layer 11 is formed by high-temperature self-oxidation of the gate, the oxidation temperature is 800-1200°C, the material is silicon oxide, and the thickness is 0.1-0.5um. Due to the self-oxidation process, the two side walls and the top thickness of the first high-K dielectric layer are equal, there is no registration deviation, and the contact area between the gate top angle and the oxidizing atmosphere is large, and more polysilicon is consumed, which can achieve the effect of rounding the polysilicon top angle. The rounded polysilicon top angle can reduce the electric field concentration here, improve the reliability of the device, and provide a guarantee for further thinning of the dielectric layer.

[0061] exist Fig.12 In the implementation method, the source ohmic contact metal 12 is formed by metal deposition, rapid thermal annealing (RTA), and metal stripping on the dielectric layer. The material is nickel silicide with a thickness of 50-500nm. The source ohmic contact metal is distributed on the sidewall and bottom surface of the source contact hole, which increases the ohmic contact area and reduces the ohmic contact resistance.

[0062] exist Fig.13 In the embodiment shown, the source metal electrode 13 is formed by metal deposition, photolithography, and etching. The material is titanium nitride titanium aluminum or titanium nitride titanium aluminum copper or titanium nitride titanium aluminum silicon copper. The metal thickness is titanium 10-500nm, titanium nitride 10-200nm, aluminum or aluminum copper or aluminum silicon copper 1-8um. The spin-coated photoresist is exposed and developed, and the metal PAD coverage area is defined by etching.

[0063] exist Fig.14In the embodiment shown, the drain metal electrode 14 is formed by thinning the back side of a silicon carbide wafer, evaporating an ohmic contact metal, annealing, and evaporating a drain metal. The material is nickel silicide titanium nickel silver, with a thickness of nickel silicide of 50-500nm, titanium of 0.1-2um, nickel of 0.1-1.5um, and silver of 0.5-3um. Thinning can reduce the thickness of the N+ substrate, reduce the forward on-resistance and heat generation, and the thin chip thickness is also beneficial to reducing the volume of subsequent packaged devices. Annealing generally adopts laser annealing or rapid thermal annealing (RTA) to form an ohmic contact area on the back side of the chip and reduce the forward on-resistance.

[0064] Example 2

[0065] This embodiment provides a buried body diode separated gate SiC MOSFET device and a manufacturing method thereof. The same points as those in Embodiment 1 are not described here one by one. The difference is that:

[0066] When etching to form the gate 10, a silicon oxide mask layer is added with a thickness of 0.1-0.5um. After the photoresist forms a window, the silicon oxide is first etched until the polysilicon surface; the silicon oxide window is further enlarged by wet etching; the polysilicon is further etched through the photoresist and silicon oxide mask window. Since the silicon oxide mask window is larger, the polysilicon top angle is more likely to react with the etching atmosphere, and a rounded polysilicon top angle is easily formed; the photoresist is further removed, and the silicon oxide mask is retained as the top of the gate. A high-K dielectric layer 11; further removing the gate oxide layer 9 in the source contact hole by photolithography and isotropic etching; further forming the gate vertex angle and the sidewall dielectric layer by high-temperature polysilicon self-oxidation, the oxidation temperature is 800-1200°C, and the polysilicon vertex angle can be further rounded due to the large contact area between the polysilicon vertex angle and the oxidizing atmosphere; further reflowing to round the dielectric layer vertex angle, the reflow temperature is 900-1100°C; further forming an ohmic contact metal, a source metal electrode, and a drain metal electrode.

[0067] Example 3

[0068] This embodiment provides a buried body diode separated gate SiC MOSFET device and a manufacturing method thereof. The same points as those in Embodiment 1 are not described here one by one. The difference is that:

[0069] When etching to form the gate 10, a silicon oxide mask layer is added with a thickness of 0.1-0.5um. After the photoresist forms a window, the silicon oxide is etched for the first time until the polysilicon surface; the silicon oxide window is further enlarged by wet back etching; the polysilicon is further etched through the photoresist and silicon oxide mask window. Since the silicon oxide mask window is larger, the polysilicon top angle and the etching atmosphere are more likely to react with each other, and it is easy to form a rounded polysilicon top angle; the photoresist is further removed, and the silicon oxide mask is retained as the first high-K dielectric layer 11 on the top of the gate; the gate oxide layer 9 in the source contact hole is further removed by photolithography and isotropic etching; silicon oxide is further deposited to form a gate top angle and a sidewall dielectric layer with a thickness of 0.1-0.5um; the top angle of the dielectric layer is further rounded by reflow, and the reflow temperature is 900-1100°C; the excess silicon oxide between the side walls of the dielectric layer is further etched away; and an ohmic contact metal, a source metal electrode, and a drain metal electrode are further formed.

[0070] Those skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present invention is limited to these examples; under the concept of the present invention, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity. Any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A buried body diode split-gate SiC MOSFET device, comprising an N+ type substrate (1), characterized in that: Also includes: A first N-type epitaxial layer (2) located above the N+ type substrate (1); a P+ type injection region (3) located at the top of the first N-type epitaxial layer (2) and distributed in a strip shape; a second N-type epitaxial layer (4) located above the first N-type epitaxial layer (2); a P-type injection region (5) located at the top of the second N-type epitaxial layer (2) and distributed perpendicular to the P+ type injection region (3); an N+ type injection region (6) located at the middle of the top of the P-type injection region (5); a source contact hole (7) located at the middle of the N+ type injection region (6) and penetrating into the P+ type injection region (3); an N-type injection region (8) located at the top of the P-type injection region (5); and a source contact hole (9) located at the middle of the N+ type injection region (6) and penetrating into the P+ type injection region (3). The invention relates to a P-type implantation region (5) at the bottom and both sides thereof; a gate oxide layer (9) located above the P-type implantation region (5) and a portion of the N+ type implantation region (6) and a portion of the N-type implantation region (8); a gate electrode (10) located above the gate oxide layer (9); a first high-K dielectric layer (11) located on both sides and above the gate electrode (10); a source ohmic contact metal (12) located in the source contact hole (7); a source metal electrode (13) located above the source ohmic contact metal (12) and on both sides and above the first high-K dielectric layer (11); and a drain metal electrode (14) located below the N+ type substrate (1) and forming an ohmic contact with the N+ type substrate.

2. The buried body diode split-gate SiC MOSFET device according to claim 1, characterized in that: The P+ type injection region (3) is located on the top of the first N-type epitaxial layer (2) and is distributed in a strip shape, and a second N-type epitaxial layer (4) is disposed thereon and is designed as a buried layer.

3. A buried body diode split-gate SiC MOSFET device according to claim 1, characterized in that: The N+ type injection region (6) and the source contact hole (7) are both formed by a self-alignment process, and there is no alignment deviation between the P-type injection region (5), the N+ type injection region (6) and the source contact hole (7).

4. A buried body diode split-gate SiC MOSFET device according to claim 1, characterized in that: The P-type injection region (5), the N+ type injection region (6) and the source contact hole (7) are all distributed perpendicularly to the P+ type injection region (3) without any registration deviation.

5. The buried body diode split gate SiC MOSFET device according to claim 1, characterized in that: The source contact hole (7) acts as a source current channel, vertically penetrates the N+ type injection area (6) and stops in the P+ type injection area (3).

6. A buried body diode split-gate SiC MOSFET device according to claim 1, characterized in that: The N-type injection region (8) is completely opened in the active region for general injection, so there is no alignment deviation between the N-type injection region (8) and the P+ type injection region (3), the P-type injection region (5), the N+ type injection region (6), and the source contact hole (7).

7. The buried body diode split gate SiC MOSFET device according to claim 1, characterized in that: The gate oxide layer (9) is formed by high-temperature self-oxidation of silicon carbide and is made of oxide; The gate (10) in the unit cell is made of P-doped polysilicon, which is obtained by depositing P-doped polysilicon or depositing undoped polysilicon and then implanting P. The gate top angle is rounded by using a gate double mask etching or self-oxidation method to form a dielectric layer. The gate (10) in the unit cell is a separated gate.

8. The buried body diode split gate SiC MOSFET device according to claim 1, characterized in that: The first high-K dielectric layer (11) is formed by gate high-temperature self-oxidation or self-aligned deposition etching, and its top is rounded by high-temperature reflow to make its thickness distribution more uniform.

9. A method for manufacturing a buried body diode split-gate SiC MOSFET device according to any one of claims 1 to 8, characterized in that: The method comprises: Step 1: Implanting to form a P+ type implantation region (3), and then growing to form a second N-type epitaxial layer (4); Step 2: Implanting to form a P-type implantation region (5), then implanting to form an N+ type implantation region (6) through a self-alignment process, etching to form a source contact hole (7), and then implanting to form an N-type implantation region (8); Step 3: A gate oxide layer (9) is formed by high-temperature self-oxidation, and then a gate (10) is formed by doping polycrystalline, photolithography, and etching, or a photoresist + silicon oxide double mask layer is used. After the photoresist is developed, silicon oxide is etched to the surface of the polycrystalline silicon; then the silicon oxide window is enlarged by wet etching; then the polycrystalline silicon is etched to form the gate (10), and then the gate oxide layer (9) in the source contact hole is removed by photolithography and isotropic etching; Step 4: The first high-K dielectric layer (11) is formed by high-temperature self-oxidation of the gate (10), or the photoresist is removed after the gate is etched, and the silicon oxide mask is retained as the first high-K dielectric layer (11) on the top of the gate; then the high-temperature polysilicon is self-oxidized to form the gate top angle and side wall dielectric layer; then the top angle of the dielectric layer is rounded by reflow, or the photoresist is removed after the gate is etched, and the silicon oxide mask is retained as the first high-K dielectric layer (11) on the top of the gate; then silicon oxide is deposited to form the gate top angle and side wall dielectric layer; then the top angle of the dielectric layer is rounded by reflow; and then the excess silicon oxide between the side walls of the dielectric layer is etched away; Step 5: Annealing is performed to form a source ohmic contact metal (12), then etching is performed to form a source metal electrode (13), and then metal evaporation is performed to form a back drain metal electrode (14).

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