Packaging structure and packaging method of third-generation semiconductor chip

Abstract

The invention discloses a packaging structure and a packaging method of a third-generation semiconductor chip, and the packaging structure comprises a frame carrier, a silicon-based chip, a gallium nitride chip or a silicon carbide chip, a ceramic substrate and / or a capacitor. Through the packaging method, the packaging technology requirements of high performance and high reliability are met after packaging, the stability and durability of the device are improved, and it is ensured that the device can still work stably in a high-voltage environment. The gallium nitride (GaN) hybrid packaging device can consume less energy in the using process, so that the overall energy consumption is reduced, meanwhile, due to the highly-integrated circuit design, the number of components is reduced, the debugging process is quicker and more convenient, and the cost optimization is remarkably achieved. The silicon carbide (SiC) mixed packaging device has the characteristics of high pressure resistance and high temperature resistance, so that the device can work stably in a hostile environment, the overall reliability is improved, the service life is prolonged, and the silicon carbide mixed packaging device has a wide application prospect in the fields of new energy automobiles, photovoltaic power generation and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of hybrid packaging of power device chips, and in particular to combined packaging of third-generation semiconductor chips with silicon-based chips, ceramic substrates, and the like. Background Art

[0002] As a core component of the electronic industry chain, the development of power devices is not only closely related to technological progress, but also inseparable from the continuous expansion of market demand. The third-generation semiconductor chips are chips manufactured based on the third-generation semiconductor materials (also known as wide-bandgap semiconductor materials), which mainly include silicon carbide (SiC) and gallium nitride (GaN). The emergence of third-generation wide-bandgap semiconductor materials such as silicon carbide and gallium nitride provides power devices with higher voltage and high temperature resistance, as well as lower on-resistance and faster switching speed.

[0003] With the development of packaging technology, power devices have also evolved towards low impedance, high power, and high frequency characteristics. Traditional packaging technology has been unable to meet the requirements of fast switching characteristics and reliability under high temperature operation, which has prompted the innovation and development of packaging technology. At the same time, in order to improve the performance and reliability of power devices, the manufacturing process is also being optimized, such as the use of environmentally friendly materials such as halogen-free and antimony oxide, and the use of special materials and processes such as roughening or spraying. Driven by market demand, the rise of new energy vehicles, and the significant increase in demand for power semiconductors in new energy vehicles, power devices have been driven towards high efficiency and high stability.

[0004] With the continuous advancement of power electronics technology, the performance requirements for power devices are getting higher and higher. The traditional single material packaging method can no longer meet the needs of modern power electronics systems. Therefore, a new hybrid packaging technology is needed to integrate the excellent properties of different materials and improve the overall performance of power devices. Summary of the invention

[0005] In response to the above-mentioned problems, the present invention aims to provide a packaging structure and packaging method for a third-generation semiconductor chip, which provides two processes: side-by-side packaging and stacked packaging. At the same time, laser grooving technology and special spraying process materials are used to achieve high-performance and high-reliability packaging technology requirements, thereby improving the stability and durability of the device and ensuring that it can still work stably under high-voltage environments.

[0006] In order to achieve the above-mentioned object, the technical solution adopted by the present invention is as follows: a packaging structure of a third-generation semiconductor chip, including a frame carrier, a silicon-based chip and a gallium nitride chip or a silicon carbide chip thereof, and also including a ceramic substrate and / or a capacitor;

[0007] The silicon-based chip, a gallium nitride chip or a silicon carbide chip are arranged and bonded together on the frame carrier;

[0008] Or a gallium nitride chip or a silicon carbide chip is arranged and bonded with a ceramic substrate on a frame carrier, and a silicon-based chip is bonded on the ceramic substrate;

[0009] Alternatively, a gallium nitride chip or a silicon carbide chip is arranged and bonded to a ceramic substrate on a frame carrier, and a capacitor and a silicon-based chip are arranged and bonded to the ceramic substrate.

[0010] Preferably, the bonding material between the frame carrier and the silicon-based chip, a gallium nitride chip or a silicon carbide chip, and the ceramic substrate is one or more of soft solder, conductive glue, insulating glue or nano-sintered silver.

[0011] Preferably, the welding materials between the silicon-based chip, a gallium nitride chip or a silicon carbide chip, the ceramic substrate and the capacitor are one or more of aluminum wire, gold-copper wire or gold-palladium-copper wire.

[0012] A packaging method for a third-generation semiconductor chip packaging structure, wherein the semiconductor chip includes a silicon-based chip, a gallium nitride chip or a silicon carbide chip, and the semiconductor chip also includes a ceramic substrate and / or a capacitor. The packaging method mainly includes the following steps:

[0013] S1. Laser slotting: slotting is performed by laser after thinning and back-metal processing;

[0014] S2, dicing: dicing the laser-grooved semiconductor wafer into individual chips;

[0015] S3, chip loading: arranging or stacking the diced single chips and bonding them on the frame carrier;

[0016] S4, plasma cleaning: plasma cleaning the chip after core baking;

[0017] S5, pressure welding: bonding the plasma cleaned semiconductor chips using metal bonding wires to form electrical connections;

[0018] S6, plasma cleaning: plasma cleaning the semiconductor chip after pressure welding;

[0019] S7, Glue spraying: Spray glue on the semiconductor chip after plasma cleaning to form a uniform film on the frame carrier, pins and chip surface.

[0020] Preferably, the silicon-based chip, a gallium nitride chip or a silicon carbide chip are arranged and bonded together on the frame carrier;

[0021] Or a gallium nitride chip or a silicon carbide chip is arranged and bonded with a ceramic substrate on a frame carrier, and a silicon-based chip is bonded on the ceramic substrate;

[0022] Alternatively, a gallium nitride chip or a silicon carbide chip is arranged and bonded to a ceramic substrate on a frame carrier, and a capacitor and a silicon-based chip are arranged and bonded to the ceramic substrate.

[0023] Preferably, the bonding material between the frame carrier and the silicon-based chip, a gallium nitride chip or a silicon carbide chip, and the ceramic substrate is one or more of soft solder, conductive glue, insulating glue or nano-sintered silver.

[0024] Preferably, the welding materials between the silicon-based chip, a gallium nitride chip or a silicon carbide chip, the ceramic substrate and the capacitor are one or more of aluminum wire, gold-copper wire or gold-palladium-copper wire.

[0025] The beneficial effects of the present invention are as follows: according to the characteristics and application fields of the products, adhesive materials and metal wires with different properties are selected for electrical connection, and laser grooving technology and special spraying materials and processes are used (such as AP8000 adhesion promoter spraying for gallium nitride (GaN) products, the baking temperature after spraying is 70°C, and the baking time is 3 minutes; GC-3688 adhesion promoter spraying for silicon carbide (SiC) products, without baking) to achieve high-performance and high-reliability packaging technology requirements, improve the stability and durability of the device, and ensure that it can still work stably under high-voltage environment.

[0026] Gallium nitride (GaN) hybrid packaged devices can consume less energy during use (packaged devices can achieve higher energy conversion efficiency, reduce power loss, and have fast switching speeds, thereby reducing switching losses and energy consumption), thereby reducing overall energy consumption. At the same time, the highly integrated circuit design (by integrating multiple devices in one package, the number of peripheral devices is greatly reduced, simplifying the circuit design) reduces the number of components, making the debugging process faster and more convenient, and plays a significant role in cost optimization.

[0027] Silicon carbide (SiC) hybrid packaging devices have the characteristics of high voltage and high temperature resistance (such as attached Fig.12 The reliability assessment results are shown in the figure. It can pass HTRB 1000 hours and HTGB 1000 hours, so that the device can maintain stable operation in harsh environments, improve the overall reliability and life, and show broad application prospects in new energy vehicles, photovoltaic power generation and other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a diagram of the chip side-by-side packaging structure of the present invention.

[0029] Figure 2 This is a diagram of the chip stacking package structure of the present invention.

[0030] Figure 3This is a plan view of the side-by-side packaging of chips of the present invention.

[0031] Figure 4 This is a plan view of the chip stacking package of the present invention.

[0032] Figure 5 This is a process flow chart of the gallium nitride (GaN) hybrid packaging technology of the present invention.

[0033] Figure 6 This is a process flow chart of the silicon carbide (SiC) hybrid packaging technology of the present invention.

[0034] Figure 7 This is a rendering of the key technology effect of laser grooving of gallium nitride (GaN) wafers in the present invention.

[0035] Figure 8 It is a schematic diagram of the bonding process of BBOS and BSOB of the present invention.

[0036] Fig. 9 This is a diagram showing the phenomenon of third-generation chips being prone to breakage after bonding.

[0037] Fig.10 The figure shows that there is no delamination between the third-generation chip and the plastic packaging material, between the chip and the glue layer, and between the glue layer and the frame carrier after packaging of the present invention.

[0038] Fig.11 This is a diagram illustrating the laser grooving process of the present invention.

[0039] Fig.12 This is the reliability assessment result of the 1200V product of the present invention.

[0040] In the figure: 1-bonding wire; 2-lead frame pin; 3-frame carrier; 4-gallium nitride chip; 5-silicon-based chip; 6-ceramic substrate; 7-capacitor; 8-silicon carbide chip. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0042] See attached Figures 1 to 8 The packaging structure of a third-generation semiconductor chip shown in the figure includes a frame carrier 3, a silicon-based chip 5 and a gallium nitride chip 4 or a silicon carbide chip 8, and also includes a ceramic substrate 6 and / or a capacitor 7, wherein the ceramic substrate 6 is mainly an aluminum oxide (Al2O3) ceramic substrate, and the main function of the ceramic substrate 6 is the switching application of the circuit connection of the external component; while the capacitor increases the reliability of the component comparison product. The packaging structure has two processes: side-by-side packaging and stacked packaging. The side-by-side packaging process structure Figure 1 , Figure 3As shown, one of the chips is a gallium nitride chip 4 or a silicon carbide chip 8, and the other is a silicon-based chip 5. On the surface of the lead frame, soft solder, conductive glue, insulating glue or nano-sintered silver bonding materials are used to bond the chips in sequence. The bonding sequence is: first bond the chip using high-temperature materials or a chip with a higher baking curve temperature, and then bond the chip using low-temperature materials or a chip with a lower baking curve temperature.

[0043] Figure 1 As shown, after the chip bonding is completed, according to the characteristics and application fields of the product, aluminum wire, gold copper wire or gold palladium copper wire with excellent electrical properties is selected to form precise electrical welding between the chip and the lead frame pin 2 and between the chips.

[0044] The stacked packaging process structure includes one chip being a gallium nitride chip 4 or a silicon carbide chip 8 and the other being a silicon-based chip 5, or a ceramic substrate 6 and a capacitor 7 are added.

[0045] Figure 2 Middle a and Figure 4 As shown, in a product that does not use a ceramic substrate 6, the silicon carbide chip 8 and the silicon-based chip 5 can also be directly stacked, and the process structure is to first bond the silicon carbide chip 8 and then bond the silicon-based chip 5.

[0046] Figure 2 Middle b and Figure 4 As shown, on the surface of the heat dissipation substrate, the ceramic substrate 6 is first fixed on the heat dissipation substrate using soft solder or nano-sintered silver, and then the gallium nitride chip 4 or the silicon carbide chip 8 is bonded to the other side of the ceramic substrate 6, and finally the silicon-based chip 5 stacked on the ceramic substrate 6 is bonded.

[0047] After the three or two chips are stacked and bonded, appropriate metal wires (such as aluminum wire, gold-copper wire or gold-palladium-copper wire) are selected to form precise electrical welding between the chip and the lead frame pin 2, between the chip and the lead frame carrier 3, and between the chip and the ceramic substrate 6. The advantages of the gallium nitride chip 4 and the power chip, the silicon carbide chip 8 and the silicon-based chip 5 and the ceramic substrate 6 can be effectively combined, and precise electrical connections are made using aluminum wire, gold-copper wire, and gold-palladium-copper wire to achieve efficient thermal management and excellent electrical performance.

[0048] Based on the above packaging structure, the present invention also provides a packaging method for a third-generation semiconductor chip packaging structure, comprising the following steps:

[0049] 1) Thinning process: Gallium nitride (GaN) wafers are relatively brittle, and the initial thickness of the wafer is generally 1000um. The back of the wafer needs to be thinned before packaging. The back thinning adopts the In-Feed grinding method to thin the gallium nitride (GaN) wafer to 250-300um to improve the chip's thermal diffusion efficiency, electrical properties, mechanical properties, etc. Silicon carbide (SiC) wafers are relatively hard, and the wafer thickness is generally between 150-250um, so no thinning process is required.

[0050] 2) Back-gold process: According to the characteristics of the bonding material, the back of the GaN wafer using soft solder or nano-sintered silver bonding will have micro-damage after thinning. In order to eliminate the damage and further roughen it, and provide a good evaporation environment for the back metal, the back of the wafer needs to be chemically corroded. After the etching, there is residual moisture on the surface of the wafer after cleaning, which needs to be dehydrated with isopropyl alcohol and dried with nitrogen. Back-gold uses an electron beam to generate high temperature (up to 1000°C) to evaporate the metal, so that the metal atoms move linearly in a vacuum and deposit on the wafer to achieve back-metallization of the wafer. At present, the back-gold materials of GaN wafers are generally titanium (Ti), nickel (Ni) and silver (Ag), and the evaporation order is titanium (Ti) -> nickel (Ni) -> silver (Ag).

[0051] 3) Laser grooving process: After the thinned back-gold GaN wafer is made, in order to reduce the cutting stress and the risk of chip edge collapse before dicing, the laser grooving process is used to first groove through the GaN layer in the wafer scribe line, and then mechanical cutting is performed with a blade. Fig.11 As shown, this distributed dicing technology greatly improves the yield of chip cutting.

[0052] 4) Slicing process: The laser-grooved GaN wafer is not cut into individual chips. After grooving, a conventional scriber is used to cut in the middle of the scribe groove. Since the GaN layer has been penetrated, the cutting stress is reduced during the slicing process, which improves the chip cutting yield. However, due to its high Mohs hardness, the slicing process of silicon carbide (SiC) wafers is more difficult. Compared with traditional diamond mechanical slicing, ultrasonic slicing technology uses ultrasonic high-frequency oscillation to reduce the sawing force during the slicing process, thereby greatly reducing the back collapse abnormality of silicon carbide (SiC) wafers, and at the same time increasing the UPH by 10 times, as shown in Table 1 below:

[0053] Table 1

[0054]

[0055] 5) Core bonding process: After dicing, the GaN chip 4 and the SiC chip 8 are bonded during the packaging process using nano-sintered silver with high thermal conductivity, conductive glue or soft solder to maintain good thermal contact. Figure 1 , Figure 3 As shown, in the side-by-side packaging structure, the gallium nitride chip 4 and the silicon-based chip 5 are bonded in parallel. The gallium nitride chip 4 generally uses nano-sintered silver or conductive glue as the bonding material, and the silicon-based chip 5 generally uses insulating adhesive to play a role in controlling the drive.

[0056] Figure 2 , Figure 4 As shown, in the stacked packaging structure, the gallium nitride chip 4 can be mixed with the ceramic substrate 6, the capacitor 7, and the silicon-based chip 5 for packaging. The bonding method is to first bond and fix the ceramic substrate 6 on the lead frame, and then bond the gallium nitride chip 4 or the silicon carbide chip 8 on the other side of the substrate, and then stack the capacitor 7 or the silicon-based chip 5 on the ceramic substrate 6. The chips stacked on top need to strictly control the overflow of the adhesive material, so nano-sintered silver is often used as the adhesive material for the silicon-based chip 5. Chips using nano-sintered silver, conductive glue and insulating adhesive need to be baked in an oven after bonding to fix the position of the chip. Different adhesive materials have different baking curves. If different adhesive materials are used for the same product, they need to be baked in sequence after bonding before continuing to bond the next chip.

[0057] 6) Plasma cleaning process: The products after core baking need to be plasma cleaned before pressure welding, which removes the organic solvents volatilized by various adhesive materials during the baking process and remains on the chip surface. The chip after plasma cleaning can greatly improve the bonding strength in the next pressure welding process.

[0058] 7) Compression welding process: In the third-generation semiconductor hybrid packaging technology, the selection of metal wires and the debugging of bonding parameters are extremely important. There are differences in the physical properties and flexibility of different metal wires, resulting in different welding strengths between the bonding wire 1 and the chip and substrate. The gallium nitride chip 4 is more sensitive to temperature and packaging stress due to its relatively brittle material, and chip cracks are a common packaging technology problem. For the hybrid packaging of gallium nitride chip 4, gold-copper wire or gold-palladium-copper wire is selected as the welding material, and gold-palladium-copper wire is used as the bonding wire 1. Its flexibility is better than copper wire, which can effectively overcome the abnormal chip cracks caused by packaging stress. The price is lower than that of gold-copper wire, making it the preferred material in terms of material selection.

[0059] During the welding process, in order to ensure the reliability of metal wire welding, the wire bonding 1 between the chip and the lead frame pin 2 and between the chips can be welded by BSOB or BBOS ( Figure 8As shown). For the hybrid packaging of silicon carbide chip 8, aluminum wire is selected as the welding material. In the stacking process, the chip and the ceramic substrate 6 are connected by aluminum wire bonding, and the ceramic substrate 6 is used as the second welding point. It is necessary to use a back cutter and an "eight" wire bonding method to prevent the chip from being cut when the cutter cuts the wire.

[0060] 8) Crater test: Crater test is an effective means to quickly detect cracks after bonding. Different solutions and ratios are used for wafers of different materials. For example, for GaN chip 4 with copper-nickel-gold (CuNiAu) RDL surface metal, aqua regia and hydrogen peroxide solution are used to remove the coating on the chip surface; for non-RDL GaN chip 4 with aluminum-copper (AlCu) surface metal, pure phosphoric acid is used to remove the coating on the chip surface.

[0061] 9) Glue spraying process: In order to enhance the mechanical stability and environmental tolerance of the package, the third-generation semiconductor hybrid packaging technology uses a special packaging material coating technology, the glue spraying process, which mainly coats a layer of adhesion promoter on the surface of the chip, carrier and pin after pressure welding to form a uniform film, thereby increasing the bonding force between the chip and the epoxy molding compound and the frame or substrate. All glue spraying products need to be plasma cleaned before processing to remove contamination and oxidation on the surface of the chip and frame.

[0062] For the hybrid packaging process of gallium nitride chips 4, for products using silver-plated base materials, AP8000 adhesion promoter can effectively isolate the silver-plated surface from the epoxy molding compound, and enhance the adhesion between the epoxy molding compound and the frame and the chip. The spray glue material needs to be baked after spraying, and the baking temperature is generally 70°C for 3 minutes. For the hybrid packaging of silicon carbide chips 8, for products using nickel-plated base materials, GC-3688 adhesion promoter has a significant improvement on the delamination after reliability. The material needs to be diluted before spraying (95% isopropyl alcohol: 5% water): tackifier = 9:1. The product does not need to be baked after spraying, but needs to be left to stand for at least 2 hours before the subsequent process can be carried out.

[0063] 10) Compression molding process: After spraying, the product needs to be plasma cleaned before compression molding to remove the contaminants on the mixed bonding chip, welding wire 1, the pins of the lead frame, and the carrier part. The cleaned product can be well combined with the epoxy resin molding compound during the compression molding process, reducing the stratification ratio of the product. The mixed bonding chip, welding wire 1, the pins of the lead frame, and the carrier part are plastic-encapsulated, and then post-cured, tinned, and rib-cut and separated to form a single device.

[0064] 11) Post-curing process: The plastic-encapsulated product needs to be put into an oven for baking so that the epoxy resin plastic encapsulation material can be heated and more firmly combined with the chip and bonding wire 1, lead frame pin 2, and carrier, further improving the stratification performance of the product.

[0065] 12) Tinning process: After post-curing, the heat sink and pins of the entire product are brass-colored. The tinning process is to plate a layer of tin on the heat sink and pins to form a metal protective layer to improve their corrosion resistance and electrical properties and prevent pin oxidation and damage. In this process, 99.99% pure tin balls are used.

[0066] 13) Cutting process: After tinning, the entire lead frame is cut and formed, and the connecting ribs are removed to separate it into individual power devices. Depending on the application of the product, it is formed into a direct-insert or labeled device.

[0067] Fig. 9 As shown in the figure, the GaN packaged chip is currently sintered with Kyocera CT2700R7S fully sintered nanosilver. After 2000 cycles of TCT (temperature cycle test), the nanosilver glue layer breaks at the chip and carrier.

[0068] Fig.10 As shown, the present invention uses Henkel ABP 8068TB semi-sintered nano-silver adhesive sheet during packaging, and adds plasma cleaning and AP8000 spraying processes to solve the abnormality of nano-silver adhesive layer breakage. There is no delamination between the chip and the plastic packaging material, between the chip and the adhesive layer, and between the adhesive layer and the carrier.

[0069] The principle of the present invention is: to provide two processes of side-by-side packaging and stacked packaging when bonding the third generation chip. In the side-by-side packaging process structure, one chip is a gallium nitride chip 4 or a silicon carbide chip 8, and the other is a silicon-based chip 5. On the surface of the lead frame, soft solder, conductive glue, insulating glue or nano-sintered silver adhesive material are used to bond the chips in sequence. The order of bonding is: first bond the chip using high-temperature materials or a chip with a higher baking curve temperature, and then bond the chip using low-temperature materials or a chip with a lower baking curve temperature. After completing the chip bonding, according to the characteristics and application fields of the product, select aluminum wire, gold-copper wire or gold-palladium-copper wire with the best electrical performance to form precise electrical welding between the chip and the lead frame pin 2, and between the chips.

[0070] In the stacked packaging process structure, one chip is a gallium nitride chip 4 or a silicon carbide chip 8, and the other is a silicon-based chip 5, or a ceramic substrate 6 and a capacitor 7 are added. On the surface of the heat dissipation substrate, the ceramic substrate 6 is first fixed on the heat dissipation substrate using soft solder or nano-sintered silver, and then the gallium nitride chip 4 or the silicon carbide chip 8 is bonded to the other side of the ceramic substrate 6, and finally the silicon-based chip 5 stacked on the ceramic substrate 6 is bonded.

[0071] In products that do not use the ceramic substrate 6, the silicon carbide chip 8 and the silicon-based chip 5 can also be stacked directly, and the process structure is to first bond the silicon carbide chip 8 and then bond the silicon-based chip 5.

[0072] After three chips or two chips are stacked and bonded, suitable metal wires are selected to form precise electrical welding between the chip and the lead frame pin 2, between the chip and the lead frame carrier 3, and between the chip and the ceramic substrate 6. This can effectively combine the advantages of the gallium nitride chip 4 and the power chip, the silicon carbide chip 8 and the silicon-based chip 5 and the ceramic substrate 6, and achieve precise electrical connections using aluminum wire, gold-copper wire, and gold-palladium-copper wire to achieve efficient thermal management and excellent electrical performance.

[0073] According to the characteristics and application fields of the product, adhesive materials and metal wires with different properties are selected for electrical connection. Advanced laser grooving technology and special spraying process materials are used to achieve high-performance and high-reliability packaging technology requirements. It is an advanced packaging technology that improves the stability and durability of the device and ensures that it can still work stably under high-voltage environments.

[0074] The above shows and describes the basic principle, main features and advantages of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention claimed.

Claims

1. A packaging structure of a third-generation semiconductor chip, comprising a frame carrier, a silicon-based chip and a gallium nitride chip or a silicon carbide chip, characterized in that: Also includes a ceramic substrate and / or a capacitor; The silicon-based chip, a gallium nitride chip or a silicon carbide chip are arranged and bonded together on the frame carrier; Or a gallium nitride chip or a silicon carbide chip is arranged and bonded with a ceramic substrate on a frame carrier, and a silicon-based chip is bonded on the ceramic substrate; Alternatively, a gallium nitride chip or a silicon carbide chip is arranged and bonded to a ceramic substrate on a frame carrier, and a capacitor and a silicon-based chip are arranged and bonded to the ceramic substrate.

2. The packaging structure of a third generation semiconductor chip according to claim 1, characterized in that: The bonding material between the frame carrier and the silicon-based chip, a gallium nitride chip or a silicon carbide chip, and the ceramic substrate is one or more of soft solder, conductive glue, insulating glue or nano-sintered silver.

3. The packaging structure of a third generation semiconductor chip according to claim 1, characterized in that: The welding materials between the silicon-based chip, a gallium nitride chip or a silicon carbide chip, the ceramic substrate and the capacitor are one or more of aluminum wire, gold-copper wire or gold-palladium-copper wire.

4. A packaging method for a third-generation semiconductor chip packaging structure, wherein the semiconductor chip comprises a silicon-based chip, a gallium nitride chip or a silicon carbide chip, characterized in that: The semiconductor chip further includes a ceramic substrate and / or a capacitor, and the packaging method mainly includes the following steps: S1. Laser slotting: slotting is performed by laser after thinning and back-metal processing; S2, dicing: dicing the laser-grooved semiconductor wafer into individual chips; S3, chip loading: arranging or stacking the diced single chips and bonding them on the frame carrier; S4, plasma cleaning: plasma cleaning the chip after core baking; S5, pressure welding: bonding the plasma cleaned semiconductor chips using metal bonding wires to form electrical connections; S6, plasma cleaning: plasma cleaning the semiconductor chip after pressure welding; S7, Glue spraying: Spray glue on the semiconductor chip after plasma cleaning to form a uniform film on the frame carrier, pins and chip surface.

5. The packaging method of a third generation semiconductor chip packaging structure according to claim 4, characterized in that: The silicon-based chip, a gallium nitride chip or a silicon carbide chip are arranged and bonded together on the frame carrier; Or a gallium nitride chip or a silicon carbide chip is arranged and bonded with a ceramic substrate on a frame carrier, and a silicon-based chip is bonded on the ceramic substrate; Alternatively, a gallium nitride chip or a silicon carbide chip is arranged and bonded to a ceramic substrate on a frame carrier, and a capacitor and a silicon-based chip are arranged and bonded to the ceramic substrate.

6. The packaging method of a third generation semiconductor chip packaging structure according to claim 5, characterized in that: The bonding material between the frame carrier and the silicon-based chip, a gallium nitride chip or a silicon carbide chip, and the ceramic substrate is one or more of soft solder, conductive glue, insulating glue or nano-sintered silver.

7. The packaging method of a third generation semiconductor chip packaging structure according to claim 6, characterized in that: The welding materials between the silicon-based chip, a gallium nitride chip or a silicon carbide chip, the ceramic substrate and the capacitor are one or more of aluminum wire, gold-copper wire or gold-palladium-copper wire.

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