Semiconductor device configured for gate dielectric monitoring

Abstract

The invention relates to a semiconductor device configured for gate dielectric monitoring. The disclosed techniques generally relate to semiconductor devices, and more particularly to semiconductor devices including MOS transistors, and configured to accelerate and monitor degradation of gate dielectric of the MOS transistors. In one aspect, a semiconductor device configured with gate dielectric monitoring capability includes a MOS transistor including a source, a drain, a gate, and a back gate region formed in a semiconductor substrate. The semiconductor device further includes a BJT including a collector, a base, and an emitter formed in the semiconductor substrate, where the back gate region of the MOS transistor functions as the base of the BJT and is independently accessible to activate the BJT. The MOS transistor and the BJT are configured to be simultaneously activated by biasing the back gate region independently of the source of the MOS transistor such that the base of the BJT injects carriers of a first charge type into the back gate region of the MOS transistor, where the first charge type is opposite the charge type of the channel current carriers.

Description

[0001] This application is a divisional application of the Chinese invention patent application filed on September 9, 2020, with application number 202010940339.5 and invention name “Semiconductor device configured for gate dielectric monitoring”. Technical Field

[0002] The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including metal oxide semiconductor (MOS) transistors configured to accelerate and monitor degradation of a gate dielectric of the MOS transistor. Background Art

[0003] In order to improve the reliability of the gate dielectric in a metal oxide semiconductor (MOS) field effect transistor (e.g., a DMOS transistor), certain reliability tests may be performed. For example, a transistor having a gate dielectric may be placed under, for example, temperature, cycle, and / or bias conditions, under which the degradation of the gate dielectric may be accelerated. The information obtained from such reliability tests may be used to perform fault diagnosis on the fault characteristics, so that the reliability of the transistor may be improved. For example, by accelerating the gate dielectric failure and statistically analyzing the failure behavior, the cause of such failure may be determined. However, since many existing reliability tests may be performed under accelerated stress conditions, which may be very different from actual use conditions, these reliability tests may not necessarily provide accurate information that can be used to troubleshoot failures that occur in actual use. Therefore, there is a need for a device and method for accelerating the degradation of the gate dielectric of a transistor such as a DMOS transistor under conditions that subject the transistor to actual use of the device and / or when the transistor is placed under conditions close to actual use conditions. Summary of the invention

[0004] In a first aspect, a semiconductor device configured with gate dielectric monitoring capability includes a metal oxide semiconductor (MOS) transistor including a source, a drain, a gate, and a back gate region formed in a semiconductor substrate. The semiconductor device also includes a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the back gate region of the MOS transistor serves as a base of the BJT and is independently accessible to activate the BJT. The MOS transistor and the BJT are configured to be simultaneously activated by biasing the back gate region independently of the source of the MOS transistor, so that the base of the BJT injects carriers of a first charge type into the back gate region of the MOS transistor, the first charge type being opposite to the charge type of the channel current carriers.

[0005] In a second aspect, a semiconductor device includes: a double diffused metal oxide semiconductor (DMOS) transistor and a bipolar junction transistor (BJT) formed in a semiconductor substrate, wherein a first type well serving as a back gate region of the DMOS transistor and a base of the BJT is configured to be independently biased through separate well contacts, wherein the DMOS transistor and the BJT are configured to be simultaneously activated by biasing the back gate region independently of the source of the DMOS transistor.

[0006] In a third aspect, a method for monitoring a gate dielectric of a metal oxide semiconductor (MOS) transistor includes providing a semiconductor device including a metal oxide semiconductor (MOS) transistor and a bipolar junction transistor (BJT), wherein a back gate region of the MOS transistor serving as a base of the BJT is independently accessible to activate the BJT. The method also includes simultaneously activating the MOS transistor and the BJT by biasing the back gate region independently of a source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the back gate region of the MOS transistor, the first charge type being opposite to the charge type of channel current carriers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] These and other features, aspects and advantages of the present invention will now be described with reference to the accompanying drawings of several embodiments which are intended to illustrate rather than to limit the present invention.

[0008] Figure 1A is a cross-sectional view of a semiconductor device having a gate dielectric monitoring capability according to a configuration of an embodiment.

[0009] Figure 1B Shows Figure 1A A close-up view of a high field region of a semiconductor device is shown, the high field region including a portion of the gate dielectric that is subject to hole injection.

[0010] Figure 1C A schematic energy band diagram is shown, which depicts the Figure 1B Hole injection in the gate dielectric in the high field region shown.

[0011] Figure 1D Shown in Figure 1B Simulation of the spatial distribution of the electric field in the high-field region shown.

[0012] Figure 1E Shown in Figure 1B Simulation of the spatial distribution of the electric field intensity in the high field region shown.

[0013] Figure 2A A cross-sectional view and a circuit diagram of a semiconductor device with an example biasing scheme in a product mode according to an embodiment are shown.

[0014] Figure 2B FIG. 1 shows an exemplary biasing scheme with an accelerated stress mode according to an embodiment. Figure 2A , in which the back gate region is actively biased differently from the source in the accelerated stress mode.

[0015] Figure 3 It is a comparison Figure 2A The product modes shown and Figure 2B A plot of the spatial distribution of the hole density between the accelerated stress modes is shown.

[0016] Figure 4A and Figure 4B The above respectively shows Figure 2A The product model described above is Figure 2B Figure 2. Simulated spatial distribution of the relative strength and direction of the electric field in the high-field region under the accelerated stress mode described.

[0017] Figure 5 As shown above Figure 2A The product model described above is similar to Figure 2B Figure 2. Simulated spatial distribution of the electric field intensity in the high-field region under the accelerated stress mode.

[0018] Figure 6 FIG. 1 shows an exemplary biasing scheme with an accelerated stress mode according to an embodiment. Figure 2A A cross-sectional view and a circuit diagram of a semiconductor device are shown in FIG. , wherein the back gate region is electrically floated in an accelerated stress mode.

[0019] Fig. 7A and Figure 7B The above respectively shows Figure 2A The product model described above is Figure 6 Depicted are the simulated spatial distribution of the relative strength and direction of the electric field in the high-field region under the accelerated stress mode. DETAILED DESCRIPTION

[0020] The following detailed description of the embodiments presents various descriptions of specific embodiments of the present invention. However, the present invention can be embodied in many different ways as defined and covered by the claims. In this description, reference is made to the accompanying drawings in which like reference numerals may indicate the same or functionally similar elements.

[0021] As used herein, terms such as upper, lower, and upper refer to devices oriented as shown and should be interpreted accordingly. It should also be understood that since regions within a semiconductor device (e.g., a transistor) are defined by doping different portions of the semiconductor material with different impurities or different impurity concentrations, there may not actually be discrete physical boundaries between different regions in the complete device, but rather regions may transition from one to another. Some of the boundaries shown in the accompanying drawings may be of this type, but may still be shown as abrupt structures that are only used to assist the reader. In the embodiments described below, a p-type region in silicon may include a p-type semiconductor material such as boron as a dopant. In addition, an n-type region in silicon may include an n-type semiconductor material such as phosphorus as a dopant. Those skilled in the art will understand the various concentrations of dopants in the regions described below.

[0022] Power devices such as radio frequency (RF) power devices are used in many applications, such as wireless technology. For some applications, the power devices are based on metal oxide semiconductor (MOS) device technology, such as double diffused metal oxide semiconductor transistor (DMOS) technology. DMOS technology can be used for amplifiers, including microwave power amplifiers, RF power amplifiers, and audio power amplifiers.

[0023] In recent years, lateral DMOS (LDMOS) has become a popular device for monolithic high voltage and smart power applications. Silicon-based RF lateral DMOS (RF LDMOS) can be found extensively in mobile networks and supports much of the world's cellular voice and data traffic. The advantages of LDMOS include reduced manufacturing steps, multiple output capabilities on the same chip, and compatibility with advanced VLSI technology. LDMOS devices are widely used in RF power amplifiers in base stations due to their high output power and correspondingly high (e.g., >60V) drain-source breakdown voltage. DMOS such as LDMOS can include an extended drain drift region that can be lightly doped to gradually reduce the relatively large voltage amplitude between the gate and drain of the DMOS. This allows DMOS technology to be used in high voltage devices such as power supply devices. However, DMOS technology associated with the extended drain drift region may result in some reliability degradation.

[0024] In particular, various reliability degradations in MOS technology may be associated with degradation of the gate dielectric. Reliability degradation of the gate dielectric may lead to various faults, including threshold voltage drift, gate leakage, and breakdown between the gate and the source, drain, or channel. Such faults may in turn be caused by carrier injection and / or capture in the gate dielectric. The inventors have found that one type of reliability failure is associated with the effect of drain bias on degradation of the gate dielectric of some MOS devices. For example, in the case of an n-channel DMOS (nDMOS) transistor, electrons that form a channel under certain bias conditions may result in, for example, the generation of holes in an extended drain drift region. The holes generated in this way may, for example, accumulate above the drain drain region or be injected into certain portions of the gate dielectric, which in turn may result in degradation and / or failure of the dielectric. For example, without being bound by any theory, holes may tunnel to available states in the gate dielectric and be trapped therein at least temporarily. Over a period of time, the trapped holes may weaken the gate dielectric and ultimately cause the device to fail. For example, trapped holes can increase the local electric field in the gate dielectric and lead to dielectric breakdown.

[0025] Due to the adverse effects of holes on the gate dielectric, understanding the correlation between failures and physical parameters (such as process parameters) is very valuable for improving reliability and yield. The information obtained from this correlation can be used to troubleshoot the cause of the failure. For example, by accelerating gate dielectric failures and statistically analyzing the failure behavior at the chip level, wafer level, or batch level, the cause of such failures can be traced back to physical monitor parameters collected at different manufacturing process steps. Based on such information, the process parameters that cause the failure can be adjusted to improve reliability and yield. Therefore, a stress acceleration scheme is needed that can reproduce the failure in a predictable way.

[0026] However, since gate dielectric failures may occur in the latter half of the operating life of a semiconductor device, it is difficult to reproduce gate dielectric failures in laboratory time. For example, the inventors have found that simply attempting to subject the DMOS to a higher operating voltage in an attempt to accelerate hole injection into the gate dielectric does not effectively reproduce actual gate dielectric failures that occur in a product, or successfully correlate the failures with process parameters. To illustrate this reliability failure mode and the technical solution discovered by the inventors according to the embodiments, Figure 1A A MOS device according to an embodiment is shown in FIG.

[0027] Figure 1AA cross-sectional view of a semiconductor device 100 (e.g., a power semiconductor device) including a lateral DMOS (LDMOS) transistor is shown by way of example. Although the semiconductor device 100 shown includes an LDMOS transistor, it should be understood that the various embodiments described herein are not limited to devices including DMOS or LDMOS devices, but rather they can be implemented in any device including a MOS device, wherein the drain bias of the MOS device may cause gate dielectric degradation or failure due to injection of majority carriers (e.g., holes in an NMOS device). The semiconductor device 100 includes various regions formed in a semiconductor substrate 101. As described herein and throughout the specification, it will be understood that the semiconductor substrate 101 can be implemented in a variety of ways, including but not limited to a doped semiconductor substrate or a silicon-on-insulator (SOI) substrate, including a silicon-insulator-silicon structure, wherein various structures such as transistor regions are isolated from a supporting substrate using an insulator layer such as a buried SiO2 (BOX) layer. In addition, it will be understood that the various structures described herein can be at least partially formed in an epitaxial layer formed at or near a surface region. When the substrate 101 is an SOI substrate, the illustrated portion of the substrate 101 may be a portion above the BOX layer (not illustrated for clarity).

[0028] Still reference Figure 1A , below, but without limitation, a semiconductor device 100 including a DMOS transistor implemented as an n-channel LDMOS (nLDMOS) transistor will be described. When the LDMOS transistor is an nLDMOS transistor, the semiconductor substrate 101 may be a p-doped semiconductor substrate. The semiconductor device 100 also includes an n-doped well or region (n-well) 102 formed in the substrate 101. The n-well 102 may be formed by an epitaxially grown n-doped layer. A portion of the n-well 102 forms a lightly doped (n-) extended drain drift region 111 of the nLDMOS transistor, in which the conductivity is primarily attributed to electrons. Although not shown for clarity, the n-well 102 may be a multilayer region including a buried n-doped region in the p-doped substrate 101 and an n-doped region above the buried n-doped region.

[0029] The LDMOS transistor shown also includes a gate 105, a back gate region 106, a source 107, and a drain 108. The source 107 and the drain 108 are laterally interposed by the gate 105. The drain 108 is formed within the n-well 102, for example, completely enclosed therein. The back gate region 106 is laterally adjacent to the source 107 on one side and to the n-well 102 on the other side. The source 107 and the drain 108 have a higher overall n-type dopant concentration than the n-well 102. The source 107 and the drain 108 may include, for example, heavily n-doped (n +) region. A back gate contact region 109 is formed in the back gate region 106. The back gate contact region 109 has a higher overall p-type dopant concentration than the back gate region 106. The back gate contact region 109 may be, for example, heavily p-doped (p + )area.

[0030] Still reference Figure 1A , the semiconductor device 100 further includes one or more isolation regions, which include an isolation region 110a formed above the n-well 102 and at least one additional isolation region 110b formed above the semiconductor substrate 101. Electrical contacts with the source 107 and with the drain 108 are respectively achieved using conductive contact vias 107a, 108a. An electrical contact with the back gate contact region 109 is formed using a back gate contact hole 109a. The isolation regions 110a, 110b may be formed of an oxide, such as a field oxide including SiO2, which may be formed by local oxidation (LOCOS). However, the embodiment is not limited thereto, and the isolation region may be formed of any suitable structure, including shallow trench isolation (STI).

[0031] In some embodiments, the back gate region 106 may have a higher overall p-type dopant concentration than the substrate 101. For example, the back gate region 106 may be formed in a p-doped well or region (p-well) and may be defined as a p-doped region between the source 107 and the n-well 102. The p-doped well and source 107 are formed by sequentially diffusing p-type and n-type dopants through a common substrate opening formed between the gate 105 and the isolation region 110b (hence the term "double diffusion" in DMOS). Therefore, the p-well may also be formed by an epitaxial layer. The back gate contact region 109 may also be formed after the p-type doped well is formed by further diffusing p-type dopants. In the embodiment shown, the source 107 and the back gate contact region 109 are completely enclosed within the p-well. The channel region 104 is disposed within the p-well between the source 107 and the n-well 102. The effective channel length is defined by the difference in lateral diffusion of the p-well and the source 107. A gate dielectric 110c is formed over the channel region 104 between the gate 105 and the substrate 101. The gate dielectric 110c may be formed, for example, by thermal oxidation, and may include SiO2. It will be appreciated that the gate dielectric 110c includes a portion over the p-well and a portion over the n-well 102. The portion of the gate dielectric 110c over the n-well 102 abuts the isolation region 110c.

[0032] As described herein, the various p + Area and n + The region may have more than about 1×10 19 cm -3 , more than about 1×10 20 cm -3, or about 1×10 20 cm -3 About 8×10 20 cm -3 In the range (e.g. about 2×10 20 cm -3 ) of the peak doping concentration. Various wells such as p-type wells and n-type wells may have a peak doping concentration of about 1.5×10 16 cm -3 About 7.5×10 16 cm -3 , for example, about 5.0×10 16 cm -3 The peak doping concentration is within the range of . - The extended drain drift region may have a value of about 1.0×10 15 cm -3 About 1×10 16 cm -3 The peak doping concentration.

[0033] In some embodiments, gate 105 may be formed of a doped polysilicon layer, for example, heavily n-doped (n + ) or p-doped (p + ) polysilicon layer. Gate 105 extends over n-well 102 and a portion of channel region 104. Gate 105 is vertically separated from n-well 102 and p-well by isolation region 110a and gate dielectric 110c.

[0034] The isolation region 110a extends between the drain 108 and the gate dielectric 110c. When formed by LOCOS, due to the volume expansion of silicon when oxidized in the LOCOS process, the resulting SiO2 extends vertically into the n-well 102 and protrudes above the surface level of the gate dielectric 110c. The gate dielectric 110c extends laterally on the p-well between one end of the isolation region 110a on one side and the source 107 on the other side. The gate dielectric 110c is substantially thinner than the isolation region 110a. For example, the thickness of the gate dielectric 110c can be at least two orders of magnitude smaller than the thickness of the isolation region 110a. For example, depending on the application, the thickness of the gate oxide region can exceed, for example, 10nm, while the thickness of the isolation region 110a can exceed, for example, 200nm.

[0035] In some LDMOS transistors, the source can be electrically shorted to the back gate and maintained at the same potential to avoid activating the parasitic NPN bipolar junction transistor. It will be understood that the embodiments disclosed herein can be distinguished from this configuration, and the back gate region r106 and the source 107 are independently connected, for example, through the back gate contact hole 109a and the source contact via 107a that are not electrically shorted.

[0036] Still reference Figure 1A , in operation, for the illustrated semiconductor device 100 including nLDMOS, applying a positive voltage at the gate 105 relative to the back gate region 106 can form a conductive inversion layer including electrons in the channel region 104 between the source 107 and the extended drain-drain drift region 111. In combination with the voltage on the gate 105, applying a positive voltage on the drain 108 relative to the source 107 allows electrons to move from the source 107 through the channel region 104 to the drain 108. Biasing the gate 105 relative to the drain 108 of the LDMOS transistor results in the formation of a depletion region in the channel region 104 and in the lightly doped (n-) extended drain drift region 111, which reduces most of the internal electric field, thereby enabling high voltage operation of the LDMOS transistor.

[0037] The inventors have found that, in some cases, the electrons 114 drifting in the extended drain drift region 111 can generate minority carriers (holes) 118 therein by a process referred to herein as weak impact ionization, which is described herein without theoretical limitation. Weak impact ionization occurs when the energy obtained by the electrons in the extended drain drift region 111 exceeds the band gap energy of silicon to generate electron-hole pairs. Under normal operation of the nLDMOS transistor, the electrons have an energy distribution defined by fermion statistics. Although the median energy of the electrons may not be sufficient to create electron-hole pairs, since the electrons have a statistical energy distribution, according to probability, some electrons may have enough energy to generate electron-hole pairs below the critical electric field, thereby forming a breakdown of the semiconductor material caused by a chain reaction. The electron-hole pairs generated in this way are distinguished from the electron-hole pairs generated at the critical electric field of the semiconductor breakdown breakdown or above the critical electric field. Under breakdown conditions, electrons are accelerated by a relatively strong field, which initiates a chain reaction in which the electrons generate electron-hole pairs, which in turn generate additional electron-hole pairs. The chain reaction leads to impact ionization decomposition.

[0038] In the semiconductor device 100 under normal operation, the electron-hole pairs thus generated are under a subcritical electric field and do not obtain sufficient energy to sustain a chain reaction. Therefore, this process is called weak impact ionization. This mechanism generates holes, which then Figure 1AAs shown by the positive sign in , the holes are transferred to the back gate region 106, and a back gate current is generated when the LDMOS is in the on state. These holes are minority carriers in the extended drain drift region 111, and they experience many scattering events as they drift on the extended drain drift region 111 and easily reach thermal equilibrium with the surrounding lattice. That is, without being bound by any theory, the effective average temperature of the holes 118 in equilibrium with the lattice can be about the lattice temperature (e.g., 26 meV at room temperature). Some of the generated holes 118 that reach the high field region 122 formed at the dielectric junction or transition region between the isolation region 110a and the gate dielectric 110c can be injected into the gate dielectric 110c within the extended drain drift region 111. Figure 1B A view of the high field region 122 is shown in FIG.

[0039] Figure 1B Shows the above Figure 1A A close-up view of a high field region 122 of a semiconductor device 100 is depicted, which includes a dielectric junction 110d between a gate dielectric 110c and an isolation region 110a. The portion shown includes a portion of the gate dielectric 110c that is subject to hole injection over an extended drain drift region 111. Figure 1B , it will be understood that in the high field region 122, the holes 118 are still within the extended drain drift region 111. As a result, as shown by the direction of the arrow representing the electric field 126 within the high field region 122, the electric field points in an upward direction from the extended drain drift region 111 toward the gate 105. That is, the field 126 has a tendency to inject positively charged holes into the gate dielectric 110c. In addition, due to the relatively sudden decrease in the thickness of the dielectric layer from the isolation region 110a to the gate dielectric 110c, the electric field 126 increases sharply accordingly. The electric field 126 pulls the holes 118 from the extended drain drift region 111 toward the gate dielectric 110c. The holes 118 can at least partially tunnel through the gate dielectric 110c and become at least temporarily trapped holes 118a. Thereafter, the trapped holes 118 may further tunnel through the remaining thickness of the gate dielectric 110c to be injected into the gate 105, thereby generating a gate (drain) current. As described above, since the energy of the injected holes is below the critical field for breakdown, this process may be referred to herein as cold carrier injection (CCI). The inventors have determined that the trapped holes may increase the peak electric field across the gate dielectric 110c to more than several MV / cm.

[0040] Figure 1C A schematic energy band diagram is shown, which depicts the Figure 1BHole injection in the gate dielectric 110c in the high field region 122 shown. Holes 118 that partially tunnel through the gate dielectric 110c can be captured by traps having an energy level Et equal to or lower than the energy level of the tunneling holes 118. The inventors have discovered that when the gate dielectric 110c captures a sufficient number of holes or holes and / or is damaged by tunneling holes under CCI, the electric field accumulation or damage caused in the gate dielectric 110c will eventually lead to what is referred to herein as gate dielectric rupture. As described herein, gate dielectric rupture refers to a situation in which a permanent leakage path is formed through the gate dielectric 110c, which is essentially an ohmic short. The inventors have discovered that the rupture of the gate dielectric 110c in this manner may depend on the density of holes generated as described above, which in turn results in proportional holes being injected into and / or trapped in the gate dielectric 110c, as well as on the electric field strength across the gate dielectric 110c.

[0041] It should be understood that the degradation of the gate dielectric by hole tunneling under the CCI process is significantly different from the known hot carrier injection (HCI) process, which involves the injection of high-energy "hot" channel carriers, which are electrons for nMOS transistors. Unlike HCI, hole injection under the CCI process involves carriers of the opposite charge type to the channel current carriers, or holes in n-channel devices.

[0042] Figure 1D Shows Figure 1B 1 shows a simulated spatial distribution of the electric field in the high field region 122. The length of the arrow indicates the relative strength, and the direction of the arrow indicates the direction of the electric field at various locations within the high field region 122. The largest vector represents the net magnitude and direction of the electric field. Figure 1B As described, since the gate dielectric 110c subjected to CCI is formed above the extended drain drift region 111, the electric field generally points in an upward direction from the extended drain drift region 111 to the gate 105, as shown by the direction of the arrow representing the electric field 126. In addition, since the thickness of the dielectric from the isolation region 110a to the gate dielectric 110c decreases relatively steeply, a correspondingly steep increase in the electric field 126 is observed across the extended drain drift region 111. At or near the semiconductor junction between the extended drain drift region 111 and the back gate region 106, the direction of the electric field is opposite, as shown in FIG. Figure 1A As shown by the box arrows in FIG. 1 , holes subjected to the upward electric field in the high field region 122 can be injected into the gate dielectric 110c, so that at least some holes are trapped in the gate dielectric 110c. It should be understood that these trapped holes can be injected into the gate dielectric 110c in the channel region 104 ( Figure 1A) and may not be measurable as an electrical signal (e.g., threshold voltage) of the transistor defined by the channel. However, the trapped holes 118a ( Figure 1B ) may cause degradation of the gate dielectric 110c, such as gate dielectric cracking as described above.

[0043] Figure 1E It is shown that for different numbers of trapped holes, Figure 1B The simulated spatial distribution of the electric field strength in the high field region 122 is shown. The arrow indicates the direction in which the number of trapped holes increases. Figure 1B As described above, the peak value of the electric field strength near the dielectric junction 110d can increase several times. It should be understood that the above-mentioned reduction in the reliability of the gate dielectric is due to the following reasons: Figure 1A and 1B The device structure shown results in that the nLDMOS transistor includes an extended drain drift region 111 that extends laterally across the dielectric junction 110d toward the back gate region 106, so that a portion of the gate dielectric 110c extends laterally partially into the n-doped extended drain drift region 111, thereby subjecting the high field region 122 to a bias that tends to inject holes into the gate dielectric 110.

[0044] Typically, degradation of the gate dielectric of a MOS transistor occurs gradually through use, and therefore it may be impractical to diagnose such degradation on a laboratory time scale without some method of accelerating the process. At least partially addressing the above-mentioned need to accelerate gate dielectric degradation in a laboratory time frame, the inventors have discovered that by applying an independent voltage to the back gate region 106 of the semiconductor device 100. In particular, by configuring the back gate region 106 to function as the base of a bipolar junction transistor (BJT), a high hole concentration relative to normal operating conditions can be generated, thereby accelerating the degradation of the gate dielectric caused by CCI. In addition, gate dielectric failure caused by CCI can be accelerated while subjecting the relevant region of the MOS transistor to an electric field representative of the electric field under actual product use.

[0045] To apply these advantageous concepts to address the above and other reliability issues associated with MOS devices including LDMOS, where drain bias causes degradation of the gate dielectric via hole injection, the inventors have configured a semiconductor device 100 as described above to accelerate stress on the gate dielectric of the LDMOS transistor and monitor its degradation. According to the configuration, the semiconductor device 100 includes a bipolar junction transistor (BJT), where the back gate region 106 of the LDMOS transistor serves as the base of the BJT and can be independently used to activate the BJT to customize the generation of excess holes, thereby accelerating the above stress on the gate dielectric 110c for transistor-level, die-level, and / or wafer-level monitoring of the gate dielectric 110a. Among other things, the implementations described herein can achieve statistical quantification of gate dielectric failures to improve yield and reliability.

[0046] It should be understood that in existing applications of LDMOS transistors, the source 107 and the back gate region 106 can be short-circuited above the substrate, for example at the metallization level, to prevent activation of a parasitic NPN bipolar junction transistor. Unlike this configuration, by having an independently accessible back gate region 106, the number of excess holes used to accelerate gate dielectric failure can be customized according to the application. In addition, according to the device configuration and method described herein, monitoring can be performed in an accelerated stress mode, in which the LDMOS can be operated so that the relevant device area is under electric field conditions representative of the mode in which the device is used in an actual product. Due to this advantageous construction, the LDMOS can be operated in an accelerated stress mode in which the degradation of the gate dielectric is accelerated while the device parameters are similar to those in an actual product (e.g., a power semiconductor device).

[0047] As described herein, the product mode refers to a bias mode in which various terminals of a semiconductor device including source, drain, gate and back gate are subjected to voltages used in actual products. In the product mode, the bipolar junction used to provide excess carriers to accelerate stress on the gate dielectric is not activated.

[0048] On the other hand, the accelerated stress mode refers to a bias mode in which the various terminals of the semiconductor device are subjected to a voltage different from that in the product mode to accelerate the degradation of the gate dielectric. In the accelerated stress mode, a bipolar junction for providing excess carriers to accelerate the stress on the gate dielectric is activated. The electric field in the gate dielectric region stressed in the accelerated stress mode is approximately the same as the electric field in the product mode.

[0049] Figure 2A and Figure 2B2 shows a cross-sectional view and a circuit diagram of semiconductor devices 200A and 200B, wherein exemplary biases on various terminals represent a production mode and an accelerated stress mode, respectively. The semiconductor devices 200A and 200B are similar to the semiconductor devices 200A and 200B, respectively. Figure 1A The semiconductor device 100 is configured as shown. Figure 2A and 2B , semiconductor devices 200A and 200B are also shown as circuit diagrams 204A and 204B, respectively. Figure 1A-1B The similar features in Figure 2A and 2B The features in the circuit diagrams 204A and 204B may be represented by the same reference numerals. In addition, the circuit diagrams 204A and 204B are also labeled with corresponding reference numerals. As shown in the circuit diagrams 204A and 204B, the semiconductor devices 200A and 200B include an LDMOS transistor 208 and a bipolar junction transistor (BJT) 212 electrically connected to each other.

[0050] Referring to the circuit diagrams 204A and 204B, the BJT 212 includes an emitter, a base, and a collector of the BJT, which are electrically connected to the source 107, the back gate region 106, and the drain 108 of the LDMOS transistor 208, respectively. The emitter of the BJT 212 is electrically connected to or shares the same heavy n as the source 107 of the LDMOS transistor 208. + The base of BJT 212 is electrically connected to the back gate region 106 of LDMOS transistor 208 or shares a p-doped well. The collector of BJT 212 is electrically connected to the drain 108 of LDMOS transistor 208 or shares an n-doped well with it. + The configuration of BJT 212 is an NPN BJT transistor. It can be indicated that the back gate region 106 has a back gate resistor R between the back gate region 106 and the source 107 and between the back gate region 106 and the drain 107, respectively. bg and the back gate capacitor C bg .

[0051] Figure 2A A cross-sectional view 200A and a circuit diagram 204A of a semiconductor device with an example biasing scheme in a production mode are shown. In this mode, the source voltage (V s ) and back gate voltage (V bg ) are all set to the same potential, for example, at ground potential. Under this condition, BJT 212 is not activated, and no excess holes are injected from the base region of BJT 212 into the back gate region 106. In this product mode, the semiconductor device 200A is similar to the above-mentioned Figures 1A-1E The similar operation is performed in a similar manner, wherein the dielectric junction 110d ( Figure 1B) may generate holes near the gate 105. As described above, by applying a gate bias (V g ) is introduced between the source 107 and the drain 108 or between the extended drain drift region 111 of the LDMOS transistor 208 to activate the LDMOS transistor 208. The carriers that form the conductive channel 104 are electrons formed by inversion of the p-well surface, which are also referred to as channel current carriers in this article. When the LDMOS transistor 208 is activated, the electrons flow from the source 107 to the drain 108 in the channel 104 under the bias between the source 107 and the drain 108. However, as described above, the drift of electrons in the extended drain drift region 106 also generates carriers of the opposite charge type to the channel current carriers (holes in n-channel devices) through weak impact ionization. In the high field region 122 ( Figures 1A-1D ), the upwardly directed electric field draws holes from the extended drain drift region 111 toward the gate 105, which may be undesirably injected and / or trapped in the gate dielectric 110c, thereby weakening or destroying the gate dielectric 110c.

[0052] As described herein, the same voltage applied to both the source 107 and the back gate region 106 can be achieved in a variety of ways. In one embodiment, each of the source 107 and the back gate region 106 can be commonly grounded. For example, by connecting the back gate contact hole 109a and the source contact via 107a ( Figure 1A ) can be used to apply a ground voltage to the source 107 and the back gate region 106. Alternatively, independent electrical connections to the electrically isolated back gate contact hole 109a and the source contact via 107a can be used to independently ground the source 107 and the back gate region 106.

[0053] Figure 2B shows an example biasing scheme in accelerated stress mode. Figure 2A 200B and circuit diagram 204B of the same semiconductor device shown in FIG. In this mode, the back gate region 106 is actively and independently biased to be different from the source 107. It is worth noting that, unlike the above description of Figure 2A The product mode described is different, and the source voltage (V s ) and back gate voltage (V bg ) are different. For example, V bg Set to V which can be at ground potential sA higher potential. In this case, the BJT 212 is activated, and a large amount of excess holes are injected from the base of the BJT into the back gate 106 of the LDMOS transistor 208. That is, unlike the product mode, the back gate region 106 of the LDMOS transistor 208 is biased independently from the source 107, and the concentration of holes in the back gate region 106 can be controlled by controlling the bias on the back gate region 106, which serves as the base of the BJT 212 for activating the BJT 212. The p-well formed in the substrate 101 includes or serves as the back gate region 106 of the LDMOS transistor 208 and the base of the BJT 212, and is configured to be independently biased through a back gate contact hole 109a formed on the p-well. The back gate contact hole 109a can be, for example, formed through a dedicated back gate contact hole 109a ( Figure 1A ) and / or a dedicated voltage source electrically connected thereto, is controlled independently of the other terminals including the source 107. After the BJT 212 is activated, its base injects holes into the back gate region 106 at a concentration exceeding the concentration in the product relative to the product mode of the unactivated BJT 212, as described above with reference to Figure 2A By injecting holes into the back gate region 106, the BJT 212 increases the hole density in the back gate region 106, which is the majority carrier in the back gate region 106. These holes travel toward the gate dielectric 110a above the extended drain drift region 111, and once in the high field region 122, they can be injected into the gate dielectric 110c due to the electric field strength and direction as described above.

[0054] Still reference Figure 2B , during the accelerated stress mode, by using a higher V than that used during production mode g The gate bias voltage (V g ) introduces a conductive channel 104 between the source 107 and the drain 108 of the LDMOS transistor 208 to activate the LDMOS transistor 208. In addition, the normally-off or dormant BJT 212 is activated by applying a bias to the back gate region 106 of the LDMOS transistor 208 as the base of the BJT 212, thereby injecting excess holes into the back gate region 106.

[0055] Reference Figure 2A and Figure 2BAs described above, the source 107 and the back gate region 106 are biased differently in the semiconductor device 200A in the product mode than in the semiconductor device 200B in the accelerated stress mode. That is, advantageously, the same device can be implemented to function in either or interchangeably in the product mode and the accelerated stress mode. As described above, the source 107 and the back gate region 106 are under the same voltage condition in the product mode, while in the accelerated stress mode, the source 107 and the back gate region 106 are provided with independent and different voltages. The same device can be operated interchangeably in two different modes, in part by the independently accessible back gate region 106, for example, the back gate electrical contact hole 109a ( Figure 1A ) is realized, and the contact is not electrically connected to other terminals, such as the source contact through hole 107a ( Figure 1A ). In some embodiments, the back gate region 106 can be connected to a separate or dedicated voltage source to provide independent bias. Advantageously, such a configuration can be implemented so that the LDMOS transistor 208 is operated to have substantially the same relative bias between the gate 105, the drain 108, and the back gate region 106. For example, Figure 2A and 2B As shown, although the product ( Figure 2A ) and accelerated stress ( Figure 2B ) mode between V g and V d Different, gate-back gate bias (V g -V bg ), gate-drain bias (V g -V d ) and the drain-back gate bias (V d -V bg ) in magnitude between the two modes. As used herein, substantially identical voltages are within approximately 10% of each other. As a result, acceleration of gate dielectric degradation can be performed at these device biases that are very similar to those during actual use in product mode, while providing an increased concentration of holes to be injected into the gate dielectric 110c to accelerate degradation or failure. Therefore, the electric field experienced by the holes injected into the gate dielectric 110c in the high field region 122 can be configured to be substantially the same between the two. As used herein, substantially identical electric fields are within approximately 10% of each other. This configuration is advantageous for a variety of reasons. For example, degradation or failure caused in the accelerated stress mode can be more reliably attributed to hole injection into the gate dielectric 110c as described above for accurate troubleshooting and mitigation, while more reliably excluding (V g -V bg ))、(V g -V d ) and (V d -V bg)Other faults caused by differences.

[0056] exist Figure 2A In the bias scheme shown for the semiconductor device 200A in the production mode, the gate voltage (V g ) can be 0.7V; the drain voltage (V d ) may be 207V; the back gate voltage (V bg ) can be a ground voltage; the source voltage (V s ) may be a ground voltage. In comparison, for the semiconductor device 200B in the accelerated stress mode, the gate voltage (V g ) can be 1.6V; the drain voltage (V d ) may be 207.9V; the back gate voltage (V bg ) can be 0.9V; the source voltage (V s ) can be a ground voltage. As described above, during operation in the accelerated stress mode, V s and V bg Different. Advantageously, Figure 2A and 2B As shown, although the V g and V d different, but the gate-backgate bias (V g -V bg ), gate-drain bias (V g -V d ) and the drain-back gate bias (V d -V bg ) is substantially the same between the two modes. As a result, the degradation of the gate dielectric can be accelerated while the relevant bias for hole injection is substantially the same between the two modes.

[0057] It will be understood that Figure 2A and Figure 2B The exemplary bias conditions in are provided by way of illustration only to provide a compact example. However, it will be appreciated that the bias conditions between the two modes (V g -Vb g )、(V g -V d ) and (V d -V bg) are substantially equal, any suitable biasing scheme may be applied while achieving similar results. For example, the biasing scheme may be configured with drain-source voltages (V d -V s ) or a voltage within the range defined by any of these values ​​and a gate-source voltage (V g -V s ) or with voltages within the range defined by any of these values.

[0058] Advantageously, because the back gate region 106 of the LDMOS transistor 208 serving as the base of the BJT 212 is independently accessible, the amount of excess holes injected into the back gate region 106 and available for accelerated stress of the gate dielectric 110 c can be adjusted in the accelerated stress mode by adjusting the bias voltage on the back gate region 106 serving as the base of the BJT 212. For example, the V applied to the back gate region 106 can be increased. bg , and V g and V d Adjust V upward by the same amount bg Added. Ability to switch (V g -V bg )、(V g -V d ) and (V d -V bg ) remains constant while increasing the hole density by more than two orders of magnitude in the accelerated stress mode compared to the product mode.

[0059] For illustrative purposes only and without loss of generality, the above FIG. 2A to FIG. 2BThe described semiconductor device includes an nLDMOS 208 and an NPN BJT 212. As configured, degradation and / or failure of the gate dielectric 110c may be caused by holes injected into the gate dielectric 110c from the n-doped extended drain drift region 111 under the action of an electric field from the extended drain drift region 111 toward the gate electrode 105 biased with a positive voltage. However, those skilled in the art will recognize that the inventive concepts described herein may be similarly applied to similar semiconductor devices including p-channel LDMOS and PNP BJTs. In such a device, degradation and / or failure of the gate dielectric may be caused by electrons injected into the gate dielectric from the p-doped extended drain drift region under the action of an electric field directed by the gate electrode, which is biased toward the extended drain by a negative voltage. Similarly, the excess carriers injected from the base of the PNP BJT into the back gate region of the p-channel LDMOS transistor are similarly electrons.

[0060] As described above, the semiconductor device according to the embodiment advantageously allows the hole concentration in the back gate region to be controllably increased, which in turn increases the hole concentration in the gate dielectric 110c available for injection into the extended drain drift region 111, as shown in FIG. Figures 1A-1D and as described in 2A-2B. Figure 3 is near the dielectric junction 110d ( Figure 1B ) of the high field region 122( Figure 1A ) Figure 2A The product modes shown and Figure 2B Graphs 304 and 308 of the spatial distribution of hole density between accelerated stress modes are shown. The top curve 308 shows the relative density of the device versus the hole density in the accelerated stress mode in which the BJT 212 is activated, as described above with respect to Figure 2B As described. The bottom curve 304 shows the relationship between the hole density of the device in the product mode and the relative position of the device, in which the BJT is not activated. As shown, the difference in hole density between the two modes can be as high as three orders of magnitude depending on the distance from the dielectric junction 110d. Therefore, the holes available for injection into the gate dielectric 110c are correspondingly increased to accelerate the degradation of the gate dielectric 110c or cause failure.

[0061] Figure 4A and Figure 4B It is shown in the above Figure 2A The product model described above is similar to Figure 2B The high field region 122 ( Figure 1A and 1B ) simulates the spatial distribution of the relative strength and direction of the electric field in the Figure 1D, the length of the arrow indicates the relative strength, and the direction of the arrow indicates the direction of the electric field at each location. Figure 1D As described above, since the thickness of the dielectric from the isolation region 110a to the gate dielectric 110c decreases relatively steeply, the electric field 126 ( Figure 1B ) increases steeply accordingly. As described above, holes subjected to the electric field may be injected into the gate dielectric 110c, so that at least some holes are trapped in the gate dielectric 110c, resulting in degradation and / or failure of the gate dielectric 110c. Advantageously, as Figure 4A and 4B As shown, due to (V g -V bg )、(V g -V d ) and (V d -V bg ) remains constant between product and accelerated stress mode, so the spatial distribution of the electric field is substantially similar between product and accelerated stress mode. As described above, this result is particularly advantageous because the degradation of the gate dielectric can be substantially accelerated in the accelerated stress mode while keeping the spatial distribution of the electric field substantially the same as the electric field in the product mode.

[0062] exist Figure 5 The substantially similar electric field spatial distribution between the product mode and the accelerated stress mode is further shown in FIG. Figure 2A The product model described above is Figure 2B The high field region 122 ( Figure 1A and 1B ) is the simulated spatial distribution of the electric field in Figure 4A and Figure 4B The results described are similar, Figure 5 shows that although the hole concentration available for gate dielectric degradation in the accelerated stress mode ( Figure 3 ) is significantly higher, but the spatial distribution of the electric field can be essentially the same between the product mode and the accelerated stress mode.

[0063] Reference Figure 6 , shows an example bias voltage in an accelerated stress mode according to an alternative embodiment. It is worth noting that Figure 2A The product model shown is different, the source voltage (V s ) and back gate voltage (V bg ) are set to be different. However, Figure 2B Unlike the accelerated stress mode shown, the back gate region 106 is electrically floating. g is set higher than Figure 2B The V under the accelerated stress mode is shown g .exist Figure 6 In the accelerated stress mode configuration shown, V bg is pulled up above V s The potential, V s can be at ground potential and have a magnitude similar to Figure 2B That is, V bg The BJT 212 is pulled up to a sufficient bias voltage to activate the BJT 212, thereby injecting a large number of excess holes from the base of the BJT 212 into the back gate region 106 of the LDMOS transistor 208, so that the result is similar to the above description for Figure 2B The results are as follows. Figure 2B Unlike the example shown, by passing V on gate 105 g Control V bg The back gate region 106 can be connected to other terminals including the source 107 independently, for example, through a dedicated back gate contact hole 109a ( Figure 1A ), the contact can be electrically floating. The base of the BJT 212 thus activated injects holes into the back gate region 106 at a concentration more than two orders of magnitude relative to the product mode in which the BJT 212 is not activated, as described above with respect to Figure 2A As mentioned above. Figure 2B In a similar manner, holes travel toward the gate dielectric 110a above the extended drain drift region 111 and may be injected into the gate dielectric 110c to accelerate its degradation. Figure 2A and Figure 6 As described above, the source 107 and the back gate 106 are biased differently in the semiconductor device 200A in the product mode than in the semiconductor device 600 in the accelerated stress mode. Operation of the same device in two different modes is achieved in part by independently connected back bias region 106, which can be electrically floating, for example, via back gate electrical contact 109a, which is not electrically connected to other terminals (e.g., source contact via 107a). Figure 1A ). The back gate electrical contact hole 109a may be connected to a separate or dedicated terminal that may be electrically floating. Advantageously, such a configuration may be implemented so that the LDMOS transistor 208 may be operated with substantially the same drain-back gate bias (V d -V bg ). As a result, while an increased hole concentration is injected into the gate dielectric 110c to accelerate its degradation, the electric field experienced by the holes injected into the gate dielectric can be substantially the same between the two modes. Figure 2A and 2BThis configuration is advantageous for similar reasons as described above.

[0064] As an illustrative example only, for the semiconductor device 600 in the accelerated stress mode, the gate voltage (V g ) can be 2.7V; the drain voltage (V d ) may be 207.9V; the back gate voltage (V bg ) can be 0.9V; the source voltage (V s ) can be a ground voltage. As described above, during operation in the accelerated stress mode, V s and V bg Different. Advantageously, as Figure 2A and 6 As shown, although there is a significant difference between the product and accelerated stress modes, V g and V d different, but the magnitude of the drain-backgate bias (V d -V bg ) are substantially the same. As a result, the degradation of the gate dielectric can be accelerated without subjecting the injected holes to different electric fields between the two modes.

[0065] Fig. 7A and 7B It is shown in the above Figure 2A The product model described above is similar to Figure 6 In the accelerated stress mode described above, the high field region 122 ( Figure 1A and 1B ) is a simulated spatial distribution of the relative strength and direction of the electric field in the image. The length of the arrow indicates the relative strength, and the direction of the arrow indicates the direction of the electric field at each location. Advantageously, as Fig. 7A and 7B As shown, because (V d -V bg ) remains relatively constant between the product and accelerated stress modes, so the spatial distribution of the electric field is advantageously in the high field region 122 ( Figure 1A and 1B ) is substantially similar between the product mode and the accelerated stress. As mentioned above, this result is particularly advantageous because, although the concentration of holes in the accelerated stress mode ( Figure 3 ) is much higher than that in the product mode, but the spatial distribution of the electric field in the high electric field region can be basically the same between the product and accelerated stress modes.

[0066] It will be understood that although the examples discussed above relate to DMOS devices, those skilled in the art will appreciate that the present disclosure may be suitable for use in any metal oxide semiconductor transistor (MOS) including source, drain and back gate regions, where there is a problem of carriers of opposite charge type to direct current carriers to tunnel into the gate dielectric. In MOS, the source and drain are highly doped regions, and the channel is doped with dopants of opposite charge to the source and / or drain. In some embodiments, the MOS has an extended drain drift region, which may be a lightly doped region with a dopant type similar to that of the drain. As described above, the back gate region and the source are independently accessible so that the BJT can be activated and carrier injection of the opposite charge type to the channel current carriers, such as holes in an n-channel device, is increased, into the back gate region. In addition, it will be recognized that the injection of carriers of the opposite charge type to the channel current carriers, such as holes, accelerates gate dielectric failure.

[0067] Additional examples:

[0068] 1. A semiconductor device having a gate dielectric monitoring capability, comprising:

[0069] a metal oxide semiconductor (MOS) transistor including a source, a drain, a gate, and a back gate region formed in a semiconductor substrate; and

[0070] a bipolar junction transistor (BJT) comprising a collector, a base and an emitter formed in the semiconductor substrate, wherein a back gate region of the MOS transistor serves as a base of the BJT and is independently accessible to activate the BJT,

[0071] The MOS transistor and the BJT are configured to be simultaneously activated by biasing the back gate region independently of the source of the MOS transistor, so that the base of the BJT injects carriers of a first charge type into the back gate region of the MOS transistor, and the first charge type is opposite to the charge type of the channel current carriers.

[0072] 2. The semiconductor device of embodiment 1, wherein the MOS transistor is a double diffused metal oxide semiconductor (DMOS).

[0073] 3. A semiconductor device, comprising a double diffused metal oxide semiconductor (DMOS) transistor, configured to accelerate degradation of a gate dielectric of the DMOS transistor when the DMOS transistor is operated under target product bias conditions by supplying excess carriers to a back gate region of the DMOS transistor using a bipolar junction transistor (BJT).

[0074] 4. A semiconductor device comprising a double diffused metal oxide semiconductor (DMOS) transistor and a bipolar junction transistor (BJT) formed in a semiconductor substrate, wherein a first type well serving as a back gate region of the DMOS transistor and a base of the BJT is configured to be independently biased through separate well contacts, wherein the DMOS transistor and the BJT are configured to be simultaneously activated by biasing the back gate region independently of the source of the DMOS transistor.

[0075] 5. The semiconductor device of any of the above embodiments, wherein when activated, the BJT injects carriers of the first type to accelerate gate dielectric degradation or failure of the DMOS transistor.

[0076] 6. The semiconductor device of any one of the above embodiments, wherein the source of the DMOS transistor serves as the emitter of the BJT, and wherein the drain of the DMOS transistor is electrically connected to the collector of the BJT.

[0077] 7. The semiconductor device of any one of the above embodiments, wherein the DMOS transistor is an n-channel DMOS transistor, so that the first type of carriers injected into the back gate region are holes.

[0078] 8. A semiconductor device according to any of the above embodiments, wherein the DMOS transistor includes an extended drain drift region formed in a substrate and covered by a field oxide between the drain and the channel of the DMOS transistor, wherein the extended drain drift region is doped at a lower concentration using the same dopant type as the drain compared to the drain.

[0079] 9. The semiconductor device of any one of the above embodiments, further comprising:

[0080] a first contact electrically connected to the source and configured to apply a source voltage (Vs) to the source; and

[0081] a second contact electrically connected to the back gate region and configured to apply a back gate voltage (Vbg) to the back gate region,

[0082] Wherein the semiconductor device is configured to operate interchangeably between a gate dielectric test and a production mode in which different back-gate voltages are applied to the second contact.

[0083] 10. The semiconductor device of any one of the above embodiments, wherein the semiconductor device is configured so that Vs and Vbg having the same amplitude are applied in a product mode, while Vs and Vbg having different amplitudes are applied in a gate dielectric test mode.

[0084] 11. The semiconductor device of any one of the above embodiments, wherein the first contact and the second contact are electrically isolated from each other, so that the semiconductor device is configured to apply Vs and Vbg independently of each other.

[0085] 12. The semiconductor device of any of the above embodiments further comprises a third contact, which is generally electrically connected to the source and the back gate region and is configured to apply a common voltage to both the source and the back gate region, thereby operating the semiconductor device in a product mode.

[0086] 13. The semiconductor device of any one of the above embodiments, wherein in a product mode, a common voltage to the source and the back gate is a ground voltage.

[0087] 14. The semiconductor device of any one of the above embodiments, wherein the back gate region of the DMOS and the base of the BJT are accessible through dedicated contacts formed on the substrate.

[0088] 15. A method of monitoring a gate dielectric of a metal oxide semiconductor (MOS) transistor, the method comprising:

[0089] activating the MOS transistor by inducing a conductive channel between the source and drain of the MOS transistor under a gate bias; and

[0090] A bipolar junction transistor (BJT) is activated or deactivated by applying an appropriate bias to the back gate region of the MOS transistor, which serves as the base of the BJT and is independently accessible to activate the BJT, thereby injecting a first type of carrier into the back gate region, the first type of carrier having a charge opposite to that of the channel current carriers.

[0091] 16. The method of embodiment 15, wherein the MOS transistor is a double diffused metal oxide semiconductor (DMOS) transistor.

[0092] 17. The method of claim 16, wherein activating the DMOS transistor and activating the BJT comprises:

[0093] applying a first voltage to a drain of the DMOS transistor, wherein the drain is electrically connected to a collector of the BJT;

[0094] applying a second voltage to a back gate region of the DMOS transistor, wherein the back gate region of the DMOS serves as a base of the BJT; and

[0095] applying a third voltage to the source of the DMOS transistor, wherein the source of the DMOS transistor serves as the emitter of the BJT,

[0096] The first, second and third voltages are different.

[0097] 18. The method of embodiment 17, wherein the first voltage is 0V to 240V, the second voltage is 0.5V to 5.5V, and the third voltage is 0V to 5V.

[0098] 19. The method of embodiment 17, wherein the second voltage is greater than or equal to 0.5 V higher than the third voltage.

[0099] 20. The method of any one of embodiments 15-19, further comprising applying a fourth voltage to the gate of the MOS transistor.

[0100] 21. The method of embodiment 20, further comprising applying a fourth voltage to the gate of the MOS transistor, wherein the fourth voltage is 0V to 5V.

[0101] 22. The method of any one of embodiments 15-21, wherein applying a second voltage to the back gate region activates the BJT and injects carriers of the first type into the back gate region.

[0102] 23. The method of any one of embodiments 15-22, wherein the MOS transistor is an n-channel MOS transistor, so that the first type of carriers injected into the back gate region are holes.

[0103] 24. The method of any one of embodiments 15-23, further comprising adding a second voltage to the back gate region to increase the first type of carriers.

[0104] 25. The method of any one of embodiments 15-24, further comprising applying a ground voltage to the source and back gate regions of the MOS transistor simultaneously.

[0105] 26. The method of embodiment 25, wherein the applying of the ground voltage is performed during normal operation of the MOS transistor.

[0106] 27. A method of using a semiconductor device including a double diffused metal oxide semiconductor (DMOS) transistor, the method comprising:

[0107] activating the DMOS by inducing a conductive channel between the source and drain of the DMOS under a gate bias; and

[0108] A current of a first type of carriers is caused to flow through a conductive channel by applying a bias between a source and a drain, wherein by causing the first type of current carriers to flow, a current of a second type of carriers opposite to the first charge type of the first type of carriers flows in an opposite direction, and wherein the current of the second type of carriers causes gate dielectric failure of the DMOS.

[0109] 28. The method of claim 26, wherein activating the DMOS comprises:

[0110] Applying a first voltage to the drain of the DMOS;

[0111] applying a second voltage to the back gate of the DMOS;

[0112] applying a third voltage to a source of the DMOS, wherein the second voltage and the third voltage are the same voltage; and

[0113] A fourth voltage is applied to the gate of the DMOS.

[0114] 29. The method of embodiment 27 or 28 also includes activating a bipolar junction transistor (BJT) by applying a bias to a back gate region of the DMOS transistor, which transistor serves as a base of the BJT and is independently accessible to activate the BJT, thereby injecting a second type of carriers into the back gate region.

[0115] 30. The method of claim 29, wherein activating the DMOS transistor and activating the BJT comprises:

[0116] applying a first voltage to a drain of the DMOS transistor, wherein the drain is electrically connected to a collector of the BJT;

[0117] applying a fifth voltage to a back gate region of the DMOS transistor, wherein the back gate region of the DMOS serves as a base of the BJT; and

[0118] A third voltage is applied to a source of the DMOS transistor, wherein the source of the DMOS transistor serves as an emitter of the BJT, and the first, third, and fifth voltages are different.

[0119] 31. The method of embodiment 27 or 28, further comprising statistically testing the device by activating the BJT and then activating the DMOS transistor to test device performance.

[0120] 32. Semiconductor devices, including:

[0121] A double diffused metal oxide semiconductor (DMOS) transistor including a source, a drain, a gate and a back gate region formed in a semiconductor substrate;

[0122] a first contact configured to apply a first voltage to the gate;

[0123] a second contact configured to apply a second voltage to the drain;

[0124] a third contact configured to apply a third voltage to the source; and

[0125] The fourth contact is configured to apply a fourth voltage to the back gate, wherein the third voltage and the fourth voltage are different.

[0126] 33. The semiconductor device of embodiment 32 further includes a fifth contact configured to apply a fifth voltage to both the source and the back gate.

[0127] 34. The semiconductor device of embodiment 32 or 33, wherein the fifth voltage is a ground voltage.

[0128] 35. The semiconductor device of any one of embodiments 32-34, further comprising a bipolar junction transistor (BJT), comprising a collector, a base, and an emitter formed in the semiconductor substrate, wherein the back gate region of the DMOS transistor serves as the base of the BJT and is independently accessible to activate the BJT, and wherein when the BJT is activated, the base injects a first type of carrier into the back gate region, the first type of carrier being of opposite charge type to the channel current carrier.

[0129] 36. The semiconductor device of embodiment 35, wherein when activated, the BJT injects majority carriers to accelerate failure of the gate dielectric of the DMOS transistor.

[0130] 37. The semiconductor device of any one of embodiments 32-36, wherein the source serves as an emitter of a BJT, and wherein the drain is electrically connected to the collector.

[0131] 38. The semiconductor device of any one of embodiments 32-37, wherein the DMOS transistor is an n-channel DMOS transistor, so that the first type of carriers injected into the back gate region are holes.

[0132] 39. The semiconductor device of any one of embodiments 32-38, wherein the DMOS transistor includes an extended drain drift region covered by a field oxide between the drain and the channel of the DMOS.

[0133] 40. A semiconductor device configured with gate dielectric monitoring capability, comprising: a metal oxide semiconductor (MOS) transistor including a source, a drain, and a back gate region formed in a semiconductor substrate, wherein the source and the back gate regions are independently accessible.

[0134] 41. The semiconductor device of embodiment 40, wherein the MOS transistor includes an extended drain drift region formed in a semiconductor substrate.

[0135] 42. A semiconductor device according to embodiment 41, wherein the extended drain drift region is covered by a field oxide between the drain and the channel of the MOS transistor.

[0136] 43. The semiconductor device of any one of embodiments 40-42, wherein the MOS transistor is a double diffused metal oxide semiconductor (DMOS) transistor.

[0137] 44. The semiconductor device of any one of embodiments 40-43, wherein the drain is a highly doped region of the semiconductor substrate.

[0138] 45. The semiconductor device of any one of embodiments 40-44, wherein the source is a highly doped region of the semiconductor substrate.

[0139] 46. ​​The semiconductor device of any one of embodiments 40 or 42, wherein the extended drain drift region is a lightly doped region of the semiconductor substrate.

[0140] 47. The semiconductor device of any one of embodiments 32-46, wherein the channel is doped with a dopant having a charge opposite to that of the source and / or drain.

[0141] 48. A semiconductor device according to embodiment 41, wherein the extended drain drift region is doped with dopants having a charge opposite to that of the channel.

[0142] 49. The semiconductor device of any one of embodiments 32-48 also includes a first contact connected to the source and a second contact connected to the back gate region, wherein the first contact and the second contact are independently accessible so that the voltage provided by the first contact to the source is different from the voltage provided by the second contact to the back gate region.

[0143] In the above embodiments, the apparatus, system and method for monitoring and accelerating the degradation of the gate dielectric in the transistor are described in conjunction with specific embodiments. However, it will be understood that the principles and advantages of the embodiments can be applied to any other system, apparatus or method.

[0144] The principles and advantages described herein can be implemented in various devices. Examples of such equipment may include, but are not limited to, consumer electronics, components of consumer electronics, electronic test equipment, etc. Examples of components of consumer electronics may include clock circuits, analog-to-digital converters, amplifiers, rectifiers. Examples of electronic devices may also include memory chips, storage modules, circuits of optical networks or other communication networks, and disk drive circuits. Consumer electronics may include, but are not limited to, wireless devices, mobile phones (e.g., smart phones), cellular base stations, phones, televisions, computer monitors, computers, handheld computers, tablet computers, notebook computers, personal digital assistants (PDAs), microwave ovens, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, digital video recorders (DVRs), VCRs, MP3 players, radios, camcorders, cameras, digital cameras, portable memory chips, washing machines, dryers, washing machines / dryers, copiers, fax machines, scanners, watches, smart watches, clocks, wearable health monitoring devices, etc. In addition, equipment may include unfinished products.

[0145] Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprise", "include", "contain", "have", etc. should be interpreted in an inclusive sense, rather than an exclusive or unique meaning, that is, in the sense of "including but not limited to". As generally used herein, the term "coupled" refers to two or more elements that can be directly connected or connected through one or more intermediate elements. In addition, when used in the present application, the words "herein", "above", "below" and words of similar meanings should refer to the present application as a whole, rather than any particular part of the present application. Where the context permits, words used in the singular or plural in the detailed description may also include the plural or singular, respectively. The word "or" in a list involving two or more items is intended to cover all the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list. All numerical values ​​provided herein are intended to include similar values ​​within measurement errors.

[0146] Additionally, conditional language used herein, such as "may," "might," "for example," "such as," etc., is generally intended to convey that some embodiments include and some embodiments do not include certain features, elements, and / or states, unless specifically stated otherwise or understood otherwise from the context.

[0147] The teaching of the embodiments provided herein can be applied to other systems, not necessarily the above-mentioned systems. The elements and actions of the various embodiments described above can be combined to provide other embodiments. The actions of the methods discussed herein can be appropriately performed in any order. Moreover, when appropriate, the actions of the methods discussed herein can be performed serially or in parallel.

[0148] Although certain embodiments of the present invention have been described, these embodiments are given by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel methods and systems described herein can be implemented in a variety of other forms. In addition, various omissions, substitutions and changes can be made to the form of the methods and systems described herein without departing from the spirit of the present disclosure. The attached claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the present disclosure. Therefore, the scope of the present invention is defined by reference to the claims.

Claims

1. A method for monitoring a semiconductor device, the method comprising: Providing a semiconductor device, the semiconductor device comprising a metal oxide semiconductor (MOS) transistor, the MOS transistor comprising a source, a drain, a gate and a back gate region, the semiconductor device further comprising a bipolar junction transistor (BJT) integrated on the same substrate as the MOS transistor, wherein the back gate region of the MOS transistor serves as a base of the BJT and is independently accessible for activating the BJT; as well as The semiconductor device is operated in an accelerated stress mode in which the source voltage (V S ) and the back gate voltage (V bg )different.

2. The method of claim 1 , further comprising operating the semiconductor device interchangeably between an accelerated stress mode and a production mode, wherein in the production mode, V S and V bg same.

3. The method of claim 1, wherein the MOS transistor is a double diffused metal oxide semiconductor (DMOS) transistor including an extended drain drift region covered by a field oxide between a drain and a channel of the DMOS transistor.

4. The method of claim 3, wherein operating the semiconductor device in an accelerated stress mode further comprises: By applying a voltage greater than V S and V bg The gate voltage (V g ) to activate the DMOS transistor and further apply a drain voltage (V d );as well as By applying an amplitude greater than V S V bg to activate the BJT.

5. The method according to claim 4, wherein V g With V bg The difference between (V g -V bg ), V g With V d The difference between (V g -V d ) and V d With V bg The difference between (V d -V bg ) remain substantially constant between the accelerated stress mode and the production mode.

6. A method for monitoring a semiconductor device, the method comprising: activating the MOS transistor by inducing a conductive channel between a source and a drain of the MOS transistor under a gate bias; as well as A bipolar junction transistor (BJT) is activated or deactivated by applying an appropriate bias to a back gate region of the MOS transistor, which back gate region serves as a base of the BJT and is independently accessible for activating the BJT, thereby injecting a first type of carriers into the back gate region, the first type of carriers being of opposite charge type to the channel current carriers.

7. The method of claim 6, wherein the MOS transistor is a double diffused metal oxide semiconductor (DMOS) transistor.

8. The method of claim 7, wherein activating the DMOS transistor and activating the BJT comprises: Apply a drain voltage (V d ), wherein the drain is electrically connected to the collector of the BJT; Apply a back-gate voltage (V bg ), wherein the back gate region of the DMOS is used as the base of the BJT; as well as Apply source voltage (V S ), where the source of the DMOS transistor is used as the emitter of the BJT, Where V bg and V S are different.

9. The method according to claim 8, wherein V d 0V to 240V, V bg is 0.5V to 5.5V, and V S 0V to 5V.

10. The method according to claim 8, wherein V bg V S High is greater than or equal to 0.5V.

11. The method of claim 8, wherein deactivating the BJT comprises applying V bg and V S .

12. The method according to claim 11, wherein V g With V bg The difference between (V g -V bg ), V g With V d The difference between (V g -V d ) and V d With V bg The difference between (V d -V bg ) remains substantially constant between activating and deactivating the BJT.

13. The method according to claim 8, further comprising setting the gate voltage (V g ) is applied to the gate of the DMOS transistor.

14. The method according to claim 13, wherein V g 0V to 5V.

15. The method according to claim 8, wherein V is applied to the back gate region. bg The BJT is activated and carriers of the first type are injected into the back gate region.

16. The method of claim 8, wherein the DMOS transistor is an n-channel DMOS transistor such that the first type of carriers injected into the back gate region are holes.

17. The method of claim 8, further comprising increasing the V bg To increase the first type of carriers.

18. The method of claim 8, further comprising applying a ground voltage to both a source and a back gate region of the DMOS transistor.

19. The method of claim 18, wherein applying the ground voltage is performed during normal operation of the DMOS transistor.

20. A method of operating a semiconductor device including a double diffused metal oxide semiconductor (DMOS) transistor, the method comprising: activating the DMOS transistor by inducing a conductive channel between the source and drain of the DMOS transistor under a gate bias; as well as A current of a first carrier type is caused to flow through a conductive channel by applying a bias between a source and a drain, wherein by causing the current of the first carrier type to flow, a current of a second carrier type opposite to a first charge type of the first carrier type flows in an opposite direction, and wherein the current of the second carrier type causes gate dielectric failure of the DMOS transistor.

21. The method of claim 20, wherein activating the DMOS transistor comprises: Apply a drain voltage (V d ); Apply a back gate voltage (V bg ); Apply source voltage (V S ), where V S and V bg are the same voltage; and Apply gate voltage (V g ).

22. The method according to claim 21, further comprising applying a voltage with an amplitude higher than V S V bg To activate a bipolar junction transistor (BJT), wherein a back gate region of the DMOS transistor serves as a base of the BJT and is independently accessible for activating the BJT, thereby injecting carriers of the second type into the back gate region.

23. The method of claim 22, wherein applying V of the same magnitude bg and V S To deactivate BJT included.

24. The method of claim 22, wherein activating the DMOS transistor and activating the BJT comprises: V d applied to a drain of the DMOS transistor, wherein the drain is electrically connected to a collector of the BJT; Apply V to the back gate region of the DMOS transistor. bg , where the back gate region of the DMOS is used as the base of the BJT; as well as Vs is applied to a source of a DMOS transistor, wherein the source of the DMOS transistor serves as an emitter of the BJT, and wherein the first, third, and fifth voltages are different.

25. The method of claim 24, further comprising statistically testing the device by activating the BJT and then the DMOS transistor to test device performance.

26. The method according to claim 21, wherein V g With V bg The difference between (V g -V bg ), V g With V d The difference between (V g -V d ) and V d With V bg The difference between (V d -V bg ) remains substantially constant between activating and deactivating the BJT.

27. A semiconductor device comprising: A double diffused metal oxide semiconductor (DMOS) transistor including a source, a drain, a gate and a back gate region formed in a semiconductor substrate; a first contact configured to apply a first voltage to the gate; a second contact configured to apply a second voltage to the drain; a third contact configured to apply a third voltage to the source; and The fourth contact is configured to apply a fourth voltage to the back gate, wherein the third voltage and the fourth voltage are different. 28 . The semiconductor device according to claim 27 , further comprising a fifth contact configured to apply a fifth voltage to both the source and the back gate.

29. The semiconductor device according to claim 28, wherein the fifth voltage is a ground voltage.

30. The semiconductor device of claim 27, further comprising a bipolar junction transistor (BJT) comprising a collector, a base, and an emitter formed in the semiconductor substrate, wherein a back gate region of the DMOS transistor serves as a base of the BJT and is independently accessible for activating the BJT, and wherein when the BJT is activated, the base injects a first type of carrier into the back gate region, the first type of carrier being of opposite charge type to the channel current carriers.

31. The semiconductor device of claim 30, wherein when activated, the BJT injects majority carriers to cause acceleration of failure of the gate dielectric of the DMOS transistor.

32. The semiconductor device of claim 30, wherein the source serves as an emitter of the BJT, and wherein the drain is electrically connected to the collector.

33. The semiconductor device of claim 27, wherein the DMOS transistor is an n-channel DMOS transistor such that the first type of carriers injected into the back gate region are holes.

34. The semiconductor device of claim 27, wherein the DMOS transistor comprises an extended drain drift region between the drain and the channel of the DMOS and covered by a field oxide.

35. A semiconductor device configured with gate dielectric monitoring capability, comprising: A metal oxide semiconductor (MOS) transistor includes a source, a drain, and a back gate region formed in a semiconductor substrate, wherein the source and back gate regions are independently accessible.

36. The semiconductor device of claim 35, wherein the MOS transistor comprises an extended drain drift region formed in the substrate.

37. The semiconductor device of claim 36, wherein the extended drain drift region is covered by a field oxide between the drain and the channel of the MOS transistor.

38. The semiconductor device of claim 35, wherein the MOS transistor is a double diffused metal oxide semiconductor (DMOS) transistor.

39. The semiconductor device of claim 35, wherein the drain is a highly doped region of the semiconductor substrate.

40. The semiconductor device of claim 35, wherein the source is a highly doped region of the semiconductor substrate.

41. The semiconductor device of claim 35, wherein the extended drain drift region is a lightly doped region of the semiconductor substrate.

42. The semiconductor device of claim 37, wherein the channel is doped with a dopant having a charge opposite to that of the source and / or drain.

43. The semiconductor device of claim 36, wherein the extended drain drift region is doped with a dopant having a charge opposite to that of a channel of the MOS transistor.

44. The semiconductor device of claim 35 further comprises a first contact connected to the source and a second contact connected to the back gate region, wherein the first contact and the second contact are independently accessible so that the voltage that the first contact can provide to the source is different from the voltage that the second contact can provide to the back gate region.

45. A semiconductor device comprising a double diffused metal oxide semiconductor (DMOS) transistor configured to accelerate degradation of a gate dielectric of the DMOS transistor when the DMOS transistor is operated under target product bias conditions by supplying excess majority carriers to a back gate region of the DMOS transistor using a bipolar junction transistor (BJT).

46. ​​The semiconductor device of claim 45, wherein when activated, the BJT injects carriers of the first type to cause acceleration of degradation or failure of the gate dielectric of the DMOS transistor.

47. The semiconductor device of claim 45, wherein a source of the DMOS transistor serves as an emitter of the BJT, and wherein a drain of the DMOS transistor is electrically connected to a collector of the BJT.

48. The semiconductor device of claim 45, wherein the DMOS transistor is an n-channel DMOS transistor such that the first type of carriers injected into the back gate region are holes.

49. A semiconductor device according to claim 45, wherein the DMOS transistor includes an extended drain drift region formed in the substrate and covered by a field oxide between the drain and the channel of the DMOS transistor, wherein the extended drain drift region is doped with a lower doping concentration using the same dopant type as the drain compared to the drain.

50. The semiconductor device according to claim 45, further comprising: A first contact is electrically connected to the source and configured to apply a source voltage (V s ); and A second contact is electrically connected to the back gate region and configured to apply a back gate voltage (V bg ), Wherein the semiconductor device is configured to interchangeably operate between a gate dielectric test mode and a production mode in which different back-gate voltages are applied to the second contact.

51. The semiconductor device according to claim 50, wherein the semiconductor device is configured so that V having the same magnitude is applied in the product mode S and V bg , while in the gate dielectric test mode, different back gate voltages V S and V bg .

52. The semiconductor device of claim 50, wherein the first contact and the second contact are electrically isolated from each other so that the semiconductor device is configured to apply V independently of each other. S and V bg .

53. The semiconductor device of claim 50, further comprising a third contact electrically connected in common to the source and the back gate region and configured to apply a common voltage to both the source and the back gate region, thereby operating the semiconductor device in a product mode.

54. The semiconductor device of claim 50, wherein in the product mode, a common voltage to the source and the back gate is a ground voltage.

55. The semiconductor device of claim 50, wherein the back gate region of the DMOS and the base of the BJT are accessible through dedicated contacts formed on the substrate.

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