SRD and Gunn diode integrated device based on InP substrate and preparation method of SRD and Gunn diode integrated device

Abstract

The invention relates to an InP substrate-based SRD and Gunn diode integrated device and a preparation method thereof, the device comprises an InP substrate, a buffer layer, a cathode contact layer, an N interlayer, an anode contact layer, a device isolation groove, an electrode groove, an anode and a cathode, and the InP substrate, the buffer layer, the cathode contact layer, the N interlayer and the anode contact layer are sequentially arranged from bottom to top; the doping concentration of the N interlayer is gradually increased from bottom to top; the device isolation groove penetrates from the upper surface of the anode contact layer to the lower surface of the buffer layer; one side of the device isolation groove is an SRD region, and the other side of the device isolation groove is a Gunn diode region. The SRD and the Gunn diode are prepared on the same substrate, the step time of the SRD is reduced and the oscillation frequency of the Gunn diode is increased through the gradually-changed doping concentration of the N interlayer, the problems of large size, high loss, complex assembly and the like caused by device separation design are avoided, and compact and efficient pulse generation and high-frequency oscillation functions are realized.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor device integration, and in particular relates to an SRD and Gunn diode integrated device based on an InP substrate and a preparation method thereof. Background Art

[0002] The terahertz band refers to electromagnetic waves with a frequency between 0.1 and 10 THz and a wavelength between 3 mm and 30 microns. Terahertz application technology has extremely important applications in imaging, security inspection, public safety, biomedicine, non-destructive testing, communications and even military fields. However, due to the lack of high-performance terahertz sources and detectors, the development and application of terahertz science and technology are largely limited. There are many ways to generate terahertz, among which microelectronics methods are relatively easy to implement. Gunn diodes can convert direct current into microwaves without adding complex circuits. The operating frequency of Gunn diodes can reach the terahertz range, and it is a relatively cheap and stable viable device. As a solid-state terahertz source, Gunn diodes can be used in millimeter-wave and submillimeter-wave frequency sources. They can be used in airport security inspections, material imaging and detection, and environmental monitoring.

[0003] With the continuous development of science and technology, ultra-wideband radar has been widely used in short-distance communication and precise indoor positioning due to its high penetration and ultra-wide signal bandwidth. Ultra-wideband narrow pulses are an important part of ultra-wideband communication and ultra-wideband radar, and are also a key part of high-speed samplers. Therefore, a pulse source with a higher voltage amplitude and narrower pulse width is particularly important in the ultra-wideband field. Since the emergence of the step recovery diode (SRD), it has been widely used in the generation of narrow pulses and comb signal generators due to its extremely fast reverse recovery time, high pulse repetition frequency, long life, and suitability for many circuits with high requirements on edge time.

[0004] In the prior art, SRD and Gunn diode are manufactured and used separately. In practical applications, they need to be used in combination, usually requiring independent packaging and interconnection. This approach not only increases the complexity and volume of the system, but also causes loss in the signal transmission process, affecting the overall performance. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides an SRD and Gunn diode integrated device based on an InP substrate and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] The first aspect of the present invention provides an SRD and Gunn diode integrated device based on an InP substrate, comprising: an InP substrate, a buffer layer, a cathode contact layer, an N interlayer, an anode contact layer, a device isolation groove, an electrode groove, an anode and a cathode, wherein:

[0007] The InP substrate, the buffer layer, the cathode contact layer, the N interlayer and the anode contact layer are arranged in sequence from bottom to top;

[0008] The doping concentration of the N interlayer increases gradually from bottom to top;

[0009] The device isolation groove extends from the upper surface of the anode contact layer to the lower surface of the buffer layer; one side of the device isolation groove is the SRD region, and the other side is the Gunn diode region;

[0010] The electrode groove is located at the edge of the SRD region and the edge of the Gunn diode region, and penetrates from the upper surface of the anode contact layer to the upper surface of the cathode contact layer;

[0011] The anode is located on the upper surface of the anode contact layer;

[0012] The cathode is located on an upper surface of the cathode contact layer in the electrode groove.

[0013] In one achievable manner, the material of the anode contact layer in the SRD region is P-type doped InP;

[0014] The material of the anode contact layer in the Gunn diode region is N-type doped InP.

[0015] In one achievable manner, the doping concentration of the anode contact layer in the SRD region is 1×10 19 ~2×10 19 cm -3 ;

[0016] The doping concentration of the anode contact layer in the Gunn diode region is 1×10 19 ~2×10 19 cm -3 .

[0017] In one achievable manner, the materials of the buffer layer, the cathode contact layer and the N interlayer are all InP.

[0018] In one achievable manner, the cathode contact layer is doped with an N-type doping type.

[0019] In one achievable manner, the doping concentration of the cathode contact layer is 1×10 19 ~2×10 19 cm -3 ;

[0020] The doping concentration of the N interlayer is 2×10 15 ~2×10 16 cm -3 ;

[0021] The thickness of the N interlayer is 0.5-5 μm.

[0022] In an achievable manner, the product of the thickness of the N interlayer and the minimum doping concentration of the N interlayer is greater than or equal to 10 12 cm -2 .

[0023] In an achievable manner, the N interlayer includes: a first sub-N interlayer, a second sub-N interlayer and a third sub-N interlayer which are sequentially arranged from bottom to top and whose doping concentrations increase sequentially, wherein:

[0024] The doping concentration of the third N-sub-layer (43) is less than or equal to 2×10 16 cm -3 ;

[0025] The doping concentration of the first N-sub-layer (41) is greater than or equal to 2×10 15 cm -3 , and the product of the thickness of the N interlayer and the doping concentration of the first sub-N interlayer is greater than or equal to 10 12 cm -2 .

[0026] The second aspect of the present invention provides a method for preparing an SRD and Gunn diode integrated device based on an InP substrate, comprising the following steps:

[0027] S1: preparing a buffer layer, a cathode contact layer, an N interlayer and an anode contact layer in order from bottom to top on the upper surface of an InP substrate; the doping concentration of the N interlayer gradually increases from bottom to top;

[0028] S2: etching the upper surface of the anode contact layer to form a device isolation groove extending from the upper surface of the anode contact layer to the lower surface of the buffer layer; one side of the device isolation groove is the SRD region, and the other side is the Gunn diode region; etching the upper surface of the anode contact layer at the edge of the SRD region and the upper surface of the anode contact layer at the edge of the Gunn diode region to form an electrode groove extending from the upper surface of the anode contact layer to the upper surface of the cathode contact layer;

[0029] S3: preparing an anode on the upper surface of the anode contact layer; preparing a cathode on the upper surface of the cathode contact layer in the electrode groove.

[0030] In one achievable manner, the following steps are further included between step S1 and step S2:

[0031] P-type doping ions are implanted at one end of the anode contact layer to form a P-type doping region; the implantation energy is 50-100 keV.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The SRD and Gunn diode integrated device based on InP substrate of the present invention and the preparation method thereof divide the device into SRD area and Gunn diode area through device isolation groove, realize the preparation of SRD and Gunn diode on the same substrate, and introduce the built-in electric field from top to bottom in the N interlayer through the gradual doping concentration of N interlayer, thereby reducing the step time of SRD and increasing the oscillation frequency of Gunn diode, avoiding the problems of large volume, high loss and complex assembly caused by device separation design, and realizing compact and efficient pulse generation and high-frequency oscillation function. The SRD and Gunn diode integrated device provided by the present invention can be used in the fields of microwave pulse generator, millimeter wave radar, broadband communication, etc., and can be used as an independent high-frequency oscillator, and can also provide precise signal control in applications requiring short pulse signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic structural diagram of an SRD and Gunn diode integrated device based on an InP substrate provided by an embodiment of the present invention;

[0035] Figure 2a to Figure 2d It is a step structure diagram of a method for preparing an SRD and Gunn diode integrated device based on an InP substrate provided in an embodiment of the present invention.

[0036] Reference numerals:

[0037] 1: InP substrate; 2: buffer layer; 3: cathode contact layer; 4: N interlayer; 41: first sub-N interlayer; 42: second sub-N interlayer; 43: third sub-N interlayer; 5: anode contact layer; 6: anode; 7: cathode. DETAILED DESCRIPTION

[0038] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0039] Embodiment 1

[0040] See also Figure 1 , Figure 1 It is a schematic structural diagram of an SRD and Gunn diode integrated device based on an InP substrate provided in an embodiment of the present invention.

[0041] The SRD and Gunn diode integrated device based on the InP substrate provided in this embodiment includes: an InP substrate 1, a buffer layer 2, a cathode contact layer 3, an N interlayer 4, an anode contact layer 5, a device isolation groove, an electrode groove, an anode 6 and a cathode 7. Among them, the InP substrate 1, the buffer layer 2, the cathode contact layer 3, the N interlayer 4 and the anode contact layer 5 are arranged in sequence from bottom to top. The doping concentration of the N interlayer 4 gradually increases from bottom to top. The device isolation groove runs through the upper surface of the anode contact layer 5 to the lower surface of the buffer layer 2, one side of the device isolation groove is the SRD area, and the other side of the device isolation groove is the Gunn diode area. The electrode groove is located at the edge of the SRD area and the edge of the Gunn diode area, and runs through the upper surface of the anode contact layer 5 to the upper surface of the cathode contact layer 3. The anode 6 is located on the upper surface of the anode contact layer 5; the cathode 7 is located on the upper surface of the cathode contact layer 3 in the electrode groove.

[0042] Specifically, Figure 1 As shown, the device isolation groove penetrates from the upper surface of the anode contact layer 5 to the upper surface of the substrate 1, and the device is divided into the SRD region and the Gunn diode region. The anode 6 is located on the upper surface of the anode contact layer 5 in the SRD region and the upper surface of the anode contact layer 5 in the Gunn diode region. Exemplarily, the electrode groove is located at the leftmost end of the SRD region and the rightmost end of the Gunn diode region. The electrode groove penetrates from the upper surface of the anode contact layer 5 to the upper surface of the cathode contact layer 3 to expose the upper surface of the cathode contact layer 3 to form electrode steps in the SRD region and the Gunn diode region. The cathode 7 is located on the electrode steps in the SRD region and the electrode steps in the Gunn diode region. The buffer layer 2, cathode contact layer 3, N interlayer 4, anode contact layer 5, anode 6 and cathode 7 located in the SRD region form an SRD device, and the buffer layer 2, cathode contact layer 3, N interlayer 4, anode contact layer 5, anode 6 and cathode 7 located in the Gunn diode region form a Gunn diode device. Moreover, since the doping concentration of the N interlayer 4 gradually increases from bottom to top, a built-in electric field from top to bottom can be introduced in the N interlayer 4. For the SRD device, in the reverse pumping stage of the pulse discharge, the minority carrier holes in the N interlayer 4 can be extracted faster and accelerated to the saturation speed earlier, thereby reducing the step time, making the voltage change rate of the voltage pulse front formed on the load in the pulse discharge loop larger and the time shorter, so that the SRD device has a fast recovery characteristic. For the Gunn diode device, when a forward bias voltage is applied, the electrons in the N interlayer 4 can be accelerated earlier and transferred from the low energy valley to the high energy valley, thereby forming the required Gunn domain, reducing the problem of device performance degradation caused by the excessive length of the "dead zone" in the traditional Gunn diode device, and can improve the oscillation frequency and power of the Gunn diode. It should be understood that the N interlayer is an N-type doped interlayer.

[0043] In this embodiment, the device is divided into an SRD region and a Gunn diode region by a device isolation groove, so that the SRD and the Gunn diode are prepared on the same substrate, and the step time of the SRD is reduced by the N interlayer 4, and the oscillation frequency of the Gunn diode is increased, thereby avoiding the problems of large volume, high loss, and complex assembly caused by the device separation design, and realizing compact and efficient pulse generation and high-frequency oscillation functions.

[0044] In an achievable manner, the length of the device isolation trench is 200-500μm, that is, the distance between the SRD region and the Gunn diode region is 200-500μm, ensuring that both the SRD device and the Gunn diode device can operate normally. If the distance between the SRD region and the Gunn diode region is too close, there may be a direct connection between the SRD device and the Gunn diode device, resulting in heat transfer, signal coupling, and damage to device performance. If the distance is too far, it will increase the delay of signal transmission and reduce the integration.

[0045] In this embodiment, the material of the anode contact layer 5 in the SRD region is P-type doped InP, and the doping concentration of the anode contact layer 5 in the SRD region is 1×10 19 ~2×10 19 cm -3 The material of the anode contact layer 5 in the Gunn diode region is N-type doped InP, and the doping concentration of the anode contact layer 5 in the Gunn diode region is 1×10 19 ~2×10 19 cm -3 The materials of the buffer layer 2, cathode contact layer 3 and N interlayer 4 are all InP. The doping types of the cathode contact layer 3 and N interlayer 4 are all N-type. The doping concentration of the cathode contact layer 3 is 1×10 19 ~2×10 19 cm -3 The doping concentration of N interlayer 4 is 2×10 15 ~2×10 16 cm -3 The thickness of the N interlayer 4 is 0.5 to 5 μm. The product of the thickness of the N interlayer 4 and the minimum doping concentration of the N interlayer 4 is greater than or equal to 10 12 cm -2 .

[0046] The device provided in this embodiment uses the second-generation semiconductor material InP as the material of the entire device, and the SRD region is P + NN + Type doping structure, Gunn diode region is N + NN +InP has the advantages of high mobility, low effective electron mass, and better noise performance. The band gap of InP is larger than that of Si, and the mobility of electrons is also much higher than that of Si. Therefore, compared with traditional Si-based SRD, InP-based SRD has a higher breakdown voltage and a faster reverse recovery time. Compared with GaAs, the potential difference between the central energy valley and the satellite energy valley of InP semiconductor is larger, which is 0.52eV. The threshold field strength of the maximum value of electron mobility of InP is also relatively larger than that of GaAs. Therefore, compared with traditional GaAs-based Gunn diode, InP-based Gunn diode has a higher oscillation frequency and output power.

[0047] Furthermore, the doping concentration of the N interlayer 4 increases linearly from bottom to top, or the doping concentration of the N interlayer 4 increases stepwise from bottom to top. For SRD, the thinner the N interlayer 4 is, the less charge is stored, and the more obvious the step effect is; while for Gunn diode, the condition for generating Gunn domain is: the product of doping concentration N and vertical distance L between anode and cathode is higher than 10 12 cm -2 Therefore, while the N interlayer 4 is as thin as possible, the product of the thickness of the N interlayer 4 and the minimum doping concentration of the N interlayer 4 is ensured to be greater than or equal to 10 12 cm -2 , allowing SRD and Gunn diode to be realized based on the same material, so that SRD and Gunn diode can coexist on the same semiconductor substrate, and can simultaneously utilize the fast switching characteristics of SRD and the high-frequency oscillation characteristics of Gunn diode, effectively reducing the interconnection loss between devices, improving the integration and performance of the system, and greatly reducing packaging and assembly costs.

[0048] In this embodiment, the N interlayer 4 includes: a first sub-N interlayer 41, a second sub-N interlayer 42, and a third sub-N interlayer 43, which are arranged in sequence from bottom to top and whose doping concentrations increase in sequence. Furthermore, the sum of the thicknesses of the first sub-N interlayer 41, the second sub-N interlayer 42, and the third sub-N interlayer 43 is 0.5-5 μm, and the doping concentration of the third sub-N interlayer 43 is less than or equal to 2×10 16 cm -3 , the doping concentration of the first N-sub-layer 41 is greater than or equal to 2×10 15 cm -3 , and the product of the thickness of the N interlayer 4 and the doping concentration of the first sub-N interlayer 41 is greater than or equal to 10 12 cm -2 In one achievable manner, the doping concentration of the third N-sub-layer 43 is 1×10 16 ~2×10 16 cm-3 For example, the thickness of the N interlayer 4 is 1 μm, and the doping concentration of the first sub-N interlayer 41 is 1×10 16 cm -3 The doping concentration of the second N-sub-layer 42 is 1.5×10 16 cm -3 The doping concentration of the third N-sub-layer 43 is 2×10 16 cm -3 Here, the thickness of the N interlayer 4 is the sum of the thicknesses of the first sub-N interlayer 41 , the second sub-N interlayer 42 and the third sub-N interlayer 43 .

[0049] This embodiment also provides a method for preparing an SRD and Gunn diode integrated device based on an InP substrate, which is used to prepare the SRD and Gunn diode integrated device based on an InP substrate provided in this embodiment, see Figure 2a to Figure 2d , Figure 2a to Figure 2d It is a step structure diagram of a method for preparing an SRD and Gunn diode integrated device based on an InP substrate provided by an embodiment of the present invention.

[0050] The method for preparing the SRD and Gunn diode integrated device based on the InP substrate provided in this embodiment comprises the following steps:

[0051] S1: A buffer layer 2, a cathode contact layer 3, an N interlayer 4 and an anode contact layer 5 are prepared on the upper surface of an InP substrate 1 in order from bottom to top; the doping concentration of the N interlayer 4 increases gradually from bottom to top.

[0052] Specifically, Figure 2a As shown, an InP epitaxial structure is grown by metal organic chemical vapor deposition (MOCVD) on a clean semi-insulating InP substrate 1. The InP epitaxial structure includes a buffer layer 2, a cathode contact layer 3, an N interlayer 4, and an anode contact layer 5. Furthermore, a 50 nm thick InP is grown on the upper surface of the InP substrate 1 as the buffer layer 2. A 100 nm thick N interlayer is grown on the upper surface of the buffer layer 2. + Type InP, doping concentration is 1×10 19 ~2×10 19 cm -3 , and obtain the cathode contact layer 3. On the upper surface of the cathode contact layer 3, grow a 0.5-5 μm thick N-type InP with a doping concentration of 2×10 15 ~2×10 16 cm -3 , and the N interlayer 4 is obtained, and the doping concentration of the N interlayer 4 increases gradually from bottom to top. A 100nm thick N + Type InP, with a doping concentration of 1×10 19 ~2×10 19 cm-3 , and obtain the anode contact layer 5.

[0053] In this embodiment, the process conditions of MOCVD include: the raw material of group III is trimethyl indium (TMIn), the raw material of group V is phosphine (PH3), the carrier gas is hydrogen (H2) or nitrogen (N2), the N-type dopant is silane (SiH4), the growth temperature is 550-650°C, and the reaction pressure is 50-100 Torr. The doping concentration of InP can be achieved by changing the gas dosage of SiH4. For example, the doping concentration is increased from 1×10 16 cm -3 becomes 2×10 16 cm -3 The gas flow rate of SiH4 varies from 0.01 sccm to 0.03 sccm. The carrier gas is used to carry the metal organic source into the reaction chamber while providing a reducing environment to help prevent oxidation.

[0054] In this embodiment, the following steps are also included between step S1 and step S2:

[0055] P-type doping ions are implanted at one end of the anode contact layer 5 to form a P-type doping region. The implantation energy is 50-100 keV.

[0056] Specifically, Figure 2b As shown, zinc, beryllium or magnesium is selected as the P-type doping ion, and the P-type doping ion is implanted at one end of the anode contact layer 5, the implantation depth is equal to the thickness of the anode contact layer 5, the implantation energy is 50keV to 100keV, and the doping concentration is 1×10 19 ~2×10 19 cm -3 P-type InP. Furthermore, InP material is brittle and easily damaged by heat. After ion implantation, a low-temperature rapid annealing process is used for annealing. The annealing temperature is 600-700°C and the annealing time is controlled within 30 seconds. The length of the P-type doped region is less than half the length of the anode contact layer 5. After annealing, the epitaxial wafer is placed in an organic solvent of N-methylpyrrolidone (NMP) at a heating temperature of 80°C for 10 minutes, then rinsed with deionized water, dried with nitrogen, and single-sided polished.

[0057] S2: Etching is performed on the upper surface of the anode contact layer 5 to form a device isolation groove that penetrates from the upper surface of the anode contact layer 5 to the lower surface of the buffer layer 2; one side of the device isolation groove is the SRD region, and the other side is the Gunn diode region. Etching is performed on the upper surface of the anode contact layer 5 at the edge of the SRD region and the upper surface of the anode contact layer 5 at the edge of the Gunn diode region to form an electrode groove that penetrates from the upper surface of the anode contact layer 5 to the upper surface of the cathode contact layer 3.

[0058] Specifically, Figure 2c As shown, etching is performed at the middle position of the upper surface of the anode contact layer 5 by wet etching or dry etching process, and the etching depth is the thickness of the InP epitaxial structure, that is, the sum of the thickness of the buffer layer 2, the cathode contact layer 3, the N interlayer 4 and the anode contact layer 5, to form a device isolation groove penetrating from the upper surface of the anode contact layer 5 to the lower surface of the buffer layer 2. The device isolation groove divides the epitaxial structure into an SRD region and a Gunn diode region, and the side where the P-type doped region is located is the SRD region. Etching is performed at the leftmost end of the SRD region and the rightmost end of the Gunn diode region by wet etching or dry etching process, to form an electrode groove penetrating from the upper surface of the anode contact layer 5 to the upper surface of the cathode contact layer 3, so as to expose the upper surface of the cathode contact layer 3, and form electrode steps of the SRD region and the Gunn diode region.

[0059] Furthermore, the wet etching process includes: using a mixed solution of H3PO4:H2O2:H2O=2:3:30 for wet etching, controlling the etching depth by reaction time, and measuring the etching depth with a step profiler.

[0060] The dry etching process includes: setting the BCl3 gas flow rate to 6 sccm, the Ar gas flow rate to 10 sccm, the ICP power to 500 W, the DC bias voltage to 120 V, and performing dry etching on the InP epitaxial structure at an etching rate of 800 nm / min.

[0061] S3: preparing an anode 6 on the upper surface of the anode contact layer 5, and preparing a cathode 7 on the upper surface of the cathode contact layer 3 in the electrode groove.

[0062] Specifically, Figure 2d As shown, the required metal electrode pattern is photoetched on the upper surface of the anode contact layer 5 and the upper surface of the cathode contact layer 3 in the electrode groove, and then Ge / Au / Ni / Au (90 / 50 / 30 / 200nm) laminated metal is evaporated by electron beam, and then annealed at a temperature of 380°C to form an ohmic contact anode 6 and cathode 7. Furthermore, ohmic contact can reduce the contact resistance between the electrode and the semiconductor material.

[0063] The present embodiment provides an SRD and Gunn diode integrated device based on an InP substrate and a preparation method thereof. By growing the same epitaxial material on an InP substrate 1, SRD and Gunn diodes in different regions on a unified InP substrate 1 are formed by vapor deposition, ion implantation, isolation and other processes, so that the SRD and Gunn diode are integrated on the same substrate, the mutual isolation of the two devices is ensured, and the electrical performance is optimized, so that the integrated device can work in a higher frequency range. In addition, the present embodiment changes the N-type doping concentration of InP by changing the gas dose of SiH4, and prepares an N interlayer 4 with a doping concentration gradually increasing from bottom to top, so that the SRD device has a fast recovery characteristic, and the oscillation frequency and power of the Gunn diode are improved. Since the present embodiment adopts a unified substrate design, the SRD and Gunn diode do not need to be packaged separately, which reduces the occupied space of the system, simplifies the circuit wiring of the system, and improves the overall integration. At the same time, since the SRD and Gunn diode are integrated on the same substrate, the interconnection of the devices can be realized directly through a microwave waveguide structure or a transmission line, without the need for external wiring, which greatly reduces the transmission loss of the signal and the complexity of the circuit. The parasitic effects and connection losses generated when the traditional SRD and Gunn diode are connected through an external circuit are avoided, and the transmission efficiency of high-frequency signals is improved. In addition, the assembly steps can be reduced in the manufacturing process, the production efficiency is improved, the packaging and assembly costs are reduced, and the manufacturing cost of the entire system is reduced. The SRD and Gunn diode integrated device provided in this embodiment can be used in the fields of microwave pulse generators, millimeter wave radars, broadband communications, etc., and can be used as an independent high-frequency oscillator, and can also provide precise signal control in applications that require short pulse signals.

[0064] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. An SRD and Gunn diode integrated device based on an InP substrate, characterized in that: include: InP substrate (1), buffer layer (2), cathode contact layer (3), N interlayer (4), anode contact layer (5), device isolation groove, electrode groove, anode (6) and cathode (7), wherein: The InP substrate (1), the buffer layer (2), the cathode contact layer (3), the N interlayer (4) and the anode contact layer (5) are arranged in sequence from bottom to top; The doping concentration of the N interlayer (4) gradually increases from bottom to top; The device isolation groove runs through the upper surface of the anode contact layer (5) to the lower surface of the buffer layer (2); one side of the device isolation groove is the SRD region, and the other side is the Gunn diode region; The electrode groove is located at the edge of the SRD region and the edge of the Gunn diode region, and penetrates from the upper surface of the anode contact layer (5) to the upper surface of the cathode contact layer (3); The anode (6) is located on the upper surface of the anode contact layer (5); The cathode (7) is located on the upper surface of the cathode contact layer (3) in the electrode groove.

2. The SRD and Gunn diode integrated device based on InP substrate according to claim 1, characterized in that: The material of the anode contact layer (5) in the SRD region is P-type doped InP; The material of the anode contact layer (5) in the Gunn diode region is N-type doped InP.

3. The SRD and Gunn diode integrated device based on InP substrate according to claim 2, characterized in that: The doping concentration of the anode contact layer (5) in the SRD region is 1×10 19 ~2×10 19 cm -3 ; The doping concentration of the anode contact layer (5) in the Gunn diode region is 1×10 19 ~2×10 19 cm -3 .

4. The SRD and Gunn diode integrated device based on InP substrate according to claim 1, characterized in that: The materials of the buffer layer (2), the cathode contact layer (3) and the N interlayer (4) are all InP.

5. The SRD and Gunn diode integrated device based on InP substrate according to claim 4, characterized in that: The doping type of the cathode contact layer (3) is N-type.

6. The SRD and Gunn diode integrated device based on InP substrate according to claim 5, characterized in that: The doping concentration of the cathode contact layer (3) is 1×10 19 ~2×10 19 cm -3 ; The doping concentration of the N interlayer (4) is 2×10 15 ~2×10 16 cm -3 ; The thickness of the N interlayer (4) is 0.5-5 μm.

7. The SRD and Gunn diode integrated device based on InP substrate according to claim 1, characterized in that: The product of the thickness of the N interlayer (4) and the minimum doping concentration of the N interlayer (4) is greater than or equal to 10 12 cm -2 .

8. The SRD and Gunn diode integrated device based on InP substrate according to claim 1, characterized in that: The N interlayer (4) comprises: a first sub-N interlayer (41), a second sub-N interlayer (42) and a third sub-N interlayer (43) which are arranged in sequence from bottom to top and whose doping concentrations increase in sequence, wherein: The doping concentration of the third N-sub-layer (43) is less than or equal to 2×10 16 cm -3 ; The doping concentration of the first N-sub-layer (41) is greater than or equal to 2×10 15 cm -3 , and the product of the thickness of the N interlayer (4) and the doping concentration of the first sub-N interlayer (41) is greater than or equal to 10 12 cm -2 .

9. A method for preparing an SRD and Gunn diode integrated device based on an InP substrate, characterized in that: The following steps are involved: S1: preparing a buffer layer (2), a cathode contact layer (3), an N interlayer (4) and an anode contact layer (5) arranged in order from bottom to top on the upper surface of an InP substrate (1); the doping concentration of the N interlayer (4) gradually increases from bottom to top; S2: etching the upper surface of the anode contact layer (5) to form a device isolation groove extending from the upper surface of the anode contact layer (5) to the lower surface of the buffer layer (2); one side of the device isolation groove is the SRD region, and the other side is the Gunn diode region; etching the upper surface of the anode contact layer (5) at the edge of the SRD region and the upper surface of the anode contact layer (5) at the edge of the Gunn diode region to form an electrode groove extending from the upper surface of the anode contact layer (5) to the upper surface of the cathode contact layer (3); S3: preparing an anode (6) on the upper surface of the anode contact layer (5); and preparing a cathode (7) on the upper surface of the cathode contact layer (3) in the electrode groove.

10. The method for preparing an SRD and Gunn diode integrated device based on an InP substrate according to claim 9, characterized in that: The following steps are also included between step S1 and step S2: P-type doping ions are implanted at one end of the anode contact layer (5) to form a P-type doping region; the implantation energy is 50-100 keV.

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