Integrated circuit device

Abstract

An integrated circuit device includes a substrate having a first surface and a second surface; a fin-type active region extending in a first horizontal direction on the first surface of the substrate and including a first region and a second region adjacent to each other; a first source / drain region disposed on the first region of the fin-type active region; a second source / drain region disposed on a second region of the fin-type active region; and a filling insulating layer extending between the first source / drain region and the second source / drain region, in which the first region includes a first conductivity type, in which the second region includes a second conductivity type different from the first conductivity type, and in which the filling insulating layer extends between the first and second source / drain regions. A boundary between the first region and the second region includes a portion substantially perpendicular to the first horizontal direction and overlapping the filling insulating layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0138920 filed on October 17, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concept relate to an integrated circuit device, and more particularly, to an integrated circuit device formed by a self-alignment method. Background Art

[0004] As electronic products become more miniaturized, multifunctional, and high-performance, circuit devices are also required to have high capacity and high integration. Therefore, in order to achieve high integration while ensuring the function and operation speed of integrated circuit devices, effective wiring structure design is required. Summary of the invention

[0005] According to an embodiment conceived in the present invention, an integrated circuit device includes: a substrate including a first surface and a second surface opposite to each other; a fin-type active region extending along a first horizontal direction on the first surface of the substrate and including a first region and a second region adjacent to each other in the first horizontal direction; a first source / drain region arranged on the first region of the fin-type active region; a second source / drain region arranged on the second region of the fin-type active region; and a filling insulating layer extending between the first source / drain region and the second source / drain region along a second horizontal direction intersecting the first horizontal direction, wherein the first region of the fin-type active region includes a first conductive type, wherein the second region of the fin-type active region includes a second conductive type different from the first conductive type, and wherein a boundary between the first region and the second region of the fin-type active region includes a portion substantially perpendicular to the first horizontal direction and overlapping with the filling insulating layer.

[0006] According to an embodiment conceived in the present invention, an integrated circuit device includes: a substrate including a first surface and a second surface opposite to each other; a fin-type active region extending along a first horizontal direction on the first surface of the substrate and including a first region and a second region adjacent to each other in the first horizontal direction; a first source / drain region arranged on the first region of the fin-type active region; a second source / drain region arranged on the second region of the fin-type active region; a filling insulating layer extending between the first source / drain region and the second source / drain region along a second horizontal direction intersecting the first horizontal direction; a power pad and a grounding pad, each arranged on the second surface of the substrate, wherein each of the first region and the first source / drain region of the fin-type active region includes a first conductivity type, wherein each of the second region and the second source / drain region of the fin-type active region includes a second conductivity type different from the first conductivity type, and wherein a current path is formed in the fin-type active region along the first horizontal direction.

[0007] According to an embodiment of the present invention, an integrated circuit device includes: a substrate including a first surface and a second surface opposite to each other; a fin-type active region extending along a first horizontal direction on the first surface of the substrate, wherein the fin-type active region includes a first region, a second region, and a third region, the third region is spaced apart from the second region, and the first region is disposed between the third region and the second region, wherein the first region, the second region, and the third region are arranged along the first horizontal direction; a first source / drain region arranged on the first region of the fin-type active region; a second source / drain region arranged on the second region of the fin-type active region; a third source / drain region arranged on the third region of the fin-type active region; and a filling insulating layer between the first source / drain region and the second extending between source / drain regions and between the first source / drain region and the third source / drain region; and a power pad and a ground pad, each arranged on the second surface of the substrate, wherein the first region of the fin-type active region includes a first conductivity type, wherein the second region and the third region of the fin-type active region each include a second conductivity type different from the first conductivity type, wherein the first source / drain region includes the first conductivity type, wherein the second source / drain region and the third source / drain region each include the second conductivity type, and wherein each of the boundaries between the first region and the second region of the fin-type active region and the boundaries between the first region and the third region include a portion that is substantially perpendicular to the first horizontal direction and overlaps with the filling insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects of the inventive concept will become more apparent by describing embodiments in detail with reference to the accompanying drawings, in which:

[0009] Figure 1 is a plan layout diagram of an integrated circuit device according to an embodiment of the inventive concept;

[0010] Figure 2A and Figure 2B is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0011] Figure 3 is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0012] Figure 4A , Figure 4B , Figure 4C and Figure 4D is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0013] Figure 5A , Figure 5B , Figure 5C and Figure 5D is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0014] Fig. 6A and Figure 6B is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0015] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F , Figure 7G , Figure 7H , Fig.7I , Figure 7J , Figure 7K , Figure 7L , Figure 7M , Figure 7N and Fig.7O is a cross-sectional view illustrating a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept;

[0016] Fig. 8A , Figure 8B , Figure 8C and Fig.8D is a cross-sectional view illustrating a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept; and

[0017] Fig.9A , Fig. 9B , Fig. 9C and Fig.9D is a cross-sectional view of an integrated circuit device according to an embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the specification and the drawings, the same reference numerals are used for the same elements, and repeated descriptions thereof may be omitted or briefly discussed.

[0019] Figure 1 is a plan layout diagram of an integrated circuit device 100 according to an embodiment of the inventive concept. Figure 2A and Figure 2B is a cross-sectional view of an example configuration of an integrated circuit device 100 according to an embodiment of the inventive concept. Figure 2A is along Figure 1 A cross-sectional view taken along line XX in FIG. Figure 2B is along Figure 1 A cross-sectional view taken along line YY in FIG.

[0020] Reference Figure 1 , Figure 2A and Figure 2B , the integrated circuit device 100 may include: a substrate 102 having a first surface 102_1 and a second surface 102_2; and a plurality of fin-type active areas FA protruding from an upper surface of the first surface 102_1 of the substrate 102. The plurality of fin-type active areas FA may extend long along a first horizontal direction (X direction) on the substrate 102, and may extend parallel to each other.

[0021] In an embodiment of the present inventive concept, the substrate 102 may include a semiconductor such as Si and Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, and InP. The terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", and "InP" used in the present inventive concept may refer to materials including the elements included in each term, but do not represent a chemical formula indicating a stoichiometric relationship. The substrate 102 may include a conductive region, such as a well doped with an impurity or a structure doped with an impurity.

[0022] like Figure 2B As shown, the device isolation layer 112 may be arranged in a groove defining a plurality of fin-type active areas FA. For example, the device isolation layer 112 may be formed in a groove formed between two adjacent fin-type active areas FA. The device isolation layer 112 may cover a portion of the sidewall of each of the plurality of fin-type active areas FA, and may be spaced apart from the substrate 102 in the vertical direction (Z direction). The device isolation layer 112 may include, for example, a silicon oxide layer. The device isolation layer 112 may include a material having an etching selectivity different from that of the substrate 102.

[0023] like Figure 2A As shown, the fin type active area FA may include a plurality of doping regions arranged along a first horizontal direction (X direction), namely, a first region FA_1 , a second region FA_2 , and a third region FA_3 .

[0024] The first area FA_1 may be arranged between the second area FA_2 and the third area FA_3, and may be adjacent to the second area FA_2 and the third area FA_3. According to an embodiment of the present inventive concept, when the first area FA_1 is adjacent to the second area FA_2 and / or the third area FA_3, although the first area FA_1 is not in direct contact with the second area FA_2 and / or the third area FA_3, it may mean that the first area FA_1 is arranged relatively close to them. The second area FA_2 may be spaced apart from the third area FA_3, the first area FA_1 is arranged between the second area FA_2 and the third area FA_3, and the second area FA_2 may be adjacent to the first area FA_1. The third area FA_3 may be spaced apart from the second area FA_2, the first area FA_1 is arranged between the third area FA_3 and the second area FA_2, and the third area FA_3 may be adjacent to the first area FA_1.

[0025] For example, the first area FA_1 may contact the second area FA_2 and the third area FA_3. In an embodiment of the inventive concept, when the first area FA_1 contacts the second area FA_2 and / or the third area FA_3, it may mean that the first area FA_1 shares a border with each of the second area FA_2 and / or the third area FA_3.

[0026] In an embodiment of the present inventive concept, the fin-type active area FA may include a plurality of doped regions including different conductivity types from each other. The first region FA_1 and the second region FA_2 may include different conductivity types from each other. For example, the first region FA_1 may include a first conductivity type, and the second region FA_2 may include a second conductivity type different from the first conductivity type. The first region FA_1 and the third region FA_3 may include different conductivity types from each other. For example, the first region FA_1 may include a first conductivity type, and the third region FA_3 may include a second conductivity type different from the first conductivity type.

[0027] In an embodiment of the present inventive concept, the fin-type active area FA may include a plurality of doped regions having the same conductivity type. The second region FA_2 and the third region FA_3 may include the same conductivity type as each other. For example, both the second region FA_2 and the third region FA_3 may include the second conductivity type. In other words, the second region FA_2 and the third region FA_3 may be spaced apart from each other, the first region FA_1 is disposed between the second region FA_2 and the third region FA_3, and the second region FA_2 and the third region FA_3 may include the same conductivity type as each other. In other words, both the second region FA_2 and the third region FA_3 spaced apart from each other via the first region FA_1 may include the second conductivity type, while the first region FA_1 includes the first conductivity type.

[0028] In an embodiment of the present inventive concept, when the first region FA_1 is doped with N type, the second and third regions FA_2 and FA_3 may be doped with P type. In an embodiment of the present inventive concept, when the first region FA_1 is doped with P type, the second and third regions FA_2 and FA_3 may each be doped with N type.

[0029] like Figure 2A As shown, the boundaries between the adjacent doping regions in the plurality of doping regions may be perpendicular to the first horizontal direction (X direction). The boundary FAB_12 between the first region FA_1 and the second region FA_2 adjacent to each other may be perpendicular to the first horizontal direction (X direction). For example, the boundary FAB_12 between the first region FA_1 and the second region FA_2 may be parallel to the YZ flat surface (e.g., plane) and perpendicular to the first horizontal direction (X direction). The boundary FAB_13 between the first region FA_1 and the third region FA_3 adjacent to each other may be perpendicular to the first horizontal direction (X direction). For example, the boundary FAB_13 between the first region FA_1 and the third region FA_3 may be parallel to the YZ flat surface and perpendicular to the first horizontal direction (X direction).

[0030] In an embodiment of the present inventive concept, a boundary between mutually adjacent doping regions among the plurality of doping regions may include a portion substantially perpendicular to the first horizontal direction (X direction). A boundary FAB_12 between mutually adjacent first regions FA_1 and second regions FA_2 may include a portion substantially perpendicular to the first horizontal direction (X direction). A boundary FAB_13 between mutually adjacent first regions FA_1 and third regions FA_3 may include a portion substantially perpendicular to the first horizontal direction (X direction).

[0031] In an embodiment of the present invention, a current path may be formed by two doping regions that are adjacent to each other and include different conductivity types from each other. The current path may be formed between a first region FA_1 and a second region FA_2 that are adjacent to each other and include different conductivity types from each other. For example, current may flow from the first region FA_1 to the second region FA_2. For example, current may flow from the second region FA_2 to the first region FA_1. The current path may be formed between a first region FA_1 and a third region FA_3 that are adjacent to each other and include different conductivity types from each other. For example, current may flow from the first region FA_1 to the third region FA_3. For example, current may flow from the third region FA_3 to the first region FA_1.

[0032] In an embodiment of the present inventive concept, in the fin-type active area FA, a current path may be formed to pass through a boundary between two doping regions adjacent to each other. In other words, in the fin-type active area FA, a current may flow through a boundary between two doping regions adjacent to each other. As described above, the boundary between adjacent doping regions in the plurality of doping regions may be perpendicular to the first horizontal direction (X direction), and therefore, in the fin-type active area FA, a current path may be formed along the first horizontal direction (X direction).

[0033] The current path between the first area FA_1 and the second area FA_2 adjacent to each other may be formed along the first horizontal direction (X direction). For example, the current path flowing from the first area FA_1 to the second area FA_2 may be formed along the first horizontal direction (X direction). For example, the current path flowing from the second area FA_2 to the first area FA_1 may be formed along the first horizontal direction (X direction).

[0034] The current path between the first area FA_1 and the third area FA_3 adjacent to each other may be formed along the first horizontal direction (X direction). For example, the current path flowing from the first area FA_1 to the third area FA_3 may be formed along the first horizontal direction (X direction). For example, the current path flowing from the third area FA_3 to the first area FA_1 may be formed along the first horizontal direction (X direction).

[0035] In an embodiment of the present inventive concept, in the fin-type active area FA, the current path may include a current path formed along the first horizontal direction (X direction). The current path between the first region FA_1 and the second region FA_2 adjacent to each other may include a current path formed along the first horizontal direction (X direction). The current path between the first region FA_1 and the third region FA_3 adjacent to each other may include a current path formed along the first horizontal direction (X direction).

[0036] According to an embodiment of the present invention, an integrated circuit device 100 including a plurality of doped regions (e.g., a first region FA_1 and a second region FA_2 in a fin-type active region FA) adjacent to each other in a first horizontal direction (X direction) may be provided. Since the integrated circuit device 100 according to an embodiment of the present invention includes a plurality of doped regions adjacent to each other, in a process of manufacturing the integrated circuit device 100, even if the substrate 102 is thinned, current may flow between the plurality of doped regions. In other words, according to an embodiment of the present invention, an integrated circuit device 100 having increased performance and reliability may be provided.

[0037] like Figure 2A As shown, a plurality of recesses may be formed in the fin type active area FA. A vertical level of a lowermost surface of each of the plurality of recesses may be lower than a vertical level of a fin top surface FT.

[0038] like Figure 2A As shown, in the plurality of recesses, a plurality of source / drain regions 130 may be respectively arranged. The plurality of source / drain regions 130 may be arranged along a first horizontal direction (X direction) and may include a first source / drain region 130_1, a second source / drain region 130_2, and a third source / drain region 130_3.

[0039] The first source / drain region 130_1 may be disposed between the second source / drain region 130_2 and the third source / drain region 130_3, and may be adjacent to the second source / drain region 130_2 and the third source / drain region 130_3. The second source / drain region 130_2 may be spaced apart from the third source / drain region 130_3, the first source / drain region 130_1 may be disposed between the second source / drain region 130_2 and the third source / drain region 130_3, and the second source / drain region 130_2 may be adjacent to the first source / drain region 130_1. The third source / drain region 130_3 may be spaced apart from the second source / drain region 130_2, the first source / drain region 130_1 may be disposed between the third source / drain region 130_3 and the second source / drain region 130_2, and the third source / drain region 130_3 may be adjacent to the first source / drain region 130_1.

[0040] like Figure 2A As shown, a plurality of source / drain regions 130 may be arranged on the fin-type active area FA. The plurality of source / drain regions 130 may be arranged to contact the fin-type active area FA. Each of the plurality of source / drain regions 130 may be arranged on each of the plurality of doped regions of the fin-type active area FA. Each of the plurality of source / drain regions 130 may be arranged to contact each of the plurality of doped regions of the fin-type active area FA, respectively.

[0041] The first source / drain region 130_1 may be arranged on the first area FA_1. The first source / drain region 130_1 may be arranged to contact the first area FA_1. The second source / drain region 130_2 may be arranged on the second area FA_2. The second source / drain region 130_2 may be arranged to contact the second area FA_2. The third source / drain region 130_3 may be arranged on the third area FA_3. The third source / drain region 130_3 may be arranged to contact the third area FA_3.

[0042] In an embodiment of the present inventive concept, a portion of the plurality of source / drain regions 130 may include conductivity types different from each other. The first source / drain region 130_1 and the second source / drain region 130_2 may include conductivity types different from each other. For example, the first source / drain region 130_1 may include a first conductivity type, and the second source / drain region 130_2 may include a second conductivity type different from the first conductivity type. The first source / drain region 130_1 and the third source / drain region 130_3 may include conductivity types different from each other. For example, the first source / drain region 130_1 may include a first conductivity type, and the third source / drain region 130_3 may include a second conductivity type different from the first conductivity type.

[0043] In an embodiment of the present inventive concept, a portion of the plurality of source / drain regions 130 may include the same conductivity type as each other. The second source / drain region 130_2 and the third source / drain region 130_3 may include the same conductivity type as each other. For example, both the second source / drain region 130_2 and the third source / drain region 130_3 may include the second conductivity type. In other words, the second source / drain region 130_2 and the third source / drain region 130_3 spaced apart from each other via the first source / drain region 130_1 may include the same conductivity type as each other. In other words, both the second source / drain region 130_2 and the third source / drain region 130_3 include the second conductivity type, while the first source / drain region 130_1 includes the first conductivity type.

[0044] In an embodiment of the present inventive concept, some doped regions of the fin-type active area FA and the source / drain area 130 adjacent to each other may include the same conductivity type as each other. The first region FA_1 and the first source / drain area 130_1 of the fin-type active area FA adjacent to each other may both include the first conductivity type. The second region FA_2 and the second source / drain area 130_2 of the fin-type active area FA adjacent to each other may both include the second conductivity type. The third region FA_3 and the third source / drain area 130_3 of the fin-type active area FA adjacent to each other may both include the second conductivity type.

[0045] In an embodiment of the present inventive concept, each of the plurality of source / drain regions 130 may be doped with a concentration of a dopant higher than that of a portion of the fin-type active region FA in contact with each of the plurality of source / drain regions 130. The first region FA_1 of the fin-type active region FA may be doped with a first concentration, and the first source / drain region 130_1 in contact with the first region FA_1 may be doped with a second concentration higher than the first concentration. The second region FA_2 of the fin-type active region FA may be doped with a third concentration, and the second source / drain region 130_2 in contact with the second region FA_2 may be doped with a fourth concentration higher than the third concentration. The third region FA_3 of the fin-type active region FA may be doped with a fifth concentration, and the third source / drain region 130_3 in contact with the third region FA_3 may be doped with a sixth concentration higher than the fifth concentration.

[0046] In an embodiment of the inventive concept, the first source / drain region 130_1 may be doped with N type, and the second and third source / drain regions 130_2 and 130_3 may be doped with P type. For example, when the first region FA_1 is doped with N type and the second and third regions FA_2 and FA_3 are doped with P type, the first source / drain region 130_1 may be doped with N type, and the second and third source / drain regions 130_2 and 130_3 may be doped with P type.

[0047] In an embodiment of the inventive concept, the first source / drain region 130_1 is doped with a P type, and the second and third source / drain regions 130_2 and 130_3 may be doped with an N type. For example, when the first region FA_1 is doped with a P type and the second and third regions FA_2 and FA_3 are doped with an N type, the first source / drain region 130_1 may be doped with a P type, and the second and third source / drain regions 130_2 and 130_3 may be doped with an N type.

[0048] like Figure 2A and Figure 2B As shown, a plurality of filling insulating layers 161 may extend along the second horizontal direction (Y direction) and may be arranged between each of the plurality of source / drain regions 130. The filling insulating layer 161 may be arranged between the first source / drain region 130_1 and the second source / drain region 130_2. The filling insulating layer 161 may be arranged between the first source / drain region 130_1 and the third source / drain region 130_3.

[0049] In an embodiment of the inventive concept, each of the plurality of source / drain regions 130 may be spaced apart from each other, with a plurality of filling insulating layers 161 disposed therebetween. The first source / drain region 130_1 and the second source / drain region 130_2 may be spaced apart from each other, with the filling insulating layer 161 disposed therebetween. The first source / drain region 130_1 and the third source / drain region 130_3 may be spaced apart from each other, with the filling insulating layer 161 disposed therebetween. The first source / drain region 130_1 and the third source / drain region 130_3 may be spaced apart from each other, with the filling insulating layer 161 disposed therebetween.

[0050] According to an embodiment of the inventive concept, the integrated circuit device 100 includes a filling insulating layer 161 extending along the second horizontal direction (Y direction) between each of adjacent source / drain regions 130 of the plurality of source / drain regions 130. Since the integrated circuit device 100 according to an embodiment of the inventive concept includes the filling insulating layer 161 disposed between each of the plurality of source / drain regions 130, leakage current that may occur between each of the plurality of source / drain regions 130 can be prevented. In other words, according to an embodiment of the inventive concept, an integrated circuit device 100 having increased performance and reliability can be provided.

[0051] like Figure 2A As shown, the boundaries between the adjacent doping regions in the plurality of doping regions of the fin-type active region FA may overlap with the filling insulating layer 161 in the vertical direction (Z direction). The boundary FAB_12 between the first region FA_1 and the second region FA_2 adjacent to each other may overlap with the filling insulating layer 161 in the vertical direction (Z direction). The boundary FAB_13 between the first region FA_1 and the third region FA_3 adjacent to each other may overlap with the filling insulating layer 161 in the vertical direction (Z direction).

[0052] In an embodiment of the present inventive concept, a boundary between mutually adjacent doping regions among a plurality of doping regions may overlap with the filling insulating layer 161 in the vertical direction (Z direction). A boundary FAB_12 between mutually adjacent first and second regions FA_1 and FA_2 may include a portion overlapping with the filling insulating layer 161 in the vertical direction (Z direction). A boundary FAB_13 between mutually adjacent first and third regions FA_1 and FA_3 may include a portion overlapping with the filling insulating layer 161 in the vertical direction (Z direction).

[0053] The metal silicide layer 172 may be formed on the upper surface of each of the plurality of source / drain regions 130. The metal silicide layer 172 may include a metal. For example, the metal silicide layer 172 may include at least one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and / or Pd. For example, the metal silicide layer 172 may include titanium silicide, but the inventive concept is not limited thereto.

[0054] On the substrate 102, a plurality of source / drain regions 130 and a plurality of metal silicide layers 172 may be covered with an insulating liner 142. In an embodiment of the inventive concept, the insulating liner 142 may be omitted. An inter-gate insulating layer 144 may be disposed on the insulating liner 142. When the insulating liner 142 is omitted, the inter-gate insulating layer 144 may contact the plurality of source / drain regions 130.

[0055] The insulating liner 142 and the inter-gate insulating layer 144 may be sequentially arranged on the plurality of source / drain regions 130 and the plurality of metal silicide layers 172. The insulating liner 142 and the inter-gate insulating layer 144 may constitute an insulating structure. In an embodiment of the inventive concept, the insulating liner 142 may include silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, but the inventive concept is not limited thereto. The inter-gate insulating layer 144 may include a silicon oxide layer, but the inventive concept is not limited thereto.

[0056] like Figure 2A As shown, a plurality of source / drain contacts CA may be arranged on a plurality of source / drain regions 130. Each of the plurality of source / drain contacts CA may penetrate the inter-gate insulating layer 144 and the insulating liner 142 in a vertical direction (Z direction), and may be disposed on the metal silicide layer 172. For example, each of the plurality of source / drain contacts CA may contact the metal silicide layer 172. Each of the plurality of source / drain contacts CA may be configured to be electrically connected to the source / drain region 130 via the metal silicide layer 172. For example, the plurality of source / drain contacts CA may include a first source / drain contact CA_1 arranged on the first source / drain region 130_1, a second source / drain contact CA_2 arranged on the second source / drain region 130_2, and a third source / drain contact CA_3 arranged on the third source / drain region 130_3.

[0057] The plurality of source / drain contacts CA may include a conductive barrier pattern 174 and a contact plug 176 sequentially stacked on the source / drain region 130. The conductive barrier pattern 174 may at least partially surround the lower surface and the sidewall of the contact plug 176. For example, the conductive barrier pattern 174 may contact the lower surface and the sidewall of the contact plug 176. Each of the plurality of source / drain contacts CA may penetrate the inter-gate insulating layer 144 and the insulating liner 142, and extend longer in the vertical direction (Z direction). The conductive barrier pattern 174 may be arranged between the metal silicide layer 172 and the contact plug 176. For example, the conductive barrier pattern 174 may include a first surface in contact with the metal silicide layer 172 and a second surface in contact with the contact plug 176. In an embodiment of the inventive concept, the conductive barrier pattern 174 may include a metal or a metal nitride. For example, the conductive barrier pattern 174 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but the inventive concept is not limited thereto. The contact plug 176 may include, for example, molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but the inventive concept is not limited thereto.

[0058] like Figure 2A and Figure 2B As shown, the upper surface of each of the plurality of source / drain contacts CA, the insulating liner 142, and the inter-gate insulating layer 144 may be covered by an upper insulating structure 180. The upper insulating structure 180 may include an etch stop layer 182 and an interlayer insulating layer 184 sequentially stacked on each of the plurality of source / drain contacts CA, the insulating liner 142, and the inter-gate insulating layer 144. The etch stop layer 182 may include, for example, silicon carbide (SiC), SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The interlayer insulating layer 184 may include, for example, an oxide layer, a nitride layer, an ultra-low k (ULK) layer having an ultra-low dielectric constant K of about 2.2 to about 2.4, or a combination thereof. For example, the interlayer insulating layer 184 may include a tetraethyl orthosilicate (TEOS) layer, a high density plasma (HDP) layer, a borophosphosilicate glass (BPSG) layer, a flowable chemical vapor deposition (FCVD) oxide layer, a SiON layer, a SiOC layer, a SiCOH layer, or a combination thereof, but the inventive concept is not limited thereto.

[0059] like Figure 2A and Figure 2BAs shown, a plurality of source / drain via contacts VA may be arranged on a plurality of source / drain contacts CA, respectively. Each of the plurality of source / drain via contacts VA may penetrate the upper insulating structure 180 and contact the source / drain contact CA. Each of the plurality of source / drain regions 130 may be electrically connected to the source / drain via contact VA via the metal silicide layer 172 and the source / drain contact CA. For example, the lower surface of each of the plurality of source / drain via contacts VA may contact the upper surface of the source / drain contact CA. For example, each of the plurality of source / drain via contacts VA may include Mo or W, but the inventive concept is not limited thereto.

[0060] like Figure 2A As shown, the power pad PP and the ground pad GP may be arranged below the second surface 102_2 of the substrate 102. The power pad PP and the ground pad GP may be arranged below the back insulating layer 101, and the back insulating layer 101 is arranged below the second surface 102_2 of the substrate 102. For example, the back insulating layer 101 may include silicon oxide. In an embodiment of the inventive concept, current may flow through the integrated circuit device 100 via the power pad PP. The integrated circuit device 100 may be grounded via the ground pad GP.

[0061] like Figure 2A As shown in , the integrated circuit device 100 may include a first through electrode 150_1 and a second through electrode 150_2, which penetrate the back insulating layer 101 and extend in the vertical direction (Z direction). The integrated circuit device 100 may include a first wiring line M1, a second wiring line M2, and a third wiring line M3 arranged above the first surface 102_1 of the substrate 102. The integrated circuit device 100 may include a plurality of wiring contacts MC, and the plurality of wiring contacts MC are used to mediate the electrical connection between the first wiring line M1, the second wiring line M2, and the third wiring line M3.

[0062] For example, the first wiring line M1 may be connected to the power pad PP via the first through-electrode 150_1. The second wiring line M2 may be connected to the ground pad GP via the second through-electrode 150_2. The third wiring line M3 may be connected to the first and second wiring lines M1 and M2 via the wiring contact MC.

[0063] Reference Figure 1 , Figure 2A and Figure 2B The described integrated circuit device 100 may include an electrostatic discharge (ESD) diode element. In other words, when static electricity occurs, current may flow through the integrated circuit device 100 via the power pad PP, and the current may be discharged via the ground pad GP. FIG. 4A to FIG. 4D as well as FIG. 5A to FIG. 5DThe current paths in the integrated circuit device 100 are described in detail.

[0064] Figure 3 1 is a cross-sectional view of an integrated circuit device 100A according to an embodiment of the present inventive concept. Figure 1 , Figure 2A and Figure 2B The differences in the integrated circuit device 100 are described.

[0065] Reference Figure 3 , the integrated circuit device 100A may include a plurality of gate portions 160_P, a plurality of gate dielectric layer portions 152_P, a plurality of nanosheet portions NS_P, and / or a plurality of outer insulating spacers 118. The integrated circuit device 100A may include a gate portion 160_P, a gate dielectric layer portion 152_P, a nanosheet portion NS_P, and / or an outer insulating spacer 118 disposed between each of the plurality of source / drain regions 130 and the filling insulating layer 161A. For example, the gate portion 160_P, the gate dielectric layer portion 152_P, the nanosheet portion NS_P, and the outer insulating spacer 118 may be disposed between the first source / drain region 130_1 and the filling insulating layer 161A, between the second source / drain region 130_2 and the filling insulating layer 161A, and / or between the third source / drain region 130_3 and the filling insulating layer 161A. For example, the gate dielectric layer portion 152_P may be disposed between the gate portion 160_P and the nanosheet portion NS_P.

[0066] In an embodiment of the present invention, a plurality of gate portions 160_P and a plurality of nanosheet portions NS_P may be alternately arranged on the fin upper surface FT of the fin-type active area FA. For example, each of the plurality of gate portions 160_P may be arranged between the fin-type active area FA and the bottommost nanosheet portion NS_P and / or between each of the plurality of nanosheet portions NS_P. For example, each of the plurality of nanosheet portions NS_P may be arranged between each of the plurality of gate portions 160_P and / or between the topmost gate portion 160_P and the outer insulating spacer 118. In an embodiment of the present invention, the outer insulating spacer 118 may be arranged on the plurality of gate portions 160_P, the gate dielectric layer portion 152_P, and the plurality of nanosheet portions NS_P.

[0067] Figure 4A and Figure 4D is a cross-sectional view of an integrated circuit device 100_1 according to an embodiment of the inventive concept. FIG. 4A to FIG. 4D is a cross-sectional view for describing a current path in the integrated circuit device 100_1 .

[0068] like FIG. 4A to FIG. 4DAs shown, the integrated circuit device 100_1 may include a first region FA_1 and a first source / drain region 130_1 doped with N type, and may include a second region FA_2, a third region FA_3, a second source / drain region 130_2, and a third source / drain region 130_3 doped with P type.

[0069] For example, the first region FA_1 may be doped with N well or N - type, and the first source / drain region 130_1 may be doped with N + In other words, the first source / drain region 130_1 may include an N-type having a concentration greater than that of the first region FA_1. For example, the second region FA_2 may be doped with a P-well or a P- - type, and the second source / drain region 130_2 may be doped with P + In other words, the second source / drain region 130_2 may include a P type having a concentration greater than that of the second region FA_2. For example, the third region FA_3 may be doped with a P well region or a P - type, and the third source / drain region 130_3 may be doped with P + In other words, the third source / drain region 130_3 may include a P-type conductivity type having a concentration greater than that of the third region FA_3.

[0070] Reference Figure 4A , a voltage may be applied to the power pad PP. When a voltage is applied to the power pad PP, a current may flow to the back-end wiring region BR via the first through-electrode 150_1. For example, a current may sequentially pass through the first through-electrode 150_1, the first wiring line M1, and the wiring contact portion MC, and may flow to the third wiring line M3. In other words, a first current path CP11 may be formed through the first through-electrode 150_1 in a vertical direction (Z direction).

[0071] Reference Figure 4B , the current can flow from the first source / drain region 130_1 to the first area FA_1. For example, the current can flow from the third wiring line M3 through the wiring contact MC, the second wiring line M2, the source / drain via contact VA, and the source / drain contact CA in sequence, and enter the middle line region MR (i.e., the first source / drain region 130_1). Next, the current can flow from the first source / drain region 130_1 to the channel region CR (i.e., the first area FA_1). In other words, the second current path CP12 after the first current path CP11 can be formed to pass through the first source / drain region 130_1 in the vertical direction (Z direction) until the first area FA_1.

[0072] Reference Figure 4C, the current may flow from the first region FA_1 to the second region FA_2, i.e., CP13_1, and / or from the first region FA_1 to the third region FA_3, i.e., CP13_2. In other words, the third current path CP13 after the second current path CP12 may include a current path formed along the first horizontal direction (X direction) from the first region FA_1 to the second region FA_2 and / or the third region FA_3.

[0073] Reference Figure 4D , the current may flow from the second region FA_2 to the ground pad GP via the second source / drain region 130_2, and / or the current may flow from the third region FA_3 to the ground pad GP via the third source / drain region 130_3. For example, the current may flow from the second region FA_2 through the second source / drain region 130_2, the source / drain contact CA, and the source / drain via contact VA, which may collectively form the first flow line CP14_1, to the second wiring line M2, and then, may flow through the second through electrode 150_2 to the ground pad GP. The current may flow to the outside of the integrated circuit device 100_1 through the ground pad GP. Similarly, the current may flow from the third region FA_3 through the third source / drain region 130_3, the source / drain contact CA, and the source / drain via contact VA, which may collectively form the second flow line CP14_2, to the second wiring line M2, and then, may flow through the second through electrode 150_2 to the ground pad GP. In other words, the current may flow from the channel region CR through the middle line region MR to the back line region BR, and may flow to the outside of the integrated circuit device 100_1. In other words, the fourth current path CP14 after the third current path CP13 may include a current path formed from the second region FA_2 to the second source / drain region 130_2 and / or from the third region FA_3 to the third source / drain region 130_3, and a current path formed along the vertical direction (Z direction) through the second through electrode 150_2.

[0074] Already referred to FIG. 4A to FIG. 4D The current flow inside the integrated circuit device 100_1 is described. As described above, the integrated circuit device 100_1 may include an ESD element, and therefore, the voltage applied to the power pad PP may include an abnormal current (ie, static electricity). In other words, when static electricity is generated, by referring to FIG. 4A to FIG. 4D By describing the current path, static electricity can be discharged via the ground pad GP.

[0075] Figure 5A and Figure 5D is a cross-sectional view of an integrated circuit device 100_2 according to an embodiment of the inventive concept. FIG. 5A to FIG. 5D is a cross-sectional view for describing a current path in the integrated circuit device 100_2.

[0076] like FIG. 5A to FIG. 5D As shown, the integrated circuit device 100_2 may include a first region FA_1 and a first source / drain region 130_1 doped with P type, and may include a second region FA_2, a third region FA_3, a second source / drain region 130_2 and a third source / drain region 130_3 doped with N type.

[0077] For example, the first region FA_1 may be doped with P well or P - type, and the first source / drain region 130_1 may be doped with P + In other words, the first source / drain region 130_1 may include a P type having a concentration greater than that of the first region FA_1. For example, the second region FA_2 may be doped with an N well or N - type, and the second source / drain region 130_2 may be doped with N + In other words, the second source / drain region 130_2 may include an N-type having a concentration greater than that of the second region FA_2. For example, the third region FA_3 may be doped with an N-well or N- - type, and the third source / drain region 130_3 may be doped with N + In other words, the third source / drain region 130_3 may include an N type having a concentration greater than that of the third region FA_3.

[0078] Reference Figure 5A , a voltage may be applied to the power pad PP. When a voltage is applied to the power pad PP, a current may flow to the back-end wiring region BR via the first through-electrode 150_1. For example, a current may sequentially pass through the first through-electrode 150_1, the first wiring line M1, and the wiring contact portion MC, and may flow to the third wiring line M3. In other words, a first current path CP21 may be formed through the first through-electrode 150_1 in a vertical direction (Z direction).

[0079] Reference Figure 5B, the current may flow from the second source / drain region 130_2 to the second area FA_2 and / or from the third source / drain region 130_3 to the third area FA_3. For example, the current may flow out from the third wiring line M3 and sequentially pass through the wiring contact MC, the second wiring line M2, the source / drain via contact VA and the source / drain contact CA, and enter the middle line region MR (i.e., the second source / drain region 130_2 and / or the third source / drain region 130_3). Next, the current may flow from the second source / drain region 130_2 to the channel region CR (i.e., the second area FA_2), and / or the current may flow from the third source / drain region 130_3 to the third area FA_3. For example, the current may flow through the first flow line CP221 that may be provided by the second source / drain region 130_2 and the second area FA_2, and / or the current may flow through the second flow line CP222 that may be provided by the third source / drain region 130_3 and the third area FA_3. In other words, the second current path CP22 after the first current path CP21 may include a current path formed from the second source / drain region 130_2 to the second area FA_2 along the vertical direction (Z direction), and / or a current path formed from the third source / drain region 130_3 to the third area FA_3 along the vertical direction (Z direction).

[0080] Reference Figure 5C , the current may flow from the second area FA_2 to the first area FA_1, and / or from the third area FA_3 to the first area FA_1. For example, the current may flow through the first flow line CP23_1 that may be provided by the second area FA_2 and the first area FA_1, and / or the current may flow through the second flow line CP232 that may be provided by the third area FA_3 and the first area FA_1. In other words, the third current path CP23 after the second current path CP22 may include a current path formed from the second area FA_2 to the first area FA_1 along the first horizontal direction (X direction), and / or a current path formed from the third area FA_3 to the first area FA_1 along the first horizontal direction (X direction).

[0081] Reference Figure 5D, the current may flow from the first region FA_1 through the first source / drain region 130_1 to the ground pad GP. For example, the current may flow from the first region FA_1 through the first source / drain region 130_1, the source / drain contact CA, and the source / drain via contact VA to the second wiring line M2, and then, may flow through the second through electrode 150_2 to the ground pad GP. The current may flow to the outside of the integrated circuit device 1002 through the ground pad GP. In other words, the current may flow from the channel region CR through the middle line region MR to the back end line region BR, and may flow to the outside of the integrated circuit device 100_1. In other words, the fourth current path CP24 after the third current path CP23 may include a current path formed from the first region FA_1 to the first source / drain region 130_1, and a current path formed along the vertical direction (Z direction) through the second through electrode 150_2.

[0082] Fig. 6A and Figure 6B is a cross-sectional view of an example configuration of an integrated circuit device 200 according to an embodiment of the inventive concept. Fig. 6A is along Figure 1 A cross-sectional view taken along line XX in FIG. Figure 6B is along Figure 1 Main description and reference Figure 1 , Figure 2A and Figure 2B The differences in the integrated circuit device 100 are described.

[0083] Reference Fig. 6A and Figure 6B , the integrated circuit device 200 may further include a plurality of nanosheet stacks NSS, and the plurality of nanosheet stacks NSS are in contact with the plurality of source / drain regions 230 between each of the plurality of source / drain regions 230. The plurality of source / drain regions 230 may be connected to the wiring lines M1, M2, and M3 via source / drain contacts CA penetrating the insulating liner 242 and the inter-gate insulating layer 244 and source / drain via contacts VA2 penetrating the upper insulating structure 280. The upper insulating structure 280 may include an etching stop layer 282 and an interlayer insulating layer 284. The back insulating layer 201 may be arranged on the second surface 202_2 of the substrate 202.

[0084] In the region where the plurality of fin-type active areas FA and the plurality of filling insulating layers 261 intersect each other, a plurality of nanosheet stacks NSS may be disposed on the fin top surface FT of each of the plurality of fin-type active areas FA. Each of the plurality of nanosheet stacks NSS may include at least one nanosheet facing the fin top surface FT, the at least one nanosheet being spaced apart from the fin top surface FT of the fin-type active area FA in the vertical direction (Z direction). The term "nanosheet" used in the inventive concept may refer to a conductive structure having a cross section substantially perpendicular to the direction of current flow. The nanosheet should be understood to include nanowires.

[0085] like Fig. 6A and Figure 6B As shown, each of the plurality of nanosheet stacks NSS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 overlapping each other in the vertical direction (Z direction) on the fin-type active area FA. The vertical distances (Z direction distances) of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 from the fin top surface FT of the fin-type active area FA may be different from each other. Each of the plurality of filling insulating layers 261 may surround the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 overlapping each other.

[0086] In this example, a configuration is shown in which a plurality of nanosheet stacks NSS and a plurality of filling insulating layers 261 are formed on one fin-type active area FA, and the plurality of nanosheet stacks NSS are arranged in a row along the first horizontal direction (X direction) on the one fin-type active area FA. However, the number of each nanosheet stack NSS and filling insulating layer 261 arranged above one fin-type active area FA is not particularly limited.

[0087] like Fig. 6A As shown, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in a nanosheet stack NSS may have the same or similar sizes as each other in the first horizontal direction (X direction). Fig. 6A , at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in one nanosheet stack NSS may have different sizes from each other in the first horizontal direction (X direction). In this example, the case where each of the plurality of nanosheet stacks NSS includes three nanosheets is an example, but the inventive concept is not limited thereto. For example, the nanosheet stack NSS may include at least one nanosheet, and the number of nanosheets constituting the nanosheet stack NSS is not particularly limited.

[0088] like Fig. 6A and Figure 6BAs shown, each of the plurality of filling insulating layers 261 may include a first filling insulating layer 261_1 and a plurality of second filling insulating layers 261_2. The first filling insulating layer 261_1 may cover the upper surface of the nanosheet stack NSS and extend along the second horizontal direction (Y direction). The plurality of second filling insulating layers 261_2 may be integrally connected to the first filling insulating layer 261_1, and each of the plurality of second filling insulating layers 261_2 may be arranged between each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and between the first nanosheet N1 and the fin-type active area FA. In the vertical direction (Z direction), the thickness of each of the plurality of second filling insulating layers 261_2 may be less than the thickness of the first filling insulating layer 261_1.

[0089] 7A to 7O is a cross-sectional view illustrating a method of manufacturing the integrated circuit device 100 according to an embodiment of the inventive concept. 7A to 7O is along Figure 1 A cross-sectional view taken along line XX in FIG.

[0090] Reference Fig. 7A , a plurality of sacrificial semiconductor layers 103 and a plurality of nanosheet semiconductor layers NS may be alternately stacked on the substrate 102. In an embodiment of the inventive concept, the fin-type active area FA of the substrate 102 may be doped with the second conductivity type. For example, the fin-type active area FA may be doped with the second conductivity type at a low concentration. In an embodiment of the inventive concept, the fin-type active area FA may include a P-well region. In an embodiment of the inventive concept, the fin-type active area FA may include an N-well region.

[0091] The plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS may include semiconductor materials having different etching selectivities from each other. In an embodiment of the inventive concept, the plurality of nanosheet semiconductor layers NS may include a Si layer, and the plurality of sacrificial semiconductor layers 103 may include a SiGe layer. In an embodiment of the inventive concept, the Ge content in the plurality of sacrificial semiconductor layers 103 may be substantially constant. The SiGe layer constituting the plurality of sacrificial semiconductor layers 103 may have a substantially constant Ge content in the range of about 5 atomic percent (atom%) to about 60atom%, for example, about 10atom% to about 40atom%. The Ge content in the SiGe layer constituting the plurality of sacrificial semiconductor layers 103 may be selected differently as needed.

[0092] Reference Figure 7B, the first area FA_1, the second area FA_2, and the third area FA_3 may be formed by performing a doping process of a first conductivity type different from the second conductivity type on a partial area of ​​the fin type active area FA. The doping process of the first conductivity type may be performed at a concentration higher than the concentration of the existing second conductivity type. The remaining partial areas where the doping process of the first conductivity type has not been performed may be spaced apart from each other, and the first area FA_1 is disposed between them. For example, a first area FA_1 including a first conductivity type may be formed, and a second area FA_2 and a third area FA_3 including a second conductivity type may be formed, the second area FA_2 and the third area FA_3 are spaced apart from each other, and the first area FA_1 is disposed between the second area FA_2 and the third area FA_3.

[0093] Reference Figure 7C , a plurality of dummy gate structures DGS may be formed on the stacked structure of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS.

[0094] Each of the plurality of dummy gate structures DGS may be formed to extend along the second horizontal direction (Y direction). Each of the plurality of dummy gate structures DGS may have a structure in which an oxide layer D122, a dummy gate layer D124, and a capping layer D126 are sequentially stacked. In an embodiment of the inventive concept, the dummy gate layer D124 may include polysilicon, and the capping layer D126 may include a silicon nitride layer.

[0095] Reference Fig.7D , after forming a plurality of outer insulating spacers 118 covering both sidewalls of each of the plurality of dummy gate structures DGS, a portion of each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS and a portion of the fin-type active area FA may be etched by using the plurality of dummy gate structures DGS and the plurality of outer insulating spacers 118 as etching masks. In addition, the plurality of nanosheet semiconductor layers NS may be divided into a plurality of nanosheet stacks NSS, and a plurality of recessed portions may be formed on an upper portion of the fin-type active area FA. Each of the plurality of nanosheet stacks NSS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3. In order to form the plurality of recessed portions, an etching process may be performed by using a dry etching operation, a wet etching operation, or a combination thereof.

[0096] Reference Fig. 7E, a plurality of first source / drain regions 130 may be formed inside each of the plurality of recessed portions. The first source / drain region 130_1 may be formed on the first region FA_1. For example, the first source / drain region 130_1 having the first conductivity type may be formed on the first region FA_1 having the first conductivity type. The second source / drain region 130_2 may be formed on the second region FA_2. For example, the second source / drain region 130_2 having the second conductivity type may be formed on the second region FA_2 having the second conductivity type. The third source / drain region 130_3 may be formed on the third region FA_3. For example, the third source / drain region 130_3 having the second conductivity type may be formed on the third region FA_3 having the second conductivity type.

[0097] In an embodiment of the present invention, in order to form a plurality of source / drain regions 130, semiconductor material may be epitaxially grown from a surface of the fin-type active area FA exposed on the bottom of the recess, a sidewall of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS, and a sidewall of each of the plurality of sacrificial semiconductor layers 103.

[0098] Reference Figure 7F , in forming a covering layer in which a plurality of source / drain regions 130 are formed Fig. 7E The insulating liner 142 of the resultant product is formed, and after forming the inter-gate insulating layer 144 on the insulating liner 142 , the insulating liner 142 and the inter-gate insulating layer 144 may be planarized to expose the upper surface of the capping layer D126 .

[0099] Reference Figure 7G The capping layer D126 can be removed to expose the upper surface of the dummy gate layer D124, and the insulating liner 142 and the inter-gate insulating layer 144 can be partially removed so that the upper surface of the insulating liner 142, the upper surface of the inter-gate insulating layer 144, and the upper surface of the dummy gate layer D124 are approximately at the same level with each other.

[0100] Reference Figure 7H , the dummy gate layer D124 and the oxide layer D122 disposed under the dummy gate layer D124 may be removed to prepare a main gate space GSM, and the plurality of nanosheet stacks NSS may be exposed through the main gate space GSM.

[0101] Next, the plurality of sacrificial semiconductor layers 103 remaining on the fin type active area FA may be removed through the main gate space GSM to provide a sub gate space GSS between each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and between the first nanosheet N1 and the upper surface of the fin type active area FA.

[0102] In an embodiment of the inventive concept, in order to selectively remove the plurality of sacrificial semiconductor layers 103 , a difference in etching selectivity between the first nanosheet N1 , the second nanosheet N2 , and the third nanosheet N3 and the plurality of sacrificial semiconductor layers 103 may be utilized.

[0103] Reference Fig.7I , a gate dielectric layer 152 may be formed in the main gate space GSM and the sub-gate space GSS. A gate dielectric layer 152 covering the exposed surface of the third nanosheet N3 may be formed in the main gate space GSM. A gate dielectric layer 152 covering the first nanosheet N1 to the third nanosheet N3 may be formed in the sub-gate space GSS. An atomic layer deposition (ALD) process may be used to form the gate dielectric layer 152.

[0104] Reference Figure 7J , a gate-forming conductive layer 160L filling the main gate space GSM and the sub-gate space GSS and simultaneously covering the upper surface of the inter-gate insulating layer 144 may be formed. For example, the gate-forming conductive layer 160L may include a metal, a metal nitride, a metal carbide, or a combination thereof. An ALD process or a CVD process may be used to form the gate-forming conductive layer 160L.

[0105] Reference Figure 7K , a portion of the gate-forming conductive layer 160L may be removed from the upper surface of the gate-forming conductive layer 160L, so that the upper surface of the insulating liner 142 and the upper surface of the inter-gate insulating layer 144 are exposed, and the main gate space (see Figure 7J A portion of the upper side of the main gate space GSM) is emptied again. As a result, a plurality of gate lines 160 may be formed from the gate-forming conductive layer 160L. In this case, in the main gate space GSM, the gate dielectric layer 152 and the outer insulating spacer 118 may be partially consumed from the upper side of each of them, so that the height of each of the gate dielectric layer 152 and the outer insulating spacer 118 may be reduced. Next, a capping insulating pattern 165 filling the main gate space GSM may be formed on the gate line 160.

[0106] Reference Figure 7L , the gate lines 160 between the plurality of source / drain regions 130 may be removed, and a filling insulating layer 161 extending along the second horizontal direction (Y direction) may be formed by filling an insulating material in a space formed by the removed gate lines 160 .

[0107] By using a non-selective etching process, the gate line 160, the gate dielectric layer 152, and the first to third nanosheets N1 to N3 between the plurality of source / drain regions 130 may be removed together. For example, by using a dry etching process, the gate line 160, the gate dielectric layer 152, and the first to third nanosheets N1 to N3 between the plurality of source / drain regions 130 may be removed. In this case, the capping insulating pattern 165 and the outer insulating spacer 118 on the gate line 160 may be removed together.

[0108] Reference Figure 7M , a source / drain contact hole may be formed, the source / drain contact hole penetrating the insulating structure including the insulating liner 142 and the inter-gate insulating layer 144 and exposing the source / drain region 130. Thereafter, a metal silicide layer 172 may be formed on the exposed source / drain region 130, and a source / drain contact portion CA including a conductive barrier pattern 174 and a contact plug 176 may be formed on the metal silicide layer 172.

[0109] Next, an upper insulating structure 180 including an etch stop layer 182 and an interlayer insulating layer 184 may be formed on the insulating liner 142 , the intergate insulating layer 144 , and the source / drain contacts CA. Next, a plurality of source / drain via contacts VA penetrating the upper insulating structure 180 may be formed.

[0110] Next, a first wiring line M1, a second wiring line M2 and a third wiring line M3 extending along the first horizontal direction (X direction) on multiple source / drain via contact portions VA, and multiple wiring contact portions MC providing electrical connections between the first wiring line M1, the second wiring line M2 and the third wiring line M3 can be formed.

[0111] Reference Figure 7N , Figure 7M The resulting product may be flipped relative to the vertical direction (Z direction). Thereafter, a portion of the substrate 102 may be removed. For example, a thinning operation may be performed on the substrate 102. For example, a grinding operation may be performed on the second surface 102_2 of the substrate 102.

[0112] Reference Fig.7O , a back insulating layer 101 may be disposed on the second surface 102_2 of the substrate 102, and a first through electrode 150_1 and a second through electrode 150_2 may be formed penetrating the back insulating layer 101. Next, a power pad PP connected to the first through electrode 150_1 and a ground pad GP connected to the second through electrode 150_2 may be formed to manufacture the integrated circuit device 100.

[0113] In other words, according to the reference 7A to 7OThe manufacturing method of the integrated circuit device 100 according to the embodiment of the present invention can provide such an integrated circuit device 100: even if a portion of the substrate 102 is removed, current flows between the uncut first area FA_1 and the second area FA_2 and between the first area FA_1 and the third area FA_3. In other words, an integrated circuit device 100 with improved electrostatic performance and reliability can be provided.

[0114] Refer to above 7A to 7O Describes the manufacturing Figure 1 , Figure 2A and Figure 2B The example method of the integrated circuit device 100 shown in FIG. 1 is shown in FIG. 1 , however, those skilled in the art should appreciate that by applying reference to FIG. 1 within the scope of the present invention, 7A to 7O Various modifications and changes given the description can be made Figure 3 , FIG. 4A to FIG. 4D as well as FIG. 5A to FIG. 5D The integrated circuit devices 100A, 100_1 and 100_2 shown, and integrated circuit devices to which various structural modifications and changes are made.

[0115] FIG. 8A to FIG. 8D is a cross-sectional view illustrating a method of manufacturing an integrated circuit device 200 according to an embodiment of the inventive concept. FIG. 8A to FIG. 8D is a cross-sectional view showing a method of manufacturing an integrated circuit device 200 according to a process sequence, showing a Figure 7L The method of fabricating the integrated circuit device 200 follows the fabrication operations described. FIG. 8A to FIG. 8D is along Figure 1 A cross-sectional view taken along line XX in FIG.

[0116] Reference Fig. 8A The gate lines 260 between the plurality of source / drain regions 230 may be removed, and a filling insulating layer 261 extending along the second horizontal direction (Y direction) may be formed by filling an insulating material in a space formed by removing the gate lines 260 .

[0117] For example, the gate line 260 between the plurality of source / drain regions 230 may be removed using a selective etching process. In this case, the first to third nanosheets N1 to N3 may remain without being removed due to a difference in etching selectivity with the gate line 260. In an embodiment of the inventive concept, the gate dielectric layer 252 and the capping insulating pattern 265 may be removed together.

[0118] Thereafter, by filling the removed space with an insulating material, a filling insulating layer 261 extending in the second horizontal direction (Y direction) and surrounding the first, second, and third nanosheets N1, N2, and N3 may be formed.

[0119] Reference Figure 8B , and reference Figure 7M Similar to the description given, a plurality of source / drain contacts CA and a plurality of source / drain via contacts VA may be formed. Next, a first wiring line M1, a second wiring line M2, and a third wiring line M3 extending along a first horizontal direction (X direction) on the plurality of source / drain via contacts VA, and a plurality of wiring contacts MC providing electrical connections between the first wiring line M1, the second wiring line M2, and the third wiring line M3 may be formed.

[0120] Reference Figure 8C , and reference Figure 7N The description given is similar to, Figure 8B The resulting product may be flipped relative to the vertical direction (Z direction). Thereafter, a portion of the substrate 202 may be removed. For example, a grinding operation may be performed on the second surface 202_2 of the substrate 202.

[0121] Reference Fig.8D , and reference Fig.7O Similar to the description given, first and second through electrodes 250_1 and 250_2 penetrating the silicon wafer 201 disposed on the second surface 202_2 of the substrate 202 may be formed. Next, a power pad PP connected to the first through electrode 250_1 and a ground pad GP connected to the second through electrode 250_2 may be formed to manufacture the integrated circuit device 200.

[0122] Fig.9A and Fig.9D 3 is a cross-sectional view of integrated circuit devices 300A, 300B, 300C, and 300D according to an embodiment of the inventive concept. Figure 1 , Figure 2A and Figure 2B The differences of the integrated circuit device 100 are described, and redundant descriptions may be omitted or briefly discussed.

[0123] Reference Fig.9A , the integrated circuit device 300A may include a first fin type active area FAA extending along a first horizontal direction (X direction) on a substrate 302. The fin type active area FAA may include a first region FAA_1, a second region FAA_2, and a third region FAA_3 adjacent to each other in the first horizontal direction (X direction), and the second region FAA_2 and the third region FAA_3 may be spaced apart from each other, and the first region FAA_1 is disposed between the second region FAA_2 and the third region FAA_3.

[0124] A plurality of source / drain regions 330A may be formed on the fin active area FAA. A first source / drain region 330A_1 may be formed on the first area FAA_1, and a second source / drain region 330A_2 may be formed on the second area FAA_2. A third source / drain region 330A_3 may be formed on the third area FAA_3.

[0125] In an embodiment of the inventive concept, the first region FAA_1 may be doped with N type, and the second and third regions FAA_2 and FAA_3 may each be doped with P type. The first, second, and third source / drain regions 330A_1, 330A_2, and 330A_3 may all be doped with N type.

[0126] The first region FAA_1 may be doped with N-type (N-well) at a low concentration, and the second region FAA_2 and the third region FAA_3 may each be doped with P-type (P-well) at a low concentration. Each of the first source / drain region 330A_1, the second source / drain region 330A_2, and the third source / drain region 330A_3 may be doped with a concentration (N-type) higher than that of each of the first region FAA_1, the second region FAA_2, and / or the third region FAA_3. + ) is doped with N-type.

[0127] Reference Fig. 9B , the integrated circuit device 300B may include a fin-type active region FAB extending along a first horizontal direction (X direction) on a substrate 302. A plurality of source / drain regions 330B may be formed on the fin-type active region FAB. A first source / drain region 330B_1, a second source / drain region 330B_2, and a third source / drain region 330B_3 may be formed on the fin-type active region FAB.

[0128] In an embodiment of the inventive concept, the fin type active region FAB may be doped with a P type. The first source / drain region 330B_1 , the second source / drain region 330B_2 , and the third source / drain region 330B_3 may all be doped with an N type.

[0129] The fin type active region FAB may be doped with a P type (P well) at a low concentration. The first source / drain region 330A_1, the second source / drain region 330A_2, and the third source / drain region 330A_3 may all be doped with a concentration (N) higher than that of the fin type active region FAB. + ) is doped with N-type.

[0130] Reference Fig. 9C, the integrated circuit device 300C may include a fin-type active region FAC extending along a first horizontal direction (X direction) on a substrate 302. A plurality of source / drain regions 330C may be formed on the fin-type active region FAC. A first source / drain region 330C_1, a second source / drain region 330C_2, and a third source / drain region 330C_3 may be formed on the fin-type active region FAC.

[0131] In an embodiment of the present inventive concept, the fin active region FAC may be doped with a P type. The first source / drain region 330C_1 may be doped with an N type, and the second source / drain region 330C_2 and the third source / drain region 330C_3 may each be doped with a P type. For example, the second source / drain region 330C_2 and the third source / drain region 330C_3 doped with a P type may be spaced apart from each other, and the first source / drain region 330C_1 doped with an N type is disposed between the second source / drain region 330C_2 and the third source / drain region 330C_3.

[0132] The fin type active region FAC may be doped with a P type (P well) at a low concentration. The first source / drain region 330C_1 may be doped with a concentration (N ) higher than that of the fin type active region FAC. + ) is doped with N type. The second source / drain region 330C_2 and the third source / drain region 330C_3 may be doped with N type at a concentration (P) higher than that of the fin type active region FAC. + ) is doped with P type.

[0133] Reference Fig.9D , the integrated circuit device 300D may include a fin-type active region FAD extending along a first horizontal direction (X direction) on a substrate 302. A plurality of source / drain regions 330D may be formed on the fin-type active region FAD. A first source / drain region 330D_1, a second source / drain region 330D_2, and a third source / drain region 330D_3 may be formed on the fin-type active region FAD.

[0134] In an embodiment of the inventive concept, the fin active region FAD may be doped with an N type. The first source / drain region 330D_1 may be doped with an N type, and the second source / drain region 330D_2 and the third source / drain region 330D_3 may each be doped with a P type. For example, the second source / drain region 330D_2 and the third source / drain region 330D_3 doped with a P type may be spaced apart from each other, and the first source / drain region 330D_1 doped with an N type is disposed between the second source / drain region 330D_2 and the third source / drain region 330D_3.

[0135] The fin type active region FAD may be doped with N type (N well) at a low concentration. The first source / drain region 330D_1 may be doped with N type (N well) at a concentration higher than that of the fin type active region FAD. +) is doped with N type. The second source / drain region 330D_2 and the third source / drain region 330D_3 may be doped with N type at a concentration (P) higher than that of the fin type active region FAD. + ) is doped with P type.

[0136] While the inventive concepts have been described with reference to example embodiments of the inventive concepts, persons skilled in the art will understand that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concepts.

Claims

1. An integrated circuit device comprising: a substrate including a first surface and a second surface opposite to each other; a fin-type active region extending along a first horizontal direction on the first surface of the substrate and comprising a first region and a second region adjacent to each other in the first horizontal direction; A first source / drain region, arranged on the first region of the fin-type active region; A second source / drain region, arranged on the second region of the fin type active region; as well as a filling insulating layer extending between the first source / drain region and the second source / drain region along a second horizontal direction intersecting the first horizontal direction, The first region of the fin-type active region includes a first conductivity type. wherein the second region of the fin-type active region comprises a second conductivity type different from the first conductivity type, and The boundary between the first region and the second region of the fin-type active region includes a portion that is substantially perpendicular to the first horizontal direction and overlaps the filling insulating layer.

2. The integrated circuit device according to claim 1, Also includes: a plurality of nanosheets, contacting the first source / drain region and the second source / drain region, and arranged between the first source / drain region and the second source / drain region, The filling insulating layer surrounds each of the plurality of nanosheets.

3. The integrated circuit device according to claim 1, wherein: The first source / drain region includes the first conductivity type, and the second source / drain region includes the second conductivity type.

4. The integrated circuit device according to claim 1, wherein: A current path is formed in the fin type active region along the first horizontal direction.

5. The integrated circuit device according to claim 1, Also includes: a power pad and a ground pad, each arranged on the second surface of the substrate, Wherein the integrated circuit device is configured to allow current to flow between the first region and the second region when a voltage is applied to the power pad.

6. The integrated circuit device according to claim 5, in, The first conductivity type includes an N type, and the second conductivity type includes a P type, and A current path is formed in the fin-type active region from the first region to the second region.

7. The integrated circuit device according to claim 1, further comprising: a third region spaced apart from the second region, the first region being disposed between the third region and the second region, wherein the third region is adjacent to the first region; and a third source / drain region, arranged on the third region of the fin-type active region, wherein the third region includes the second conductivity type, and The boundary between the first region and the third region of the fin-type active region includes a portion substantially perpendicular to the first horizontal direction.

8. The integrated circuit device according to claim 1, wherein: The first source / drain region and the second source / drain region each include a first conductivity type or a second conductivity type.

9. An integrated circuit device comprising: a substrate including a first surface and a second surface opposite to each other; a fin-type active region extending along a first horizontal direction on the first surface of the substrate and comprising a first region and a second region adjacent to each other in the first horizontal direction; A first source / drain region, arranged on the first region of the fin-type active region; A second source / drain region, arranged on the second region of the fin type active region; A filling insulating layer extending between the first source / drain region and the second source / drain region along a second horizontal direction intersecting the first horizontal direction; as well as a power pad and a ground pad, each arranged on the second surface of the substrate, wherein each of the first region and the first source / drain region of the fin-type active region comprises a first conductivity type, wherein each of the second region and the second source / drain region of the fin-type active region comprises a second conductivity type different from the first conductivity type, and Wherein, a current path is formed in the fin-type active area along the first horizontal direction.

10. The integrated circuit device according to claim 9, further comprising: a back insulating layer, disposed on the second surface of the substrate; a first through electrode penetrating the back insulating layer and connected to the power pad; a second through electrode penetrating the back insulating layer and connected to the ground pad; a first contact portion connected to the first source / drain region; as well as The second contact portion is connected to the second source / drain region.

11. The integrated circuit device according to claim 10, wherein: The integrated circuit device is configured to allow current to flow from the first through-electrode to the first source / drain region via the first contact when a voltage is applied to the power pad.

12. The integrated circuit device according to claim 10, wherein: The integrated circuit is configured to allow current to flow from the second source / drain region to the second through-electrode via the second contact.

13. The integrated circuit device according to claim 9, in, The first conductivity type includes an N type, and the second conductivity type includes a P type, and A current path is formed in the fin-type active region from the first region to the second region.

14. The integrated circuit device according to claim 9, in, The first region of the fin-type active region is doped with a first concentration, wherein the first source / drain region is doped with a second concentration higher than the first concentration, The second region of the fin-type active region is doped with a third concentration, and The second source / drain region is doped with a fourth concentration higher than the third concentration.

15. The integrated circuit device according to claim 9, wherein: A boundary between the first region and the second region of the fin type active region includes a portion that is substantially perpendicular to the first horizontal direction and overlaps the filling insulation layer.

16. An integrated circuit device comprising: a substrate including a first surface and a second surface opposite to each other; a fin-type active region extending along a first horizontal direction on the first surface of the substrate, wherein the fin-type active region includes a first region, a second region, and a third region, the third region is spaced apart from the second region, and the first region is disposed between the third region and the second region, wherein the first region, the second region, and the third region are arranged along the first horizontal direction; A first source / drain region, arranged on the first region of the fin-type active region; A second source / drain region, arranged on the second region of the fin type active region; A third source / drain region, arranged on the third region of the fin-type active region; A filling insulating layer extending between the first source / drain region and the second source / drain region and between the first source / drain region and the third source / drain region; and a power pad and a ground pad, each arranged on the second surface of the substrate, The first region of the fin-type active region includes a first conductivity type. wherein each of the second region and the third region of the fin-type active region comprises a second conductivity type different from the first conductivity type, wherein the first source / drain region comprises the first conductivity type, wherein each of the second source / drain region and the third source / drain region comprises the second conductivity type, and Each of a boundary between the first region and the second region of the fin-type active region and a boundary between the first region and the third region includes a portion substantially perpendicular to the first horizontal direction and overlapping the filling insulating layer.

17. The integrated circuit device according to claim 16, Also includes: a plurality of nanosheets, contacting the first source / drain region and the second source / drain region, and arranged between the first source / drain region and the second source / drain region, The filling insulating layer surrounds each of the plurality of nanosheets.

18. The integrated circuit device according to claim 16, wherein: A current path is formed in the fin type active region along the first horizontal direction.

19. The integrated circuit device according to claim 16, wherein: The integrated circuit device is configured to allow current to flow between the first region and the second region and between the first region and the third region when a voltage is applied to the power pad.

20. The integrated circuit device according to claim 19, in, The first conductivity type includes an N type, and the second conductivity type includes a P type, wherein a current path is formed from the first region to the second region, and A current path is formed from the first region to the third region.

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