Light emitting diode chip and preparation method thereof

Abstract

The invention provides a light-emitting diode chip and a preparation method thereof, and the light-emitting diode chip comprises a conductive silicon wafer, a metal bonding layer, an N-type conductive metal layer, a first insulation protection layer, a P-type conductive metal layer, a P-type reflection metal layer, a current blocking layer, a current expansion layer, and an epitaxial layer which are stacked from bottom to top. The projection of the edge of the P-type conductive metal layer on the current expansion layer is located in the projection of the isolation groove on the current expansion layer, and the ratio of the distance between the projection of the edge of the P-type conductive metal layer on the current expansion layer and the projection of the edge of the isolation groove on the current expansion layer to the width of the isolation groove is 1 / 3-2 / 3. The isolation groove and the cutting wall are arranged on the current expansion layer, and the distance proportion relation between the edge of the P-type conductive metal layer and the isolation groove is favorable for controlling the distribution of current in the light-emitting diode chip, so that the current is prevented from being excessively concentrated, the current is more uniformly expanded to the epitaxial layer, and the overall light-emitting efficiency and stability of the light-emitting diode chip are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a light emitting diode chip and a preparation method thereof. Background Art

[0002] Light-emitting diode chips are energy-efficient and highly efficient, and are widely used in the fields of lighting and display, many of which involve applications with extremely high power, such as outdoor lighting and automotive lighting.

[0003] However, in the prior art, the luminous efficiency of light-emitting diode chips is relatively low and needs to be improved urgently to meet high-power scene applications. Summary of the invention

[0004] In view of the above situation, it is necessary to provide a light emitting diode chip and a method for manufacturing the same to address the problem in the prior art that the bottom of the electrode is too wide and absorbs a large amount of emitted light.

[0005] A light-emitting diode chip, comprising a conductive silicon wafer, a metal bonding layer, an N-type conductive metal layer, a first insulating protection layer, a P-type conductive metal layer, a P-type reflective metal layer, a current blocking layer, a current spreading layer and an epitaxial layer stacked from bottom to top; An isolation groove and a cutting wall are arranged on opposite sides of the current spreading layer, the isolation groove is located between the epitaxial layer and the cutting wall in the horizontal direction, the projection of the edge of the P-type conductive metal layer on the current spreading layer is located within the projection of the isolation groove on the current spreading layer, and the ratio of the distance between the projection of the edge of the P-type conductive metal layer on the current spreading layer and the projection of the edge of the isolation groove on the current spreading layer to the width of the isolation groove is 1 / 3 to 2 / 3, and a second insulating protective layer is arranged on the surface of the epitaxial layer and the cutting wall; A P-type pad layer is disposed on the P-type conductive metal layer.

[0006] Beneficial effects of the present invention: By setting isolation grooves and cutting walls on the current expansion layer, and the edge position of the P-type conductive metal layer has a specific distance ratio relationship with the isolation groove, it is helpful to control the distribution of current in the light-emitting diode chip and avoid excessive concentration of current in certain areas. In the absence of such a structure, the current will form hot spots at the edge of the P-type conductive metal layer, resulting in local overheating and reduced efficiency. With this structure, the current can be more evenly extended to the epitaxial layer, thereby improving the overall luminous efficiency and stability of the light-emitting diode chip.

[0007] Furthermore, the P-type conductive metal layer completely covers the P-type reflective metal layer, and the distance between the edge of the P-type reflective metal layer and the edge of the P-type conductive metal layer is greater than 1 um.

[0008] Furthermore, a projection of an edge of the N-type conductive metal layer on the current spreading layer is located within a projection of an edge of the P-type conductive metal layer on the current spreading layer, and a distance between an edge of the N-type conductive metal layer and an edge of the P-type conductive metal layer is greater than 10 um.

[0009] Furthermore, the side surfaces of the isolation groove and the cutting wall are roughened.

[0010] On the other hand, the present invention further provides a method for preparing a light emitting diode chip, which is used to prepare the light emitting diode chip as described above, comprising the following steps: Providing a substrate, depositing an epitaxial layer and an N-type semiconductor layer conductive step on the substrate; forming a current spreading layer on the epitaxial layer and the conductive steps of the N-type semiconductor layer; forming a current blocking layer on the epitaxial layer and the conductive steps of the N-type semiconductor layer; forming a P-type reflective metal layer on the current blocking layer; forming a P-type conductive metal layer on the P-type reflective metal layer and a portion of the current blocking layer; forming a first insulating protection layer on the P-type conductive metal layer and a portion of the current blocking layer; Forming an N-type conductive metal layer by evaporation on the first insulating protective layer; Forming a first metal bonding layer by evaporation on the N-type conductive metal layer, providing a conductive silicon wafer, forming a second metal bonding layer by evaporation on the conductive silicon wafer, and bonding the first metal bonding layer and the second metal bonding layer to form a metal bonding layer; Using laser to peel off the substrate and the epitaxial layer; Etching part of the epitaxial layer to form an isolation groove and a cutting wall on the current spreading layer, and roughening the side surfaces of the isolation groove and the cutting wall using a KOH solution; A P-type pad layer is formed by evaporating on the P-type conductive metal layer.

[0011] Furthermore, the step of providing a substrate and depositing an epitaxial layer and an N-type semiconductor layer conductive step on the substrate comprises: A substrate is provided, on which an epitaxial layer is deposited by using an MOCVD process, wherein the epitaxial layer comprises an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer stacked from bottom to top, and then a photoresist is coated on the surface of the P-type semiconductor layer, and then a part of the photoresist is removed by exposure and development to expose the P-type semiconductor layer under the part of the photoresist, and then a part of the P-type semiconductor layer and the active light-emitting layer under the P-type semiconductor layer are removed by using an inductively coupled plasma etching process until the N-type semiconductor layer is exposed, and then the photoresist is removed to form a conductive step of the N-type semiconductor layer, and then the photoresist is removed.

[0012] Furthermore, the step of forming a current spreading layer on the epitaxial layer and the conductive steps of the N-type semiconductor layer includes: Indium tin oxide is deposited on the conductive step surfaces of the P-type semiconductor layer and the N-type semiconductor layer by using a magnetron sputtering process, a photoresist is coated on the surface of the indium tin oxide, and then a portion of the photoresist is removed by exposure and development to expose a portion of the indium tin oxide, and then the exposed indium tin oxide is removed by an indium tin oxide etching solution, and then the photoresist is removed to form the current spreading layer.

[0013] Furthermore, the step of forming a current blocking layer on the epitaxial layer and the conductive steps of the N-type semiconductor layer includes: SiO2 is deposited as a current blocking layer on the surface of the P-type semiconductor layer and the N-type semiconductor conductive step by using the PECVD process, and then a photoresist is coated on the surface of the current blocking layer. Then, part of the photoresist is removed by exposure and development to expose the current blocking layer under the photoresist, and then the exposed current blocking layer is removed by BOE etching to form a current blocking layer through hole, and then the photoresist is removed.

[0014] Furthermore, the step of forming a P-type reflective metal layer on the current blocking layer includes: A negative photoresist is coated on the surface of the current blocking layer through hole and the current blocking layer, and then a portion of the photoresist is removed by exposure and development. Ag metal, Ni metal and Ti metal are sequentially evaporated by electron beam evaporation process, and then the metal on the photoresist is removed by lift-off process, and then the photoresist is removed to form a P-type reflective metal layer.

[0015] Furthermore, the step of forming a P-type conductive metal layer on the P-type reflective metal layer and part of the current blocking layer includes: A negative photoresist is coated on the surface of the P-type reflective metal layer and the current blocking layer not covered by the P-type reflective metal layer, and then a portion of the photoresist is removed by exposure and development. Then, Ti metal, Pt metal, Au metal and Cr metal are sequentially evaporated by an electron beam evaporation process, and then the metal located on the photoresist is removed by a Lift-Off process, and then the photoresist is removed to form a P-type conductive metal layer.

[0016] Furthermore, the step of forming a first insulating protection layer on the P-type conductive metal layer and part of the current blocking layer includes: On the surface of the P-type conductive metal layer and the current blocking layer not covered by the P-type conductive metal layer, an Al2O3 layer is first deposited by an atomic layer deposition process, and then a SiO2 layer is deposited by a PECVD process. The Al2O3 layer and the SiO2 layer together constitute a first insulating protective layer. Then, photoresist is coated on the surface of the SiO2 layer. Then, a portion of the photoresist is removed by an exposure and development process to expose the first insulating protective layer under the portion of the photoresist. Then, an ICP etching process is used to remove the exposed portion of the first insulating protective layer and the current blocking layer under the portion of the first insulating protective layer to form an N-type conductive through hole. The N-type conductive through hole is located on the conductive step of the N-type semiconductor layer. Then, the substrate is thinned by a grinding process, and the remaining thickness after thinning is 300um.

[0017] Furthermore, the step of forming an N-type conductive metal layer by evaporating on the first insulating protective layer comprises: Cr metal, Al metal, Ti metal and Pt metal are sequentially deposited on the first insulating protection layer and the N-type conductive through hole by electron beam evaporation process to form an N-type conductive metal layer.

[0018] Further, the steps of forming a first metal bonding layer by evaporating on the N-type conductive metal layer, providing a conductive silicon wafer, forming a second metal bonding layer by evaporating on the conductive silicon wafer, and bonding the first metal bonding layer and the second metal bonding layer to form a metal bonding layer include: A metal bonding layer is evaporated using an electron beam evaporation process, wherein the metal bonding layer includes a first metal bonding layer and a second metal bonding layer, and the first metal bonding layer is formed by evaporation on the N-type conductive metal layer. A conductive silicon wafer is provided, and the second metal bonding layer is formed by evaporation on the conductive silicon wafer. The first metal bonding layer and the second metal bonding layer both include a stack of Ti metal and 2-5 groups of Sn metal and Ni metal, and then the first metal bonding layer and the second metal bonding layer are bonded using a hot pressing bonding process.

[0019] Furthermore, the step of peeling the substrate and the epitaxial layer by using laser comprises: The substrate is irradiated with laser light to decompose Gann at a junction surface between a portion of the substrate and the N-type semiconductor layer to generate metal Ga and N2, thereby decomposing and removing the substrate.

[0020] Furthermore, the step of etching a portion of the epitaxial layer to form an isolation groove and a cutting wall on the current spreading layer, and roughening the side surfaces of the isolation groove and the cutting wall using a KOH solution comprises: After stripping and removing the substrate, the surface of the epitaxial layer is coated with photoresist, and then a mask is used to expose part of the photoresist, and then developed to remove the exposed part of the photoresist, exposing the epitaxial layer under the part of the photoresist, and then, an inductively coupled plasma etching process is used to remove the exposed part of the epitaxial layer, and an isolation groove and a cutting wall are formed on the current spreading layer, and then the sides of the isolation groove and the cutting wall are roughened using a KOH solution, and then the photoresist is removed.

[0021] Further, in said S11, the step of preparing the P-type pad layer includes: Using atomic layer deposition equipment, Al2O3 is deposited on the surface of the remaining epitaxial layer as a second insulating protective layer, and a negative photoresist is coated on the surface of the second insulating protective layer. Then, part of the photoresist is removed by exposure and development to expose part of the second insulating protective layer. Then, BOE is used to corrode the exposed part of the second insulating protective layer and the current blocking layer thereunder until the P-type conductive metal layer is formed to form a P-type conductive metal layer through hole; then, Ti metal, Pt metal, Au metal, Ni metal and Au metal are sequentially evaporated using an electron beam evaporation process; then, the metal on the photoresist is removed using a Lift-Off process, and then the photoresist is removed to form a P-type pad layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0023] Figure 1 This is a schematic structural diagram of a light emitting diode chip according to a first embodiment of the present invention; Figure 2 for Figure 1 The enlarged view of point A in the middle; Figure 3FIG. 4 is a flow chart of the preparation of a light emitting diode chip in the second embodiment of the present invention.

[0024] In the figure: 11, epitaxial layer; 111, N-type semiconductor layer; 112, active light-emitting layer; 113, P-type semiconductor layer; 114, N-type semiconductor layer conductive step; 12, current spreading layer; 13, current blocking layer; 131, current blocking layer through hole; 14, P-type reflective metal layer; 15, P-type conductive metal layer; 16, first insulating protection layer; 161, N-type conductive through hole; 17, N-type conductive metal layer; 18, metal bonding layer; 19, conductive silicon wafer; 201, isolation groove; 202, cutting wall; 21, second insulating protection layer; 22, P-type pad layer.

[0025] The embodiments of the present invention will be further described below with reference to the accompanying drawings. DETAILED DESCRIPTION

[0026] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the embodiments of the present invention, and should not be construed as limiting the present invention.

[0027] In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0028] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0029] Embodiment 1 A light emitting diode chip, see Figure 1 and Figure 2, including a conductive silicon wafer 19, a metal bonding layer 18, an N-type conductive metal layer 17, a first insulating protection layer 16, a P-type conductive metal layer 15, a P-type reflective metal layer 14, a current blocking layer 13, a current spreading layer 12, an epitaxial layer 11, an isolation groove 201, a cutting wall 202, a second insulating protection layer 21 and a P-type pad layer 22 stacked from bottom to top; wherein, the isolation groove 201 and the cutting wall 202 are arranged on opposite sides of the current spreading layer 12, and the isolation groove 201 is located between the epitaxial layer 11 and the cutting wall 202 in the horizontal direction, the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 is located within the projection of the isolation groove 201 on the current spreading layer 12, and the ratio of the distance L1 between the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 and the projection of the edge of the isolation groove 201 on the current spreading layer 12 to the width L of the isolation groove 201 is 1 / 3, and the P-type pad layer 22 is arranged on the P-type conductive metal layer 15.

[0030] Specifically, the P-type conductive metal layer 15 completely covers the P-type reflective metal layer 14 , and the distance between the projection of the edge of the P-type reflective metal layer 14 on the current spreading layer 12 and the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 is 1.2 um.

[0031] Specifically, the projection of the edge of the N-type conductive metal layer 17 on the current spreading layer 12 is located within the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12, and the distance L2 between the projection of the edge of the N-type conductive metal layer 17 on the current spreading layer 12 and the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 is 11um.

[0032] Specifically, the side surfaces of the isolation groove 201 and the cutting wall 202 are roughened.

[0033] It should be noted that the light-emitting diode chip is a stacked structure of a conductive silicon wafer 19 to an epitaxial layer 11, and each layer has a reasonable connection and isolation design (such as a P-type pad layer 22 running through the current spreading layer 12 and the epitaxial layer 11), which improves the overall structural stability of the chip. Under different working environment conditions (such as temperature changes, mechanical stress, etc.), the chip can better maintain its performance and structural integrity.

[0034] It is understandable that the structural layout of different layers such as the current spreading layer 12 and the P-type conductive metal layer 15 and their relationship with the isolation groove 201 and the cutting wall 202 optimizes the heat dissipation path of the entire light-emitting diode chip. Heat can be dissipated more effectively through the reasonable layout of these structures, thereby improving the heat dissipation performance of the light-emitting diode chip.

[0035] It should be noted that in the light-emitting diode chip, the isolation groove 201 is used to divide different functional areas or circuit elements. Roughening the side of the isolation groove 201 can increase the surface area of ​​the side; when the current passes through the area near the isolation groove 201, the probability of electron scattering increases due to the increase in surface area, which helps to reduce the unevenness of the current density. For example, in a light-emitting diode with a high current density, the smooth side of the isolation groove 201 that has not been roughened may cause the current to accumulate in certain local areas, while the roughened side can disperse the current more evenly, thereby improving the overall luminous efficiency and stability of the chip. Roughening the side of the cutting wall 202 helps to improve the bonding force between the relevant film layer and the side of the cutting wall 202, prevent the relevant film layer from falling off or peeling off, and ensure the integrity of the light-emitting diode chip structure and the stability of its performance.

[0036] In addition, it is important that the isolation groove 201 and the cutting wall 202 are set on the current expansion layer 12, and the edge position of the P-type conductive metal layer 15 has a specific distance ratio relationship with the isolation groove 201, which helps to control the distribution of current in the light-emitting diode chip and avoid excessive concentration of current in certain areas. For example, in a structure without such a precise design, the current will form a hot spot at the edge of the P-type conductive metal layer 15, resulting in local overheating and reduced efficiency. Through this structure, the current can be more evenly extended to the epitaxial layer 11, improving the overall luminous efficiency and stability of the light-emitting diode. The presence of the current blocking layer 13 can effectively prevent the current from diffusing in an unnecessary direction, so that the current passes through the epitaxial layer 11 along a predetermined path, thereby improving the current utilization rate. Combined with the structure of the isolation groove 201 and the cutting wall 202, the direction of the current can be further accurately controlled to ensure that the current is mainly concentrated in the active light-emitting area.

[0037] Embodiment 2 See also Figure 3 This embodiment provides a method for preparing a flip-chip light-emitting diode chip, which is used to prepare the flip-chip light-emitting diode chip described in Embodiment 1. The preparation method comprises the following steps: S1, providing a substrate, and depositing an epitaxial layer 11 and an N-type semiconductor layer conductive step 114 on the substrate; In this embodiment, the specific process for preparing the epitaxial layer 11 and the N-type semiconductor layer conductive step 114 is as follows: A substrate (not shown) is provided, and an epitaxial layer 11 is deposited on the substrate by using an MOCVD process, wherein the epitaxial layer 11 includes an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 stacked from bottom to top, and then a photoresist is coated on the surface of the P-type semiconductor layer 113, and then a portion of the photoresist is removed by exposure and development to expose the P-type semiconductor layer 113 under the portion of the photoresist, and then a portion of the P-type semiconductor layer 113 and the active light-emitting layer 112 under the P-type semiconductor layer 113 are removed by an inductively coupled plasma etching process until the N-type semiconductor layer 111 is exposed, and then the photoresist is removed to form an N-type semiconductor layer conductive step 114, and then the photoresist is removed.

[0038] S2, forming a current spreading layer 12 on the epitaxial layer 11 and the N-type semiconductor layer conductive step 114; The specific process for preparing the current spreading layer 12 in the embodiment is as follows: Indium tin oxide is deposited on the surface of the P-type semiconductor layer 113 and the conductive step 114 of the N-type semiconductor layer by using a magnetron sputtering process, a photoresist is coated on the surface of the indium tin oxide, and then a portion of the photoresist is removed by exposure and development to expose a portion of the indium tin oxide, and then the exposed indium tin oxide is removed by an indium tin oxide etching solution, and then the photoresist is removed to form the current spreading layer 12.

[0039] S3, forming a current blocking layer 13 on the epitaxial layer 11 and the N-type semiconductor layer conductive step 114; The specific process for preparing the current blocking layer 13 in the embodiment is as follows: SiO2 is deposited as a current blocking layer 13 on the surface of the P-type semiconductor layer 113 and the N-type semiconductor layer conductive step 114 by using a PECVD process, and then a photoresist is coated on the surface of the current blocking layer 13. Then, a portion of the photoresist is removed by exposure and development to expose the current blocking layer 13 under the photoresist. Then, the exposed current blocking layer 13 is also removed by BOE etching to form a current blocking layer through hole 131, and then the photoresist is removed.

[0040] S4, forming a P-type reflective metal layer 14 on the current blocking layer 13; The specific process for preparing the P-type reflective metal layer 14 in this embodiment is as follows: A negative photoresist is coated on the surface of the current blocking layer 13 and the current blocking layer through hole 131, and then a portion of the photoresist is removed by exposure and development. Ag metal, Ni metal and Ti metal are sequentially evaporated by electron beam evaporation process, and then the metal on the photoresist is removed by lift-off process, and then the photoresist is removed to form a P-type reflective metal layer 14.

[0041] S5, forming a P-type conductive metal layer 15 on the P-type reflective metal layer 14 and a portion of the current blocking layer 13; In this embodiment, the specific process of preparing the P-type conductive metal layer 15 is as follows: A negative photoresist is coated on the surface of the P-type reflective metal layer 14 and the surface of the current blocking layer 13 not covered by the P-type reflective metal layer 14, and then a portion of the photoresist is removed by exposure and development. Then, an electron beam evaporation process is used to sequentially evaporate Ti metal, Pt metal, Au metal and Cr metal, and then a Lift-Off process is used to remove the metal on the photoresist. Then, the photoresist is removed to form a P-type conductive metal layer 15.

[0042] The P-type conductive metal layer 15 completely covers the P-type reflective metal layer 14 , and the distance between the projection of the edge of the P-type reflective metal layer 14 on the current spreading layer 12 and the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 is 1.2 um.

[0043] S6, forming a first insulating protection layer 16 on the P-type conductive metal layer 15 and a portion of the current blocking layer 13; In this embodiment, the specific process for preparing the first insulating protection layer 16 is as follows: On the surface of the P-type conductive metal layer 15 and the current blocking layer 13 not covered by the P-type conductive metal layer 15, an Al2O3 layer is first deposited by an atomic layer deposition process, and then a SiO2 layer is deposited by a PECVD process. The Al2O3 layer and the SiO2 layer together constitute a first insulating protective layer 16. Then, photoresist is coated on the surface of the SiO2 layer, and then a portion of the photoresist is removed by an exposure and development process to expose the first insulating protective layer 16 under the portion of the photoresist. Then, the exposed portion of the first insulating protective layer 16 and the current blocking layer 13 under the portion of the first insulating protective layer 16 are removed by an ICP etching process to form an N-type conductive through hole 161, and the N-type conductive through hole 161 is located on the conductive step 114 of the N-type semiconductor layer. Then, the substrate is thinned by a grinding process, and the remaining thickness after thinning is 300um.

[0044] S7, forming an N-type conductive metal layer 17 by evaporation on the first insulating protection layer 16; In this embodiment, the specific process for preparing the N-type conductive metal layer 17 is as follows: Cr metal, Al metal, Ti metal and Pt metal are sequentially deposited on the first insulating protection layer 16 and the N-type conductive via 161 by electron beam evaporation process to form an N-type conductive metal layer 17 .

[0045] Among them, the projection of the edge of the N-type conductive metal layer 17 on the current spreading layer 12 is located within the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12, and the distance between the projection of the edge of the N-type conductive metal layer 17 on the current spreading layer 12 and the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 is 11um.

[0046] S8, forming a first metal bonding layer by evaporation on the N-type conductive metal layer 17, providing a conductive silicon wafer 19, forming a second metal bonding layer by evaporation on the conductive silicon wafer 19, and bonding the first metal bonding layer and the second metal bonding layer to form a metal bonding layer 18; In this embodiment, the specific process of bonding the first metal bonding layer and the second metal bonding layer to form the metal bonding layer 18 is: The first metal bonding layer is formed by evaporation on the N-type conductive metal layer 17 by electron beam evaporation process, a conductive silicon wafer 19 is provided, and the second metal bonding layer is formed by evaporation on the conductive silicon wafer 19, the first metal bonding layer and the second metal bonding layer both include Ti metal and 2-5 groups of Sn metal and Ni metal stacks, and then the first metal bonding layer and the second metal bonding layer are bonded to form a metal bonding layer 18 by a hot pressing bonding process.

[0047] S9, peeling off the substrate and the N-type semiconductor layer 111 by using laser; In this embodiment, the specific process of peeling the substrate and the N-type semiconductor layer 111 is as follows: The substrate is irradiated with a laser to decompose GaN at the interface between the substrate and the N-type semiconductor layer 111 to generate metal Ga and N2, thereby decomposing and removing the substrate. The laser is a 266nm ultraviolet laser, the spot radius of the laser is 14um, the spot movement speed of the laser is 2600 mm / s, and the power of the laser is 92W.

[0048] S10, etching a portion of the epitaxial layer 11 to form an isolation groove 201 and a cutting wall 202 on the current spreading layer 12, and roughening the side surfaces of the isolation groove 201 and the cutting wall 202 using a KOH solution; In this embodiment, the specific process of preparing the isolation groove 201 and the cutting wall 202 is as follows: After stripping and removing the substrate, the surface of the epitaxial layer 11 is coated with photoresist, and then a mask is used to expose part of the photoresist, and then developed to remove the exposed part of the photoresist, exposing the epitaxial layer 11 under the part of the photoresist, and then, an inductively coupled plasma etching process is used to remove the exposed part of the epitaxial layer 11, and an isolation groove 201 and a cutting wall 202 are formed on the current spreading layer 12, and then the sides of the isolation groove 201 and the cutting wall 202 are roughened using a KOH solution, and then the photoresist is removed.

[0049] Among them, isolation grooves 201 and cutting walls 202 are arranged on opposite sides of the current expansion layer 12, and the isolation groove 201 is located between the epitaxial layer 11 and the cutting wall 202 along the horizontal direction. The projection of the edge of the P-type conductive metal layer 15 on the current expansion layer 12 is located within the projection of the isolation groove 201 on the current expansion layer 12, and the distance L1 between the projection of the edge of the P-type conductive metal layer 15 on the current expansion layer 12 and the projection of the edge of the isolation groove 201 on the current expansion layer 12 is in a ratio of 1 / 3 to the width L of the isolation groove 201.

[0050] S11, forming a P-type pad layer 22 by evaporation on the P-type conductive metal layer 15; In this embodiment, the specific process for preparing the P-type pad layer 22 is as follows: Using atomic layer deposition equipment, Al2O3 is deposited on the surface of the remaining epitaxial layer 11 as a second insulating protective layer 21, and a negative photoresist is coated on the surface of the second insulating protective layer 21. Then, part of the photoresist is removed by exposure and development to expose part of the second insulating protective layer 21. Then, BOE is used to corrode the exposed part of the second insulating protective layer 21 and the current blocking layer 13 thereunder until the P-type conductive metal layer 15 to form a P-type conductive metal layer through hole. Then, Ti metal, Pt metal, Au metal, Ni metal and Au metal are sequentially evaporated using an electron beam evaporation process. Then, the metal on the photoresist is removed using a Lift-Off process, and then the photoresist is removed to form a P-type pad layer 22 on the P-type conductive metal layer.

[0051] Embodiment 3 The difference from the second embodiment is that: The ratio of the distance L1 between the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 and the projection of the edge of the isolation trench 201 on the current spreading layer 12 to the width L of the isolation trench 201 is 1 / 2.

[0052] Embodiment 4 The difference from the second embodiment is that: The ratio of the distance L1 between the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 and the projection of the edge of the isolation trench 201 on the current spreading layer 12 to the width L of the isolation trench 201 is 2 / 3.

[0053] Comparative Example This comparative example is a conventional method, in which the isolation groove 201 and the cutting wall 202 are not provided.

[0054] The luminous efficiency of the light-emitting diode chip prepared in the comparative example is compared with that of the light-emitting diode chips prepared in Example 2, Example 3 and Example 4, and the corresponding test results are shown in Table 1: Table 1

[0055] It should be noted that in order to ensure the reliability of the verification results, when comparing the luminous efficiency of the light-emitting diode chips prepared in the above-mentioned comparative example of the present invention and the light-emitting diode chips prepared in Example 2, Example 3 and Example 4, except for the above-mentioned parameters, other processes and parameters should remain consistent.

[0056] It can be seen from the above table that the luminous efficiency of the light-emitting diode chips prepared in Example 2, Example 3 and Example 4 is improved compared with the light-emitting diode chip prepared in the comparative example, and the improvement ratios are 7.61%, 8.21% and 9.06% respectively, which shows that the luminous efficiency is significantly improved.

[0057] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0058] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A light emitting diode chip, characterized in that: It includes a conductive silicon wafer, a metal bonding layer, an N-type conductive metal layer, a first insulating protection layer, a P-type conductive metal layer, a P-type reflective metal layer, a current blocking layer, a current spreading layer and an epitaxial layer stacked from bottom to top; An isolation groove and a cutting wall are arranged on opposite sides of the current spreading layer, the isolation groove is located between the epitaxial layer and the cutting wall in the horizontal direction, the projection of the edge of the P-type conductive metal layer on the current spreading layer is located within the projection of the isolation groove on the current spreading layer, and the ratio of the distance between the projection of the edge of the P-type conductive metal layer on the current spreading layer and the projection of the edge of the isolation groove on the current spreading layer to the width of the isolation groove is 1 / 3 to 2 / 3, and a second insulating protective layer is arranged on the surface of the epitaxial layer and the cutting wall; A P-type pad layer is disposed on the P-type conductive metal layer.

2. The light emitting diode chip according to claim 1, characterized in that: The P-type conductive metal layer completely covers the P-type reflective metal layer, and a distance between a projection of an edge of the P-type reflective metal layer on the current spreading layer and a projection of an edge of the P-type conductive metal layer on the current spreading layer is greater than 1 um.

3. The light emitting diode chip according to claim 1, characterized in that: The projection of the edge of the N-type conductive metal layer on the current spreading layer is located within the projection of the edge of the P-type conductive metal layer on the current spreading layer, and the distance between the projection of the edge of the N-type conductive metal layer on the current spreading layer and the projection of the edge of the P-type conductive metal layer on the current spreading layer is greater than 10um.

4. The light emitting diode chip according to claim 1, characterized in that: The side surfaces of the isolation groove and the cutting wall are roughened.

5. A method for preparing a light emitting diode chip, for preparing the light emitting diode chip according to any one of claims 1 to 4, characterized in that: The following steps are involved: Providing a substrate, depositing an epitaxial layer and an N-type semiconductor layer conductive step on the substrate; forming a current spreading layer on the epitaxial layer and the conductive steps of the N-type semiconductor layer; forming a current blocking layer on the epitaxial layer and the conductive steps of the N-type semiconductor layer; forming a P-type reflective metal layer on the current blocking layer; forming a P-type conductive metal layer on the P-type reflective metal layer and a portion of the current blocking layer; forming a first insulating protection layer on the P-type conductive metal layer and a portion of the current blocking layer; Forming an N-type conductive metal layer by evaporation on the first insulating protective layer; Forming a first metal bonding layer by evaporation on the N-type conductive metal layer, providing a conductive silicon wafer, forming a second metal bonding layer by evaporation on the conductive silicon wafer, and bonding the first metal bonding layer and the second metal bonding layer to form a metal bonding layer; Using laser to peel off the substrate and the epitaxial layer; Etching part of the epitaxial layer to form an isolation groove and a cutting wall on the current spreading layer, and roughening the side surfaces of the isolation groove and the cutting wall using a KOH solution; A P-type pad layer is formed by evaporating on the P-type conductive metal layer.

6. The method for preparing a light emitting diode chip according to claim 5, characterized in that: The step of forming a P-type conductive metal layer on the P-type reflective metal layer and a portion of the current blocking layer comprises: A negative photoresist is coated on the surface of the P-type reflective metal layer and the current blocking layer not covered by the P-type reflective metal layer, and then a portion of the photoresist is removed by exposure and development. Then, Ti metal, Pt metal, Au metal and Cr metal are sequentially evaporated by an electron beam evaporation process, and then the metal located on the photoresist is removed by a Lift-Off process, and then the photoresist is removed to form a P-type conductive metal layer.

7. The method for preparing a light emitting diode chip according to claim 5, characterized in that: The steps of forming a first metal bonding layer by evaporating on the N-type conductive metal layer, providing a conductive silicon wafer, forming a second metal bonding layer by evaporating on the conductive silicon wafer, and bonding the first metal bonding layer and the second metal bonding layer to form a metal bonding layer include: A metal bonding layer is evaporated by an electron beam evaporation process, wherein the metal bonding layer includes a first metal bonding layer and a second metal bonding layer, and the first metal bonding layer is formed by evaporation on the N-type conductive metal layer. A conductive silicon wafer is provided, and the second metal bonding layer is formed by evaporation on the conductive silicon wafer. The first metal bonding layer and the second metal bonding layer both include a stack of Ti metal and 2-5 groups of Sn metal and Ni metal. Then, the first metal bonding layer and the second metal bonding layer are bonded to form a metal bonding layer by a hot pressing bonding process.

8. The method for preparing a light emitting diode chip according to claim 5, characterized in that: The step of peeling the substrate and the epitaxial layer by laser comprises: The substrate is irradiated with laser light to decompose GaN at a junction surface between a portion of the substrate and the N-type semiconductor layer to generate metal Ga and N2, thereby decomposing and removing the substrate.

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