A light-emitting diode chip and a preparation method thereof

Abstract

The present invention provides a light-emitting diode chip and a method for manufacturing the same. The light-emitting diode chip includes a conductive silicon wafer, a metal bonding layer, an N-type conductive metal layer, a first insulating protective layer, a P-type conductive metal layer, a P-type reflective metal layer, a current blocking layer, a current spreading layer, and an epitaxial layer, which are stacked from bottom to top. The projection of the edge of the P-type conductive metal layer on the current spreading layer is located within the projection of the isolation groove on the current spreading layer, and the ratio of the distance between the projection of the edge of the P-type conductive metal layer on the current spreading layer and the projection of the edge of the isolation groove on the current spreading layer to the width of the isolation groove is 1 / 3 to 2 / 3. By providing an isolation groove and a cutting wall on the current spreading layer and the proportional relationship between the edge of the P-type conductive metal layer and the isolation groove, it helps to control the distribution of current in the light-emitting diode chip, avoid excessive current concentration, and spread the current more evenly to the epitaxial layer, thereby improving the overall light-emitting efficiency and stability of the light-emitting diode chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a light-emitting diode chip and a method for preparing the same. Background Art

[0002] Light-emitting diode chips are widely used in the two fields of lighting and display due to their energy efficiency and high efficiency. Many aspects involve applications with extremely high power, such as outdoor lighting and automotive lighting.

[0003] However, in the prior art, the luminous efficiency of light-emitting diode chips is relatively low and urgently needs to be improved to meet the application scenarios of high power. Summary of the Invention

[0004] In view of the above situation, it is necessary to provide a light-emitting diode chip and a method for preparing the same to address the problem of the overly wide bottom of the electrode and the absorption of a large amount of emitted light in the prior art.

[0005] A light-emitting diode chip includes a conductive silicon wafer, a metal bonding layer, an N-type conductive metal layer, a first insulating protective layer, a P-type conductive metal layer, a P-type reflective metal layer, a current blocking layer, a current spreading layer, and an epitaxial layer stacked from bottom to top;

[0006] Isolation grooves and cutting walls are provided on both opposite sides of the current spreading layer. Horizontally, the isolation grooves are located between the epitaxial layer and the cutting walls. The projection of the edge of the P-type conductive metal layer on the current spreading layer is located within the projection of the isolation grooves on the current spreading layer, and the ratio of the distance between the projection of the edge of the P-type conductive metal layer on the current spreading layer and the projection of the edge of the isolation grooves on the current spreading layer to the width of the isolation grooves is 1 / 3 to 2 / 3. A second insulating protective layer is provided on the surfaces of the epitaxial layer and the cutting walls;

[0007] A P-type pad layer is provided on the P-type conductive metal layer.

[0008] Advantages of the Present Invention:

[0009] By providing isolation grooves and cutting walls on the current spreading layer, and having a specific distance ratio relationship between the edge position of the P-type conductive metal layer and the isolation grooves, it helps to control the distribution of current in the light-emitting diode chip, avoiding excessive current concentration in certain areas. In the absence of such a structure, current will form hot spots at the edge of the P-type conductive metal layer, resulting in local overheating and reduced efficiency. With this structure, current can be more evenly spread to the epitaxial layer, improving the overall luminous efficiency and stability of the light-emitting diode chip.

[0010] Further, the P-type conductive metal layer completely covers the P-type reflective metal layer, and the distance between the edge of the P-type reflective metal layer and the edge of the P-type conductive metal layer is greater than 1 um.

[0011] Further, the projection of the edge of the N-type conductive metal layer on the current spreading layer is located within the projection of the edge of the P-type conductive metal layer on the current spreading layer, and the distance between the edge of the N-type conductive metal layer and the edge of the P-type conductive metal layer is greater than 10 um.

[0012] Further, the side surfaces of the isolation grooves and the cutting walls are both roughened.

[0013] On the other hand, the present invention also provides a method for manufacturing a light-emitting diode chip for manufacturing the light-emitting diode chip as described above, including the following steps:

[0014] Provide a substrate, and deposit an epitaxial layer and an N-type semiconductor layer conductive step on the substrate;

[0015] Form a current spreading layer on the epitaxial layer and the N-type semiconductor layer conductive step;

[0016] Form a current blocking layer on the epitaxial layer and the N-type semiconductor layer conductive step;

[0017] Form a P-type reflective metal layer on the current blocking layer;

[0018] Form a P-type conductive metal layer on the P-type reflective metal layer and a part of the current blocking layer;

[0019] Form a first insulating protective layer on the P-type conductive metal layer and a part of the current blocking layer;

[0020] Evaporate and deposit an N-type conductive metal layer on the first insulating protective layer;

[0021] Evaporate and deposit a first metal bonding layer on the N-type conductive metal layer, provide a conductive silicon wafer, evaporate and deposit a second metal bonding layer on the conductive silicon wafer, and bond the first metal bonding layer and the second metal bonding layer to form a metal bonding layer;

[0022] Use a laser to separate the substrate from the epitaxial layer;

[0023] Etch a part of the epitaxial layer, form isolation grooves and cutting walls on the current spreading layer, and use a KOH solution to roughen the side surfaces of the isolation grooves and the cutting walls;

[0024] Evaporate and deposit a P-type pad layer on the P-type conductive metal layer.

[0025] Further, the steps of providing a substrate and depositing an epitaxial layer and an N-type semiconductor layer conductive step on the substrate include:

[0026] Provide a substrate, deposit an epitaxial layer on the substrate by using the MOCVD process. The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer stacked from bottom to top. Then, coat a photoresist on the surface of the P-type semiconductor layer, and then use exposure and development to remove part of the photoresist, exposing the P-type semiconductor layer under this part of the photoresist. Then, use an inductively coupled plasma etching process to remove part of the P-type semiconductor layer and the active light-emitting layer under the P-type semiconductor layer until the N-type semiconductor layer is exposed. Then, remove the photoresist to form an N-type semiconductor layer conductive step, and then remove the photoresist.

[0027] Further, the steps of forming a current spreading layer on the epitaxial layer and the N-type semiconductor layer conductive step include:

[0028] On the surfaces of the P-type semiconductor layer and the N-type semiconductor layer conductive step, deposit indium tin oxide by using the magnetron sputtering process. Coat a photoresist on the surface of the indium tin oxide, and then use exposure and development to remove part of the photoresist, exposing part of the indium tin oxide. Then, use an indium tin oxide etching solution to remove the exposed indium tin oxide, and then remove the photoresist to form the current spreading layer.

[0029] Further, the steps of forming a current blocking layer on the epitaxial layer and the N-type semiconductor layer conductive step include:

[0030] On the surfaces of the P-type semiconductor layer and the N-type semiconductor conductive step, deposit SiO 2 as a current blocking layer. Then, coat a photoresist on the surface of the current blocking layer, and then use exposure and development to remove part of the photoresist, exposing the current blocking layer under this part of the photoresist. Then, use BOE etching to also remove the exposed current blocking layer to form a current blocking layer through hole, and then remove the photoresist.

[0031] Further, the steps of forming a P-type reflective metal layer on the current blocking layer include:

[0032] Coat a negative photoresist on the surfaces of the current blocking layer through hole and the current blocking layer, and then use exposure and development to remove part of the photoresist. Use the electron beam evaporation process to sequentially evaporate Ag metal, Ni metal, and Ti metal. Then, use the lift-Off process to remove the metal located on the photoresist, and then remove the photoresist to form a P-type reflective metal layer.

[0033] Further, the step of forming a P-type conductive metal layer on the P-type reflective metal layer and a part of the current blocking layer includes:

[0034] Coat a negative photoresist on the surfaces of the P-type reflective metal layer and the current blocking layer not covered by the P-type reflective metal layer, then use exposure and development to remove part of the photoresist, and then use an electron beam evaporation process to sequentially evaporate Ti metal, Pt metal, Au metal, and Cr metal. Then use the Lift-Off process to remove the metal located above the photoresist, and then remove the photoresist to form a P-type conductive metal layer.

[0035] Further, the step of forming a first insulating protective layer on the P-type conductive metal layer and a part of the current blocking layer includes:

[0036] On the surfaces of the P-type conductive metal layer and the current blocking layer not covered by the P-type conductive metal layer, first deposit an Al 2 O 3 layer by atomic layer deposition, and then deposit an SiO 2 layer by PECVD process. The Al 2 O 3 layer and the SiO 2 layer together form a first insulating protective layer. Then coat a photoresist on the surface of the SiO 2 layer, and then use the exposure and development process to remove part of the photoresist, exposing the first insulating protective layer below this part of the photoresist. Then use the ICP etching process to remove the exposed part of the first insulating protective layer and the current blocking layer below this part of the first insulating protective layer to form an N-type conductive via, and the N-type conductive via is located on the conductive step of the N-type semiconductor layer. Then use a grinding process to thin the substrate, and the remaining thickness after thinning is 300 um.

[0037] Further, the step of evaporating and forming an N-type conductive metal layer on the first insulating protective layer includes:

[0038] Use an electron beam evaporation process to sequentially evaporate Cr metal, Al metal, Ti metal, and Pt metal on the first insulating protective layer and the N-type conductive via to form an N-type conductive metal layer.

[0039] Further, the step of evaporating and forming a first metal bonding layer on the N-type conductive metal layer, providing a conductive silicon wafer, evaporating and forming a second metal bonding layer on the conductive silicon wafer, and bonding the first metal bonding layer and the second metal bonding layer to form a metal bonding layer includes:

[0040] The metal bonding layer is deposited by an electron beam evaporation process. The metal bonding layer includes a first metal bonding layer and a second metal bonding layer. The first metal bonding layer is deposited on the N-type conductive metal layer. A conductive silicon wafer is provided, and the second metal bonding layer is deposited on the conductive silicon wafer. Both the first metal bonding layer and the second metal bonding layer include a stack of Ti metal and 2 - 5 groups of Sn metal and Ni metal. Then, the first metal bonding layer and the second metal bonding layer are bonded using a thermocompression bonding process.

[0041] Further, the step of separating the substrate from the epitaxial layer using a laser includes:

[0042] The substrate is irradiated with a laser, causing the Gann decomposition at the interface between a part of the substrate and the N-type semiconductor layer, generating metallic Ga and N 2 , thereby decomposing and removing the substrate.

[0043] Further, the step of etching a part of the epitaxial layer to form isolation grooves and cutting walls on the current spreading layer and roughening the sides of the isolation grooves and cutting walls using a KOH solution includes:

[0044] After the substrate is removed after peeling, a photoresist is coated on the surface of the epitaxial layer. Then, a part of the photoresist is exposed using a mask and then developed to remove the exposed part of the photoresist, exposing the epitaxial layer under this part of the photoresist. Then, the exposed part of the epitaxial layer is etched using an inductively coupled plasma etching process to form isolation grooves and cutting walls on the current spreading layer. Then, the sides of the isolation grooves and the cutting walls are roughened using a KOH solution, and then the photoresist is removed.

[0045] Further, in S11, the step of preparing the P-type pad layer includes:

[0046] Using an atomic layer deposition device, Al 2 O 3 is deposited on the surface of the remaining epitaxial layer as a second insulating protection layer. A negative photoresist is coated on the surface of the second insulating protection layer, then exposed and developed to remove a part of the photoresist, exposing a part of the second insulating protection layer. Then, this exposed part of the second insulating protection layer and the current blocking layer under it are etched using BOE until the P-type conductive metal layer, forming a P-type conductive metal layer via hole. Then, using an electron beam evaporation process, Ti metal, Pt metal, Au metal, Ni metal, and Au metal are sequentially deposited. Then, the metal above the photoresist is removed using a Lift-Off process, and then the photoresist is removed to form the P-type pad layer. Description of the Drawings

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0048] Figure 1 It is a schematic structural diagram of a light-emitting diode chip according to the first embodiment of the present invention;

[0049] Figure 2 For Figure 1 an enlarged view of part A in

[0050] Figure 3 It is a flowchart for preparing a light-emitting diode chip according to the second embodiment of the present invention.

[0051] In the figure: 11, epitaxial layer; 111, N-type semiconductor layer; 112, active light-emitting layer; 113, P-type semiconductor layer; 114, N-type semiconductor layer conductive step; 12, current spreading layer; 13, current blocking layer; 131, current blocking layer through hole; 14, P-type reflective metal layer; 15, P-type conductive metal layer; 16, first insulating protective layer; 161, N-type conductive through hole; 17, N-type conductive metal layer; 18, metal bonding layer; 19, conductive silicon wafer; 201, isolation groove; 202, cutting wall; 21, second insulating protective layer; 22, P-type pad layer.

[0052] The following will further illustrate the embodiments of the present invention with reference to the drawings. Specific Embodiments

[0053] The following will describe in detail the embodiments of the present invention. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals throughout indicate the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the drawings are exemplary and are intended to explain the embodiments of the present invention, and should not be construed as limiting the present invention.

[0054] In the description of the embodiments of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present invention.

[0055] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present invention, "a plurality" means two or more, unless otherwise specifically defined.

[0056] Embodiment 1

[0057] A light-emitting diode chip, please refer to Figure 1 and Figure 2 , which includes a conductive silicon wafer 19, a metal bonding layer 18, an N-type conductive metal layer 17, a first insulating protective layer 16, a P-type conductive metal layer 15, a P-type reflective metal layer 14, a current blocking layer 13, a current spreading layer 12, an epitaxial layer 11, isolation grooves 201, cutting walls 202, a second insulating protective layer 21, and a P-type pad layer 22 that are stacked from bottom to top; wherein, isolation grooves 201 and cutting walls 202 are provided on both opposite sides of the current spreading layer 12. Along the horizontal direction, the isolation grooves 201 are located between the epitaxial layer 11 and the cutting walls 202. The projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 is located within the projection of the isolation grooves 201 on the current spreading layer 12, and the ratio of the distance L1 between the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 and the projection of the edge of the isolation grooves 201 on the current spreading layer 12 to the width L of the isolation grooves 201 is 1 / 3. The P-type pad layer 22 is provided on the P-type conductive metal layer 15.

[0058] Specifically, the P-type conductive metal layer 15 completely covers the P-type reflective metal layer 14, and the distance between the projection of the edge of the P-type reflective metal layer 14 on the current spreading layer 12 and the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 is 1.2 um.

[0059] Specifically, the projection of the edge of the N-type conductive metal layer 17 on the current spreading layer 12 is located within the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12, and the distance L2 between the projection of the edge of the N-type conductive metal layer 17 on the current spreading layer 12 and the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 is 11 um.

[0060] Specifically, the side surfaces of the isolation grooves 201 and the cutting walls 202 are roughened.

[0061] It should be noted that the light-emitting diode chip has a stacked structure from the conductive silicon wafer 19 to the epitaxial layer 11, and there are reasonable connection and isolation designs between the layers (such as the P-type pad layer 22 penetrating through the current spreading layer 12 and the epitaxial layer 11), which improves the overall structural stability of the chip. Under different working environmental conditions (such as temperature changes, mechanical stresses, etc.), the chip can better maintain its performance and structural integrity.

[0062] It can be understood that the structural layout of different layers such as the current spreading layer 12 and the P-type conductive metal layer 15, and their relationship with the isolation groove 201 and the cutting wall 202 optimize the overall heat dissipation path of the light-emitting diode chip. Heat can be more effectively dissipated through the reasonable layout of these structures, improving the heat dissipation performance of the light-emitting diode chip.

[0063] It should be noted that in the light-emitting diode chip, the isolation groove 201 is used to divide different functional regions or circuit elements. Roughening the side surface of the isolation groove 201 can increase the side surface area; when current passes through the area near the isolation groove 201, due to the increased surface area, the probability of electron scattering increases, which helps to reduce the non-uniformity of current density. For example, in a light-emitting diode with a high current density, the smooth side surface of the unroughened isolation groove 201 may cause current to accumulate in some local areas, while the roughened side surface can make the current disperse more evenly, thereby improving the overall light-emitting efficiency and stability of the chip. Roughening the side surface of the cutting wall 202 helps to improve the bonding force between the relevant film layers and the side surface of the cutting wall 202, preventing the relevant film layers from peeling off or flaking, and ensuring the structural integrity and performance stability of the light-emitting diode chip.

[0064] In addition, importantly, by setting the isolation groove 201 and the cutting wall 202 on the current spreading layer 12, and having a specific distance ratio relationship between the edge position of the P-type conductive metal layer 15 and the isolation groove 201, this helps to control the current distribution in the light-emitting diode chip and avoid excessive current concentration in some areas. For example, in a structure without this precise design, current will form hot spots at the edge of the P-type conductive metal layer 15, resulting in local overheating and reduced efficiency. With this structure, the current can spread more evenly to the epitaxial layer 11, improving the overall light-emitting efficiency and stability of the light-emitting diode. The presence of the current blocking layer 13 can effectively prevent the current from spreading in the unwanted direction, enabling the current to pass through the epitaxial layer 11 along the predetermined path, thereby improving the current utilization rate. Combining the structures of the isolation groove 201 and the cutting wall 202 can further precisely control the current direction and ensure that the current is mainly concentrated in the active light-emitting region.

[0065] Embodiment 2

[0066] Please refer to Figure 3, this embodiment provides a method for fabricating an inverted light-emitting diode chip for fabricating the inverted light-emitting diode chip described in Embodiment 1. The fabrication method includes the following steps:

[0067] S1, provide a substrate, and deposit an epitaxial layer 11 and an N-type semiconductor layer conductive step 114 on the substrate;

[0068] Among them, in this embodiment, the specific process for fabricating the epitaxial layer 11 and the N-type semiconductor layer conductive step 114 is as follows:

[0069] Provide a substrate (not shown), deposit an epitaxial layer 11 on the substrate by using the MOCVD process. The epitaxial layer 11 includes an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 stacked from bottom to top. Then, coat a photoresist on the surface of the P-type semiconductor layer 113, and then use exposure and development to remove part of the photoresist, exposing the P-type semiconductor layer 113 under this part of the photoresist. Then, use an inductively coupled plasma etching process to remove part of the P-type semiconductor layer 113 and the active light-emitting layer 112 under the P-type semiconductor layer 113 until the N-type semiconductor layer 111 is exposed. Then, remove the photoresist to form an N-type semiconductor layer conductive step 114, and then remove the photoresist.

[0070] S2, form a current spreading layer 12 on the epitaxial layer 11 and the N-type semiconductor layer conductive step 114;

[0071] Among them, in the embodiment, the specific process for fabricating the current spreading layer 12 is as follows:

[0072] On the surfaces of the P-type semiconductor layer 113 and the N-type semiconductor layer conductive step 114, deposit indium tin oxide by using the magnetron sputtering process. Coat a photoresist on the surface of the indium tin oxide, and then use exposure and development to remove part of the photoresist, exposing part of the indium tin oxide. Then, use an indium tin oxide etching solution to remove the exposed indium tin oxide, and then remove the photoresist to form the current spreading layer 12.

[0073] S3, form a current blocking layer 13 on the epitaxial layer 11 and the N-type semiconductor layer conductive step 114;

[0074] Among them, in the embodiment, the specific process for fabricating the current blocking layer 13 is as follows:

[0075] On the surfaces of the P-type semiconductor layer 113 and the N-type semiconductor layer conductive step 114, deposit SiO by using the PECVD process 2Take the current blocking layer 13, then coat photoresist on the surface of the current blocking layer 13, then use exposure and development to remove part of the photoresist, exposing the current blocking layer 13 under this part of the photoresist, then use BOE etching to also remove the exposed current blocking layer 13 to form a current blocking layer through hole 131, and then remove the photoresist.

[0076] S4. Form a P-type reflective metal layer 14 on the current blocking layer 13;

[0077] Among them, the specific process for preparing the P-type reflective metal layer 14 in this embodiment is:

[0078] Coat negative photoresist on the surface of the current blocking layer 13 and the current blocking layer through hole 131, then use exposure and development to remove part of the photoresist, use the electron beam evaporation process to sequentially evaporate Ag metal, Ni metal and Ti metal, then use the lift-Off process to remove the metal on the photoresist, and then remove the photoresist to form a P-type reflective metal layer 14.

[0079] S5. Form a P-type conductive metal layer 15 on the P-type reflective metal layer 14 and part of the current blocking layer 13;

[0080] Among them, the specific process for preparing the P-type conductive metal layer 15 in this embodiment is:

[0081] Coat negative photoresist on the surface of the P-type reflective metal layer 14 and the current blocking layer 13 not covered by the P-type reflective metal layer 14, then use exposure and development to remove part of the photoresist, then use the electron beam evaporation process to sequentially evaporate Ti metal, Pt metal, Au metal and Cr metal, then use the Lift-Off process to remove the metal on the photoresist, and then remove the photoresist to form a P-type conductive metal layer 15.

[0082] Among them, the P-type conductive metal layer 15 completely covers the P-type reflective metal layer 14, and the distance between the projection of the edge of the P-type reflective metal layer 14 on the current spreading layer 12 and the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 is 1.2 um.

[0083] S6. Form a first insulating protective layer 16 on the P-type conductive metal layer 15 and part of the current blocking layer 13;

[0084] Among them, the specific process for preparing the first insulating protective layer 16 in this embodiment is:

[0085] On the surface of the P-type conductive metal layer 15 and the current blocking layer 13 not covered by the P-type conductive metal layer 15, first deposit Al 2 O3 layer, and then deposit SiO by PECVD process 2 layer, Al 2 O 3 layer and SiO 2 layer together form the first insulating protection layer 16. Then, apply photoresist on the surface of the SiO 2 layer, and then use the exposure and development processes to remove part of the photoresist, exposing the first insulating protection layer 16 under this part of the photoresist. Then, use the ICP etching process to remove the exposed part of the first insulating protection layer 16 and the current blocking layer 13 under this part of the first insulating protection layer 16, forming an N-type conductive via 161. The N-type conductive via 161 is located on the N-type semiconductor layer conductive step 114. Then, use the grinding process to thin the substrate, and the remaining thickness after thinning is 300 um.

[0086] S7. Evaporate and deposit an N-type conductive metal layer 17 on the first insulating protection layer 16;

[0087] Among them, in this embodiment, the specific process for preparing the N-type conductive metal layer 17 is:

[0088] Use the electron beam evaporation process to evaporate and deposit Cr metal, Al metal, Ti metal, and Pt metal on the first insulating protection layer 16 and the N-type conductive via 161 in sequence to form the N-type conductive metal layer 17.

[0089] Among them, the projection of the edge of the N-type conductive metal layer 17 on the current spreading layer 12 is located inside the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12, and the distance between the projection of the edge of the N-type conductive metal layer 17 on the current spreading layer 12 and the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 is 11 um.

[0090] S8. Evaporate and deposit a first metal bonding layer on the N-type conductive metal layer 17, provide a conductive silicon wafer 19, evaporate and deposit a second metal bonding layer on the conductive silicon wafer 19, and bond the first metal bonding layer and the second metal bonding layer to form a metal bonding layer 18;

[0091] Among them, in this embodiment, the specific process for bonding the first metal bonding layer and the second metal bonding layer to form the metal bonding layer 18 is:

[0092] Using an electron beam evaporation process, deposit and form the first metal bonding layer on the N-type conductive metal layer 17, provide a conductive silicon wafer 19, deposit and form the second metal bonding layer on the conductive silicon wafer 19. Both the first metal bonding layer and the second metal bonding layer include a stack of Ti metal and 2 - 5 groups of Sn metal and Ni metal. Then, use a thermocompression bonding process to bond the first metal bonding layer and the second metal bonding layer to form the metal bonding layer 18.

[0093] S9. Use a laser to separate the substrate from the N-type semiconductor layer 111;

[0094] Among them, in this embodiment, the specific process for separating the substrate from the N-type semiconductor layer 111 is as follows:

[0095] Use a laser to irradiate the substrate, so that GaN at the bonding surface of part of the substrate and the N-type semiconductor layer 111 decomposes to generate metallic Ga and N 2 , thereby decomposing and removing the substrate. The laser is a 266 nm ultraviolet laser, the spot radius of the laser is 14 um, the moving speed of the laser spot is 2600 mm / s, and the power of the laser is 92 W.

[0096] S10. Etch part of the epitaxial layer 11 to form isolation grooves 201 and cutting walls 202 on the current spreading layer 12, and use a KOH solution to roughen the sides of the isolation grooves 201 and the cutting walls 202;

[0097] Among them, in this embodiment, the specific process for preparing the isolation grooves 201 and the cutting walls 202 is as follows:

[0098] Coat a photoresist on the surface of the epitaxial layer 11 after removing the substrate after separation. Then, use a mask to expose part of the photoresist, and then develop it to remove the exposed part of the photoresist, exposing the epitaxial layer 11 under this part of the photoresist. Then, use an inductively coupled plasma etching process to etch and remove this exposed part of the epitaxial layer 11 to form isolation grooves 201 and cutting walls 202 on the current spreading layer 12. Then, use a KOH solution to roughen the sides of the isolation grooves 201 and the cutting walls 202, and then remove the photoresist.

[0099] Among them, isolation grooves 201 and cutting walls 202 are provided on both opposite sides of the current spreading layer 12. Along the horizontal direction, the isolation grooves 201 are located between the epitaxial layer 11 and the cutting walls 202. The projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 is located within the projection of the isolation grooves 201 on the current spreading layer 12. The ratio of the distance L1 between the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 and the projection of the edge of the isolation grooves 201 on the current spreading layer 12 to the width L of the isolation grooves 201 is 1 / 3.

[0100] S11, depositing and forming a P-type pad layer 22 on the P-type conductive metal layer 15;

[0101] Among them, in this embodiment, the specific process for preparing the P-type pad layer 22 is as follows:

[0102] Using an atomic layer deposition device, depositing Al 2 O 3 as the second insulating protective layer 21. Coating a negative photoresist on the surface of the second insulating protective layer 21, then exposing and developing to remove part of the photoresist, exposing part of the second insulating protective layer 21, and then using BOE to etch this exposed part of the second insulating protective layer 21 and the current blocking layer 13 below it until the P-type conductive metal layer 15 is formed to form a P-type conductive metal layer through hole. Then, using an electron beam evaporation process, successively evaporating Ti metal, Pt metal, Au metal, Ni metal, and Au metal; then, using the Lift-Off process to remove the metal above the photoresist, and then removing the photoresist to form a P-type pad layer 22 on the P-type conductive metal layer.

[0103] Embodiment Three

[0104] The difference from Embodiment Two is that:

[0105] The ratio of the distance L1 between the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 and the projection of the edge of the isolation grooves 201 on the current spreading layer 12 to the width L of the isolation grooves 201 is 1 / 2.

[0106] Embodiment Four

[0107] The difference from Embodiment Two is that:

[0108] The ratio of the distance L1 between the projection of the edge of the P-type conductive metal layer 15 on the current spreading layer 12 and the projection of the edge of the isolation grooves 201 on the current spreading layer 12 to the width L of the isolation grooves 201 is 2 / 3.

[0109] Comparative Example

[0110] This comparative example is an existing method without providing the isolation groove 201 and the cutting wall 202.

[0111] The luminous efficiency of the light-emitting diode chips prepared in the comparative example was compared with those prepared in Example 2, Example 3, and Example 4, and the corresponding test results are shown in Table 1:

[0112] Table 1

[0113]

[0114] It should be noted that in order to ensure the reliability of the verification results, for the light-emitting diode chips prepared in the above comparative example of the present invention and those prepared in Example 2, Example 3, and Example 4, when comparing the luminous efficiency of the light-emitting diode chips, except for the above different parameters, other processes and parameters should be kept consistent.

[0115] As can be seen from the above table, the luminous efficiencies of the light-emitting diode chips prepared in Example 2, Example 3, and Example 4 are all improved compared with those prepared in the comparative example, and the improvement ratios are 7.61%, 8.21%, and 9.06% respectively. It can be seen that the luminous efficiency has been significantly improved.

[0116] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0117] The above-described embodiments merely represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A light emitting diode chip, characterized in that: It includes a conductive silicon wafer, a metal bonding layer, an N-type conductive metal layer, a first insulating protection layer, a P-type conductive metal layer, a P-type reflective metal layer, a current blocking layer, a current spreading layer and an epitaxial layer stacked from bottom to top; An isolation groove and a cutting wall are arranged on opposite sides of the current spreading layer, the isolation groove is located between the epitaxial layer and the cutting wall in the horizontal direction, the projection of the edge of the P-type conductive metal layer on the current spreading layer is located within the projection of the isolation groove on the current spreading layer, and the ratio of the distance between the projection of the edge of the P-type conductive metal layer on the current spreading layer and the projection of the edge of the isolation groove on the current spreading layer to the width of the isolation groove is 1 / 3 to 2 / 3, and a second insulating protective layer is arranged on the surface of the epitaxial layer and the cutting wall; A P-type pad layer is disposed on the P-type conductive metal layer.

2. The light emitting diode chip according to claim 1, characterized in that: The P-type conductive metal layer completely covers the P-type reflective metal layer, and a distance between a projection of an edge of the P-type reflective metal layer on the current spreading layer and a projection of an edge of the P-type conductive metal layer on the current spreading layer is greater than 1 um.

3. The light emitting diode chip according to claim 1, characterized in that: The projection of the edge of the N-type conductive metal layer on the current spreading layer is located within the projection of the edge of the P-type conductive metal layer on the current spreading layer, and the distance between the projection of the edge of the N-type conductive metal layer on the current spreading layer and the projection of the edge of the P-type conductive metal layer on the current spreading layer is greater than 10um.

4. The light emitting diode chip according to claim 1, characterized in that: The side surfaces of the isolation groove and the cutting wall are roughened.

5. A method for preparing a light emitting diode chip, for preparing the light emitting diode chip according to any one of claims 1 to 4, characterized in that: The following steps are involved: Providing a substrate, depositing an epitaxial layer and an N-type semiconductor layer conductive step on the substrate; forming a current spreading layer on the epitaxial layer and the conductive steps of the N-type semiconductor layer; forming a current blocking layer on the epitaxial layer and the conductive steps of the N-type semiconductor layer; forming a P-type reflective metal layer on the current blocking layer; forming a P-type conductive metal layer on the P-type reflective metal layer and a portion of the current blocking layer; forming a first insulating protection layer on the P-type conductive metal layer and a portion of the current blocking layer; Forming an N-type conductive metal layer by evaporation on the first insulating protective layer; Forming a first metal bonding layer by evaporation on the N-type conductive metal layer, providing a conductive silicon wafer, forming a second metal bonding layer by evaporation on the conductive silicon wafer, and bonding the first metal bonding layer and the second metal bonding layer to form a metal bonding layer; Using laser to peel off the substrate and the epitaxial layer; Etching part of the epitaxial layer to form an isolation groove and a cutting wall on the current spreading layer, and roughening the side surfaces of the isolation groove and the cutting wall using a KOH solution; A P-type pad layer is formed by evaporating on the P-type conductive metal layer.

6. The method for preparing a light emitting diode chip according to claim 5, characterized in that: The step of forming a P-type conductive metal layer on the P-type reflective metal layer and a portion of the current blocking layer comprises: A negative photoresist is coated on the surface of the P-type reflective metal layer and the current blocking layer not covered by the P-type reflective metal layer, and then a portion of the photoresist is removed by exposure and development. Then, Ti metal, Pt metal, Au metal and Cr metal are sequentially evaporated by an electron beam evaporation process, and then the metal located on the photoresist is removed by a Lift-Off process, and then the photoresist is removed to form a P-type conductive metal layer.

7. The method for preparing a light emitting diode chip according to claim 5, characterized in that: The steps of forming a first metal bonding layer by evaporating on the N-type conductive metal layer, providing a conductive silicon wafer, forming a second metal bonding layer by evaporating on the conductive silicon wafer, and bonding the first metal bonding layer and the second metal bonding layer to form a metal bonding layer include: A metal bonding layer is evaporated by an electron beam evaporation process, wherein the metal bonding layer includes a first metal bonding layer and a second metal bonding layer, and the first metal bonding layer is formed by evaporation on the N-type conductive metal layer. A conductive silicon wafer is provided, and the second metal bonding layer is formed by evaporation on the conductive silicon wafer. The first metal bonding layer and the second metal bonding layer both include a stack of Ti metal and 2-5 groups of Sn metal and Ni metal. Then, the first metal bonding layer and the second metal bonding layer are bonded to form a metal bonding layer by a hot pressing bonding process.

8. The method for preparing a light emitting diode chip according to claim 5, characterized in that: The step of peeling the substrate and the epitaxial layer by laser comprises: The substrate is irradiated with laser light to decompose GaN at a junction surface between a portion of the substrate and the N-type semiconductor layer to generate metal Ga and N2, thereby decomposing and removing the substrate.

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