Apparatus and method for forming metal bonds with recesses

Abstract

Method comprising: Forming a first device die (4) comprising: Depositing a first dielectric layer (42), and Forming a first metal pad (54A) in the first dielectric layer by electrochemical plating of metallic material and planarizing with a chemical mechanical polishing (CMP) process to remove excess metallic material, wherein the CMP process is adapted such that the first metal pad (54A) has a first recess (56) adjacent to an edge portion of the first metal pad, Forming a second device die (112) comprising: a second dielectric layer (142), and a second metal pad (154) in the second dielectric layer, and Bonding the first device die (4) to the second device die (112), wherein the first dielectric layer (42) is bonded to the second dielectric layer (142) and the first metal pad (54A) is bonded to the second metal pad (154); wherein the second metal pad (154) includes a second recess (156) adjacent to an edge of the second metal pad, and the first recess (156) is separated from the second recess (156) at a time when bonding has begun, and after bonding, the first recess remains and the second recess disappears.

Description

STATE OF THE ART

[0001] Integrated circuit packages are becoming increasingly complex, with more device dies housed in the same package to achieve more functions. For example, system-on-integrate chips (SoICs) were developed to house multiple device dies, such as processors and memory cubes, in the same package. SoICs can include device dies formed using different technologies and having different functions bonded to the same device die, forming a single system. This can reduce manufacturing costs and optimize device performance.

[0002] US 4,818,728 A describes first and second semiconductor circuit devices, each comprising a semiconductor substrate with operating elements formed thereon. The semiconductor substrates each also have a plurality of electrodes on an upper surface. On both semiconductor devices, an electrically insulating layer surrounds the respective electrodes. On the first semiconductor device, metal studs are formed in contact with the electrodes protruding from the electrically insulating layer. On the second semiconductor device, solder deposits are deposited in holes of the electrically insulating layer such that the solder deposits contact the electrodes on the substrate. The first and second semiconductor devices are then placed one on top of the other, with the metal studs in the first semiconductor device each aligned with the solder deposits in the second semiconductor device.The resulting assembly is then heated to melt the solder deposits to receive the associated metal studs, which are then immersed in the molten solder deposits. JP 2011-9489 A describes a method for manufacturing a semiconductor device. Electrodes are formed in ILD layers over two semiconductor device substrates so that the electrodes are deeper than the surfaces of the ILD layers. A conductive bonding material is then applied to the surface of the recessed electrodes for the two semiconductor device substrates. The two semiconductor device substrates are then laminated so that the ILD layers touch each other and the positions of the electrodes are aligned.

[0003] US 2015 / 0 364 434 A1 describes a package component having a dielectric surface layer with a first planar surface and a metal pad in the dielectric surface layer. The metal pad includes a diffusion barrier layer containing sidewall portions and a metallic material surrounded by the sidewall portions of the diffusion barrier layer. The metallic material has a second planar surface aligned with the first planar surface. An air gap extends from the second planar surface of the metallic material into the metallic material. One edge of the air gap is aligned with an edge of the metallic material. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 to 14 are cross-sectional views of intermediate steps in manufacturing a package according to some embodiments. Fig. 15 shows a cross-sectional view of a package formed by face-to-face bonding according to some embodiments. Fig. 16A and 16B to 27 show cross-sectional views of metal bonds according to some embodiments. Fig. 28 shows a process flow for forming a package according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] In addition, terms relating to spatial relativity, such as "underlying," "beneath," "lower," "overlying," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or oriented differently), and the terms relating to spatial relativity used herein may be equally construed accordingly.

[0007] A system-on-integrate chip (SoIC) package and the method of forming the same are provided according to various embodiments. The intermediate stages of forming the SoIC package are illustrated according to some embodiments. Some variations of some embodiments are discussed. Like reference numerals are used to refer to like elements throughout the various views and embodiments. Although forming SoIC packages are used as examples to explain the concepts of embodiments of the present disclosure, it should be understood that embodiments of the present disclosure are readily applicable to other bonding methods and structures in which metal pads and vias are bonded together.

[0008] Fig. 1 to 14 show cross-sectional views of intermediate stages in forming a SoIC package according to some embodiments of the present disclosure. Fig. The steps shown in Figures 1 to 14 are also shown schematically in the Fig. The process flow 200 shown in Figure 28 is reproduced.

[0009] Fig. 1 shows the cross-sectional view when forming a package component 2. The corresponding process is shown as step 202 in the Fig. 28. According to some embodiments of the present disclosure, the package component 2 is a device wafer including active devices 22, such as transistors and / or diodes, and possibly passive devices, such as capacitors, inductors, resistors, or the like. The package component 2 may include a plurality of chips 4 therein, one of the chips 4 being illustrated. The chips 4 are alternatively referred to below as (device) dies. According to some embodiments of the present disclosure, the device die 4 is a logic die, which may be a CPU die (central processing unit), an MCU die (microcontroller), an IO die (input / output), a BB die (baseband), an AP die (application processor), or the like. The device die 4 may be a memory die, such as a DRAM die (dynamic random access memory) or an SRAM die (static random access memory).

[0010] According to alternative embodiments of the present disclosure, package component 2 includes passive devices (with no active devices). In the following discussion, a device wafer is discussed as a package component 2. The embodiments of the present disclosure may also be applied to other types of package components, such as interposer wafers.

[0011] According to some embodiments of the present disclosure, wafer 2 includes a semiconductor substrate 20 and features formed on a top surface of semiconductor substrate 20. Semiconductor substrate 20 may be formed from crystalline silicon, crystalline germanium, crystalline silicon germanium, and / or a III-V compound semiconductor, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and the like. Semiconductor substrate 20 may also be a bulk silicon substrate or an SOI (silicon on an insulator) substrate. Shallow trench isolation (STI) regions (not shown) may be formed in semiconductor substrate 20 to isolate the active regions in semiconductor substrate 20.Although not shown, vias may be formed to extend into the semiconductor substrate 20, and the vias are used to electrically couple the features on opposite sides of the wafer 2.

[0012] According to some embodiments of the present disclosure, wafer 2 includes integrated circuit devices 22 formed on the top surface of semiconductor substrate 20. Examples of integrated circuit devices 22 may include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, and / or the like. The details of integrated circuit devices 22 are not shown here. According to alternative embodiments, wafer 2 is used to form interposers, where substrate 20 may be a semiconductor substrate or a dielectric substrate.

[0013] An interlayer dielectric layer (ILD) 24 is formed over the semiconductor substrate 20 and fills the space between the gate stacks of transistors (not shown) in the integrated circuit devices 22. According to some embodiments, the ILD 24 is formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), tetraethylorthosilicate (TEOS), or the like. The ILD 24 may be formed using spin-coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or the like.

[0014] Contact plugs 28 are formed in the ILD 24 and are used to electrically connect the integrated circuit devices 22 to overlying metal lines 34 and vias 36. According to some embodiments of the present disclosure, the contact plugs 28 are formed from a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. Forming the contact plugs 28 may include forming contact openings in the ILD 24, filling a conductive material(s) into the contact openings, and performing planarization (such as a chemical mechanical polishing (CMP) process) to bring the top surfaces of the contact plugs 28 level with the top surface of the ILD 24.

[0015] An interconnect structure 30 is located above the ILD 24 and the contact plugs 28. The interconnect structure 30 includes dielectric layers 32 and metal lines 34 and vias 36 formed in the dielectric layers 32. The dielectric layers 32 are alternatively referred to below as IMD (inter-metal dielectric) layers 32. According to some embodiments of the present disclosure, at least the lower ones of the dielectric layers 32 are formed from a low-k dielectric material having a dielectric constant (k value) less than about 3.0 or about 2.5. The dielectric layers 32 may be formed from Black Diamond (a registered trademark of Applied Materials), a carbonaceous low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like.According to alternative embodiments of the present disclosure, some or all of the dielectric layers 32 are formed from non-low-k dielectric materials, such as silicon oxide, silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxide carbon nitride (SiOCN), or the like. According to some embodiments of the present disclosure, forming the dielectric layers 32 includes depositing a porogen-containing dielectric material and then performing an annealing process to expel the porogen, thus rendering the remaining dielectric layers 32 porous. Etch stop layers (not shown), which may be formed from silicon carbide, silicon nitride, or the like, are formed between the IMD layers 32 and are not shown for simplicity.

[0016] Metal lines 34 and vias 36 are formed in the dielectric layers 32. The metal lines 34 on a same level are collectively referred to below as a metal layer. According to some embodiments of the present disclosure, the interconnect structure 30 comprises multiple metal layers connected to each other by the vias 36. The metal lines 34 and the vias 36 may be formed from copper or copper alloys, and they may also be formed from other metals. The formation process may include single damascene and dual damascene processes. In a single damascene process, a trench is first formed in one of the dielectric layers 32, followed by filling the trench with a conductive material. A planarization process, such asA CMP process is then performed to remove the excess portions of the conductive material higher than the top surface of the IMD layer, leaving a metal line in the trench. In a dual damascene process, both a trench and a via opening are formed in an IMD layer, with the via opening underlying and connected to the trench. The conductive material is then filled into the trench and the via opening to form a metal line and a via, respectively. The conductive material may include a diffusion barrier and a copper-containing metallic material over the diffusion barrier. The diffusion barrier may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0017] The metal lines 34 include metal lines 34A, sometimes referred to as top metal lines. The top metal lines 34A are also collectively referred to as a top metal layer. The respective dielectric layer 32A may be formed from a non-low-k dielectric material, such as an undoped silicate glass (USG), silicon oxide, silicon nitride, or the like. The dielectric layer 32A may also be formed from a low-k dielectric material selected from the similar materials of the underlying IMD layers 32.

[0018] According to some embodiments of the present disclosure, dielectric layers 38, 40, and 42 are formed over the upper metal layer. Dielectric layers 38 and 42 may be formed from silicon oxide, silicon oxynitride, silicon oxycarbide, or the like. Dielectric layer 40 is formed from a dielectric material that is different from the dielectric material of dielectric layer 42. For example, dielectric layer 42 may be formed from silicon nitride, silicon carbide, or the like.

[0019] With reference to Fig. 2, via openings 44 and trenches 46 are formed. The corresponding process is described as step 204 in the Fig. 28. To form the via openings 44 and the trenches 46, photoresists (not shown) and / or hard masks (not shown) may be formed and patterned over the dielectric layer 42 to assist in forming the via openings 44 and the trenches 46. According to some embodiments of the present disclosure, an anisotropic etch is performed to form the trenches 46, and the etch stops on an etch stop layer 40. Another anisotropic etch is then performed to form via openings 44 by etching the exposed etch stop layer 40 and the underlying portions of the dielectric layer 38. According to some embodiments of the present disclosure, the etch stop layer 40 is not formed, and the via openings 44 and the trenches 46 are formed in a single dielectric layer.The etching may be performed using a time mode to allow the etching (to form the trenches 46) to stop at an intermediate level between a top surface and a bottom surface of the single dielectric layer.

[0020] Fig. 3 shows the filling of conductive materials. The corresponding process is described as step 206 in the Fig. 28. A conductive diffusion barrier 48 is first formed. According to some embodiments of the present disclosure, the diffusion barrier 48 is formed from titanium, titanium nitride, tantalum, tantalum nitride, or the like. The diffusion barrier 48 may be formed, for example, using atomic layer deposition (ALD), physical vapor deposition (PVD), or the like. The diffusion barrier 48 includes first portions above the surface dielectric layer 42, and second portions on the bottoms and sidewalls of the trenches 46 and the via openings 44.

[0021] Next, a metallic material 50 is deposited, for example, using electrochemical plating (ECP). The metallic material 50 fills the remaining portions of the trenches 46 and the via openings 44. The metallic material 50 further comprises some portions above the top surface of the dielectric surface layer 42. The metallic material 50 may comprise copper or a copper alloy, or another metallic material that can diffuse in a subsequent annealing process so that a direct metal-to-metal bond can be formed.

[0022] Next, as in Fig. 4, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove excess portions of the metallic material 50 and the diffusion barrier 48 until the dielectric layer 42 is exposed. The corresponding process is described as step 208 in the Fig. 28. The remaining portions of the diffusion barrier 48 and the metallic material 50 include vias 52 and metal pads 54 (which include 54A and 54B). Fig. Figure 4 shows the metal pads for bonding. It should be understood that metal lines may also be formed simultaneously with the metal pads 54. The metal pads 54 include metal pads 54A used for bonding device dies and metal pads 54B used for landing vias.

[0023] Fig. 16A shows a cross-sectional view of the via 52 and the metal pad 54 according to some embodiments of the present disclosure. Each of the metal pad 54 and the via 52 includes a portion of the diffusion barrier 48 and a portion of the metallic material 50 surrounded by the respective portion of the diffusion barrier 48. The metallic material 50 may include edge portions and a central portion between the edge portions. A top surface 50A1 of the central portion is higher than the top surfaces 50A2 of the edge portions. According to some embodiments of the present disclosure, a top surface 50A of the metallic material 50 includes curved portions. The top surface 50A1 of the central portion may be curved or it may be flat. The top surfaces 50A2 of the edge portions may be continuously curved (rounded).The height difference ΔH between the highest point and the lowest point of the upper surface 50A may range between about 10 nm and about 50 nm, and may range between about 10 nm and about 20 nm.

[0024] According to some embodiments of the present disclosure, the diffusion barrier 48 has an upper edge 48A that, depending on the CMP process, is either level with, slightly higher than, or slightly lower than the highest point of the upper surface 50A of the metallic material 50. Edge surface portions 50A2 may be lower than the upper edge 48A, such that recesses 56 are formed. According to some embodiments, a recess depth D1 is greater than about 10 nm, and may be in the range between about 10 nm and about 50 nm, and may further be in the range between about 10 nm and about 20 nm. The upper edge 48A of the diffusion barrier 48 may also be level with or slightly lower than the upper surface of the dielectric layer 42. In a top view of the bond pad 54, recesses 56 may form a ring near edges of the bond pad 54.The side walls of the diffusion barrier 48 exposed to the recesses 56 can also form a ring.

[0025] To achieve the recesses 56, the CMP process is adapted. According to some embodiments of the present disclosure, the suspension for the CMP process comprises oxalic acid (H2C2O4) and acetic acid (CH3COOH). The pH of the suspension is adjusted to be lower than about 4.0, and may range between about 2.0 and about 4.0, which may be achieved by adjusting the concentration of oxalic acid and acetic acid to a suitable amount. According to some embodiments, the weight percentage of oxalic acid in the suspension ranges between about 0.01% and about 2%, and the weight percentage of acetic acid in the suspension ranges between about 0.1% and about 2%. The ratio W Oxal / W Essigcan range between approximately 1:1 and approximately 1:10, where W Oxal represents the weight percentage of oxalic acid in the suspension, and W Essig represents the weight percentage of acetic acid in the suspension. Furthermore, the suspension may comprise an oxalic acid chelate, such as a Cu-oxalic acid chelate (CU-C2O4). The weight percentage of the oxalic acid chelate may, according to some embodiments, be in the range between about 0.01% and about 0.1%. Under these process conditions, recesses 56, as shown in Fig. 16A. The suspension may also include an abrasive, such as silicon oxide particles, aluminum oxide particles, or the like. Furthermore, the process conditions, such as the temperature of the wafer during CMP, the rotation speed of the wafer and the polishing pad, the abrasives in the suspension, etc., may be adjusted to form the recesses 56.

[0026] According to alternative embodiments of the present disclosure, the metal pad 54 and the via 52 are formed as shown in Fig. 16B. The upper surfaces of the metallic material 50, the diffusion barrier 48, and the dielectric layer 41 are flat or substantially flat (e.g., with height differences of less than about 2 nm). According to some embodiments of the present disclosure, the suspension to achieve such a profile may be free of acetic acid, oxalic acid, and the oxalic acid chelate. The pH of the suspension, according to some embodiments, also ranges between about 7.0 and about 10.0. The suspension may also include an abrasive, such as silicon oxide particles, aluminum oxide particles, or the like.

[0027] The device die 4 may, according to some embodiments, also include metal pads, such as aluminum or aluminum-copper pads, formed in the dielectric layer 38 ( Fig. 4). The aluminum pads are not shown for simplicity.

[0028] According to some embodiments of the present disclosure, no organic dielectric material, such as a polymer layer, is present in wafer 2. Organic dielectric layers typically have high coefficients of thermal expansion (CTEs), which may be 10 ppm / °C or higher. This is significantly greater than the CTE of a silicon substrate (such as substrate 20), which is approximately 3 ppm / °C. Consequently, organic dielectric layers tend to cause warpage of wafer 2. Including no organic materials in wafer 2 advantageously reduces the CTE mismatch between layers in wafer 2, resulting in a reduction in warpage. Including no organic materials in wafer 2 also facilitates the formation of metal lines with a fine pitch (such as 72 in Fig. 10) and high-density bond pads are possible, which leads to improved routing capability.

[0029] It is understood that the metal lines formed in the same layer and at the same time as the metal pad 54 may have a similar shape in cross-sectional view as the respective metal pad, as shown in Fig. 16A, Fig. 16B, Fig. 17A and Fig. 17B. Furthermore, in embodiments discussed above, the metal pads 54 are formed using a dual damascene process. According to alternative embodiments of the present disclosure, the metal pads 54 are formed using a single damascene process.

[0030] Fig. Figure 5 illustrates the formation of a wafer 100 including device dies 112 therein. According to some embodiments of the present disclosure, the device dies 112 are logic dies, which may be CPU dies, MCU dies, IO dies, baseband dies, or AP dies. The device dies 112 may be memory dies. The wafer 100 includes a semiconductor substrate 114, which may be a silicon substrate. Silicon vias (TSVs) 116, sometimes referred to as semiconductor vias or through-hole vias, are formed to penetrate the semiconductor substrate. The TSVs 116 are used to connect the devices and metal lines formed on the front side (the bottom side shown) of the semiconductor substrate 114 to the back side.In addition, the device dies 112 include interconnect structures 130 for connecting to the active devices and passive devices in the device dies 112. The interconnect structures 130 include metal lines and vias (not shown).

[0031] The device die 112 may include dielectric layers 138 and 142 and an etch stop layer 140 between the dielectric layers 138 and 142. Bond pads 154 and vias 152 are formed in the layers 138, 140, and 142. The corresponding process is described as step 210 in the Fig. 28. According to some embodiments of the present disclosure, all device dies, such as dies 112, are free of organic dielectric materials, such as polymers. The materials and methods for forming dielectric layers 138, 142, bond pads 154, and vias 152 may be similar to their corresponding parts in device die 4, and therefore, the details will not be repeated here.

[0032] Fig. 17A and Fig. 17B illustrate the bond pads 154 and the vias 152 according to some embodiments. The bond pads 154 and the vias 152 include a diffusion barrier 148 and a metallic material 150. The structures, materials, and formation methods of Fig. 17A can be those of the bond pads 54 and the vias 52, as in Fig. 16A. The profiles of the upper surface / upper edge of the diffusion barrier 148 and the metallic material 150 and the dielectric layer 142 may also be similar to those shown for the diffusion barrier 48, the metallic material 50 and the dielectric layer 42, respectively, in Fig. 16A, and are therefore not repeated here. Recesses 156 are formed, and the details of the recesses 156 may be substantially the same as those described for the recesses 56 ( Fig. 16A). When viewed from the underside of the bond pad 154, the recesses 156 may form a ring near the edges of the bond pad 154, and some sidewalls of the diffusion barrier 148 are also exposed to the recesses 156 and may form a ring. The formation process (which includes the CMP process) of the Fig. 17A may be similar to that described with reference to Fig. 16A was discussed.

[0033] The structures, materials and training procedures of Fig. 17B are those of the bond pads 54 and the vias 52, respectively, as in Fig. 16B. The profiles of the upper surface / edge of the diffusion barrier 148 and the metallic material 150 and the dielectric layer 142 may be similar to those shown for the diffusion barrier 48, the metallic material 50, and the dielectric layer 42, respectively, in Fig. 16B and are therefore not repeated here. No recesses are formed in the metallic material 150.

[0034] With further reference to Fig. 5, the wafer 100 is singulated into several discrete device dies 112. Fig. 6 shows the bonding of the device dies 112 (comprising 112A and 112B) to the device die 4. The corresponding process is shown as step 212 in the Fig. 28. Each of the device dies 112A and 112B can be formed to have the structure as shown in Fig. 5 (and uses the similar training procedure as discussed).

[0035] The device dies 112A and 112B may be identical to or different from each other. For example, the device dies 112A and 112B may be different types of dies selected from the types listed above. Furthermore, the device dies 112 may be formed using different technologies, such as 45 nm technology, 28 nm technology, 20 nm technology, or the like. Furthermore, one of the device dies 112 may be a digital circuit die, while the other may be an analog circuit die. The dies 4, 112A, and 112B function together as a system. Dividing the functions and circuits of a system into different dies, such as the dies 4, 112A, and 112B, may optimize the formation of these dies and may lead to a reduction in manufacturing costs.

[0036] At least one of the dies 4, 112A and 112B has bond pads with recesses 56 / 156, as shown in Fig. 16A and Fig. 17A. According to some embodiments, the bond pad 54 of the die 4 has the recesses 56 ( Fig. 16A) and the bond pads of each of the device dies 112A and 112B may have either the Fig. 17A or the structure shown in Fig. 17B. According to alternative embodiments of the present disclosure, the bond pads 54 of the die 4 have the structure shown in Fig. 16B (without a recess), and the bond pads 154 of one or both of the device dies 112A and 112B have recesses as shown in Fig. 17A. In Fig. 18 to 25, the embodiments shown have recesses in both of the bond pads 54 and 154, and it is understood that one of the two bond pads 54 and 154 may be free of recesses.

[0037] Bonding the device dies 112 to the die 4 ( Fig. 6) can be achieved via hybrid bonding. For example, the bond pads 154 are bonded to the bond pads 54A via metal-to-metal direct bonding. According to some embodiments of the present disclosure, the metal-to-metal direct bonding is copper-to-copper direct bonding. The bond pads 154 may have sizes larger than, equal to, or smaller than the sizes of the respective bond pads 54A. Furthermore, the dielectric layers 142 are bonded to the surface dielectric layer 42 via dielectric-to-dielectric bonding, which may, for example, be fusion bonding in which Si-O-Si bonds are created. Gaps 53 are left between adjacent device dies 112.

[0038] To achieve hybrid bonding, device dies 112 are first pre-bonded to dielectric layer 42 and bond pads 54A by gently pressing device dies 112 to die 4. After all device dies 112 have been pre-bonded, an anneal is performed to cause the interdiffusion of the metals in bond pads 54A and the corresponding overlying bond pads 154. The annealing temperature may be higher than about 350°C according to some embodiments and may range between about 350°C and about 550°C according to some embodiments. The annealing time may range between about 1.5 hours and about 3.0 hours according to some embodiments, and may range between about 1.0 hour and about 2.5 hours according to some embodiments. Through hybrid bonding, the bond pads 154 are bonded to the corresponding bond pads 54A via direct metal bonding induced by metal interdiffusion.

[0039] Fig. 18 shows a cross-sectional view of the bond pads 54 and 154 after pre-bonding and before annealing. According to some embodiments, the bond pads 54 and 154 have the same width and are vertically aligned. Accordingly, the recesses 56 are merged with the respective recess 156. Since the illustrated recesses 56 may be parts of a first recess ring, and the illustrated recesses 156 may be parts of a second recess ring, the first and second recess rings may be joined together to form a combined recess ring. According to alternative embodiments, one of the bond pads 54 and 154 has no recesses (as in Fig. 16A and Fig. 17B) and the other bond pad has the recess.

[0040] Fig. Figure 19 shows a cross-sectional view of bond pads 54 and 154 after annealing. Due to the interdiffusion of bond pads 54 and 154, metallic material 50 is bonded to metallic material 150. Forming recesses 56 and 156 advantageously reduces the stress generated in the bonded structure. For example, the coefficient of thermal expansion (CTE) of metallic materials 50 and 150 is substantially different from that of dielectric layers 42 and 142, and the recesses allow some room for expansion of the metallic materials during thermal cycling (such as pre-annealing and annealing). The stress experienced by the bonded structure is thus reduced.

[0041] After annealing, recesses 56' may be present in the bonded structure. The shapes and sizes of recesses 56' may be different from those of recesses 56 and 156 due to the diffusion of the metallic materials. For example, the size of recesses 56' may be smaller than the combined size of recesses 56 and 156 before annealing. The height of recesses 56' may be greater than about 5 nm and may range between about 5 nm and about 50 nm. According to alternative embodiments, the recesses disappear after annealing. The shape of diffusion barriers 48 and 148 may also change to accommodate the reduction and elimination of the recesses.

[0042] Fig. Figure 20 shows a cross-sectional view of bond pads 54 and 154 after pre-bonding and before annealing according to some embodiments, wherein bond pad 54 is vertically misaligned with bond pad 154. Accordingly, recesses 56 are misaligned with respective recesses 156. Fig. 21 shows a cross-sectional view of the bond pads 54 and 154 after annealing. Due to the interdiffusion of the bond pads 54 and 154, the metallic material 50 is bonded to the metallic material 150. In the cross-sectional view, the recesses 56 and 156 facing the central portion of the other metal pad may be completely filled, or they may be partially filled with reduced sizes. The recesses facing the opposing dielectric layers 42 and 142 may remain. It is understood that the Fig. 19 and Fig. 21 may be present on the same package. For example, if a rotational misalignment occurs, some bond pads will be aligned, resulting in the Fig. 19, and some other bond pads in the same package may not be aligned, resulting in the Fig. 21 shown structure.

[0043] Fig. 22 and Fig. 23 show the bond pads before and after annealing, with bond pads 54 and 154 aligned. Bond pad 54 has a size that is different from (either larger than or smaller than) that of bond pad 154. For example, in the illustrated example, bond pad 154 is larger than bond pad 54. Consequently, as shown in Fig. 23, the sizes of the recesses 56 ( Fig. 22) is reduced or completely filled after bonding, while the recesses 156 are not completely filled.

[0044] Fig. 24 and Fig. 25 show the bond pads before and after annealing, respectively, with bond pads 54 and 154 not aligned. Bond pad 54 has a size that is different from (either larger or smaller than) that of bond pad 154. For example, in the illustrated example, bond pad 154 is larger than bond pad 54. As shown in Fig. 25, after bonding both of the recesses 56 and 156 ( Fig. 24) some filled sections and some other sections that are not filled.

[0045] With further reference to Fig. 6, according to some embodiments, a backside grinding may be performed after the bonding process to thin the device dies 112, for example, to a thickness between about 15 µm and about 30 µm. Fig. 6 schematically shows dashed lines 112-BS1, which are the backsides of the device dies 112 before backside grinding. 112-BS2 are the backsides of the device dies 112 after backside grinding. By thinning the device dies 112, the aspect ratio of the gaps 53 is reduced to perform gap filling. On the other hand, it may be difficult to fill the gaps due to the otherwise high aspect ratio of the gaps 53. After backside grinding, TSVs 116 may be exposed. Alternatively, the TSVs 116 are not exposed at this time, and backside grinding is stopped when a thin layer of a substrate covering the TSVs 116 is present. According to these embodiments, the TSVs 116 may be in the Fig. 8. According to other embodiments in which the aspect ratio of the gap 53 is not too high, the back grinding may be skipped.

[0046] Fig. 7 shows the formation of gap-filling layers comprising a dielectric layer 62 and the underlying etch stop layer 60. The corresponding process is described as step 214 in the Fig. 28. The etch stop layer 60 is formed from a dielectric material having good adhesion to the sidewalls of the device dies 112 and the top surfaces of the dielectric layer 42 and the bond pads 54B. According to some embodiments of the present disclosure, the etch stop layer 60 is formed from a nitride-containing material, such as silicon nitride. The etch stop layer 60 may be a conformal layer, where, for example, the thickness T1A of horizontal portions and a thickness T1B of the vertical portions are substantially equal to each other, where, for example, the difference between the two thicknesses T1A and T1B (T1A -T1B) has an absolute value that is less than approximately 20 percent, or less than approximately 10 percent. The deposition may comprise a conformal deposition process, such as atomic layer deposition (ALD) or chemical vapor deposition (CVS).When the bond pads 54B contact the recesses 56 (. Fig. 16A), the etch stop layer 60 also extends into the recesses.

[0047] The dielectric layer 62 is formed from a material that is different from the material of the etch stop layer 60. According to some embodiments of the present disclosure, the dielectric layer 62 is formed from silicon oxide, which may be formed from TEOS, although other dielectric materials, such as silicon carbide, silicon oxynitride, silicon oxycarbonitride, PSG, BSG, BPSG, or the like, may also be used. The dielectric layer 62 may be formed using CVD, high-density plasma chemical vapor deposition (HDCVD), flowable CVD, spin coating, or the like. The dielectric layer 62 completely fills the remaining gaps 53 ( Fig. 6).

[0048] With reference to Fig. 8, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove excess portions of the gap-filling layers 60 and 62, so that the device dies 112 are exposed. The corresponding process is also described as step 214 in the Fig. 28 is shown. Furthermore, the vias 116 are exposed. The remaining portions of layers 60 and 62 are collectively referred to as (gap-filling) isolation regions 64.

[0049] Fig. 9 shows the etching of the dielectric layer 62 to form openings 66. The corresponding process is shown as step 216 in the Fig. 28. According to some embodiments of the present disclosure, a photoresist (not shown) is formed and patterned, and the dielectric layer 62 is etched using the patterned photoresist as an etch mask. Openings 66 are therefore formed and extend downward to the etch stop layer 60, which acts as the etch stop layer. According to some embodiments of the present disclosure, the dielectric layer 62 comprises an oxide, and the etching may be performed using a dry etch. The etch gas may comprise a mixture of NF3 and NH3 or a mixture of HF and NH3. Next, the etch stop layer 60 is etched such that the openings 66 extend downward to the dielectric bond pads 54B.According to some embodiments of the present disclosure, the etch stop layer 60 is formed from silicon nitride, and the etching is performed using dry etching. The etching gas may comprise a mixture of CF4, O2, and N2, a mixture of NF3 and O2, SF6, or a mixture of SF6 and O2.

[0050] Fig. 10 shows the formation of vias 70 which form the openings 66 ( Fig. 9) and connected to the bond pads 54B. The corresponding process is described as step 218 in the Fig. 28. According to some embodiments of the present disclosure, forming the vias 70 includes performing a plating process, such as an electrochemical plating process or an electroless plating process. The vias 70 may comprise a metallic material, such as tungsten, aluminum, copper, or the like. A conductive barrier layer (such as titanium, titanium nitride, tantalum, tantalum nitride, or the like) may also be formed to underlie the metallic material. Planarization, such as CMP, is performed to remove excess portions of the plated metallic material, and the remaining portions of the metallic material form the vias 70. The vias 70 may have substantially straight and vertical sidewalls.In addition, the vias 70 may have a tapered profile, with upper widths being slightly larger than the respective lower widths.

[0051] According to alternative embodiments, the TSVs 116 are not preformed in the device dies 112. Rather, they are formed after the formation of the isolation regions 64. For example, the device dies 112 are formed either before or after the formation of the openings 66 ( Fig. 8) to form additional openings (occupied by the illustrated TSVs 116). The additional openings in the device dies 112 and the openings 66 may be filled simultaneously to form the vias TSVs 116 and the vias 70. The resulting vias 116 may, in contrast to those shown in Fig. 10 have upper sections that are wider than the respective lower sections.

[0052] With reference to Fig. 11, redistribution lines (RDLs) 72 and a dielectric layer 74 are formed. The corresponding process is described as step 220 in the Fig. 28. According to some embodiments of the present disclosure, the dielectric layer 74 is formed from an oxide, such as silicon oxide, a nitride, such as silicon nitride, or the like. The RDLs 72 may be formed using a damascene process, which includes etching the dielectric layer 74 to form openings, depositing a conductive barrier layer in the openings, plating a metallic material, such as copper or a copper alloy, and performing planarization to remove the excess portions of the metallic material.

[0053] Fig. Figure 12 shows the formation of passivation layers, metal pads, and overlying dielectric layers. The corresponding process is also described as step 220 in the Fig. 28. A passivation layer 76 (sometimes referred to as passivation-1) is formed over the dielectric layer 74, and vias 78 are formed in the passivation layer 76 to electrically connect to the RDLs 72. Metal pads 80 are formed over the passivation layer 76 and are electrically coupled to the RDLs 72 via the vias 78. The metal pads 80 may be aluminum pads or aluminum-copper pads, and other metallic materials may be used.

[0054] As also in Fig. 12, a passivation layer 82 (sometimes referred to as passivation-2) is formed over the passivation layer 76. Each of the passivation layers 76 and 82 may be a single layer or a composite layer and may be formed from a non-porous material. According to some embodiments of the present disclosure, one or both of the passivation layers 76 and 82 are a composite layer comprising a silicon oxide layer (not shown separately) and a silicon nitride layer (not shown separately) over the silicon oxide layer. The passivation layers 76 and 82 may also be formed from other non-porous dielectric materials, such as an undoped silicate glass (USG), silicon oxynitride, and / or the like.

[0055] Next, the passivation layer 82 is patterned so that some portions of the passivation layer 82 cover the edge portions of the metal pads 80, and some portions of the metal pads 80 are exposed through the openings in the passivation layer 82. A polymer layer 84 is then formed and patterned to expose the metal pads 80. The polymer layer 84 may be formed from polyimide, polybenzoxazole (PBO), or the like.

[0056] According to some embodiments of the present disclosure, the structure underlying the metal pads 80 is free of organic materials (such as polymer layers), so that the process for forming the structures underlying the metal pads 80 can apply the process used to form device dies, and fine-pitch RDLs (such as 72) having small pits and line widths are made possible.

[0057] With reference to Fig. 13, post-passivation interconnects (PPIs) 86 are formed, which may include forming a metal seed layer and a patterned mask layer (not shown) over the metal seed layer, and plating PPIs 86 in the patterned mask layer. The patterned mask layer and the portions of the metal seed layer overlapped by the patterned mask layer are then removed in etching processes. A polymer layer 88 is then formed, which may be formed from PBO, polyimide, or the like.

[0058] With reference to Fig. 14, UBMs (solderable metallizations) 90 are formed and the UBMs 90 extend into the polymer layer 88 to be connected to the PPIs 86. The corresponding process is also described as step 220 in the Fig. 28. According to some embodiments of the present disclosure, each of the UBMs 90 includes a barrier layer (not shown) and a seed layer (not shown) over the barrier layer. The barrier layer may be a titanium layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, or a layer formed on a titanium alloy or a tantalum alloy. The seed layer materials may include copper or a copper alloy. Other metals, such as silver, gold, aluminum, palladium, nickel, nickel alloys, tungsten alloys, chromium, chromium alloys, and combinations thereof, may also be included in the UBMS 90.

[0059] As in Fig. 14, electrical connectors 92 are formed. The corresponding process is also shown as step 220 in the Fig. 28. A formation process for forming UBMs 90 and the electrical connectors 92 includes depositing a blanket UBM layer, forming and patterning a mask (which may be a photoresist, not shown), wherein portions of the blanket UBM layer are exposed through the opening in the mask. After forming the UBMs 90, the illustrated package is placed in a plating solution (not shown), and a plating step is performed to form the electrical connectors 92 on the UBMs 90. According to some embodiments of the present disclosure, the electrical connectors 92 include non-soldering portions (not shown) that are not melted in the subsequent reflow processes. The non-soldering portions may be formed from copper and are therefore referred to as copper bumps below, although they may be formed from other non-soldering materials.Each of the electrical connectors 92 may also include a cap layer(s) (not shown) selected from a nickel layer, a nickel alloy, a palladium layer, a gold layer, a silver layer, or multiple layers thereof. The cap layer(s) is (are) formed over the copper bumps. The electrical connectors 92 may further include solder caps, which may be formed from a Sn-Ag alloy, a Sn-Cu alloy, a Sn-Ag-Cu alloy, or the like, and which may be lead-free or lead-containing. The structure formed in previous steps is referred to as a composite wafer 94. A die sawing step (singling) is performed on the composite wafer 94 to separate the composite wafer 94 into a plurality of packages 96. The corresponding process is shown as step 222 in the FIG. 10 illustrated in FIG. Fig. The process flow shown in Figure 28 is shown.

[0060] The Fig. The package shown in Figure 14 has a face-to-face structure in which the front sides of the device dies 112 face the front side of the device die 4. Fig. Figure 15 shows a face-to-back structure in which the front sides of the device dies 112 face the back side of the device die 4. The device die 4 includes the TSVs 16 extending through the substrate 20 and the dielectric layer 17. The dashed region 19 in Fig. 15 represents the likely electrical connectors, such as solder areas. According to some embodiments of the present disclosure, a CMP is performed on the TSVs 16 and the dielectric layer 17. The details of the CMP process may be similar to those described with reference to Fig. 16A, and therefore recesses 156 are formed as in Fig. 25 shown.

[0061] Fig. 26 and Fig. 27 show the bonding of bond pads 154 with the TSVs 16, where Fig. 26 shows the structure before healing and Fig. 27 shows the structure after annealing. A layer 49 in Fig. 26 may be a dielectric insulation layer formed from silicon oxide, silicon nitride, or the like. Recesses 56 may be formed in the TSVs 16, with the recesses either reduced or completely eliminated after annealing. Recesses 156 may still be present after annealing.

[0062] The embodiments of the present disclosure have several advantageous features. By forming recesses in bond pads, stress in the bonded structures is reduced, particularly during thermal cycling. The reliability of the bonded structure is therefore improved.

[0063] The invention is defined by the main claim and the subordinate claims. The subclaims describe further embodiments of the invention.

Claims

[1] Method comprising: Forming a first device die (4) comprising: Depositing a first dielectric layer (42), and Forming a first metal pad (54A) in the first dielectric layer by electrochemical plating of metallic material and planarizing with a chemical mechanical polishing (CMP) process to remove excess metallic material, wherein the CMP process is adapted such that the first metal pad (54A) has a first recess (56) adjacent to an edge portion of the first metal pad, Forming a second device die (112) comprising: a second dielectric layer (142), and a second metal pad (154) in the second dielectric layer, and Bonding the first device die (4) to the second device die (112), wherein the first dielectric layer (42) is bonded to the second dielectric layer (142) and the first metal pad (54A) is bonded to the second metal pad (154); wherein the second metal pad (154) includes a second recess (156) adjacent to an edge of the second metal pad, and the first recess (156) is separated from the second recess (156) at a time when bonding has begun, and after bonding, the first recess remains and the second recess disappears. [2] The method of claim 1, wherein the first metal pad (54A) comprises: a diffusion barrier (48), and a copper-containing material between opposing portions of the diffusion barrier (48), wherein an edge portion of the copper-containing material is recessed lower than an upper edge of the diffusion barrier to form the first recess (56). [3] The method of claim 1 or 2, wherein the bonding comprises: Performing a pre-healing, and Carrying out a healing process, wherein the first recess (56) is reduced during the healing process. [4] A process according to any one of claims 1 to 3, wherein the CMP process is carried out using a suspension having a pH lower than 4.

0. [5] A process according to any one of claims 1 to 3, wherein the CMP process is carried out using a suspension comprising an acetic acid and a copper chelate. [6] A process according to any one of claims 1 to 4, wherein the CMP process is carried out using a suspension comprising acetic acid and oxalic acid. [7] The method of claim 6, wherein a weight percentage of oxalic acid in the suspension is in the range between 0.01% and 2%, and a weight percentage of acetic acid in the suspension is in the range between 0.1% and 2%. [8] The method according to claim 7, wherein a ratio of the weight percentage of oxalic acid in the suspension to the weight percentage of acetic acid in the suspension is between 1:1 and 1:

10. [9] Method comprising: Forming a dielectric layer (42) on an upper surface of a wafer (2), Etching the dielectric layer (42) to form a trench (46) in the dielectric layer (42), Forming a first metal pad (54A) in the trench (46) by: Forming a diffusion barrier (48) in the trench (46) which contacts the dielectric layer (42) on a sidewall of the trench, and Depositing a metallic material (50) in the trench (46) between opposing portions of the diffusion barrier (48) and performing a planarization process to remove excess portions of the diffusion barrier and the metallic material, wherein, in a cross-sectional view of the first metal pad (54A), an upper surface of the metallic material has a central portion and edge portions lower than the central portion, and the edge portions are lower than an upper edge of a next portion of the diffusion barrier (48) to form a recess (56); and Bonding a second metal pad (154) to the first metal pad (54A), wherein the recess (56) is at least reduced in size after bonding the second metal pad to the first metal pad. [10] The method of claim 9, wherein forming the first metal pad (54A) comprises chemical mechanical polishing, CMP, and the recess (56) is formed during the CMP. [11] The method according to claim 10, wherein the CMP is carried out using a suspension comprising acetic acid and oxalic acid, and a pH of the suspension is lower than 4.

0. [12] The method of claim 11, wherein the pH of the suspension is in a range between 2.0 and 4.

0. [13] The method according to claim 12, wherein a ratio of a weight percentage of the oxalic acid in the suspension to a weight percentage of the acetic acid in the suspension is between 1:1 and 1:

10. [14] A method according to any one of claims 9 to 13, wherein the upper surface of the metallic material (50) is curved. [15] Device comprising: a first device die (4) comprising: a first dielectric layer (42), and a first metal pad (54A) comprising: a diffusion barrier (48) formed in a trench (46) in the first dielectric layer and contacting the first dielectric layer (42) at a sidewall of the trench, and a metallic material (50) in the trench (46) between opposing portions of the diffusion barrier (48), the diffusion barrier (48) being located between the sidewall of the trench and the metallic material, wherein in a cross-sectional view of the first metal pad (54A), an edge portion of the metallic material is recessed from an upper edge of a next portion of the diffusion barrier and forms an air gap; wherein the first device die (4) further comprises a third metal pad (54B) comprising an additional recess, and the device further comprises: a dielectric etch stop layer (60) extending into the additional recess, a dielectric layer (62) over and contacting the dielectric etch stop layer, and a via (70) penetrating through the dielectric etch stop layer and the dielectric layer to be connected to the third metal pad (54B). [16] The apparatus of claim 15, further comprising: a second device die (112) comprising: a second dielectric layer (142) bonded to the first dielectric layer (42), and a second metal pad (154) bonded to the first metal pad (54A) via metal-to-metal direct bonding, wherein the air gap further extends into the second metal pad (154). [17] The device of claim 16, wherein the air gap is formed between a sidewall of the diffusion barrier (48), a surface of the metallic material (50) and a surface of the second metal pad (154). [18] The device of claim 16, wherein the air gap is formed between a sidewall of the diffusion barrier (48), a surface of the metallic material (50) and a surface of the second dielectric layer (142). [19] Device according to one of claims 15 to 18, wherein a surface of the metallic material (50) facing the air gap is curved.

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