Perovskite and crystalline silicon tandem battery module and photovoltaic system

Abstract

The present invention discloses a perovskite and crystalline silicon tandem battery module and a photovoltaic system, which include a crystalline silicon battery layer, a perovskite battery layer, a packaging material layer, and a first light-transmitting protective layer. The perovskite battery layer and the crystalline silicon battery layer are stacked and have a mutually matched rated output voltage. The perovskite battery layer and the crystalline silicon battery layer are both provided with busbars of positive and negative polarities, and the busbars of the same polarity have a safety gap on the projection plane in the stacking direction; the packaging material layer is stacked between the crystalline silicon battery layer and the perovskite battery layer; the first light-transmitting protective layer covers the crystalline silicon battery layer, and positive and negative junction boxes are arranged on the first light-transmitting protective layer. The junction boxes are provided with parallel wires, and the parallel wires have two conductive paths, and the two conductive paths are respectively conductively connected to the busbars of the same polarity of the crystalline silicon battery layer and the perovskite battery layer. The present invention can reduce the number of junction boxes, reduce the cable cost, and improve the compatibility of downstream products.

Description

Technical Field

[0001] The present invention relates to the technical field of new energy, and particularly relates to a perovskite and crystalline silicon tandem battery module and a photovoltaic system. Background Art

[0002] In photovoltaic cells, four-terminal perovskite-crystalline silicon tandem battery modules have been mass-produced and applied because of their simple process (the perovskite module and the crystalline silicon module only need to be mechanically stacked). However, in the four-terminal tandem structure, both the perovskite module and the crystalline silicon module need to be independently connected to the junction box, resulting in high cable costs and low compatibility of downstream products. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. For this purpose, the present invention provides a perovskite and crystalline silicon tandem battery module and a photovoltaic system, which can reduce the number of junction boxes, thereby reducing cable costs and improving the compatibility of downstream products.

[0004] On the one hand, an embodiment of the present invention provides a perovskite and crystalline silicon tandem battery module, including:

[0005] A crystalline silicon cell layer;

[0006] A perovskite cell layer, which is stacked with the crystalline silicon cell layer and has a rated output voltage that matches the crystalline silicon cell layer. The perovskite cell layer and the crystalline silicon cell layer are both provided with busbars of positive and negative polarities, and the busbars of the same polarity have a safety gap on the projection plane in the stacking direction.

[0007] An encapsulation material layer, which is stacked between the crystalline silicon cell layer and the perovskite cell layer;

[0008] A first light-transmitting protective layer, which covers the crystalline silicon cell layer. Positive and negative junction boxes are provided on the first light-transmitting protective layer. The junction boxes are provided with parallel wires, and the parallel wires have two conductive paths, and the two conductive paths are respectively conductively connected to the busbars of the same polarity of the crystalline silicon cell layer and the perovskite cell layer.

[0009] According to some embodiments of the present invention, the perovskite cell layer is cut into multiple cell units based on a scribing and dividing method, and the multiple cell units are connected in series to obtain a rated output voltage that matches the crystalline silicon cell layer.

[0010] According to some embodiments of the present invention, the two conductive paths of the parallel wires are coaxially arranged, and an insulating layer is provided between the two conductive paths.

[0011] According to some embodiments of the present invention, the two conductive paths of the parallel wires are respectively connected with a first electrode and a second electrode, and the first electrode and the second electrode are coaxially arranged.

[0012] According to some embodiments of the present invention, two conductive paths of the parallel wire are respectively connected to an adjacent first terminal and a second terminal. A first electrode is disposed in the first terminal, and a second electrode is disposed in the second terminal.

[0013] According to some embodiments of the present invention, the junction box with positive polarity is connected to a male connector through the corresponding parallel wire, and the junction box with negative polarity is connected to a female connector through the corresponding parallel wire. The male connector and the female connector are mutually adapted.

[0014] According to some embodiments of the present invention, two conductive paths of the parallel wire are integrated into one body.

[0015] According to some embodiments of the present invention, the first light-transmitting protective layer is provided with an adjacent first clearance hole and a second clearance hole. The first clearance hole extends to the crystalline silicon cell layer, the second clearance hole penetrates the encapsulation material layer and extends to the perovskite cell layer. The bus bar of the crystalline silicon cell layer penetrates through the first clearance hole, and the bus bar of the perovskite cell layer penetrates through the second clearance hole.

[0016] According to some embodiments of the present invention, the bus bar of the perovskite cell layer has a first segment, a second segment and a third segment. The first segment is located in the perovskite cell layer, the second segment is located in the second clearance hole, and the third segment is located in the junction box. The first segment and the third segment are both on the same side of the second segment and are both angularly connected to the second segment.

[0017] On the other hand, an embodiment of the present invention provides a photovoltaic system, including the above-mentioned perovskite and crystalline silicon tandem cell module.

[0018] The embodiments of the present invention at least have the following beneficial effects:

[0019] Through the voltage matching design and the safety gap design of the bus bars with the same polarity, the mutual interference between the outputs of the crystalline silicon cell layer and the perovskite cell layer can be reduced, meeting the requirements of output voltage stability and safety. By using parallel wires to parallelly output the signals of the bus bars with the same polarity, the number of junction boxes can be reduced, thereby reducing the cable cost and improving the compatibility of downstream products.

[0020] The additional aspects and advantages of the present invention will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the following description of embodiments in conjunction with the accompanying drawings, in which:

[0022] Figure 1 Schematic diagram of the stacked structure of the perovskite and crystalline silicon tandem cell module according to an embodiment of the present invention;

[0023] Figure 2 Schematic diagram of the structure of the perovskite and crystalline silicon tandem cell module according to an embodiment of the present invention;

[0024] Figure 3 is Figure 2 Perspective structure schematic diagram of the perovskite and crystalline silicon tandem cell module shown (one junction box is hidden);

[0025] Figure 4 is Figure 2 Cross-sectional schematic diagram of two examples of the parallel wires of the perovskite and crystalline silicon tandem cell module shown;

[0026] Figure 5 is Figure 2 Partial enlarged view of the circled position A in;

[0027] Figure 6 is Figure 2 Partial enlarged view of the circled position B in;

[0028] Figure 7 Schematic diagram of the structure of the terminal according to some embodiments of the present invention;

[0029] Figure 8 is Figure 3 Cross-sectional structure schematic diagram marked C-C in;

[0030] Figure 9 is Figure 8 Partial enlarged view of the circled position D in.

[0031] Reference numerals:

[0032] Crystalline silicon cell layer 100, first positive bus bar 110, first negative bus bar 120, perovskite cell layer 200, second positive bus bar 210, second negative bus bar 220, first segment 211, second segment 212, third segment 213, encapsulation material layer 300, first light-transmitting protective layer 400, first clearance hole 401, second clearance hole 402, second light-transmitting protective layer 500, junction box 600, parallel wire 610, first path 611, second path 612, insulating layer 613, first electrode 614, second electrode 615, first terminal 616, second terminal 617. Detailed implementation manners

[0033] Embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention.

[0034] In the description of the present invention, it should be understood that with regard to the orientation description, such as the orientation or positional relationship indicated by up, down, front, back, left, right, etc., is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0035] In the description of the present invention, the meaning of "several" is one or more, the meaning of "multiple" is more than two, greater than, less than, exceeding, etc. are understood not to include the present number, and "above", "below", "within", etc. are understood to include the present number. If there is a description of "first", "second", etc., it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0036] In the description of the present invention, unless otherwise clearly defined, words such as "set", "installed", "connected", etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0037] Solar energy, as a clean and renewable energy source, has received extensive attention. As a key device for converting solar energy into electrical energy, the conversion efficiency and stability of solar cells have always been the focus of research. Perovskite cells and crystalline silicon cells are two important technologies in the current solar cell field. Perovskite cells have the advantages of low cost, high conversion efficiency, and flexible preparation, while crystalline silicon cells have mature technologies and high stability. Stacking perovskite cells with crystalline silicon cells can make full use of the advantages of both and improve the overall performance of solar cells. However, traditional stacked cells have technical bottlenecks in current matching and process compatibility, which limit their development.

[0038] The wiring structure design of perovskite and crystalline silicon stacked cells is directly related to the efficiency, cost of the cell module, and compatibility with the downstream industrial chain. The current mainstream technical routes are two-terminal stacking and four-terminal stacking, and there are significant differences in their wiring methods, bus bar extraction, and the number of junction boxes.

[0039] The core of the structural design of the two-terminal tandem cell is to connect the perovskite cell and the crystalline silicon cell in series through a tunneling connection layer (composite junction) to form a single circuit output (i.e., one positive and one negative electrode each), and its wiring characteristics include:

[0040] 1) Internal series connection: The perovskite cell layer and the crystalline silicon cell layer are directly connected through a tunneling junction without external wiring, and the current is transmitted inside the tandem structure.

[0041] 2) Electrode simplification: Only one layer of transparent conductive electrode (such as TCO, Transparent Conductive Oxide) is required, avoiding the metal grid line design of traditional crystalline silicon cells and reducing light absorption loss.

[0042] 3) No need for laser scribing: The electrode adopts a conductive film + grid line process and is directly integrated with the crystalline silicon substrate, eliminating the P1 - P3 laser scribing steps of the perovskite single-junction cell.

[0043] In terms of busbars and junction boxes, since the output of the two-terminal tandem cell is a single positive and negative electrode, the busbar is usually led out from the edge of the module, and only one junction box is required.

[0044] The core of the structural design of the four-terminal tandem cell is mechanically stacked by independent perovskite cell layers and crystalline silicon cell layers, and the circuits are independent of each other. Its wiring characteristics include:

[0045] 1) Parallel optical coupling: The perovskite cell layer and the crystalline silicon cell layer are only optically coupled (i.e., sharing incident light), and the circuits are not directly connected. External wiring is required to achieve energy output.

[0046] 2) Dual-circuit output: The perovskite cell layer and the crystalline silicon cell layer each have a pair of positive and negative electrodes, that is, a total of four electrodes (two positives and two negatives) are required.

[0047] In terms of busbars and junction boxes, due to the mechanical stacking process, the perovskite cell layer and the crystalline silicon cell layer do not need to consider the voltage and current matching problems. Only the busbars need to be independently led out. The busbars are arranged vertically along the stacking direction and are isolated by encapsulation materials. Due to the need for independent wiring, the usage of cables and junction boxes is significantly higher than that of two-terminal tandem cells, resulting in an increase in material costs, and the wiring is complex, making it difficult for downstream products to be compatible.

[0048] In terms of applications, the two-terminal tandem cell is compatible with the existing industrial chain and has a lower cost, making it suitable for large-scale promotion, but the current matching problem needs to be solved; while the four-terminal tandem cell is easier to mass-produce in the short term due to its simple process (only mechanical stacking), but it faces challenges in industrial chain adaptation due to its split wiring and the design of four junction boxes.

[0049] To this end, this embodiment discloses a photovoltaic system including a perovskite and crystalline silicon tandem cell module, which can reduce the number of junction boxes, thereby reducing the cable cost and improving the compatibility of downstream products.

[0050] Please refer to Figure 1 , Figure 2 and Figure 3 , the perovskite and crystalline silicon tandem cell module includes a crystalline silicon cell layer 100, a perovskite cell layer 200, a packaging material layer 300 (such as EVA, ethylene-vinyl acetate copolymer, Ethylene Vinyl Acetate Copolymer), and a first light-transmitting protective layer 400. The perovskite cell layer 200 and the crystalline silicon cell layer 100 are stacked and have a mutually matching rated output voltage. The perovskite cell layer 200 and the crystalline silicon cell layer 100 are both provided with busbars of positive and negative polarities, and the busbars of the same polarity have a safety gap on the projection plane in the stacking direction (such as Figure 3 marked as L in

[0051] ); the packaging material layer 300 is stacked between the crystalline silicon cell layer 100 and the perovskite cell layer 200; the first light-transmitting protective layer 400 covers the crystalline silicon cell layer 100, and junction boxes 600 of positive and negative polarities are provided on the first light-transmitting protective layer 400. The junction boxes 600 are provided with parallel wires 610, and the parallel wires 610 have two conductive paths, and the two conductive paths are respectively conductively connected to the busbars of the same polarity of the crystalline silicon cell layer 100 and the perovskite cell layer 200.Exemplarily, the crystalline silicon cell layer 100 is located below the stack of the perovskite cell layer 200. The surface of the perovskite cell layer 200 is covered with a second light-transmitting protective layer 500. The crystalline silicon cell layer 100 and the perovskite cell layer 200 follow the design concept of a four-terminal stack. The crystalline silicon cell layer 100 and the perovskite cell layer 200 are processed by mechanical stacking, which has a simple process and enables the crystalline silicon cell layer 100 and the perovskite cell layer 200 to have independent positive and negative electrodes respectively. That is, the crystalline silicon cell layer 100 is provided with a first positive bus bar 110 and a first negative bus bar 120, and the perovskite cell layer 200 is provided with a second positive bus bar 210 and a second negative bus bar 220, which can ensure the working independence of the crystalline silicon cell layer 100 and the perovskite cell layer 200 without considering the problem of current matching. Different from the conventional four-terminal stacked cell, in this embodiment, voltage matching is performed on the crystalline silicon cell layer 100 and the perovskite cell layer 200, that is, the crystalline silicon cell layer 100 and the perovskite cell layer 200 have mutually matched rated output voltages, and the spatial layout of the bus bars with the same polarity of the crystalline silicon cell layer 100 and the perovskite cell layer 200 is adjusted, that is, the bus bars with the same polarity have a safety gap on the projection plane in the stacking direction. For example, the first positive bus bar 110 and the second positive bus bar 210 have a first safety gap on the projection plane in the stacking direction, and the first negative bus bar 120 and the second negative bus bar 220 have a second safety gap on the projection plane in the stacking direction. The bus bars with the same polarity are connected and output through the parallel wires 610 of the same junction box 600. Among them, the parallel wires 610 have two conductive paths connected in parallel, which can ensure the independence of the output of the crystalline silicon cell layer 100 and the perovskite cell layer 200, and the voltage matching design can reduce the voltage difference between the two conductive paths, thereby reducing the potential difference during parallel transmission and avoiding the circulating current or power loss caused by voltage imbalance, which is beneficial to improving the stability of energy transmission. Moreover, a safety gap is set on the projection plane in the stacking direction of the bus bars with the same polarity, and the electric field coupling and leakage current interference between conductors are weakened through physical isolation, reducing the short-circuit risk and meeting the insulation redundancy requirements under complex conditions such as high humidity and mechanical deformation. Using the parallel wires 610 with double conductive paths to connect the bus bars with the same polarity of the crystalline silicon cell layer 100 and the perovskite cell layer 200 in parallel can also reduce the number of junction boxes 600, simplify the processing process and reduce the cost of cable materials; by integrating the same-pole output of the double-cell layer through a single junction box 600, the number of connection nodes is reduced, avoiding the impedance mismatch and thermal failure hazards caused by multi-point contact, and at the same time improving the compatibility of downstream products (such as inverters or energy storage devices).

[0052] To ensure the stability of the output of the same-polarity parallel connection of the dual-battery layer, it is necessary to design the voltage matching of the dual-battery layer. In this embodiment, the perovskite battery layer 200 is cut into multiple battery units based on scribing segmentation, and the multiple battery units are connected in series to obtain a rated output voltage that matches the crystalline silicon battery layer 100. It is worth mentioning that the open-circuit voltage (Voc) of the perovskite battery layer 200 can be estimated using formula (1) according to parameters such as the bandgap (Eg), temperature (T), and Boltzmann constant (k) of the perovskite material, where n i is the intrinsic carrier concentration, N A and N D are the acceptor and donor impurity concentrations respectively, and q is the elementary charge.

[0053] Formula (1):

[0054] The related technology optimizes the open-circuit voltage of the perovskite battery layer 200 by adjusting the bandgap and impurity concentration of the material, thereby increasing the rated output voltage. However, achieving voltage matching between the two battery layers by adjusting the material bandgap and impurity concentration requires high process requirements. According to formula (1), under constant temperature conditions, the open-circuit voltage of a solar cell module is determined by the material. That is, when the material is determined, the open-circuit voltage is basically unchanged. For perovskite materials, when the product area is fixed, by dividing it into multiple battery units and connecting the multiple battery units in series, different rated output voltages can be obtained. For example, assume that in the design stage, first determine the rated output voltage of the crystalline silicon battery layer 100, such as 240V. For a product with an area of 1600*1200mm, the material used for the perovskite battery layer 200 is perovskite methylammonium lead iodide (MAPbI3), and the open-circuit voltage is about 1.2V. The perovskite methylammonium lead iodide battery panel can be laser scribed to be divided into 200 battery units, and the 200 battery units are connected in series to form the perovskite battery layer 200, obtaining a rated output voltage of about 240V. It should be noted that in this embodiment, the perovskite battery layer 200 and the crystalline silicon battery layer 100 are independent of each other for parallel output, and a safety gap is provided between the busbars of the same polarity. Therefore, the voltage matching between the perovskite battery layer 200 and the crystalline silicon battery layer 100 allows a certain range of voltage difference between the two, which is beneficial to increasing the redundancy of voltage matching and reducing the design and processing difficulties of voltage matching. In this way, by scribing and cutting and connecting multiple battery units in series, different rated output voltages can be formed, reducing the voltage matching difficulty of the dual-battery layer. In actual processing, scribing and dividing the crystalline silicon battery layer 100 causes greater damage to the photoelectric conversion efficiency of the battery layer, while the scribing processing difficulty and the damage to the photoelectric conversion efficiency of the perovskite battery layer 200 are relatively low. Therefore, in the design stage, the rated output voltage of the crystalline silicon battery layer 100 is preferably set first, and then the perovskite battery layer 200 is scribed and divided for voltage matching. Among them, the open-circuit voltage reflects the theoretical voltage output ability of the battery, while the output voltage reflects the voltage output situation of the battery under actual working conditions, and the output voltage is always less than or equal to the open-circuit voltage.

[0055] Please refer to Figure 4 , the two conductive paths of the parallel wire 610 are coaxially arranged, and the two conductive paths are as Figure 4The first path 611 and the second path 612 shown in (a) thereof, with the first path 611 disposed radially inside the second path 612, can effectively reduce the self - inductance and mutual inductance of the parallel wires 610, reduce battery interference and solve battery compatibility problems. The coaxial arrangement can also ensure uniform current distribution in the two conductive paths, avoid local overheating and current crowding, and is beneficial to improving the service life and safety of the wires. An insulating layer 613 is provided between the two conductive paths, which can control the capacitance effect between the wires, improve the stability and reliability of transmission, and has good mechanical strength and anti - bending ability, which is beneficial to improving the durability of the parallel wires 610. In some other application examples, the two conductive paths of the parallel wires 610 can be arranged side by side, such as Figure 4 the first path 611 and the second path 612 shown in (b) thereof, with an insulating layer 613 provided between the first path 611 and the second path 612.

[0056] In some application examples, the two conductive paths of the parallel wires 610 are respectively connected to a first electrode 614 and a second electrode 615, and the first electrode 614 and the second electrode 615 are coaxially arranged. Please refer to Figure 5 , Figure 5 In the terminal shown, the first electrode 614 is disposed on the inner side wall of the terminal, the second electrode 615 is located radially inside the first electrode 614, and in the axial direction, the second electrode 615 protrudes from the terminal relative to the first electrode 614. Please refer to Figure 6 , Figure 6 In the terminal shown, the first electrode 614 is disposed on the outer side wall of the terminal, and the second electrode 615 ( Figure 6 not shown, can be referred to Figure 5 ) is disposed on the inner side wall of the terminal (inside the jack K), and in the axial direction, the second electrode 615 is recessed into the terminal relative to the first electrode 614. The coaxial arrangement of the first electrode 614 and the second electrode 615 can achieve the parallel output of the double - battery layer, reduce the number of terminals, and improve the compatibility of downstream products.

[0057] In some other application examples, please refer to Figure 7 , the two conductive paths of the parallel wires 610 are respectively connected to an adjacent - arranged first terminal 616 and second terminal 617, a first electrode 614 is disposed inside the first terminal 616, and a second electrode 615 is disposed inside the second terminal 617. The first electrode 614 and the second electrode 615 are respectively disposed inside the adjacent - arranged first terminal 616 and second terminal 617, which can increase the safety gap between the first electrode 614 and the second electrode 615 and reduce the short - circuit risk. Among them, the two conductive paths in the parallel wires 610 can be coaxially arranged or arranged side by side.

[0058] Please refer to Figure 2 ,Figure 5 and Figure 6 , the positive-polarity junction box 600 is connected to a male connector (as shown at the circled position A in Figure 2 ), and the negative-polarity junction box 600 is connected to a female connector (as shown at the circled position B in Figure 2 ), and the male connector and the female connector are adapted to each other. Exemplarily, Figure 5 the terminal shown in Figure 6 is a male connector, and the terminal shown in

[0059] The first positive bus bar 110 and the second positive bus bar 210 are both connected to the male connector through the corresponding parallel wire 610 of the positive-polarity junction box 600. Similarly, the first negative bus bar 120 and the second negative bus bar 220 are both connected to the female connector through the corresponding parallel wire 610 of the negative-polarity junction box 600. It should be noted that the junction box 600 does not distinguish between positive and negative polarities before assembly. When the junction box 600 is connected to the positive-polarity bus bar, the polarity of the junction box 600 becomes positive; similarly, when the junction box 600 is connected to the negative-polarity bus bar, the polarity of the junction box 600 becomes negative. In application, the number of perovskite and crystalline silicon tandem cell modules is multiple to form a photovoltaic array, and adjacent perovskite and crystalline silicon tandem cell modules can be connected in series through the cooperation of the male connector and the female connector.

[0060] Please refer to Figure 3 , Figure 8 and Figure 9, the first light-transmitting protective layer 400 is provided with an adjacent first clearance hole 401 and a second clearance hole 402. The first clearance hole 401 extends to the crystalline silicon cell layer 100, and the second clearance hole 402 penetrates through the encapsulation material layer 300 and extends to the perovskite cell layer 200. The bus bar of the crystalline silicon cell layer 100 is inserted into the first clearance hole 401, and the bus bar of the perovskite cell layer 200 is inserted into the second clearance hole 402. The bus bars of the crystalline silicon cell layer 100 and the perovskite cell layer 200 extend to the surface of the first light-transmitting protective layer 400 through the first clearance hole 401 and the second clearance hole 402 respectively to enter the junction box 600. The bus bars can be protected by the first light-transmitting protective layer 400 and the encapsulation material layer 300. Moreover, the positions of the first clearance hole 401 and the second clearance hole 402 avoid the crystalline silicon cell layer 100 and the perovskite cell layer 200, which can prevent damage or blockage to the crystalline silicon cell layer 100 and the perovskite cell layer 200, and is beneficial to ensuring the photoelectric conversion efficiency of the crystalline silicon cell layer 100 and the perovskite cell layer 200.

[0061] Among them, please refer to Figure 9 , the bus bar of the perovskite cell layer 200 has a first segment 211, a second segment 212, and a third segment 213. The first segment 211 is located in the perovskite cell layer 200, the second segment 212 is located in the second clearance hole 402, and the third segment 213 is located in the junction box 600. The first segment 211 and the third segment 213 are both on the same side of the second segment 212 and are both angularly connected to the second segment 212. In this way, the first segment 211, the second segment 212, and the third segment 213 can form a 180° bending structure, increasing the spatial distance (such as shown by the mark H in Figure 9 ) between the bus bar of the perovskite cell layer 200 and the bus bar of the crystalline silicon cell layer 100 in the stacking direction, realizing the safety isolation between the bus bars of the same polarity, and being beneficial to reducing the mutual interference between the bus bars of the same polarity and reducing the short-circuit risk.

[0062] The embodiments of the present invention have been described in detail above with reference to the drawings. However, the present invention is not limited to the above embodiments. Various changes can be made without departing from the spirit of the present invention within the knowledge scope of those of ordinary skill in the art.

Claims

1. A perovskite and crystalline silicon stacked battery assembly, characterized in that: include: Crystalline silicon cell layer (100); A perovskite cell layer (200) is stacked and distributed with the crystalline silicon cell layer (100) and has a rated output voltage that matches the crystalline silicon cell layer (100), the perovskite cell layer (200) and the crystalline silicon cell layer (100) are both provided with positive and negative polarity bus bars, and the bus bars with the same polarity have a safety gap on a projection surface in the stacking direction; An encapsulation material layer (300), stacked and arranged between the crystalline silicon cell layer (100) and the perovskite cell layer (200); A first light-transmitting protective layer (400) is covered on the crystalline silicon cell layer (100); a junction box (600) of positive polarity and negative polarity is arranged on the first light-transmitting protective layer (400); the junction box (600) is provided with a parallel conductor (610); the parallel conductor (610) has two conductive paths that are coaxially arranged or arranged in parallel; an insulating layer (613) is provided between the two conductive paths; the two conductive paths are respectively conductively connected to bus bars of the same polarity of the crystalline silicon cell layer (100) and the perovskite cell layer (200); the two conductive paths are respectively connected to a first electrode (614) and a second electrode (615); the first electrode (614) and the second electrode (615) are coaxially arranged; or the two conductive paths are respectively connected to a first terminal (616) and a second terminal (617) arranged adjacent to each other; the first terminal (616) has the first electrode (614) provided therein; and the second terminal (617) has the second electrode (615) provided therein.

2. The perovskite and crystalline silicon stacked battery assembly according to claim 1, characterized in that: The perovskite battery layer (200) is divided into a plurality of battery units based on a line segmentation method, and the plurality of battery units are connected in series to obtain a rated output voltage matching the crystalline silicon battery layer (100).

3. The perovskite and crystalline silicon stacked battery assembly according to claim 1, characterized in that: The positive-polarity junction box (600) is connected to a male junction box via the corresponding parallel wire (610), and the negative-polarity junction box (600) is connected to a female junction box via the corresponding parallel wire (610), and the male junction box and the female junction box are adapted to each other.

4. The perovskite and crystalline silicon stacked battery assembly according to claim 1, characterized in that: The two conductive paths of the parallel conductor (610) are integrated into one.

5. The perovskite and crystalline silicon stacked battery assembly according to claim 1, characterized in that: The first light-transmitting protective layer (400) is provided with a first air-avoiding hole (401) and a second air-avoiding hole (402) which are arranged adjacent to each other; the first air-avoiding hole (401) extends to the crystalline silicon battery layer (100); the second air-avoiding hole (402) penetrates the packaging material layer (300) and extends to the perovskite battery layer (200); the bus bar of the crystalline silicon battery layer (100) is arranged through the first air-avoiding hole (401); and the bus bar of the perovskite battery layer (200) is arranged through the second air-avoiding hole (402).

6. The perovskite and crystalline silicon stacked battery assembly according to claim 5, characterized in that: The bus bar of the perovskite battery layer (200) comprises a first segment (211), a second segment (212) and a third segment (213); the first segment (211) is located in the perovskite battery layer (200); the second segment (212) is located in the second air avoidance hole (402); the third segment (213) is located in the junction box (600); the first segment (211) and the third segment (213) are both located on the same side of the second segment (212) and are both connected to the second segment (212) at an angle.

7. A photovoltaic system, characterized in that: It comprises the perovskite and crystalline silicon stacked battery assembly as described in any one of claims 1 to 6.

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