Display substrate

Abstract

The invention discloses a display substrate. The display substrate comprises a substrate body, a plurality of first electrodes and a plurality of pixel defining structures, the first electrodes and the pixel defining structures are arranged on the substrate body, the pixel defining structures are arranged between the adjacent first electrodes, and pixel openings exposing the first electrodes are formed; the pixel definition structure at least comprises a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer in the direction perpendicular to the substrate; the second insulating layer comprises a first sub-part, and the orthographic projection of the first sub-part on the substrate is not overlapped with the orthographic projection of the first electrode on the substrate; the surface, away from the substrate, of the first insulating layer is provided with a first recess recessed towards the substrate, and the orthographic projection of the first recess on the substrate is not overlapped with the orthographic projection of the first sub-part on the substrate.

Description

[0001] This application is a divisional application of an application with an application date of October 18, 2023, application number 202380011227.3, and invention name “Display substrate, preparation method thereof, and display device”. Technical Field

[0002] The embodiments of the present invention relate to but are not limited to the field of display technology, and in particular to a display substrate. Background Art

[0003] Micro Organic Light Emitting Diode (Micro OLED) is a micro display that has been developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED can not only realize active addressing of pixels, but also realize the preparation of pixel driving circuits and other structures on silicon-based substrates, which is conducive to reducing the system volume and achieving lightweight. Silicon-based OLED is prepared using mature complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) integrated circuit technology. It has the advantages of small size, high resolution (Pixels Per Inch, PPI), high refresh rate, etc. It is widely used in the field of virtual reality (VR) or augmented reality (AR) near-eye display. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiment of the present disclosure provides a display substrate, comprising a base substrate, a plurality of first electrodes and a plurality of pixel definition structures disposed on the base substrate, wherein the pixel definition structures are disposed between adjacent first electrodes and form pixel openings exposing the first electrodes; In a direction perpendicular to the substrate, the pixel definition structure at least includes a first insulating layer disposed on the substrate, a second insulating layer disposed on a side of the first insulating layer away from the substrate, a third insulating layer disposed on a side of the second insulating layer away from the substrate, and a fourth insulating layer disposed on a side of the third insulating layer away from the substrate, wherein the orthographic projections of the first insulating layer, the third insulating layer, and the fourth insulating layer on the substrate do not overlap with the orthographic projection of the first electrode on the substrate; The second insulating layer includes a first sub-portion, and an orthographic projection of the first sub-portion on the base substrate does not overlap with an orthographic projection of the first electrode on the base substrate; A first depression recessed toward the base substrate is disposed on a surface of the first insulating layer away from the base substrate, and an orthographic projection of the first depression on the base substrate does not overlap with an orthographic projection of the first sub-portion on the base substrate.

[0006] In some exemplary embodiments, an inner wall of the first recess close to the substrate is located between a surface of the first electrode away from the substrate and a surface of the first electrode close to the substrate.

[0007] In some exemplary embodiments, a third depth of the first recess is 0.01 μm to 0.03 μm, and the third depth is a maximum distance between an inner wall of the first recess on a side close to the substrate and the first sub-portion in a direction perpendicular to the substrate.

[0008] In some exemplary embodiments, the first recess is a smooth curved surface.

[0009] In some exemplary embodiments, the fourth insulating layer has a protrusion relative to a side wall of the third insulating layer, and the protrusion and the side wall of the third insulating layer form a first recessed portion that is recessed in a direction away from the pixel opening; The first depth is greater than the third depth, and the first depth is the maximum distance between a side wall of the fourth insulating layer close to the pixel opening and a side wall of the third insulating layer close to the pixel opening.

[0010] In some exemplary embodiments, a first depth of the first recess is 0.05 μm to 0.2 μm.

[0011] In some exemplary embodiments, a first height of the first recess is greater than the third depth, and the first height of the first recess is a maximum distance between a surface of the first recess close to the substrate and a surface of the first recess away from the substrate.

[0012] In some exemplary embodiments, the first indentation is a smooth curved surface.

[0013] In some exemplary embodiments, a surface of the second insulating layer away from the base substrate is provided with a first through hole extending toward the base substrate; The first through hole penetrates the second insulating layer in a direction perpendicular to the base substrate. The first through hole is connected to the first recess at one end close to the base substrate. The first through hole and the first recess constitute a second recess.

[0014] In some exemplary embodiments, a surface of the fourth insulating layer at a side away from the base substrate is provided with a smooth third recessed surface that is recessed toward the base substrate.

[0015] In some exemplary embodiments, a curvature of the third indentation is smaller than a curvature of the first indentation or a curvature of the second indentation.

[0016] In some exemplary embodiments, the first insulating layer has a first width, the third insulating layer has a third width, the fourth insulating layer has a fourth width, the first sub-portion has a fifth width, and the first width, the third width, the fourth width, and the fifth width are dimensions parallel to the substrate direction; The first width is greater than the fifth width, the fifth width is greater than the third width, and the third width is less than the fourth width.

[0017] In some exemplary embodiments, the first depth is half of a difference between the fourth width and the third width.

[0018] In some exemplary embodiments, orthographic projections of the third insulating layer and the fourth insulating layer on the base substrate are both located within a range of an orthographic projection of the first sub-portion on the base substrate.

[0019] In some exemplary embodiments, a side surface of the first insulating layer is aligned with a side surface of the first electrode.

[0020] In some exemplary embodiments, the display substrate further includes an organic light-emitting layer disposed on a side of the first electrode and the pixel definition structure away from the base substrate, the organic light-emitting layer includes a plurality of film layers, at least one film layer is disconnected at an edge of the fourth insulating layer, and a distortion region is provided at the disconnected portion of the film layer of the organic light-emitting layer.

[0021] In some exemplary embodiments, the distortion region includes at least one crack, and an orthographic projection of the distortion region on the substrate substrate does not overlap with an orthographic projection of the pixel opening on the substrate substrate.

[0022] In some exemplary embodiments, the display substrate further comprises a second electrode disposed on a side of the organic light-emitting layer away from the base substrate, the second electrode being provided with a puncture tip, the puncture tip being disposed in a crack of the distortion region, and an orthographic projection of the puncture tip on the base substrate having no overlap with an orthographic projection of the first electrode on the base substrate; The orthographic projection of the endpoint of the puncture tip on the substrate is located within the range of the orthographic projection of the first insulating layer on the substrate, and the endpoint of the puncture tip is the boundary point on the puncture tip that is closest to the substrate.

[0023] In some exemplary embodiments, an orthographic projection of an end point of the puncture tip on the base substrate is located within a range of an orthographic projection of the first sub-portion on the base substrate.

[0024] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0026] Figure 1 is a structural schematic diagram of a display device; Figure 2 It is a schematic diagram of a planar structure of a display substrate; Figure 3 A schematic diagram of a cross-sectional structure of a display substrate; Figure 4 It is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure; Figure 5 An enlarged view of a pixel definition structure of a display substrate of an exemplary embodiment of the present disclosure; Figure 6 It is a schematic diagram after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure; Fig. 7A After forming a pixel definition structure pattern for an exemplary embodiment of the present disclosure, Figure 1 ; Figure 7B After forming a pixel definition structure pattern for an exemplary embodiment of the present disclosure, Figure 2 ; Figure 7C After forming a pixel definition structure pattern for an exemplary embodiment of the present disclosure, Figure 3 ; Fig.7D After forming a pixel definition structure pattern for an exemplary embodiment of the present disclosure, Figure 4 ; Fig. 7E After forming a pixel definition structure pattern for an exemplary embodiment of the present disclosure, Figure 5 ; Figure 7F After forming a pixel definition structure pattern for an exemplary embodiment of the present disclosure, Figure 6 ; Figure 7G Schematic diagram 7 after forming a pixel definition structure pattern for an exemplary embodiment of the present disclosure; Figure 7H After forming a pixel definition structure pattern for an exemplary embodiment of the present disclosure, Figure 8 ; Figure 8 This is a schematic diagram of an exemplary embodiment of the present disclosure after forming an organic light-emitting layer pattern; Fig. 9 This is a schematic diagram after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure; Fig.10 It is a schematic structural diagram of an organic light-emitting layer according to an exemplary embodiment of the present disclosure; Fig.11 FIG. 4 is a schematic diagram of the structure of another organic light-emitting layer according to an exemplary embodiment of the present disclosure.

[0027] Description of reference numerals: 10-substrate substrate; 20-driving circuit layer; 30-light emitting structure layer; 31-first electrode; 32-pixel definition structure; 33-organic light emitting layer; 34-second electrode; 35-pixel opening; 40-first encapsulation layer; 50-color film structure layer; 60-second encapsulation layer; 70-cover plate layer; 101-first insulating layer; 102-second insulating layer; 103-third insulating layer; 104- fourth insulating layer; 105- first recess; 106- second recess; 107-distortion zone; 108-puncture tip; 109-third invagination; 111-first photoresist pattern; 112-second photoresist pattern; 33-1-first device; 33-2 - Charge generation layer; 33-3 - Second device. DETAILED DESCRIPTION

[0028] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.

[0029] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0030] The ordinal numbers such as "first", "second", and "third" in this article are set to avoid confusion among constituent elements rather than to limit the quantity.

[0031] In this document, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the implementation methods and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements can be appropriately changed according to the direction of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the text and can be appropriately replaced according to the circumstances.

[0032] In this document, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0033] In this article, a transistor refers to a component including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (or drain electrode terminal, drain region, or drain electrode) and a source electrode (or source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this article, the channel region refers to the region where the current mainly flows.

[0034] In this article, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" may sometimes be interchanged. Therefore, in this article, the "source electrode" and the "drain electrode" may be interchanged.

[0035] In this article, "electrical connection" includes the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. The "element having some electrical function" can be, for example, an electrode or wiring, or a switching element such as a transistor, or other functional elements such as a resistor, inductor or capacitor.

[0036] In this article, "parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes the state where the angle is greater than 85° and less than 95°.

[0037] In this document, "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced by "conductive film". Similarly, "insulating film" can sometimes be replaced by "insulating layer".

[0038] The term "about" as used herein refers to values ​​that are not strictly limited and allow for process and measurement errors.

[0039] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array, and the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, a clock signal suitable for the specification of the scan signal driver, a scan start signal, etc. to the scan signal driver, and a clock signal suitable for the specification of the light emitting signal driver, an emission stop signal, etc. to the light emitting signal driver. The data signal driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, and n may be a natural number. The scan signal driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may sequentially transmit a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal to generate a scan signal, and m may be a natural number. The luminous signal driver may generate an emission signal to be provided to the luminous signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the luminous signal driver may sequentially provide an emission signal having an off-level pulse to the luminous signal lines E1 to Eo. For example, the luminous signal driver may be constructed in the form of a shift register, and may sequentially transmit a luminous stop signal provided in the form of an off-level pulse to a next-level circuit under the control of a clock signal to generate a luminous signal, and o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emitting signal line, and i and j may be natural numbers. Sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0040] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.

[0041] In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in the present disclosure. In an exemplary embodiment, the shape of the sub-pixel in the pixel unit may be rectangular, rhombus, pentagonal, or hexagonal. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangle pattern. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square pattern, which is not limited in the present disclosure.

[0042] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating a structure that uses white light + color film to achieve full color. Figure 3 As shown, the display substrate of the silicon-based OLED display device may include: a base substrate 10, a driving circuit layer 20 disposed on the base substrate 10, a light emitting structure layer 30 disposed on the side of the driving circuit layer 20 away from the base substrate 10, a first encapsulation layer 40 disposed on the side of the light emitting structure layer 30 away from the base substrate 10, a color filter structure layer 50 disposed on the side of the first encapsulation layer 40 away from the base substrate 10, a second encapsulation layer 60 disposed on the side of the color filter structure layer 50 away from the base substrate 10, and a cover layer 70 disposed on the side of the second encapsulation layer 60 away from the base substrate 10. In some possible implementations, the display substrate may include other film layers, which are not limited in the present disclosure.

[0043] In an exemplary embodiment, the substrate 10 may be a bulk silicon substrate or a silicon on insulator (SOI) substrate. The driving circuit layer 20 may be prepared on the substrate 10 by a silicon semiconductor process (e.g., a CMOS process). The driving circuit layer 20 may include a plurality of circuit units, at least one of which may include a pixel driving circuit, the pixel driving circuits are respectively connected to the scanning signal lines and the data signal lines, and at least one of which may include a plurality of transistors and a storage capacitor. Figure 3 In the example, a pixel driving circuit includes only one transistor. The transistor may include a control electrode, a first electrode, and a second electrode, and the control electrode, the first electrode, and the second electrode may be connected to corresponding connection electrodes through vias filled with tungsten metal (i.e., tungsten vias, W vias), and may be connected to other electrical structures (such as wiring, etc.) through the connection electrodes.

[0044] In an exemplary embodiment, the light emitting structure layer 30 may include a plurality of light emitting devices, and the light emitting devices of the light emitting structure layer 30 may be organic light emitting diodes (OLEDs) or quantum dot light emitting diodes (QLEDs), etc. The embodiment of the present disclosure does not limit the type of light emitting devices, and the light emitting devices may include at least a first electrode, an organic light emitting layer, and a second electrode. The first electrode may be connected to the second electrode of the transistor through a connecting electrode, the organic light emitting layer is connected to the first electrode, the second electrode is connected to the organic light emitting layer, and the second electrode is connected to the second power line. The organic light emitting layer emits light under the drive of the first electrode and the second electrode. The first electrode may be arranged on a side of the driving circuit layer 20 away from the base substrate 10, and the organic light emitting layer and the second electrode are sequentially stacked on a side of the first electrode away from the base substrate 10.

[0045] In an exemplary embodiment, the light emitting structure layer 30 may further include a pixel definition layer, a pixel opening is disposed on the pixel definition layer of each sub-pixel, and the pixel opening exposes the first electrode, so that the organic light emitting layer is connected to the first electrode through the pixel opening.

[0046] In an exemplary embodiment, since the organic light-emitting layer emits light in the pixel opening area set by the pixel definition layer, the sub-pixel may include a pixel light-emitting area and a pixel spacing area, the pixel light-emitting area is the light-emitting area, and the area outside the pixel opening is the pixel spacing area, and the pixel spacing area is located at the periphery of the light-emitting area.

[0047] In an exemplary embodiment, the first encapsulation layer 40 and the second encapsulation layer 60 can adopt a thin film encapsulation (Thin Film Encapsulation, referred to as TFE) method to ensure that external water vapor cannot enter the organic light-emitting layer. The cover layer 70 can be made of glass, or a plastic colorless polyimide with flexible properties.

[0048] In an exemplary embodiment, the color film structure layer 50 may include a black matrix (BM) and a color filter (CF), and the color filters are respectively arranged in the red sub-pixel, the green sub-pixel and the blue sub-pixel to filter the white light emitted by the light-emitting device into red (R) light, green (G) light and blue (B) light, and the black matrix may be located between adjacent color filters.

[0049] In an exemplary embodiment, the organic light emitting layer is configured to emit white light, and may be prepared by evaporation or inkjet printing, and the organic light emitting layers of all sub-pixels may be a common layer connected together.

[0050] The resolution and brightness requirements of silicon-based OLED screens are increasing. The brightness has exceeded 5000nits, the resolution requirement has exceeded 3000PPI, and the sub-pixel spacing has entered the 1μm level, which further exposes the lateral leakage of some film layers in the organic light-emitting layer and the lateral current crosstalk between adjacent sub-pixels. At present, related technologies have proposed a variety of solutions to the lateral current crosstalk problem, such as adjusting the pixel spacing and adjusting the highly conductive organic film layer material. Research has found that these solutions not only have limited effects in cutting off lateral leakage, but also affect the voltage of the light-emitting device, reduce the luminous efficiency, and cause a large loss of brightness.

[0051] The embodiment of the present disclosure provides a display substrate, comprising a base substrate, a plurality of first electrodes arranged on the base substrate, and a plurality of pixel definition structures, wherein the pixel definition structures are arranged between adjacent first electrodes and form pixel openings exposing the first electrodes; in a direction perpendicular to the base substrate, the pixel definition structure comprises at least a first insulating layer arranged on the base substrate, a second insulating layer arranged on a side of the first insulating layer away from the base substrate, a third insulating layer arranged on a side of the second insulating layer away from the base substrate, and a fourth insulating layer arranged on a side of the third insulating layer away from the base substrate, wherein the orthographic projections of the first insulating layer, the third insulating layer, and the fourth insulating layer on the base substrate do not overlap with the orthographic projections of the first electrode on the base substrate, and the orthographic projections of the second insulating layer on the base substrate at least partially overlap with the orthographic projections of the first electrode on the base substrate; a second recessed portion concave toward the base substrate is arranged on a surface of the second insulating layer away from the base substrate, and an inner wall of the second recessed portion close to the base substrate is located between a surface of the first electrode away from the base substrate and a surface of the first electrode close to the base substrate. The display substrate provided in this embodiment can partition the organic light-emitting layer through the pixel definition structure to cut off lateral leakage, while preventing the second electrode from being broken, thereby improving the display effect.

[0052] In an exemplary embodiment, a second depth of the second recess is 0.01 μm to 0.06 μm, and the second depth is a maximum distance between an inner wall of the second recess close to the base substrate and a surface of the second insulating layer away from the base substrate.

[0053] In an exemplary embodiment, a surface of the first insulating layer away from the base substrate is flush with a surface of the first electrode away from the base substrate, and a surface of the first insulating layer away from the base substrate is lower than a surface of the first electrode away from the base substrate.

[0054] In an exemplary embodiment, a material of the third insulating layer is different from a material of the fourth insulating layer, and a material of the second insulating layer is the same as a material of the fourth insulating layer.

[0055] In an exemplary embodiment, the fourth insulating layer has a protrusion relative to the side wall of the third insulating layer, and the protrusion and the side wall of the third insulating layer form a first recess that is recessed in a direction away from the pixel opening, and a first depth of the first recess is greater than a second depth of the second recess, and the first depth is the maximum distance between the side wall of the fourth insulating layer close to the pixel opening and the side wall of the third insulating layer close to the pixel opening.

[0056] In an exemplary embodiment, the display substrate also includes an organic light-emitting layer arranged on a side of the first electrode and the pixel definition structure away from the base substrate, the organic light-emitting layer includes a plurality of film layers, at least one film layer is disconnected at an edge of the fourth insulating layer, and the film layers of the organic light-emitting layer form a distortion region at the disconnection.

[0057] Figure 4 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure. Figure 5 for Figure 4 A magnified image of the pixel definition structure. Figure 4 and 5 As shown, the display substrate of this exemplary embodiment may include a base substrate 10, a plurality of first electrodes 31 and a plurality of pixel definition structures 32 arranged on the base substrate 10, an organic light-emitting layer 33 arranged on a side of the first electrodes 31 and the pixel definition structure 32 away from the base substrate 10, and a second electrode 34 arranged on a side of the organic light-emitting layer 33 away from the base substrate 10.

[0058] In an exemplary embodiment, the pixel definition structure 32 is disposed between adjacent first electrodes 31 and forms a pixel opening 35 exposing the first electrode 31 . The pixel definition structure 32 may include a plurality of inorganic layers stacked on the base substrate 10 .

[0059] In an exemplary embodiment, the multiple inorganic layers of the pixel definition structure 32 may include at least a first insulating layer 101 disposed on the base substrate 10, a second insulating layer 102 disposed on a side of the first insulating layer 101 away from the base substrate 10, a third insulating layer 103 disposed on a side of the second insulating layer 102 away from the base substrate 10, and a fourth insulating layer 104 disposed on a side of the third insulating layer 103 away from the base substrate 10.

[0060] In an exemplary embodiment, the first insulating layer 101 is disposed between adjacent first electrodes 31 , the side surface of the first insulating layer 101 may be aligned with the side surface of the first electrode 31 , and the orthographic projection of the first insulating layer 101 on the base substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the base substrate 10 .

[0061] In an exemplary embodiment, a surface of the first insulating layer 101 away from the base substrate 10 is substantially flush with a surface of the first electrode 31 away from the base substrate 10 , and a surface of the first insulating layer 101 away from the base substrate 10 is lower than a surface of the first electrode 31 away from the base substrate 10 .

[0062] In an exemplary embodiment, the first insulating layer 101 has a first width L1 , which is a dimension of the first insulating layer 101 in a direction parallel to the base substrate 10 .

[0063] In an exemplary embodiment, the first width L1 may be about 1.0 μm to 1.2 μm. For example, the first width L1 may be about 1.1 μm.

[0064] In an exemplary embodiment, the orthographic projection of the second insulating layer 102 on the base substrate 10 at least partially overlaps with the orthographic projection of the first electrode 31 on the base substrate 10 , and the second insulating layer 102 has a second width L2 , which is the dimension of the second insulating layer 102 in a direction parallel to the base substrate 10 .

[0065] In an exemplary embodiment, the second width L2 of the second insulating layer 102 is greater than the first width L1 of the first insulating layer 101 , ie, L2 > L1 .

[0066] In an exemplary embodiment, the difference between the second width L2 and the first width L1 is greater than or equal to 0.1 μm. The second width L2 may be approximately 1.2 μm to 1.6 μm. For example, the second width L2 may be approximately 1.4 μm.

[0067] In an exemplary embodiment, the width of the overlapped region of the second insulating layer 102 and the first electrode 31 is greater than or equal to 0.1 μm, so that the second insulating layer 102 can effectively cover the edge of the first electrode 31. In other words, the pixel definition structure 32 does not expose the edge of the first electrode 31, which is provided by forming the second insulating layer 102 wider than the first insulating layer 101.

[0068] In an exemplary embodiment, the difference between the second width L2 and the first width L1 may be about 0.3 μm, so that the second insulating layer 102 effectively covers a single side of the first electrode 31 by about 0.15 μm.

[0069] In an exemplary embodiment, an orthographic projection of the third insulating layer 103 on the base substrate 10 does not overlap with an orthographic projection of the first electrode 31 on the base substrate 10 , and an orthographic projection of the fourth insulating layer 104 on the base substrate 10 does not overlap with an orthographic projection of the first electrode 31 on the base substrate 10 .

[0070] In an exemplary embodiment, the material of the third insulating layer 103 may be different from the material of the fourth insulating layer 104, and the material of the second insulating layer 102 may be the same as the material of the fourth insulating layer 104, so that a recessed structure can be produced due to the difference in etching rates of the two materials. For example, the materials of the second insulating layer 102 and the fourth insulating layer 104 may both be silicon oxide (SiOX), and the material of the third insulating layer 103 may be silicon nitride (SiNX).

[0071] In an exemplary embodiment, the third insulating layer 103 has a third width L3 , and the fourth insulating layer 104 has a fourth width L4 . The fourth width L4 may be greater than the third width L3 . The third width L3 and the fourth width L4 are dimensions in a direction parallel to the base substrate 10 .

[0072] In exemplary embodiments, the third width L3 may be the minimum width of the third insulating layer 103 and the fourth width L4 may be the maximum width of the fourth insulating layer 104 , or the third width L3 may be the average width of the third insulating layer 103 and the fourth width L4 may be the average width of the fourth insulating layer 104 .

[0073] In an exemplary embodiment, the difference between the fourth width L4 and the third width L3 may be approximately 0.1 μm to 0.4 μm.

[0074] In an exemplary embodiment, the third width L3 may be about 0.3 μm to 0.5 μm. In an exemplary embodiment, the third width L3 may be about 0.4 μm. The fourth width L4 may be about 0.5 μm to 0.7 μm. For example, the fourth width L4 may be about 0.6 μm.

[0075] In an exemplary embodiment, the fourth width L4 may be less than the first width L1, i.e., L4 < L1.

[0076] In an exemplary embodiment, the fourth width L4 may be less than the second width L2, i.e., L4 < L2. The difference between the fourth width L4 and the second width L2 is greater than or equal to 0.3 μm.

[0077] In an exemplary embodiment, the fourth insulating layer 104 has a protrusion with respect to the sidewall of the third insulating layer 103, and the protrusion and the sidewall of the third insulating layer 103 form a first indentation 105 that is recessed away from the pixel opening 35. The first indentation 105 may be a curved surface shape with curvature.

[0078] In an exemplary embodiment, the first indentation 105 may have a first depth ΔL. The first depth ΔL may be the maximum distance between the sidewall of the fourth insulating layer 104 closer to the pixel opening 35 and the sidewall of the third insulating layer 103 closer to the pixel opening 35. The first depth ΔL may be a dimension in the direction parallel to the substrate 10.

[0079] In an exemplary embodiment, the first depth ΔL of the first indentation 105 may be half of the difference between the fourth width L4 and the third width L3, where ΔL = (L4 - L3) / 2.

[0080] In an exemplary embodiment, the first depth ΔL of the first indentation 105 may be approximately 0.05 μm to 0.2 μm; In an exemplary embodiment, the difference between the second width L2 and the fourth width L4 may be approximately 0.8 μm, such that the orthographic projection of the first indentation 105 on the substrate 10 does not overlap with the orthographic projection of the pixel opening 35 on the substrate 10.

[0081] In an exemplary embodiment, the fourth width L4 may be less than the second width L2, and the third width L3 may be less than the fourth width L4, i.e., L3 < L4 < L2.

[0082] In an exemplary embodiment, a second indentation 106 is provided on the surface of the second insulating layer 102 away from the substrate 10 and is recessed toward the substrate 10. The inner wall of the second indentation 106 closer to the substrate 10 is located between the surface of the first electrode 31 away from the substrate 10 and the surface of the first electrode 31 closer to the substrate 10. The second indentation 106 may be a curved surface shape with curvature. The second indentation 106 may have a second depth ΔD. The second depth ΔD may be the maximum distance between the inner wall of the second indentation 106 closer to the substrate 10 and the surface of the second insulating layer 102 away from the substrate 10. The second depth ΔD may be a dimension in the direction perpendicular to the substrate 10.

[0083] In an exemplary embodiment, the second depth ΔD of the second recess 106 may be approximately 0.01 μm to 0.06 μm; and the cross-sectional size of the second recess 106 gradually increases in a direction away from the base substrate 10 .

[0084] In an exemplary embodiment, a first depth ΔL of the first indentation 105 is greater than a second depth ΔD of the second indentation 106 .

[0085] In an exemplary embodiment, a first height ΔH of the first recess 105 is greater than a second depth ΔD of the second recess 106 . The first height ΔH of the first recess 105 is the maximum distance between a surface of the first recess 105 close to the base substrate 10 and a surface of the first recess 105 far from the base substrate 10 .

[0086] In an exemplary embodiment, a surface of the fourth insulating layer 104 away from the substrate 10 is provided with a smooth third recess 109 recessed toward the substrate 10. The third recess 109 may be a curved surface with a curvature. The curvature of the third recess 109 is smaller than the curvature of the first recess 105 or the curvature of the second recess 106.

[0087] In an exemplary embodiment, the display substrate further includes an organic light-emitting layer 33 disposed on a side of the first electrode 31 and the pixel definition structure 32 away from the base substrate 10, the organic light-emitting layer 33 includes a plurality of film layers, at least one film layer is disconnected at the edge of the fourth insulating layer 104, and the film layer of the organic light-emitting layer 33 is provided with a distortion region 107 at the disconnection, as shown in a dotted box. In an exemplary embodiment, the distortion region 107 may include at least one crack, and the organic light-emitting layer 33 on both sides of the crack forms a step difference due to the disconnection.

[0088] In an exemplary embodiment, an orthographic projection of the distortion region 107 on the base substrate 10 does not overlap with an orthographic projection of the pixel opening 35 on the base substrate 10 .

[0089] In an exemplary embodiment, the display substrate further includes a second electrode 34 disposed on a side of the organic light-emitting layer 33 away from the base substrate 10, the second electrode 34 is provided with a puncture tip 108, the puncture tip 108 is disposed in a crack of the distortion region 107, and the orthographic projection of the puncture tip 108 on the base substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the base substrate 10.

[0090] The orthographic projection of the endpoint of the puncture tip 108 on the base substrate 10 is within the range of the orthographic projection of the first insulating layer 101 on the base substrate 10 . The endpoint of the puncture tip 108 is the boundary point on the puncture tip 108 closest to the base substrate 10 .

[0091] In an exemplary embodiment, the first insulating layer 101 in the pixel definition structure 32 has a first thickness D1, the second insulating layer 102 has a second thickness D2, the third insulating layer 103 has a third thickness D3, and the fourth insulating layer 104 has a fourth thickness D4. The first thickness D1, the second thickness D2, the third thickness D3, and the fourth thickness D4 are dimensions in a direction perpendicular to the substrate 10. The first thickness D1 may be about 900 angstroms to 1100 angstroms, for example, the first thickness D1 may be about 1000 angstroms. The second thickness D2 may be about 300 angstroms to 500 angstroms, for example, the second thickness D2 may be about 400 angstroms. The third thickness D3 may be about 500 angstroms to 700 angstroms, for example, the third thickness D3 may be about 600 angstroms. The fourth thickness D4 may be about 100 angstroms to 300 angstroms, for example, the fourth thickness D4 may be about 200 angstroms.

[0092] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be any one or more of sputtering, evaporation, chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged on the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0093] In an exemplary embodiment, taking three sub-pixels of a display substrate as an example, the preparation process of the display substrate may include the following operations.

[0094] A. Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on the base substrate 10, patterning the first conductive film through a patterning process to form a first conductive layer pattern, wherein the first conductive layer pattern includes at least a first electrode 31 located in each sub-pixel, such as Figure 6 shown.

[0095] In an exemplary embodiment, the first electrode 31 may be made of a metal material or a transparent conductive material. The metal material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals. The transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO). In an exemplary embodiment, the first electrode 31 may be a single-layer structure or a multi-layer composite structure. In an exemplary embodiment, the multi-layer composite structure may include a Ti layer, an Al layer, a titanium nitride (TiN) layer and an ITO layer sequentially arranged in a direction away from the base substrate 10, which can meet the conventional requirements of high reflectivity, low roughness and work function matching of the light-emitting device.

[0096] In an exemplary embodiment, the first electrode 31 has a first electrode thickness, which may be about 900 angstroms to about 1100 angstroms, and the first electrode thickness is a dimension in a direction perpendicular to the base substrate 10. For example, the first thickness D1 may be about 1000 angstroms.

[0097] B. Forming a pixel definition structure pattern. In an exemplary embodiment, the pixel definition structure pattern includes at least a pixel definition structure 32 located in each sub-pixel, the pixel definition structure 32 is disposed between adjacent first electrodes 31, and forms a pixel opening exposing the first electrode 31. Forming the pixel definition structure pattern may include:

[0098] B1. Forming a first insulating layer pattern. In an exemplary embodiment, forming the first insulating layer pattern may include: first depositing a first insulating film, such as Fig. 7A Then, the first insulating film is etched back through the entire surface to form a first insulating layer 101, as shown in FIG. Figure 7B shown.

[0099] In an exemplary embodiment, the first insulating layer 101 is disposed between adjacent first electrodes 31 , the orthographic projection of the first insulating layer 101 on the base substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the base substrate 10 , and the side surface of the first insulating layer 101 may be in contact with the side surface of the first electrode 31 .

[0100] In an exemplary embodiment, through a full-surface etching process, the surface of the first insulating layer 101 away from the base substrate 10 is substantially flush with the surface of the first electrode 31 away from the base substrate 10, and the surface of the first insulating layer 101 away from the base substrate 10 is lower than the surface of the first electrode 31 away from the base substrate 10.

[0101] In an exemplary embodiment, the first insulating layer 101 may be a planarization layer. The side surface of the first insulating layer 101 may be attached to the side surface of the first electrode 31, so that a flat area of ​​a preset width is formed at the contact between the first insulating layer 101 and the first electrode. The first insulating layer 101 has a first width L1, and the first width L1 is a dimension in a direction parallel to the base substrate 10. In an exemplary embodiment, the first width L1 may be approximately 1.0 μm to 1.2 μm. For example, the first width L1 may be approximately 1.1 μm.

[0102] In an exemplary embodiment, the first insulating layer 101 may have a first thickness D1. The first thickness D1 may be about 900 angstroms to about 1100 angstroms. For example, the first thickness D1 may be about 1000 angstroms.

[0103] In an exemplary embodiment, the material of the first insulating layer 101 is an inorganic material. For example, the material of the first insulating layer 101 is silicon oxide (SiOX).

[0104] B2. Forming second insulating film, third insulating film and fourth insulating film patterns. In an exemplary embodiment, forming the second insulating film, third insulating film and fourth insulating film patterns may include: sequentially depositing the second insulating film, the third insulating film and the fourth insulating film on the substrate on which the aforementioned patterns are formed, such as Figure 7C shown.

[0105] In an exemplary embodiment, the second insulating layer 102 in the pixel definition structure 32 has a second thickness D2, which is the size of the second insulating layer 102 in a direction perpendicular to the base substrate 10, and the second thickness D2 may be about 300 angstroms to 500 angstroms. For example, the second thickness D2 may be about 400 angstroms. In an exemplary embodiment, the third insulating layer 103 has a third thickness D3, which is the size of the third insulating layer 103 in a direction perpendicular to the base substrate 10, and the third thickness D3 may be about 500 angstroms to 700 angstroms. For example, the third thickness D3 may be about 600 angstroms. In an exemplary embodiment, the fourth insulating layer 104 has a fourth thickness D4, which is the size of the fourth insulating layer 104 in a direction perpendicular to the base substrate 10, and the fourth thickness D4 may be about 100 angstroms to 300 angstroms. For example, the fourth thickness D4 may be about 200 angstroms.

[0106] In an exemplary embodiment, the second insulating film, the third insulating film, and the fourth insulating film are all inorganic materials, the material of the third insulating film may be different from the material of the fourth insulating film, and the material of the second insulating film may be the same as the material of the fourth insulating film. For example, the materials of the second insulating film and the fourth insulating film are both silicon oxide (SiOX), and the material of the third insulating film is silicon nitride (SiNX).

[0107] B3. First, a photoresist is coated on the fourth insulating film, and a first photoresist pattern 111 is formed by exposure and development, such as Fig.7D shown.

[0108] In an exemplary embodiment, the first photoresist pattern 111 has a second width L2, which is a dimension of the second photoresist pattern 112 in a direction parallel to the base substrate 10, and the second width L2 may be greater than the first width L1. In an exemplary embodiment, the second width L2 may be approximately 1.2 μm to 1.6 μm. For example, the second width L2 may be approximately 1.4 μm.

[0109] Then, the second insulating film, the third insulating film and the fourth insulating film which are not coated with the photoresist are etched to form a first transition pattern, such as Fig. 7E shown.

[0110] In exemplary embodiments, the first transition pattern may include a stacked second insulating layer 102 , a third insulating layer 103 , and a fourth insulating layer 104 , the second insulating layer 102 , the third insulating layer 103 , and the fourth insulating layer 104 having substantially the same second width L2 .

[0111] In an exemplary embodiment, the orthographic projection of the second insulating layer 102 on the base substrate 10 includes the orthographic projection of the first insulating layer 101 on the base substrate 10 , and the orthographic projection of the second insulating layer 102 on the base substrate 10 at least partially overlaps with the orthographic projection of the first electrode 31 on the base substrate 10 .

[0112] In an exemplary embodiment, an orthographic projection of the second insulating layer 102 on the base substrate 10 at least partially overlaps an orthographic projection of the first electrode 31 on the base substrate 10 , and at least partially exposes the first electrode 31 .

[0113] In an exemplary embodiment, the difference between the second width L2 of the second insulating layer 102 and the first width L1 of the first insulating layer 101 is greater than or equal to 0.1 μm. The width of the overlapping region between the second insulating layer 102 and the first electrode 31 can be greater than 0.1 μm, such that the second insulating layer 102 can effectively wrap the edge of the first electrode 31. That is, the pixel defining structure 32 does not expose the edge of the first electrode 31, which is provided by forming the second insulating layer 102 wider than the first insulating layer 101.

[0114] In an exemplary embodiment, the difference between the second width L2 and the first width L1 can be about 0.3 μm, such that the second insulating layer 102 effectively wraps about 0.15 μm on one side of the first electrode 31.

[0115] B4. First, a photoresist indentation method is used to reduce the width of the photoresist pattern, forming a second photoresist pattern 112, as Figure 7F shown.

[0116] In an exemplary embodiment, the second photoresist pattern 113 has a fourth width L4, which is the dimension of the third photoresist pattern 113 in the direction parallel to the substrate 10. The fourth width L4 can be about 0.5 μm to 0.7 μm. For example, the fourth width L4 can be about 0.6 μm.

[0117] Subsequently, the exposed third insulating layer 103 and fourth insulating layer 104 are etched to form a pattern of the second transition pattern, as Figure 7G shown.

[0118] In an exemplary embodiment, the second transition pattern may include the stacked third insulating layer 103 and fourth insulating layer 104, and the third insulating layer 103 and the fourth insulating layer 104 have substantially the same fourth width L4.

[0119] In an exemplary embodiment, the orthographic projection of the third insulating layer 103 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10, and the orthographic projection of the fourth insulating layer 104 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10.

[0120] In an exemplary embodiment, the fourth width L4 can be less than the first width L1, i.e., L4 < L1.

[0121] In an exemplary embodiment, the fourth width L4 can be less than the second width L2, i.e., L4 < L2. The difference between the fourth width L4 and the second width L2 can be greater than or equal to 0.3 μm.

[0122] Subsequently, by changing the ratio of the etching gas, the side surface of the third insulating layer 103 is etched so that the fourth insulating layer 104 has a protrusion relative to the side wall of the third insulating layer 103, and the protrusion and the side wall of the third insulating layer 103 form a first indentation 105. In this etching process, the etching gas will etch the surface of the second insulating layer 102 away from the substrate 10 side, and a second indentation 106 is formed on the surface of the second insulating layer 102. In this etching process, the etching gas will etch the surface of the fourth insulating layer 104 away from the substrate 10 side to form a third indentation 109. After removing the remaining photoresist, a pixel definition structure pattern is formed, such as Figure 7H shown.

[0123] In an exemplary embodiment, the pixel definition structure 32 may include a second insulating layer 102, a third insulating layer 103, and a fourth insulating layer 104 sequentially disposed on the first insulating layer 101. The orthographic projection of the first insulating layer 101 on the substrate is within the range of the orthographic projection of the second insulating layer 102 on the substrate. The orthographic projection of the fourth insulating layer 1044 on the substrate is within the range of the orthographic projection of the first insulating layer 101 on the substrate. The orthographic projection of the third insulating layer 103 on the substrate is within the range of the orthographic projection of the fourth insulating layer 104 on the substrate.

[0124] In an exemplary embodiment, the first insulating layer 101 has a first width L1, the second insulating layer 102 has a second width L2, the third insulating layer 103 has a third width L3, and the fourth insulating layer 104 has a fourth width L4. In an exemplary embodiment, the first width L1 may be less than the second width L2, the fourth width L4 may be less than the first width L1, and the third width L3 may be less than the fourth width L4, that is, L3 < L4 < L1 < L2. The first width L1, the second width L2, the third width L3, and the fourth width L4 are dimensions in the direction parallel to the substrate 10.

[0125] In an exemplary embodiment, the third width L3 may be the minimum width of the third insulating layer 103, and the fourth width L4 may be the maximum width of the fourth insulating layer 104. Alternatively, the third width L3 may be the average width of the third insulating layer 103, and the fourth width L4 may be the average width of the fourth insulating layer 104.

[0126] In an exemplary embodiment, the difference between the fourth width L4 and the third width L3 may be about 0.1 μm to 0.4 μm.

[0127] In an exemplary embodiment, the third width L3 may be about 0.3 μm to 0.5 μm. In an exemplary embodiment, the third width L3 may be about 0.4 μm.

[0128] In an exemplary embodiment, the fourth insulating layer 104 has a protrusion relative to the sidewall of the third insulating layer 103, and the protrusion and the sidewall of the third insulating layer 103 form a first recess 105 recessed away from the pixel opening 35. The first recess 105 may be a curved surface with curvature.

[0129] In an exemplary embodiment, the first recess 105 may have a first depth ΔL, which may be a maximum distance between a sidewall of the fourth insulating layer 104 close to the pixel opening 35 and a sidewall of the third insulating layer 103 close to the pixel opening 35 .

[0130] In an exemplary embodiment, the first depth ΔL of the first recess 105 may be half of the difference between the fourth width L4 and the third width L3 , where ΔL=( L4 − L3 ) / 2.

[0131] In an exemplary embodiment, the first depth ΔL of the first recess 105 may be approximately 0.05 μm to 0.2 μm; In an exemplary embodiment, the difference between the second width L2 and the fourth width L4 may be about 0.8 μm, so that the orthographic projection of the first recess 105 on the base substrate 10 does not overlap with the orthographic projection of the pixel opening 35 on the base substrate 10 .

[0132] In an exemplary embodiment, a second recess 106 that is recessed toward the substrate 10 is provided on a surface of the second insulating layer 102 that is away from the substrate 10, and an inner wall of the second recess 106 that is close to the substrate 10 is located between a surface of the first electrode 31 that is away from the substrate 10 and a surface of the first electrode 31 that is close to the substrate 10. The second recess 106 may be in a curved shape with a curvature. The second recess 106 may be in a curved shape with a curvature. The second recess 106 may have a second depth ΔD, and the second depth ΔD may be the maximum distance between an inner wall of the second recess 106 that is close to the substrate 10 and a surface of the second insulating layer 102 that is away from the substrate 10, and the second depth ΔD may be a dimension of the second recess in a direction perpendicular to the substrate 10.

[0133] In an exemplary embodiment, the second depth ΔD of the second recess 106 may be approximately 0.01 μm to 0.06 μm; and the cross-sectional size of the second recess 106 gradually increases in a direction away from the base substrate 10 .

[0134] In an exemplary embodiment, a first depth ΔL of the first indentation 105 is greater than a second depth ΔD of the second indentation 106 .

[0135] In an exemplary embodiment, a first height ΔH of the first recess 105 is greater than a second depth ΔD of the second recess 106 . The first height ΔH of the first recess 105 is the maximum distance between a surface of the first recess 105 close to the substrate 10 and a surface of the first recess 105 far from the substrate 10 .

[0136] In an exemplary embodiment, a surface of the fourth insulating layer 104 away from the substrate 10 is provided with a smooth third recess 109 recessed toward the substrate 10. The third recess 109 may be a curved surface with a curvature. The curvature of the third recess 109 is smaller than the curvature of the first recess 105 or the curvature of the second recess 106.

[0137] C. Forming an organic light-emitting layer pattern. In an exemplary embodiment, forming an organic light-emitting layer pattern may include: forming an organic light-emitting layer pattern by evaporation or the like, wherein the organic light-emitting layer 33 of each sub-pixel is connected to the first electrode 31 of the sub-pixel through the pixel opening 35, such as Figure 8 shown.

[0138] In an exemplary embodiment, the organic light emitting layer 33 may include a plurality of film layers, and at least one film layer is disconnected at the edge of the fourth insulating layer 104. In an exemplary embodiment, the film layer of the organic light emitting layer 33 is provided with a distortion region 107 at the disconnected portion, and as shown in the dotted line frame, the film layer of the organic light emitting layer 33 is broken in the distortion region 107. In an exemplary embodiment, the distortion region 107 may include at least one crack, and the organic light emitting layer 33 on both sides of the crack forms a step difference due to the disconnection.

[0139] In an exemplary embodiment, an orthographic projection of the distortion region 107 on the base substrate 10 does not overlap with an orthographic projection of the pixel opening 35 on the base substrate 10 .

[0140] D. Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: forming a second electrode 34 by evaporation or deposition, and the second electrode 34 is disposed on a side of the organic light emitting layer 33 away from the base substrate 10, and is a full-surface structure, such as Fig. 9 shown.

[0141] In the exemplary embodiment, since the organic light emitting layer 33 is formed with the distortion region 107 , the second electrode 34 is provided with a puncture tip 108 , and the puncture tip 108 is disposed in a crack of the distortion region 107 .

[0142] The orthographic projection of the endpoint of the puncture tip 108 on the base substrate 10 is within the range of the orthographic projection of the first insulating layer 101 on the base substrate 10 . The endpoint of the puncture tip 108 is the boundary point on the puncture tip 108 closest to the base substrate 10 .

[0143] In an exemplary embodiment, the orthographic projection of the puncture tip 108 on the base substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the base substrate 10 .

[0144] In an exemplary embodiment, the second electrode 34 may be made of a metal material or a transparent conductive material. The metal material may include any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or alloy materials of the above metals. The transparent conductive material may include indium zinc oxide (IZO). In an exemplary embodiment, the second electrode 34 may be a single-layer structure or a multi-layer composite structure, such as Mg / Ag.

[0145] In an exemplary embodiment, an optical coupling layer pattern may be formed after forming the second conductive layer pattern. The optical coupling layer is disposed on the second electrode 34. The refractive index of the optical coupling layer may be greater than the refractive index of the second electrode 34, which is beneficial to light extraction and increases the light extraction efficiency. The material of the optical coupling layer may be organic material, or inorganic material, or both organic material and inorganic material, and may be a single layer, a multi-layer, or a composite layer, which is not limited in the present disclosure.

[0146] At this point, the display substrate is prepared, and the display substrate may include a base substrate 10 , a first electrode 31 , a pixel definition structure 32 , an organic light-emitting layer 33 and a second electrode 34 . The organic light-emitting layer 33 emits light when driven by the first electrode 31 and the second electrode 34 .

[0147] Subsequent preparation may include processes such as forming a first encapsulation layer 40 , a color filter structure layer 50 , a second encapsulation layer 60 , and a cover layer 70 , which will not be described in detail here.

[0148] The display substrate provided by the present disclosure is provided with a pixel definition structure including multiple insulating layers, and a second recess is formed on the second insulating layer in the pixel definition structure, and the inner wall of the second recess close to the substrate side is located between the upper surface and the lower surface of the first electrode, so that the second electrode is prevented from being broken while the pixel definition structure separates the organic light-emitting layer, thereby ensuring the continuity of the second electrode. The pixel definition structure proposed in the present disclosure forms a first recess on the side wall of the pixel definition structure, so that the organic light-emitting layer is disconnected at the edge of the pixel definition structure, and the lateral current in the organic light-emitting layer can be effectively blocked. The pixel definition structure proposed in the present disclosure forms a distortion zone in the organic light-emitting layer, and the orthographic projection of the distortion zone on the substrate substrate does not overlap with the orthographic projection of the pixel opening on the substrate substrate, that is, the distortion zone is located outside the pixel opening and away from the effective light-emitting zone, thereby improving the light-emitting efficiency and reducing the brightness loss. The pixel definition structure proposed in the present disclosure ensures that the orthographic projection of the puncture tip of the second electrode on the substrate does not overlap with the orthographic projection of the first electrode on the substrate, that is, the puncture tip is located outside the area where the first electrode is located, which can effectively avoid a short circuit between the second electrode and the first electrode. By setting the puncture tip in the area where the flat first insulating layer is located, the continuity of the second electrode can be further ensured, and no virtual connection or disconnection will occur.

[0149] The organic light-emitting layer is disconnected at the edge of the pixel definition structure, which can effectively avoid the crosstalk caused by the carrier transfer of the charge generation layer, greatly reduce the risk of longitudinal leakage of the organic light-emitting device, improve the luminous efficiency and enhance the display effect.

[0150] Fig.10 FIG. 1 is a schematic diagram of the structure of an organic light-emitting layer according to an exemplary embodiment of the present disclosure. Fig.10 As shown, the organic light emitting layer 33 may include a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting material layer, a hole blocking layer, an electron transport layer and an electron injection layer disposed between the first electrode and the second electrode.

[0151] Fig.11 FIG. 1 is a schematic diagram of another structure of an organic light-emitting layer according to an exemplary embodiment of the present disclosure. Fig.11 As shown, the organic light-emitting layer 33 may include a first device 33-1, a charge generating layer 33-2 and a second device 33-3 arranged between the first electrode and the second electrode, and the first device 33-1 and the second device 33-3 both include a stacked hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting material layer, a hole blocking layer, an electron transport layer and an electron injection layer.

[0152] In an exemplary embodiment, in a direction perpendicular to the substrate 10, the first device 33-1 and the charge generation layer 33-2 have a first device thickness T1, the second stacked device 33-3 has a second thickness T2, and the first device thickness T1 can be less than the second device thickness T2, that is, T1 < T2.

[0153] In an exemplary embodiment, the first device thickness T1 can be less than half of the second device thickness T2, T1 < 1 / 2 * T2, to ensure that the inscribed structure effectively isolates the organic light-emitting layer 33 while not causing virtual connection or breakage of the second electrode 34.

[0154] In an exemplary embodiment, the third thickness D3 can be less than the first device thickness T1, and the third thickness D3 can be greater than half of the first device thickness T1, that is, 1 / 2 * T1 < D3 < T1, to ensure that at least one film layer in the organic light-emitting layer 33 is disconnected at a position corresponding to the pixel definition structure 32, especially isolating the charge generation layer 33-2 in the organic light-emitting layer 33.

[0155] In an exemplary embodiment, the total thickness of the organic light-emitting layer 33 can be about 2900 angstroms to 3100 angstroms, where the first device thickness T1 can be about 900 angstroms, and the second device thickness T2 can be about 2100 angstroms.

[0156] It has been found through research that not only the width of the inorganic layer in the pixel definition structure affects the efficiency and lifetime of the light-emitting device, but also the thickness of the organic light-emitting layer is a factor affecting the quality of the light-emitting device. By setting the thickness relationship between the third insulating layer and the organic light-emitting layer, the present disclosure not only further effectively blocks lateral leakage between pixels, but also can reduce longitudinal leakage caused by distortion of the organic light-emitting layer.

[0157] The disclosed exemplary embodiment also provides a method for preparing a display substrate. In an exemplary embodiment, the preparation method includes: forming a plurality of first electrodes and a plurality of pixel definition structures on a substrate substrate; the pixel definition structure is arranged between adjacent first electrodes, and a pixel opening exposing the first electrode is formed; in a direction perpendicular to the substrate substrate, the pixel definition structure includes at least a first insulating layer arranged on the substrate substrate, a second insulating layer arranged on a side of the first insulating layer away from the substrate substrate, a third insulating layer arranged on a side of the second insulating layer away from the substrate substrate, and a fourth insulating layer arranged on a side of the third insulating layer away from the substrate substrate, the orthographic projections of the first insulating layer, the third insulating layer, and the fourth insulating layer on the substrate substrate do not overlap with the orthographic projection of the first electrode on the substrate substrate, and the orthographic projection of the second insulating layer on the substrate substrate overlaps at least partially with the orthographic projection of the first electrode on the substrate substrate; a second indentation is arranged on a surface of the second insulating layer away from the substrate substrate, which is concave toward the substrate substrate, and an inner wall of the second indentation close to the substrate substrate is located between a surface of the first electrode away from the substrate substrate and a surface of the first electrode close to the substrate substrate.

[0158] The present disclosure also provides a display device, including the display substrate of the above embodiment. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

[0159] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of this application shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, characterized in that: The invention comprises a base substrate, a plurality of first electrodes and a plurality of pixel definition structures arranged on the base substrate, wherein the pixel definition structures are arranged between adjacent first electrodes and form pixel openings exposing the first electrodes; In a direction perpendicular to the substrate, the pixel definition structure at least includes a first insulating layer disposed on the substrate, a second insulating layer disposed on a side of the first insulating layer away from the substrate, a third insulating layer disposed on a side of the second insulating layer away from the substrate, and a fourth insulating layer disposed on a side of the third insulating layer away from the substrate, wherein the orthographic projections of the first insulating layer, the third insulating layer, and the fourth insulating layer on the substrate do not overlap with the orthographic projection of the first electrode on the substrate; The second insulating layer includes a first sub-portion, and an orthographic projection of the first sub-portion on the base substrate does not overlap with an orthographic projection of the first electrode on the base substrate; A first depression recessed toward the base substrate is disposed on a surface of the first insulating layer away from the base substrate, and an orthographic projection of the first depression on the base substrate does not overlap with an orthographic projection of the first sub-portion on the base substrate.

2. The display substrate according to claim 1, characterized in that: The inner wall of the first recess on the side close to the base substrate is located between the surface of the first electrode away from the base substrate and the surface of the first electrode on the side close to the base substrate.

3. The display substrate according to claim 1, characterized in that: The third depth of the first recess is 0.01 μm to 0.03 μm, and the third depth is the maximum distance between the inner wall of the first recess on the side close to the substrate and the first sub-portion in a direction perpendicular to the substrate.

4. The display substrate according to claim 1, characterized in that: The first concave is a smooth curved surface.

5. The display substrate according to claim 3, characterized in that: The fourth insulating layer has a protrusion relative to the side wall of the third insulating layer, and the protrusion and the side wall of the third insulating layer form a first recessed portion that is concave in a direction away from the pixel opening; The first depth is greater than the third depth, and the first depth is the maximum distance between a side wall of the fourth insulating layer close to the pixel opening and a side wall of the third insulating layer close to the pixel opening.

6. The display substrate according to claim 5, characterized in that: The first depth of the first recess is 0.05 μm to 0.2 μm.

7. The display substrate according to claim 5, characterized in that: The first height of the first recess is greater than the third depth, and the first height of the first recess is the maximum distance between a surface of the first recess close to the substrate and a surface of the first recess away from the substrate.

8. The display substrate according to claim 5, characterized in that: The first indentation is a smooth curved surface.

9. The display substrate according to claim 5, characterized in that: A first through hole extending toward the base substrate is provided on a surface of the second insulating layer away from the base substrate; The first through hole penetrates the second insulating layer in a direction perpendicular to the base substrate. The first through hole is connected to the first recess at one end close to the base substrate. The first through hole and the first recess constitute a second recess.

10. The display substrate according to claim 9, characterized in that: A smooth third recessed portion that is recessed toward the base substrate is disposed on a surface of the fourth insulating layer that is away from the base substrate.

11. The display substrate according to claim 10, characterized in that: A curvature of the third indentation is smaller than a curvature of the first indentation or a curvature of the second indentation.

12. The display substrate according to claim 5, characterized in that: The first insulating layer has a first width, the third insulating layer has a third width, the fourth insulating layer has a fourth width, the first sub-portion has a fifth width, and the first width, the third width, the fourth width and the fifth width are dimensions parallel to the substrate direction; The first width is greater than the fifth width, the fifth width is greater than the third width, and the third width is less than the fourth width.

13. The display substrate according to claim 12, characterized in that: The first depth is half of a difference between the fourth width and the third width.

14. The display substrate according to claim 12, characterized in that: The orthographic projections of the third insulating layer and the fourth insulating layer on the base substrate are both located within the range of the orthographic projection of the first sub-portion on the base substrate.

15. The display substrate according to any one of claims 1 to 14, characterized in that: The side surface of the first insulating layer is in contact with the side surface of the first electrode.

16. The display substrate according to any one of claims 1 to 14, characterized in that: The display substrate also includes an organic light-emitting layer arranged on the side of the first electrode and the pixel definition structure away from the base substrate, the organic light-emitting layer includes multiple film layers, at least one film layer is disconnected at the edge of the fourth insulating layer, and a distortion region is set at the disconnected film layer of the organic light-emitting layer.

17. The display substrate according to claim 16, characterized in that: The distortion region includes at least one crack, and an orthographic projection of the distortion region on the substrate does not overlap with an orthographic projection of the pixel opening on the substrate.

18. The display substrate according to claim 16, characterized in that: The display substrate further comprises a second electrode disposed on a side of the organic light emitting layer away from the base substrate, the second electrode being provided with a puncture tip, the puncture tip being disposed in a crack of the distortion region, and an orthographic projection of the puncture tip on the base substrate not overlapping with an orthographic projection of the first electrode on the base substrate; The orthographic projection of the endpoint of the puncture tip on the substrate is located within the range of the orthographic projection of the first insulating layer on the substrate, and the endpoint of the puncture tip is the boundary point on the puncture tip that is closest to the substrate.

19. The display substrate according to claim 18, characterized in that: The orthographic projection of the endpoint of the puncture tip on the base substrate is located within the range of the orthographic projection of the first sub-portion on the base substrate.

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