Display panel and display device

Abstract

This application relates to a display panel and a display device. The display panel includes: the orthographic projection of a first capacitor dielectric layer overlaps with the orthographic projections of a first electrode region and a second electrode region of a first transistor; the orthographic projection of a second capacitor dielectric layer at least partially overlaps with the orthographic projection of the second electrode region of the first transistor but does not overlap with the orthographic projection of the first electrode region of the first transistor; the orthographic projection of a first metal structure at least partially overlaps with the orthographic projection of the first electrode region of the first transistor; and the orthographic projection of a second metal structure at least partially overlaps with the orthographic projection of the second electrode region of the first transistor. This ensures that during the initialization of the gate structure of the driving transistor using an initialization signal, the initialization of the gate structure of the driving transistor is sufficiently thorough, thereby improving the threshold voltage offset of the driving transistor and enhancing the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] An active matrix organic light-emitting diode (AMOLED) display device is a self-emissive display device that typically includes multiple organic light-emitting diodes and multiple pixel circuits. The pixel circuits are used to control the light emission of the corresponding organic light-emitting diodes.

[0003] Pixel circuits typically include multiple thin-film transistors (TFTs), and among these TFTs, the TFT used to generate drive current to drive the organic light-emitting diode (OLED) to emit light is called the driving transistor. In related technologies, when display devices display at low frequencies, due to the long frame time, the threshold voltage of the driving transistor is prone to shift, resulting in poor display effects such as image retention and low-frequency flicker. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel and display device that can improve the threshold voltage offset of the driving transistor and thus enhance the display effect, in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a display panel, the display panel comprising:

[0006] Substrate;

[0007] The first transistor is located on one side of the substrate;

[0008] An active layer is located on one side of the substrate, and the active layer includes a first electrode region and a second electrode region of the first transistor;

[0009] A gate insulating layer is located on the side of the active layer away from the substrate;

[0010] A first metal layer is located on the side of the gate insulating layer away from the active layer, and the first metal layer includes the gate structure of the first transistor;

[0011] The first capacitor dielectric layer is located on the side of the first metal layer away from the gate insulating layer;

[0012] The second capacitor dielectric layer is located on the side of the first capacitor dielectric layer away from the first metal layer;

[0013] Wherein, the orthographic projection of the first capacitor dielectric layer in the first direction overlaps with the orthographic projections of the first electrode region and the second electrode region of the first transistor in the first direction, and the orthographic projection of the second capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of the second electrode region of the first transistor in the first direction but does not overlap with the orthographic projection of the first electrode region of the first transistor in the first direction, wherein the first direction is a direction perpendicular to the surface where the display panel is located.

[0014] The second metal layer includes a first metal structure and a second metal structure. The first metal structure is located on the side of the first capacitor dielectric layer away from the first metal layer, and the second metal structure is located on the side of the second capacitor dielectric layer away from the first capacitor dielectric layer. The orthographic projection of the first metal structure in the first direction at least partially overlaps with the orthographic projection of the first electrode region of the first transistor in the first direction, and the orthographic projection of the second metal structure in the first direction at least partially overlaps with the orthographic projection of the second electrode region of the first transistor in the first direction.

[0015] Optionally, the overlap area between the first metal structure and the first electrode region of the first transistor in the first direction is greater than a first preset area, and the overlap area between the second metal structure and the second electrode region of the first transistor in the first direction is less than a second preset area, wherein the first preset area is greater than the second preset area.

[0016] Optionally, the second metal layer further includes a data signal line for transmitting data signals and an initialization signal line for transmitting initialization signals. In the second direction, the first metal structure is located between the data signal line and the gate structure of the first transistor, and the second metal structure is located between the gate structure of the first transistor and the initialization signal line. The second direction is a direction parallel to the surface of the display panel.

[0017] Optionally, the first metal structure and the second metal structure are power signal lines for transmitting power signals.

[0018] Optionally, the first metal layer further includes scan lines for transmitting scan signals, and the second metal layer further includes gate connection metal, wherein the gate connection metal is connected to the gate structure of the first transistor.

[0019] The orthographic projections of the first capacitor dielectric layer and the second capacitor dielectric layer in the first direction at least partially overlap with the orthographic projections of the scan line and the gate connection metal in the first direction.

[0020] Optionally, the first metal layer further includes scan lines for transmitting scan signals, and the second metal layer further includes gate connection metal, wherein the gate connection metal is used to connect the gate structure of the first transistor;

[0021] The gate connection metal does not overlap with the orthographic projection of the scan line in the first direction;

[0022] Optionally, the display panel further includes an anode layer located on the side of the second metal layer away from the substrate. The anode layer includes bridging traces, which are electrically connected to the gate connection metals located on both sides of the bridging region. The orthographic projection of the bridging region in the first direction at least partially overlaps with the orthographic projection of the scan line in the first direction.

[0023] Optionally, the display panel further includes a first shielding structure, the first shielding structure being insulated from the gate connecting metal, and the orthographic projection of the first shielding structure in the first direction at least partially overlapping the orthographic projection of the scan line in the first direction;

[0024] Optionally, in the first direction, the first shielding structure is located in the second capacitor dielectric layer between the scan line and the gate connection metal;

[0025] Optionally, the first shielding structure is connected to the power signal.

[0026] Optionally, the second metal layer further includes a second shielding structure, which is insulated from the gate connection metal, and the orthographic projection of the second shielding structure in the first direction at least partially overlaps with the orthographic projection of the scan line in the first direction.

[0027] Optionally, in the first direction, the second shielding structure is located between the scan line and the bridging trace;

[0028] Optionally, the second shielding structure is connected to the power signal.

[0029] Optionally, the first metal layer further includes a first capacitor plate, and the second metal layer further includes a second capacitor plate;

[0030] The orthographic projection of the first capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of the first capacitor plate in the first direction; the orthographic projection of the second capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of a portion of the first capacitor plate in the first direction; and the orthographic projection of the second capacitor plate in the first direction at least partially overlaps with the orthographic projection of the remaining first capacitor plate in the first direction.

[0031] Optionally, the first capacitor dielectric layer includes an inorganic capacitor dielectric layer; the second capacitor dielectric layer includes an organic capacitor dielectric layer.

[0032] Optionally, the thickness of the first capacitor dielectric layer is less than the thickness of the second capacitor dielectric layer.

[0033] Optionally, the first electrode region is the source region of the first transistor, and the second electrode region is the drain region of the first transistor.

[0034] Optionally, the first transistor is a driving transistor used to drive the light-emitting device to emit light.

[0035] Secondly, this application also provides a display device, including a display panel as provided in any of the above embodiments.

[0036] The aforementioned display panel and display device include a substrate, an active layer, a gate insulating layer, a first metal layer, a first capacitor dielectric layer, a second capacitor dielectric layer, and a second metal layer stacked together; the active layer includes a first electrode region and a second electrode region of a first transistor, the gate insulating layer is located between the active layer and the first metal layer, and the first metal layer includes the gate structure of the first transistor; the first transistor is, for example, a driving transistor.

[0037] A first capacitor dielectric layer is located on the side of the first metal layer away from the gate insulating layer; a second capacitor dielectric layer is located on the side of the first capacitor dielectric layer away from the first metal layer; wherein, the orthographic projection of the first capacitor dielectric layer in a first direction overlaps with the orthographic projections of the first electrode region and the second electrode region of the first transistor in the first direction, and the orthographic projection of the second capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of the second electrode region of the first transistor in the first direction but does not overlap with the orthographic projection of the first electrode region of the first transistor in the first direction, wherein the first direction is a direction perpendicular to the surface where the display panel is located;

[0038] The second metal layer includes a first metal structure and a second metal structure. The first metal structure is located on the side of the first capacitor dielectric layer away from the first metal layer, and the second metal structure is located on the side of the second capacitor dielectric layer away from the first capacitor dielectric layer. The orthographic projection of the first metal structure in a first direction at least partially overlaps with the orthographic projection of the first electrode region of the first transistor in a first direction, and the orthographic projection of the second metal structure in a first direction at least partially overlaps with the orthographic projection of the second electrode region of the first transistor in a first direction.

[0039] Thus, in the first direction, the first metal structure, the first capacitor dielectric layer, and the first electrode region can constitute the source capacitance of the source of the first transistor, while the second metal structure, the second capacitor dielectric layer, the first capacitor dielectric layer, and the second electrode region can constitute the drain capacitance of the drain of the first transistor. Since the capacitor dielectric layer in the source capacitance is the first capacitor dielectric layer (i.e., a single layer), and the capacitor dielectric layer in the drain capacitance is the first capacitor dielectric layer and the second capacitor dielectric layer (i.e., a double layer), the source capacitance is large and can store a large amount of positive charge, while the drain capacitance is small and can only store a small amount of negative charge. This results in a large gate-source voltage difference and a large gate-drain voltage difference in the first transistor during the initialization process of the gate structure of the first transistor using an initialization signal. As a result, the initialization of the gate structure of the first transistor is sufficiently sufficient, which is enough to achieve the calibration of the threshold voltage of the first transistor. In this embodiment, the threshold voltage offset of the first transistor is improved, thereby avoiding phenomena such as afterimages and low-frequency flicker that occur when the display device displays at low frequencies, and improving the display effect. Attached Figure Description

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 This is a top view of the display panel in one embodiment;

[0042] Figure 2 for Figure 1 A schematic diagram of the pixel circuit structure in a local area;

[0043] Figure 3 for Figure 2 One of the partial layout diagrams of the mid-pixel circuit;

[0044] Figure 4 for Figure 3 A partial cross-sectional schematic diagram;

[0045] Figure 5 for Figure 2 Partial layout diagram of the mid-pixel circuit (Part 2);

[0046] Figure 6 for Figure 5 A partial cross-sectional schematic diagram;

[0047] Figure 7 for Figure 2 Partial layout diagram of the mid-pixel circuit (Part 3);

[0048] Figure 8 for Figure 7 One of the partial cross-sectional schematic diagrams;

[0049] Figure 9 for Figure 7 The second partial cross-sectional schematic diagram.

[0050] Explanation of reference numerals in the attached figures:

[0051] 100 - Display panel, 110 - Substrate, 120 - Active layer, 130 - Gate insulating layer, 140 - First metal layer, 150 - First capacitor dielectric layer, 160 - Second capacitor dielectric layer, 170 - Second metal layer, 180 - Planarization layer, 190 - Anode layer, 121 - Source region, 122 - Drain region, 141 - Gate structure, 142 - Scan line, 171 - First shielding structure, 172 - Second shielding structure, 191 - Bridging trace. Detailed Implementation

[0052] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0054] It will be understood that the terms "first," "second," etc. used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.

[0055] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0056] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intervening element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc., if there is transmission of electrical signals or data between the connected objects.

[0057] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0058] As described in the background art, in related technologies, when a display device displays at low frequencies, the threshold voltage of the driving transistor is prone to shift due to the long frame time, resulting in phenomena such as image retention and low-frequency flicker. The inventors have discovered that the reason for this problem is that when the display device displays at low frequencies, the threshold voltage of the driving transistor will gradually shift positively or negatively due to the hot carrier effect during the long frame time at low frequencies, thus causing phenomena such as image retention and low-frequency flicker to occur.

[0059] Based on the above reasons, the present invention provides a solution that can improve the threshold voltage offset of the driving transistor, thereby improving the display effect.

[0060] In one exemplary embodiment, reference is made to Figure 1A display panel 100 is provided. Exemplarily, the display panel 100 can be an OLED display panel. The display panel 100 includes a plurality of organic light-emitting diodes and a plurality of pixel circuits. Exemplarily, see reference... Figure 2 The pixel circuit includes a driving transistor T1 and a storage capacitor C. ST The transistors are: data writing transistor T2, threshold compensation transistor T3, first initialization transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and second initialization transistor T7.

[0061] At least one of the following transistors can be an N-type thin-film transistor or a P-type thin-film transistor: driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first initialization transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, and second initialization transistor T7.

[0062] The gate of the first initialization transistor T4 is connected to the first scan line SCAN1. The first initialization transistor T4 is used to initialize the gate of the driving transistor T1 according to the initialization signal VREF.

[0063] The gate of data writing transistor T2 is connected to the second scan line SCAN2. Data writing transistor T2 is used to write the data signal VDATA to the gate of driving transistor T1. The gate of threshold compensation transistor T3 is connected to the second scan line SCAN2. Threshold compensation transistor T3 is used to compensate for the threshold voltage VTH of driving transistor T1. Storage capacitor C ST Used to store the voltage at the gate of driving transistor T1; driving transistor T1 is used to generate a driving current I based on the voltage at its gate. DS Drive current I DS Used to drive light-emitting devices, such as organic light-emitting diodes (OLEDs).

[0064] The gate of the second initialization transistor T7 is connected to the third scan line SCAN3. The second initialization transistor T7 is used to initialize the anode ANODE of the organic light-emitting diode D according to the initialization signal VREF. The gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both connected to the light-emitting control signal line EM. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are used to control the organic light-emitting diode D to emit light.

[0065] In this embodiment, the display panel 100 includes a substrate 110 and a first transistor, the first transistor being located on one side of the substrate 110. The first transistor includes a first electrode region, a second electrode region, and a gate structure. Optionally, the first electrode region of the first transistor is the source region of the first transistor, and the second electrode region of the first transistor is the drain region of the second transistor. Exemplarily, the first transistor is a driving transistor T1.

[0066] The following example illustrates the technical solution of this invention, using a first transistor as the driving transistor T1, the first electrode region of the first transistor as the source region of the driving transistor T1, and the second electrode region of the first transistor as the drain region of the driving transistor T1. However, this is not intended to limit the technical solution of this invention. It should be understood that the first transistor in this invention can be a transistor with other functions, the first electrode region of the first transistor can be a drain region or other electrode regions, and the second electrode region of the first transistor can be a source region or other electrode regions; all of these fall within the protection scope of this invention.

[0067] In the map structure, combined with Figure 3 and Figure 4 The display panel 100 includes a substrate 110, an active layer 120, a gate insulating layer 130, a first metal layer 140, a first capacitor dielectric layer 150, a second capacitor dielectric layer 160, and a second metal layer 170. In the accompanying drawings of this application embodiment, the areas circled by dashed lines of the "line-dot-line" type are the areas where the first capacitor dielectric layer 150 has been removed, and the areas circled by dashed lines of the "line-dot-dot-line" type are the areas where the second capacitor dielectric layer 160 has been removed.

[0068] The substrate 110 mainly serves a supporting function. The substrate 110 can be a rigid substrate made of materials such as glass or plastic, or a flexible substrate made of materials such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0069] The active layer 120 is located on one side of the substrate 110, and includes a source region 121 and a drain region 122. Specifically, the active layer 120 may include the source region 121 and drain region 122 formed by doping with N-type or P-type impurity ions, and a channel region formed between the source region 121 and drain region 122. The material of the active layer 120 includes, but is not limited to, amorphous silicon, amorphous oxide semiconductor, polycrystalline silicon, or metal oxide materials. In this embodiment, the active layer 120 may be the active layer 120 of the driving transistor T1.

[0070] The gate insulating layer 130 is located on the side of the active layer 120 away from the substrate 110, and the material of the gate insulating layer 130 may be, but is not limited to, one or more combinations of silicon nitride, silicon oxynitride and silicon oxide.

[0071] The first metal layer 140 is located on the side of the gate insulating layer 130 away from the active layer 120, and the first metal layer 140 includes a gate structure 141. The first metal layer 140 can be understood as one of the multiple metal layers between the substrate 110 and the organic light-emitting diode D in the display panel 100. The orthogonal projection of the gate structure 141 in a first direction can cover the channel region; that is, a gate insulating layer 130 is provided between the channel region and the gate structure 141. The first direction is a direction perpendicular to the surface of the display panel 100. In this embodiment, the gate structure 141 can be the gate structure 141 of the driving transistor T1.

[0072] The first capacitor dielectric layer 150 is located on the side of the first metal layer 140 away from the gate insulating layer 130. The orthographic projection of the first capacitor dielectric layer 150 in the first direction overlaps with the orthographic projections of the source region 121 and the drain region 122 in the first direction.

[0073] The second capacitor dielectric layer 160 is located on the side of the first capacitor dielectric layer 150 away from the first metal layer 140. The orthographic projection of the second capacitor dielectric layer 160 in the first direction at least partially overlaps with the orthographic projection of the drain region 122 in the first direction and does not overlap with the orthographic projection of the source region 121 in the first direction.

[0074] The first capacitor dielectric layer 150 can be understood as the insulating dielectric layer between the substrate 110 and the organic light-emitting diode D in the display panel 100, and the second capacitor dielectric layer 160 can be understood as the interlayer insulating layer between the substrate 110 and the organic light-emitting diode D.

[0075] The second metal layer 170 includes a first metal structure and a second metal structure. The first metal structure is located on the side of the first capacitor dielectric layer 150 away from the first metal layer 140, and the orthographic projection of the first metal structure in the first direction at least partially overlaps with the orthographic projection of the source region 121 in the first direction. The second metal structure is located on the side of the second capacitor dielectric layer 160 away from the first capacitor dielectric layer 150, and the orthographic projection of the second metal structure in the first direction at least partially overlaps with the orthographic projection of the drain region 122 in the first direction, covering the drain region 122. The second metal layer 170 can be understood as one of the multiple metal layers in the display panel 100 between the substrate 110 and the organic light-emitting diode D, excluding the first metal layer 140.

[0076] In this embodiment, in a direction perpendicular to the plane of the display panel 100, the first metal structure, the first capacitor dielectric layer 150, and the source region 121 constitute the source capacitance C of the driving transistor T1. SOURCE The second metal structure, the second capacitor dielectric layer 160, the first capacitor dielectric layer 150, and the drain region 122 constitute the drain capacitance C of the driving transistor T1. DRAIN Due to the source capacitance C SOURCE The capacitor dielectric layer in the figure is the first capacitor dielectric layer 150, which is a single layer with a small thickness, while the drain capacitor C... DRAIN The capacitor dielectric layer consists of a first capacitor dielectric layer 150 and a second capacitor dielectric layer 160, i.e., a double layer with a large dielectric layer thickness. Therefore, according to the capacitance C = εS / d = εS / 4πkd (ε is the dielectric constant, S is the area between the two electrode plates, k is the electrostatic constant, and d is the thickness of the capacitor dielectric layer), the source capacitance C is... SOURCE Large, capable of storing a large amount of positive charge, while the drain capacitance C DRAIN The small size of the gate structure allows it to store only a small amount of negative charge. This results in a large gate-source voltage difference |VGS| and gate-drain voltage difference |VGD| of the driving transistor T1 during the initialization process of the gate structure 141 of the driving transistor T1 using the initialization signal VREF. As a result, the initialization of the gate structure 141 of the driving transistor T1 is sufficiently complete. The sufficiently complete initialization of the gate structure 141 of the driving transistor T1 is sufficient to achieve the calibration of the threshold voltage VTH of the driving transistor T1. In this embodiment, the threshold voltage VTH offset of the driving transistor T1 is improved, thereby avoiding phenomena such as afterimages and low-frequency flicker in low-frequency display and improving the display effect.

[0077] In one exemplary embodiment, continuing to combine Figure 3 and Figure 4 The first metal structure overlaps with the source region 121 in the first direction with a larger than a first preset area, and the second metal structure overlaps with the drain region 122 in the first direction with a smaller than a second preset area, wherein the first preset area is larger than the second preset area.

[0078] In this embodiment, the source capacitor C SOURCE The area directly opposite the two electrode plates is larger than the first preset area, and the drain capacitance C DRAIN The area between the two electrode plates facing each other is smaller than the second preset area, and the first preset area is larger than the second preset area. According to the capacitance C = εS / d = εS / 4πkd (ε is the dielectric constant, S is the area between the two electrode plates facing each other, k is the electrostatic constant, and d is the thickness of the capacitor dielectric layer), it can be seen that the source capacitance C can be further increased. SOURCE It is large, capable of storing a large amount of positive charge, and can further increase the drain capacitance C.DRAIN The small size allows it to store only a small amount of negative charge, which further increases the gate-source voltage difference |VGS| and gate-drain voltage difference |VGD| of the driving transistor T1. This further ensures that the initialization of the gate structure 141 of the driving transistor T1 is sufficiently adequate. The sufficiently adequate initialization of the gate structure 141 of the driving transistor T1 is sufficient to achieve the calibration of the threshold voltage VTH of the driving transistor T1. In this embodiment, the threshold voltage VTH offset of the driving transistor T1 is improved, thereby avoiding phenomena such as afterimages and low-frequency flicker in low-frequency display and improving the display effect.

[0079] In an exemplary embodiment, by setting the source capacitor C SOURCE The capacitor dielectric layer in the figure is the first capacitor dielectric layer 150, which is a single layer with a small dielectric layer thickness d and a small source capacitance C. SOURCE The area S directly opposite the two electrode plates is greater than the first preset area, while the drain capacitance C DRAIN The capacitor dielectric layer consists of a first capacitor dielectric layer 150 and a second capacitor dielectric layer 160, i.e., a double layer with a large capacitor dielectric layer thickness d and a large drain capacitance C. DRAIN The area S directly opposite the two electrode plates is smaller than the second preset area, therefore the source capacitance C SOURCE Large enough to store a large amount of positive charge, while the drain capacitance C DRAIN The voltage is small enough to store only a small amount of negative charge. This ensures that during the initialization of the gate structure 141 of the driving transistor T1 using the initialization signal VREF, the gate-source voltage difference |VGS| and the gate-drain voltage difference |VGD| of the driving transistor T1 are both sufficiently large. As a result, the initialization of the gate structure 141 of the driving transistor T1 is sufficiently sufficient to achieve the calibration of the threshold voltage VTH of the driving transistor T1. In this embodiment, the threshold voltage VTH offset of the driving transistor T1 is improved, thereby avoiding phenomena such as afterimages and low-frequency flicker in low-frequency display and improving the display effect.

[0080] In one exemplary embodiment, continuing to combine Figure 3 and Figure 4 The second metal layer 170 also includes a data signal line for transmitting data signals and an initialization signal line for transmitting initialization signals. In the second direction, the first metal structure is located between the data signal line and the gate structure 141, and the second metal structure is located between the gate structure 141 and the initialization signal line. The second direction is a direction parallel to the surface of the display panel 100.

[0081] In this embodiment, the data signal line is used to transmit the data signal VDATA to the data writing transistor T2, and the initialization signal line is used to transmit the initialization signal VREF to the first initialization transistor T4 and the second initialization transistor T7. The second metal layer 170 can be used to form the data signal line, the initialization signal line, the first metal structure, and the second metal structure. In other words, the data signal line, the initialization signal line, the first metal structure, and the second metal structure are located in the same metal layer. A portion of the structure in the second metal layer 170 constitutes the first metal structure and the second metal structure, which allows the first metal structure and the source region 121 to form the source capacitance C of the driving transistor T1. SOURCE The two electrode plates, and the second metal structure and drain region 122 constitute the drain capacitance C of the driving transistor T1. DRAIN The two electrode plates.

[0082] In one exemplary embodiment, the first metal structure and the second metal structure are power signal lines for transmitting power signals.

[0083] In this embodiment, the power signal line is used to transmit a power signal ELVDD to the pixel circuit, for example, to the first light-emitting control transistor T5. The cathode CATHODE of the organic light-emitting diode D receives the second power signal ELVSS, thereby providing a power signal for the light emission of the organic light-emitting diode D. The first metal structure and the second metal structure can both be partial structures of the power signal line. In other words, the partial structure of the power signal line in the second metal layer 170, together with the source region 121 and the drain region 122 of the driving transistor T1, respectively, constitutes the source capacitance C of the source of the driving transistor T1. SOURCE and the drain capacitance C of the driving transistor T1 DRAIN .

[0084] In one exemplary embodiment, combined with Figure 5 , Figure 6 and Figure 8 The first metal layer 140 further includes a scan line 142 for transmitting scan signals, and the second metal layer 170 further includes a gate connection metal, wherein the gate connection metal is connected to the gate structure 141; the orthographic projection of the first capacitor dielectric layer 150 and the second capacitor dielectric layer 160 in the first direction at least partially overlaps with the orthographic projection of the scan line 142 and the gate connection metal in the first direction.

[0085] The gate connection metal is the metal used to lead out the gate structure 141, and can together with the gate structure 141 form the gate of the driving transistor T1. According to the layout structure of the pixel circuit, the scan line 142 can be the second scan line SCAN2 used to connect the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3.

[0086] In related technologies, the gate connection metal of the driving transistor T1 overlaps with the second scan line SCAN2 in the first direction, therefore a parasitic capacitance C exists between the gate connection metal of the driving transistor T1 and the second scan line SCAN2. STR This causes the coupling effect of the second scan line SCAN2 to the gate connection metal of the driving transistor T1 to weaken the compensation capability of the pixel circuit for the gate of the driving transistor T1 when the second scan line SCAN2 switches from high level VGL to low level VGH or from low level VGH to high level VGL. This results in the potential of the gate of the driving transistor T1 deviating from the ideal value and becoming VDATA-|VTH|+V SWITCH ERROE This reduces the display quality, among which V SWITCH ERROE With parasitic capacitance C STR The potential changes of the second scan line SCAN2 are positively correlated, V SWITCH ERROE With storage capacitor C ST Negative correlation.

[0087] For the reasons mentioned above, this embodiment sets the capacitor dielectric layer between the second scan line SCAN2 and the gate connection metal of the driving transistor T1 as a first capacitor dielectric layer 150 and a second capacitor dielectric layer 160, i.e., a double layer with a large capacitor dielectric layer thickness. According to the capacitance C=εS / d=εS / 4πkd (ε is the dielectric constant, S is the area between the two electrode plates, k is the electrostatic constant, and d is the capacitor dielectric layer thickness), the parasitic capacitance C between the second scan line SCAN2 and the gate connection metal of the driving transistor T1 is... STR When the second scan line SCAN2 is significantly reduced, it becomes difficult for the second scan line SCAN2 to pass through the parasitic capacitance C when it transitions from a high level VGL to a low level VGH or from a low level VGH to a high level VGL. STR The gate of the driving transistor T1 is coupled, i.e., due to V SWITCH ERROE With parasitic capacitance C STR Positive correlation V SWITCH ERROE The voltage is significantly reduced, so the final potential of the gate of the driving transistor T1 is very close to the ideal compensation potential VDATA-|VTH|, thereby improving the display effect.

[0088] In one exemplary embodiment, continuing to combine Figure 5 and Figure 6The first metal layer 140 further includes a first capacitor plate, and the second metal layer 170 further includes a second capacitor plate. The orthographic projection of the first capacitor dielectric layer 150 in the first direction at least partially overlaps with the orthographic projection of the first capacitor plate in the first direction. The orthographic projection of the second capacitor dielectric layer 160 in the first direction at least partially overlaps with the orthographic projection of a portion of the first capacitor plate in the first direction. The orthographic projection of the second capacitor plate in the first direction at least partially overlaps with the orthographic projection of the remaining first capacitor plate in the first direction.

[0089] In this embodiment, based on the layout structure of the pixel circuit, the first capacitor plate and the second capacitor plate can constitute the storage capacitor C. ST The two electrode plates, through the storage capacitor C ST The capacitor dielectric layer between the two electrode plates is set as the first capacitor dielectric layer 150, i.e., a single layer with a small thickness. According to the capacitance C = εS / d = εS / 4πkd (ε is the dielectric constant, S is the area between the two electrode plates, k is the electrostatic constant, and d is the thickness of the capacitor dielectric layer), the storage capacitance C is... ST It was significantly increased because V SWITCH ERROE With storage capacitor C ST Negative correlation, thus making V SWITCH ERRO E is significantly reduced, which further ensures that the final potential of the gate of the driving transistor T1 is basically the ideal compensation potential VDATA-|VTH|, thus ensuring good display effect.

[0090] In one exemplary embodiment, combined with Figure 7 and Figure 8 The display panel 100 also includes a first shielding structure 171, which is metal-insulated from the gate. The orthographic projection of the first shielding structure 171 in the first direction at least partially overlaps with the orthographic projection of the scan line 142 in the first direction.

[0091] In this embodiment, the first shielding structure 171 can be a metal shielding structure. The first shielding structure 171 is inserted into the capacitance dielectric layer between the second scan line SCAN2 and the gate connection metal of the driving transistor T1, for example, into the second capacitance dielectric layer 160 between the second scan line SCAN2 and the gate connection metal Gate-M3 of the driving transistor T1, so that the parasitic capacitance C between the gate connection metal Gate-M3 of the driving transistor T1 and the second scan line SCAN2... STR This is close to zero, thus further preventing the second scan line SCAN2 from passing through the parasitic capacitance C. STRThe gate of the driving transistor T1 is coupled so that the final potential of the gate of the driving transistor T1 is basically the ideal compensation potential VDATA-|VTH|, thereby further improving the display effect. Optionally, the first shielding structure 171 can be connected to the power signal ELVDD.

[0092] In one exemplary embodiment, combined with Figure 7 and Figure 9 The first metal layer 140 further includes scan lines 142, and the second metal layer 170 further includes gate connection metal, wherein the gate connection metal is used to connect the gate structure 141; the gate connection metal and the orthographic projection of the scan lines 142 in the first direction do not overlap. (Continuing with the previous sentence...) Figure 7 and Figure 9 The display panel 100 also includes an anode layer 190 located on the side of the second metal layer 170 away from the substrate 110. The anode layer 190 includes a bridging trace 191, which is electrically connected to the gate connection metal located on both sides of the bridging region. The orthographic projection of the bridging region in the first direction at least partially overlaps with the orthographic projection of the scan line 142 in the first direction.

[0093] Thus, the bridging trace 191, the gate connection metal, and the gate structure 141 together constitute the gate of the driving transistor T1. Continuing with the combination... Figure 7 and Figure 9 The second metal layer 170 also includes a second shielding structure 172, which is insulated from the gate connection metal. The orthographic projection of the second shielding structure 172 in the first direction at least partially overlaps with the orthographic projection of the scan line 142 in the first direction.

[0094] In this embodiment, the second shielding structure 172 is inserted, for example, into the planarization layer 180 between the second scan line SCAN2 and the bridging trace 191, so that the parasitic capacitance C between the bridging trace 191 and the second scan line SCAN2 is reduced. STR This is close to zero, thus further preventing the second scan line SCAN2 from passing through the parasitic capacitance C. STR The gate of the driving transistor T1 is coupled so that the final potential of the gate of the driving transistor T1 is basically the ideal compensation potential VDATA-|VTH|, thereby further improving the display effect. Optionally, the second shielding structure 172 can be connected to the power signal ELVDD.

[0095] In an exemplary embodiment, the second metal layer 170 further includes a source metal and a drain metal, both of which are located on the side of the second capacitor dielectric layer 160 away from the first capacitor dielectric layer 150. The source metal is used to connect the source region 121, and the drain metal is used to connect the drain region 122. Thus, the source and drain of the driving transistor T1 can be correspondingly formed.

[0096] In one exemplary embodiment, the first capacitor dielectric layer 150 includes an inorganic capacitor dielectric layer, and the second capacitor dielectric layer 160 includes an organic capacitor dielectric layer.

[0097] In this embodiment, the material of the first capacitor dielectric layer 150 can be a conventional insulating dielectric layer material, such as at least one of silicon oxide and silicon nitride; the material of the second capacitor dielectric layer 160 can be an organic adhesive, which is a commonly used material in the display panel 100. Therefore, it is beneficial to reduce the types of materials used in the display panel 100, thereby saving the manufacturing cost of the display panel 100.

[0098] In one exemplary embodiment, the thickness of the first capacitor dielectric layer 150 is less than the thickness of the second capacitor dielectric layer 160; this is more conducive to increasing the source capacitance C of the driving transistor T1. SOURCE Reduce the drain capacitance C of the driving transistor T1. DRAIN This makes it easier to ensure that the gate of the driving transistor T1 is fully initialized to improve the threshold voltage VTH offset of the driving transistor T1, and also makes it easier to increase the storage capacitance C. ST Reduce the parasitic capacitance C between scan line 142 and the gate connection metal of driving transistor T1. STR This makes it easier to ensure that the final gate potential of the driving transistor T1 is the ideal compensation potential VDATA-|VTH|.

[0099] In an exemplary embodiment, a display device is provided, which includes a display panel 100 as provided in any of the above embodiments. As can be seen from any of the above embodiments, the display panel 100 provided in this application embodiment can complete the pixel circuit by using only a first metal layer 140 and a second metal layer 170. That is, the display panel technology belongs to the two-metal-layer display panel technology.

[0100] The display device and display panel provided in the embodiments of this application belong to the same inventive concept and can achieve the same technical effect. Repeated content will not be described again here.

[0101] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of these terms do not necessarily refer to the same embodiment or example.

[0102] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: Substrate; The first transistor is located on one side of the substrate; An active layer is located on one side of the substrate, and the active layer includes a first electrode region and a second electrode region of the first transistor; A gate insulating layer is located on the side of the active layer away from the substrate; A first metal layer is located on the side of the gate insulating layer away from the active layer, and the first metal layer includes the gate structure of the first transistor; The first capacitor dielectric layer is located on the side of the first metal layer away from the gate insulating layer; The second capacitor dielectric layer is located on the side of the first capacitor dielectric layer away from the first metal layer; Wherein, the orthographic projection of the first capacitor dielectric layer in the first direction overlaps with the orthographic projections of the first electrode region and the second electrode region of the first transistor in the first direction, the orthographic projection of the second capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of the second electrode region of the first transistor in the first direction, and the orthographic projection of the second capacitor dielectric layer in the first direction does not overlap with the orthographic projection of the first electrode region of the first transistor in the first direction, wherein the first direction is a direction perpendicular to the surface where the display panel is located; The second metal layer includes a first metal structure and a second metal structure. The first metal structure is located on the side of the first capacitor dielectric layer away from the first metal layer, and the second metal structure is located on the side of the second capacitor dielectric layer away from the first capacitor dielectric layer. The orthographic projection of the first metal structure in the first direction at least partially overlaps with the orthographic projection of the first electrode region of the first transistor in the first direction, and the orthographic projection of the second metal structure in the first direction at least partially overlaps with the orthographic projection of the second electrode region of the first transistor in the first direction.

2. The display panel according to claim 1, characterized in that, The overlap area between the first metal structure and the first electrode region of the first transistor in the first direction is greater than a first preset area, and the overlap area between the second metal structure and the second electrode region of the first transistor in the first direction is less than a second preset area, wherein the first preset area is greater than the second preset area.

3. The display panel according to claim 2, characterized in that, The second metal layer further includes a data signal line for transmitting data signals and an initialization signal line for transmitting initialization signals. In a second direction, the first metal structure is located between the data signal line and the gate structure of the first transistor, and the second metal structure is located between the gate structure of the first transistor and the initialization signal line. The second direction is a direction parallel to the surface of the display panel.

4. The display panel according to claim 2, characterized in that, The first metal structure and the second metal structure are power signal lines used to transmit power signals.

5. The display panel according to claim 4, characterized in that, The first metal layer further includes scan lines for transmitting scan signals, and the second metal layer further includes gate connection metal, wherein the gate connection metal is connected to the gate structure of the first transistor; The orthographic projections of the first capacitor dielectric layer and the second capacitor dielectric layer in the first direction at least partially overlap with the orthographic projections of the scan line and the gate connection metal in the first direction.

6. The display panel according to claim 4, characterized in that, The first metal layer further includes scan lines for transmitting scan signals, and the second metal layer further includes gate connection metal, wherein the gate connection metal is used to connect the gate structure of the first transistor; The gate connection metal does not overlap with the orthogonal projection of the scan line in the first direction.

7. The display panel according to claim 6, characterized in that, The display panel further includes an anode layer located on the side of the second metal layer away from the substrate. The anode layer includes bridging traces, which are electrically connected to the gate connection metals located on both sides of the bridging region. The orthographic projection of the bridging region in the first direction at least partially overlaps with the orthographic projection of the scan line in the first direction.

8. The display panel according to claim 5, characterized in that, The display panel further includes a first shielding structure, which is insulated from the gate by a metal connection, and the orthographic projection of the first shielding structure in the first direction at least partially overlaps with the orthographic projection of the scan line in the first direction.

9. The display panel according to claim 8, characterized in that, In the first direction, the first shielding structure is located between the scan line and the gate connection metal.

10. The display panel according to claim 9, characterized in that, The first shielding structure is connected to the power signal.

11. The display panel according to claim 7, characterized in that, The second metal layer further includes a second shielding structure, which is insulated from the gate connecting metal, and the orthographic projection of the second shielding structure in the first direction at least partially overlaps with the orthographic projection of the scan line in the first direction.

12. The display panel according to claim 11, characterized in that, In the first direction, the second shielding structure is located between the scan line and the bridging trace.

13. The display panel according to claim 12, characterized in that, The second shielding structure is connected to the power signal.

14. The display panel according to claim 5 or 6, characterized in that, The first metal layer further includes a first capacitor plate, and the second metal layer further includes a second capacitor plate; The orthographic projection of the first capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of the first capacitor plate in the first direction; the orthographic projection of the second capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of a portion of the first capacitor plate in the first direction; and the orthographic projection of the second capacitor plate in the first direction at least partially overlaps with the orthographic projection of the remaining first capacitor plate in the first direction.

15. The display panel according to claim 1, characterized in that, The first capacitor dielectric layer includes an inorganic capacitor dielectric layer; the second capacitor dielectric layer includes an organic capacitor dielectric layer.

16. The display panel according to claim 15, characterized in that, The thickness of the first capacitor dielectric layer is less than the thickness of the second capacitor dielectric layer.

17. The display panel according to claim 1, characterized in that, The first electrode region is the source region of the first transistor, and the second electrode region is the drain region of the first transistor.

18. The display panel according to claim 17, characterized in that, The first transistor is a driving transistor used to drive the light-emitting device to emit light.

19. A display device, characterized in that, Includes the display panel as described in any one of claims 1-18.

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