Solid state variable impedance devices and systems

Abstract

Embodiments disclosed herein include an impedance matching network. In one embodiment, an impedance matching network comprises: an input; and a first matrix tuning element on a first branch from the input, where the first matrix tuning element includes a variable capacitance. In an embodiment, the impedance matching network further includes a transformer on a second branch from the input, where the transformer has at least a first tap, where a second matrix tuning element is on the first tap, and where the second matrix tuning element includes a variable capacitance. In an embodiment, the impedance matching network further includes a third matrix tuning element on the second branch after the transformer, where the third matrix tuning element includes a variable capacitance. In an embodiment, the impedance matching network further includes an output on the second branch after the third matrix tuning element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 17 / 941,976, filed on September 9, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to the field of semiconductor manufacturing, and in particular, to solid-state variable impedance matching systems for plasma processing systems. Background Art

[0004] In many semiconductor processing tools, such as plasma processing tools, an RF source is used to couple power to a chamber. The RF power can induce a plasma to process a substrate within the chamber. Due to impedance mismatch, some of the forward power is reflected back to the RF source. Accordingly, many processing tools include an impedance matching network to match the impedance of the load in the chamber.

[0005] Typically, impedance matching networks rely on electromechanical tuning systems. Electromechanical tuning systems may include vacuum variable capacitors driven by motors (e.g., servomotors). Electromechanical tuning systems are common in high power applications due to their excellent voltage and current handling properties. However, electromechanical tuning systems are slow. That is, electromechanical tuning can only operate as fast as the motor drive, which is several orders of magnitude slower than the ion transition rate across the plasma sheath.

[0006] Solid-state impedance matching networks have been proposed as an alternative to electromechanical systems. Solid-state solutions offer improved speed compared to electromechanical systems. However, existing solid-state impedance matching networks have some disadvantages. For example, the voltage / current handling capability and resolution in solid-state solutions may not be as good as those in electromechanical systems. In addition, solid-state impedance matching systems are significantly more expensive than electromechanical systems. Summary of the invention

[0007] Embodiments disclosed herein include an impedance matching network. In one embodiment, the impedance matching network includes: an input; and a first matrix tuning element, the first matrix tuning element is on a first branch from the input, wherein the first matrix tuning element includes a first variable capacitor. In one embodiment, the impedance matching network further includes: a transformer, the transformer is on a second branch from the input, wherein the transformer has at least a first tap, wherein a second matrix tuning element is on the first tap, and wherein the second matrix tuning element includes a second variable capacitor. In one embodiment, the impedance matching network further includes: a third matrix tuning element, the third matrix tuning element is after the transformer on the second branch, wherein the third matrix tuning element includes a third variable capacitor. In one embodiment, the impedance matching network further includes: an output, the output is after the third matrix tuning element on the second branch.

[0008] Embodiments disclosed herein also include a matrix tuning element. In one embodiment, the matrix tuning element includes: one or more units, wherein each unit includes: a diode array, the array coupled to the board, wherein the array includes one or more columns of diodes, and wherein each column includes four rows of diodes connected in series.

[0009] Embodiments disclosed herein also include semiconductor processing tools. In one embodiment, a semiconductor processing tool includes: a chamber; an RF source; an electrode, the electrode coupled to the RF source for delivering RF power into the chamber; and an impedance matching network, the impedance matching network coupled between the RF source and the electrode. In one embodiment, the impedance matching network includes: a first matrix tuning element, the first matrix tuning element is on a first branch, wherein the first matrix tuning element includes a first variable capacitor; a transformer, the transformer is on a second branch, wherein the transformer has at least a first tap, wherein a second matrix tuning element is on the first tap, and wherein the second matrix tuning element includes a second variable capacitor. In one embodiment, the impedance matching network further includes: a third matrix tuning element, the third matrix tuning element is on the second branch after the transformer, wherein the third matrix tuning element includes a third variable capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a perspective view of a solid-state impedance tuning unit according to an embodiment.

[0011] Figure 1B is a perspective view of a solid-state matrix tuning element according to one embodiment.

[0012] Figure 2Ais a circuit diagram of a column of diodes in an impedance tuning unit according to an embodiment.

[0013] Figure 2B is a circuit diagram of a matrix tuning element according to an embodiment.

[0014] Figure 3A is a circuit diagram of a solid-state impedance tuning network having a plurality of variable capacitors, each of which may be a unit cell or matrix tuning element, according to an embodiment.

[0015] Figure 3B is a circuit diagram of a transformer for a solid-state impedance tuning network including a plurality of taps according to an embodiment.

[0016] Figure 4A is a circuit diagram of a solid-state impedance tuning network having a plurality of variable capacitors, each of which may be a unit cell or matrix tuning element, according to additional embodiments.

[0017] Figure 4B is a circuit diagram of a solid-state impedance tuning network having a plurality of variable capacitors, each of which may be a unit cell or matrix tuning element, according to additional embodiments.

[0018] Figure 5A is a graph of capacitance versus mechanical displacement for an electromechanical impedance matching network according to one embodiment.

[0019] Figure 5B is a graph of capacitance versus DC voltage for a solid-state impedance matching network according to an embodiment.

[0020] Figure 6 is a cross-sectional view of a semiconductor processing tool including one or more solid-state impedance matching networks according to an embodiment.

[0021] Figure 7 A block diagram of an exemplary computer system that may be used in conjunction with a processing tool is illustrated in accordance with an embodiment. DETAILED DESCRIPTION

[0022] The systems described herein include a solid-state variable impedance matching system for a plasma processing system. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. It will be apparent to those skilled in the art that the embodiments may be practiced without these specific details. In other cases, well-known aspects are not described in detail to avoid unnecessarily obscuring the embodiments. In addition, it should be understood that the various embodiments shown in the drawings are exemplary representations and are not necessarily drawn to scale.

[0023] As described above, solid-state impedance matching networks have the advantage of being tuned faster than electromechanical impedance matching networks. For example, the change in capacitance of the solid-state impedance matching network described herein is controlled by changing the DC bias voltage coupled to the circuit. The limitation of the DC bias voltage for changing the capacitance of the cell arrangement of the diode is the rise time of the DC power supply. The current consumption for DC power is also a function of the rise time. The reverse bias of a diode (such as the diode used in this article) requires a low current, and the DC power rise time is expected to be less than 10 μs. Such a short rise time meets the RF pulse requirements of a plasma processing tool.

[0024] In addition to improved tuning speed, embodiments disclosed herein have improved resolution. Resolution is improved by cells arranged as diodes that change capacitance using a reverse biased DC voltage. The resolution of the DC bias voltage is equivalent to a radial electromechanical motor drive. In addition, voltage and current handling capabilities are improved. As used herein, silicon devices are distributed in a cell arrangement to enable higher current applications. Cells can be arranged with impedance transformation circuits to reduce voltage stress.

[0025] In one embodiment, the complexity of the solid-state impedance matching network disclosed herein is also minimized. In particular, adjusting the DC bias circuitry is similar to the motor drive scheme in an electromechanical system. In addition, the cost of the solid-state impedance matching network disclosed herein is reduced compared to existing solid-state solutions. In particular, the common diodes used for the impedance matching unit are suitable for this application. This narrows the cost gap between electromechanical solutions and solid-state solutions.

[0026] As will be described in more detail below, the lowest level building block of the variable capacitor used in the solid-state impedance matching network is a diode. In particular, a set of four diodes electrically connected in series are provided in a column on a board. Multiple columns electrically connected in parallel may be provided to form an impedance tuning unit (or simply referred to as a unit). In one embodiment, multiple units may be coupled together to form a matrix tuning element. It is understood that scaling to multiple columns of diodes and / or multiple units allows for improved resolution and dynamic range of the impedance matching network. In one embodiment, multiple variable capacitors may be arranged in a circuit to provide the desired tuning of the impedance matching network. In one embodiment, the variable capacitors may each have a variable capacitance. That is, each variable capacitor may have a capacitance range that can be obtained by controlling the variable capacitor (e.g., using a DC bias voltage). In some cases, each variable capacitor may have a different capacitance range, or two or more variable capacitors may have the same capacitance range.

[0027] Reference now Figure 1A, shows a perspective view of an impedance matching unit 100 according to an embodiment. In one embodiment, the impedance matching unit 100 includes a plurality of diodes 121 coupled to a board 101, such as a printed circuit board (PCB). The diodes 121 may be arranged in an array. For example, the array may include a plurality of columns 120, each column 120 including four rows. As will be described in more detail below, each column 120 of the four rows provides a building block for an impedance matching network. In the illustrated embodiment, eight columns 120 are shown in FIG. However, it should be understood that one or more columns 120 may be used in some embodiments. Increasing the number of columns 120 increases the resolution that can be achieved by the impedance matching unit 100.

[0028] In one embodiment, each column 120 may be electrically coupled to each other in electrical parallel. An input may be provided near the top edge of the board 101, and an output may be provided near the bottom edge of the board 101. The input may be coupled to an RF power source, and the output may be coupled to a load, such as a plasma load of a semiconductor processing tool. Additionally, as will be disclosed in more detail below, a first capacitor may be provided between the column 120 and the input, and a second capacitor may be provided between the column 120 and the output.

[0029] In addition to a single impedance matching unit 100, a plurality of impedance matching units 100 may be coupled together to provide a matrix tuning element. That is, the matrix tuning element may be a structure including two or more impedance matching units 100. For example, the matrix tuning element may include up to five impedance matching units 100. However, it should be understood that even more impedance matching units 100 may be included in the matrix tuning element.

[0030] Reference now Figure 1B , shows a perspective view of a matrix tuning element 105 according to an embodiment. The matrix tuning element 105 includes a plurality of impedance matching units 100 electrically coupled together. In this way, impedance tuning can be scaled to larger matrix tuning elements 105 to improve the resolution and capacitance range of the system. Although Figure 1B Four impedance matching units 100 are shown in FIG. 1 , and it should be understood that the matrix tuning element 105 may include two or more impedance matching units 100 .

[0031] Reference now Figure 2A, shows a circuit diagram of a column 220 of an impedance matching unit 100 according to an embodiment. In one embodiment, the column 220 may include a set of four diodes 221A and 221B connected in series between a first capacitor 213 and a second capacitor 215. The input 212 may be coupled to the first capacitor 213, and the output 214 may be coupled to the second capacitor 215. In one embodiment, the diode 221 may be arranged as a cathode 221A or an anode 221B. The arrangement between the first capacitor 213 and the second capacitor 215 may include a pattern of a cathode diode 221A, an anode diode 221B, a cathode diode 221A, and an anode diode 221B. In some embodiments, the diodes 221 may be substantially similar to each other. In other embodiments, the diodes 221 may have different IV characteristics.

[0032] In one embodiment, a ground connection 223 may be provided between the first capacitor 213 and the first cathode diode 221A and between the second anode diode 221B and the second capacitor 215. A resistor 224 may be provided before each ground connection 223. In one embodiment, DC bias inputs 222A and 222B may be provided between the first cathode diode 221A and the first anode diode 221B and between the second cathode diode 221A and the second anode diode 221B. A resistor 224 may be provided before each DC bias input 222A and 222B. Control of the DC bias at the DC bias input 222 allows the capacitance value of the column 220 to be modulated to provide a desired impedance matching value. In the illustrated embodiment, a resistor 224 is provided before each of the DC biases 222A and 222B. However, it should be understood that any high impedance passive device (or devices) may be provided before the DC biases 222A and 222B. In particular, the high impedance passive device prevents RF power from flowing to the DC bias 222A and 222B. In one embodiment, the two DC bias inputs 222A and 222B may apply the same DC bias. In other embodiments, the DC bias of the first DC bias input 222 may be different from the DC bias of the second DC bias input 222. In other embodiments, the bias applied to the DC bias 222A and 222B may be a differential bias, a pulse bias, etc. More particularly, the bias of the DC bias 222A and 222B is not limited to any particular waveform. In addition, it should be understood that each column 120 in the impedance matching unit 100 may be independently controllable to provide a desired capacitance value to the impedance matching unit 100.

[0033] Reference now Figure 2B , showing a pair of columns 220 according to one embodiment 1 and 220 2As shown, multiple columns 220 may be coupled in parallel between the RF input 212 and the RF output 214. A single column 220 1 and 220 2 It can be basically similar to the above reference Figure 2A The columns 220 are described in more detail. Although two columns 220 are shown 1 and 220 2 It should be understood that any number of columns 220 may be provided in parallel between the RF input 212 and the RF output 214 .

[0034] Reference now Figure 3A , shows a circuit diagram of an impedance matching network 350 according to an embodiment. In an embodiment, the impedance matching network 350 may be a solid-state impedance matching network 350. That is, unlike an electromechanical solution that uses a motor to drive different capacitors, the control of impedance is provided by solid-state components (e.g., diodes, etc.). The circuit between the input 312 and the output 314 may be considered a tuning circuit 305.

[0035] In one embodiment, impedance matching network 350 includes input 312 and output 314. Input 312 receives power from an RF source (not shown), and output 314 delivers RF power to a load (not shown), such as a plasma load in a semiconductor processing chamber.

[0036] In one embodiment, the input 312 is divided into a first branch 331 and a second branch 332. The first branch 331 includes a first variable capacitor C 1 , inductor 335, and ground 336. The first variable capacitor C 1 It can be a matrix tuning element. That is, the first variable capacitor C 1 A solid-state impedance tuning unit may be included, similar to the impedance tuning unit 100 described in more detail above. Thus, the first variable capacitor C 1 The first branch 331 may then continue to an inductor 335 having an output coupled to ground 336 .

[0037] In one embodiment, the second branch 332 includes a transformer circuit 306. The transformer circuit 306 may include a transformer 337. In one embodiment, the transformer 337 includes a single tap. However, as will be described in more detail below, the transformer 337 may include multiple taps. In one embodiment, a first end of the tap includes a third variable capacitor C 3 The third variable capacitor C 3 It can be a matrix tuning element. That is, the third variable capacitor C 3A solid-state impedance tuning unit may be included, similar to the impedance tuning unit 100 described in more detail above. Thus, the third variable capacitor C 3 The third variable capacitor C 3 The output of may be coupled to ground 336. An opposite second end of the tap may be coupled directly to ground 336.

[0038] In one embodiment, a second variable capacitor C may be provided along the second branch 332 between the transformer 337 and the output 314. 2 The second variable capacitor C 2 It can be a matrix tuning element. That is, the second variable capacitor C 2 A solid-state impedance tuning unit may be included, similar to the impedance tuning unit 100 described in more detail above. Thus, the second variable capacitor C 2 Capacitance.

[0039] It should be understood that multiple variable capacitors (e.g., C 1 , C 2 and C 3 ) can be independently controlled. In this way, various capacitance values ​​can be used to set the desired impedance in the impedance matching network. In some embodiments, all three variable capacitors C 1 , C 2 and C 3 The variable capacitor C is formed by a solid-state impedance tuning unit or a matrix tuning element. 1 , C 2 and C 3 One or both of the variable capacitors may include a solid-state impedance tuning unit or a matrix tuning element. Other variable capacitors may include electromechanical variable capacitors. That is, embodiments may include both solid-state variable capacitors and electromechanical variable capacitors. In addition, it should be understood that the variable capacitor C 1 , C 2 and C 3 It is not necessary to have the same range of capacitors. That is, C 1 The capacitance range can be related to C 2 and / or C 3 The capacitance range is different, C 2 The capacitance range can be related to C 1 and / or C 3 The capacitance range is different, and C 3 The capacitance range can be related to C 1 and / or C 2 The capacitance range is different.

[0040] Reference now Figure 3B, shows a circuit diagram of a transformer circuit 306 according to an additional embodiment. In one embodiment, the transformer circuit 306 can be replaced by the above reference Figure 3A The impedance matching network 350 is described. In one embodiment, the transformer circuit 306 may include multiple taps. For example, Figure 3B Three taps are provided in FIG. However, it should be understood that two or more taps may be included in different embodiments. In one embodiment, inductor 337 may be coupled to inductors 341 to 343. Each of inductors 341 to 343 may be a different tap.

[0041] In one embodiment, each tap includes an inductor 341 to 343 and a variable capacitor C 1 To C 3 Variable capacitor C 1 To C 3 Each of the variable capacitors C may be similar to any of the variable capacitors described in more detail above. 1 To C 3 A matrix tuning element may be included. That is, a variable capacitor C 1 To C 3 A solid-state impedance tuning unit may be included, similar to the impedance tuning unit 100 described in more detail above. Thus, the variable capacitor C is controlled by a pair of DC bias voltages. 1 To C 3 In one embodiment, each tap may further include a pair of grounds 336 on opposite sides of the inductors 341 to 343. On one side, the output of the inductors 341 to 343 is directly coupled to the ground 336. A variable capacitor C is provided between the inductors 341 to 343 and the ground 336 on the other side of the inductors 341 to 343. 1 To C 3 .

[0042] In one embodiment, the inductors 341 to 343 may have non-uniform inductances. In other embodiments, the inductors 341 to 343 may have the same inductances. Similarly, the variable capacitor C 1 To C 3 Can be uniform or variable capacitor C 1 To C 3 Available in different capacitance ranges.

[0043] Reference now Figure 4A, a circuit diagram of an impedance matching network 450 according to an additional embodiment is shown. In one embodiment, the impedance matching network 450 may include an input 412 and an output 414. The input 412 may be coupled to an RF source, and the output 414 may be coupled to a load, such as a plasma load in a semiconductor processing tool. In one embodiment, the impedance matching network 450 may include a first branch 431 and a second branch 432.

[0044] The first branch 431 may include a first variable capacitor C 1 The transformer 437 can then be coupled to the first variable capacitor C 1 The transformer 437 may have an output coupled to a second variable capacitor C 2 The single tap may have two ends coupled to ground 436. In one embodiment, the first branch 431 may also terminate at ground 436. In one embodiment, the second branch 431 may include a third variable capacitor C 3 The third variable capacitor C 3 An inductor 438 is then provided.

[0045] In one embodiment, the variable capacitor C 1 To C 3 Each of the variable capacitors C may be a capacitance tuning unit or multiple units to form a matrix tuning element. 1 To C 3 Different capacitance ranges may be included. In other embodiments, two or more variable capacitors C 1 To C 3 Can have the same capacitance range.

[0046] Reference now Figure 4B , a circuit diagram of an impedance matching network 450 according to an additional embodiment is shown. In one embodiment, the impedance matching network 450 may include an input 412 and an output 414. The input 412 may be coupled to an RF source, and the output 414 may be coupled to a load, such as a plasma load in a semiconductor processing tool. In one embodiment, the impedance matching network 450 may include a first branch 431, a second branch 432, and a third branch 433.

[0047] The first branch 431 may include a first variable capacitor C 1 Then, the inductor 439 may be coupled to the first variable capacitor C 1 In one embodiment, the first branch 431 may terminate at ground 436. In one embodiment, the second branch 432 may include a transformer 437. The transformer 437 may have a second variable capacitor C coupled to the first branch 431. 2The single tap may have two ends coupled to ground 436. In one embodiment, the second branch 432 may also terminate at ground 436. In one embodiment, the third branch 433 may include a third variable capacitor C 3 The third variable capacitor C 3 An inductor 438 is then provided.

[0048] In one embodiment, the variable capacitor C 1 To C 3 Each of the variable capacitors C may be a capacitance tuning unit or multiple units to form a matrix tuning element. 1 To C 3 Different capacitance ranges may be included. In other embodiments, the variable capacitor C 1 To C 3 Two or more of may have the same capacitance range.

[0049] Reference now Figure 5A and 5B , showing capacitance versus mechanical displacement ( Figure 5A ) and DC bias voltage ( Figure 5B ) in the table below. Figure 5A is a diagram of an electromechanically tuned system, and Figure 5B is a diagram of a solid-state tuned system, such as those described in this article. Figure 5A As shown in , the resolution of the capacitance is very high. That is, there is a substantially continuous output. This capacitance relationship enables fine tuning of the impedance. In existing solid-state solutions, the output of the capacitance graph is discontinuous, resulting in low resolution.

[0050] However, in the embodiments disclosed herein, the capacitance graph is continuous. Figure 5B An example of capacitance versus DC bias voltage is shown in FIG. As shown, high resolution enables fine tuning of impedance, similar to Figure 5A In addition, Figure 5B The curve is relatively smooth. Therefore, the performance of the solid-state solution described herein can substantially match the performance of the electromechanical solution. However, as described above, the response time of the solid-state solution described herein is several orders of magnitude faster than the response time of the electromechanical solution. Accordingly, the embodiments disclosed herein include improved resolution and improved response time compared to existing solutions.

[0051] Reference now Figure 6, shows a cross-sectional view of a semiconductor processing tool 680 according to one embodiment. In one embodiment, the semiconductor processing tool 680 may include a chamber 681. The chamber 681 may be adapted to support a low pressure environment, such as a pressure close to a vacuum. In one embodiment, a pump and exhaust system (not shown) may be included to achieve the low pressure environment. In one embodiment, one or more process gases may flow into the chamber. For example, the process gas may flow into the chamber 681 via a cover 685. The cover 685 may be a showerhead type component to more evenly distribute the gas into the chamber 681.

[0052] In one embodiment, the chamber 681 may include a pedestal 682. The pedestal 682 may be adapted to support a substrate 683. The pedestal 682 may include heating and / or cooling features to control the temperature of the substrate 683 during processing. The substrate 683 may be coupled to the pedestal 682 using any suitable chuck mechanism. For example, an electrostatic chuck, a vacuum chuck, etc. may be used to secure the substrate 683. The substrate 683 may be any substrate processed in the semiconductor processing tool 680. For example, the substrate 683 may include a semiconductor wafer, such as a silicon wafer. However, other semiconductor materials may also be used. In one embodiment, the wafer has a standard form factor, such as 150 mm, 200 mm, 300 mm, 450 mm, etc. In one embodiment, other substrates (e.g., glass, sapphire, etc.) may also be processed in the chamber 681.

[0053] In one embodiment, an RF source 686 may be coupled to the chamber 681. In particular, the RF source 686 may be coupled to a lid 685 or other electrode in the chamber 681. The RF source 686 generates RF power that may be coupled to a process gas within the chamber 681 to form a plasma 684 for processing the substrate 683. To maximize the forward power entering the chamber 681 (with minimal reflected power), an impedance matching network 687 may be provided between the RF source 686 and the lid 685.

[0054] In one embodiment, the impedance matching network 687 may be substantially similar to any impedance matching network described in more detail herein. In particular, the impedance matching network 687 may be a solid-state impedance matching network 687. For example, the impedance matching network 687 may include a variable capacitor formed by a diode array. The diode array may be arranged in four rows in any number of parallel columns on a board to form a unit. A plurality of units may be coupled together to form a matrix tuning element. A DC bias voltage may be used to control the capacitance of the variable capacitor (i.e., the variable capacitance). As described above, the rise time of the DC bias voltage may be about 10 μs or less. In this way, flexible and precise control of the variable capacitance may be achieved to control the impedance of the impedance matching network 687. In one embodiment, each of the variable capacitors may have a variable capacitance. That is, each variable capacitor may have a capacitance range that can be obtained by controlling the variable capacitor (e.g., using a DC bias voltage). In some cases, each variable capacitor may have a different capacitance range, or two or more variable capacitors may have the same capacitance range.

[0055] In one embodiment, the semiconductor processing tool 680 may also include a second RF source 688. The second RF source 688 may be coupled to the pedestal 682 and / or the substrate 683. The second RF source 688 may be used in conjunction with the RF source 686. In other embodiments, the second RF source 688 may be used in place of the RF source 686. The second RF source 686 may be coupled to the chamber via a second impedance matching network 689.

[0056] In one embodiment, the second impedance matching network 689 may be substantially similar to any impedance matching network described in more detail herein. In particular, the second impedance matching network 689 may be a solid-state impedance matching network 689. For example, the second impedance matching network 689 may include a variable capacitor formed by a diode array. The diode array may be arranged in four rows in any number of parallel columns on a board to form a unit. Multiple units may be coupled together to form a matrix tuning element. A DC bias voltage may be used to control the capacitance of the variable capacitor. As described above, the rise time of the DC bias voltage may be about 10 μs or less. In this way, flexible and precise control of the variable capacitor can be achieved to control the impedance of the second impedance matching network 689.

[0057] Reference now Figure 7, a block diagram of an exemplary computer system 700 of a processing tool according to an embodiment is illustrated. In one embodiment, the computer system 700 is coupled to the processing tool and controls the processing in the processing tool. The computer system 700 may be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The computer system 700 may operate as a server or client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The computer system 700 may be a personal computer (PC), a tablet computer, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network application device, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) to specify the actions to be taken by the machine. In addition, although only a single machine is illustrated for the computer system 700, the term "machine" should also be deemed to include a collection of any machines (e.g., computers) that execute a set of instructions (or multiple sets of instructions) individually or jointly to perform any one or more methods described herein.

[0058] The computer system 700 may include a computer program product, or software 722, a non-transitory machine-readable medium having instructions stored thereon, which can be used to program the computer system 700 (or other electronic device) to perform processing according to an embodiment. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., a computer-readable) medium includes a machine-readable (e.g., a computer) storage medium (e.g., a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.), a machine-readable (e.g., a computer) transmission medium (an electrical, optical, acoustic or other form of propagated signal (e.g., an infrared light signal, a digital signal, etc.)), etc.

[0059] In one embodiment, the computer system 700 includes a system processor 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 718 (e.g., a data storage device), which communicate with each other via a bus 730.

[0060] The system processor 702 represents one or more general-purpose processing devices, such as a microsystem processor, a central processing unit, etc. More specifically, the system processor may be a complex instruction set computing (CISC) microsystem processor, a reduced instruction set computing (RISC) microsystem processor, a very long instruction word (VLIW) microsystem processor, a system processor that implements other instruction sets, or a system processor that implements a combination of instruction sets. The system processor 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal system processor (DSP), a network system processor, etc. The system processor 702 is configured to execute processing logic 726 for performing the operations described herein.

[0061] The computer system 700 may further include a system network interface device 708 for communicating with other devices or machines. The computer system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), and a signal generating device 716 (e.g., a speaker).

[0062] The secondary memory 718 may include a machine-accessible storage medium 732 (or more specifically, a computer-readable storage medium) having stored thereon one or more sets of instructions (e.g., software 722) that embody any one or more of the methods or functions described herein. The software 722 may also reside, in whole or in part, within the main memory 704 and / or within the system processor 702 during execution by the computer system 700, the main memory 704 and the system processor 702 also constituting machine-readable storage media. The software 722 may further be sent or received over the network 720 via the system network interface device 708. In one embodiment, the network interface device 708 may operate using RF coupling, optical coupling, acoustic coupling, or inductive coupling.

[0063] Although the machine-accessible storage medium 732 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more methods. Accordingly, the term "machine-readable storage medium" should be taken to include, but is not limited to, solid-state memories, and optical and magnetic media.

[0064] In the foregoing specification, specific exemplary embodiments have been described. It will be apparent that various modifications may be made thereto without departing from the scope of the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. An impedance matching network, comprising: enter; a first matrix tuning element on a first branch from the input, wherein the first matrix tuning element comprises a first variable capacitance; a transformer on a second branch from the input, wherein the transformer has at least a first tap, wherein a second matrix tuning element is on the first tap, and wherein the second matrix tuning element comprises a second variable capacitance; a third matrix tuning element, the third matrix tuning element being after the transformer on the second branch, wherein the third matrix tuning element comprises a third variable capacitance; and An output is provided after the third matrix tuning element on the second branch.

2. The impedance matching network of claim 1, wherein the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element are identical to each other.

3. The impedance matching network of claim 1, wherein two or more of the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element are different from each other. 4 . The impedance matching network of claim 1 , wherein each of the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element comprises at least four diodes connected in series with each other.

5. The impedance matching network of claim 4, wherein the four diodes comprise: A first cathode diode, a first anode diode, a second cathode diode, and a second anode diode.

6. An impedance matching network according to claim 5, wherein a ground connection is provided before the first cathode diode and after the second anode diode.

7. The impedance matching network of claim 5, wherein a first DC bias voltage is connected between the first cathode diode and the first anode diode, and wherein a second DC bias voltage is connected between the second cathode diode and the second anode diode. 8 . The impedance matching network of claim 7 , wherein the first DC bias voltage and the second DC bias voltage are differential bias voltages or pulse bias voltages.

9. The impedance matching network of claim 1, wherein one or more of the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element comprises: An impedance tuning unit has two or more columns of diodes, wherein each column includes four rows of the diodes connected in series.

10. The impedance matching network of claim 8, wherein diodes of two or more columns are electrically connected in parallel.

11. The impedance matching network of claim 8, wherein each of the matrix tuning elements comprises a plurality of impedance tuning units.

12. The impedance matching network of claim 1, wherein the transformer comprises three or more taps, and wherein each tap comprises a matrix tuning element.

13. The impedance matching network of claim 1, wherein the output is coupled to a plasma processing tool, and wherein the input is coupled to an RF power source.

14. The impedance matching network of claim 1, wherein at least one of the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element is a solid-state device, and wherein at least one of the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element is an electromechanical device.

15. A matrix tuning element, comprising: One or more units, each of which comprises: A diode array is coupled to the board, wherein the array comprises one or more columns of diodes, and wherein each column comprises four rows of diodes connected in series.

16. The matrix tuning element of claim 15, wherein the four rows of diodes comprise: a first cathode diode; a first anode diode; a second cathode diode; as well as Second anode diode.

17. A matrix tuning element as claimed in claim 16, wherein a first DC bias connection is provided between the first cathode diode and the first anode diode, and wherein a second DC bias connection is provided between the second cathode diode and the second anode diode.

18. A semiconductor processing tool comprising: Chamber; RF source; an electrode coupled to the RF source for inducing RF power into the chamber; as well as an impedance matching network coupled between the RF source and the electrode, wherein the impedance matching network comprises: a first matrix tuning element, the first matrix tuning element being on a first branch, wherein the first matrix tuning element comprises a first variable capacitor; a transformer on a second branch, wherein the transformer has at least a first tap, wherein a second matrix tuning element is on the first tap, and wherein the second matrix tuning element comprises a second variable capacitance; and A third matrix tuning element is provided after the transformer on the second branch, wherein the third matrix tuning element comprises a third variable capacitance.

19. The semiconductor processing tool of claim 18, wherein each of the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element comprises a plurality of cells, wherein each cell comprises a plurality of columns of diodes, and wherein each column comprises four rows of diodes coupled together in series.

20. The semiconductor processing tool of claim 18, wherein the first matrix tuning element, the second matrix tuning element, and the third matrix tuning element have variable capacitance controlled by a DC bias voltage.

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