METHOD FOR IMPROVING CHANNEL MOBILITY IN SiC MOSFETS

Abstract

Disclosed is a method for manufacturing a SiC semiconductor element (10), the method comprising the steps of: providing a SiC substrate (20) having a SiC epitaxial layer (30) on top; the SiC epitaxial layer (30) is treated by plasma immersion ion implantation (PIII) using a dopant (35) of a first material. The method further comprises thermally oxidizing a top surface (31) of the SiC epitaxial layer (30) such that a thermal oxide layer (40) grows; and etching the thermal oxide layer (40). The method further includes implanting a dopant (36) of a second material in the SiC epitaxial layer (30) such that a drain (50) and a source (60) are produced; activating the dopant by activation annealing; and depositing a metal gate (70).

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a silicon carbide (SiC) semiconductor component. The present disclosure also relates to a silicon carbide (SiC) semiconductor component for high power switching applications. Background Art

[0002] Silicon carbide (SiC) is the only compound semiconductor that can be thermally oxidized like silicon. For this reason, thermally grown oxide on SiC can be used as a gate dielectric to form metal oxide semiconductor (MOS) devices. SiC MOS field effect transistors (MOSFETs) are promising candidates for high power switching applications. Low on-resistance and high load current make them ideal for use as switching devices.

[0003] A lateral MOSFET consists of a source and a drain, two highly conductive p-type semiconductor regions isolated from an n-type substrate by a reverse biased pn diode. A metal gate covers the region between the source and drain and is separated from the semiconductor by a gate oxide. The flow of charge carriers from the source to the drain (also called the channel) is controlled by a voltage applied to the gate.

[0004] However, with the development of electronic technology, high temperature, high frequency, etc. have increased the requirements for semiconductor devices and circuits. Silicon (Si) cannot meet these requirements, especially for power switches, due to its material properties, and therefore SiC materials have been developed for semiconductor devices operating at high power, high temperature and high frequency. For power switch applications, insulated gate bipolar transistors (IGBTs) and metal oxide semiconductor field effect transistors (MOSFETs) are widely used. These components have a structure in which the gate electrode portion is electrically insulated from the component body. Since only the capacitor composed of the gate electrode and the component body needs to be charged and discharged, the gate control current is significantly less than the gate control current of, for example, a gate turn-off transistor.

[0005] Despite the high bulk mobility of SiC, the inversion channel mobility in SiC MOSFETs is reported to be low, resulting in an on-state resistance much higher than expected based on the bulk SiC properties. This is attributed to the interface state density D at the SiO2 / SiC interface. it Large. D at the SiO2 / SiC interface it The range is between 10e11 and 10e13 cm -2 eV -1 and less than 10e10 cm at SiO2 / Si. -2 eV -1 . D near the conduction band edge itThe properties are usually attributed to the presence of C-related defects and intrinsic oxide acceptor defects, while D near the valence band it The properties are mainly attributed to C-related donor defects. The presence of carbon in the SiC epilayer is due to implantation during oxidation, resulting in immobile C clusters such as carbon bi-interstitial (Ci)_2.

[0006] However, standard ion implantation in SiC also creates electrically active defects that can trap charge carriers. These factors, combined with the C-related defects formed during oxidation, reduce the charge carrier mobility in the channel.

[0007] For n-channel MOSFETs, a method to reduce D it Different methods of annealing such as post oxidation annealing (POA) and pre oxidation implantation (POI) are used. The use of POA in N2O or POCl3 environment or POI based on N, P or Sb donor impurities leads to D in the upper part of the SiC band gap. it Reduced (1e11 cm for POA -2 eV -1 , for POI as low as 1e12 cm -2 eV -1 ) and the carrier mobility is improved (90 cm for POA 2 V -1 s -1 , and for POI is 20-100cm 2 V -1 s -1 ). it The reasons for the reduction and subsequent improvement of carrier mobility have been explained in terms of passivation of C clusters by N (or P) atoms. The improvement of carrier mobility has also been explained in terms of reverse doping. By this mechanism, the accumulation of N or P or Sb in the channel region close to the surface passivates the interface defects and improves the electron mobility in the n-channel by converting the epitaxial layer doping from p-type to n-type. Nevertheless, both POA and POI have some disadvantages that affect the reliability of the fabricated devices: it is difficult to control the concentration of the incorporated N or P by POA, and a flat band voltage shift occurs due to the introduction of N or P or Sb in SiO2. In addition, since P is more easily incorporated into SiC than N, normally-on devices can be obtained. Summary of the invention

[0008] The purpose is to avoid a high interface state density at the SiO2 / SiC interface.

[0009] Another object is to increase carrier mobility in the channel of a SiC semiconductor element.

[0010] These objects are solved by the features of the independent claims.

[0011] Therefore, a method for producing a SiC semiconductor component is provided, wherein neither a post-oxidation anneal nor a pre-oxidation implant is required. Furthermore, a corresponding SiC semiconductor component is provided.

[0012] Plasma immersion ion implantation (PIII) or pulsed plasma doping (pulsed PIII) is a surface modification technique that extracts accelerated ions from a plasma by applying a high voltage pulsed DC or pure DC power supply and targets them into a suitable substrate or an electrode on which a semiconductor wafer is placed so as to implant it with a suitable dopant. The electrode is the cathode for a positively charged plasma, while it is the anode for a negatively charged plasma. The plasma can be generated in a properly designed vacuum chamber with the help of various plasma sources, such as electron cyclotron resonance plasma sources (which produce plasmas with the highest ion density and the lowest contamination levels), helicon plasma sources, capacitively coupled plasma sources, inductively coupled plasma sources, DC glow discharges, and metal vapor arcs. The vacuum chamber can be of two types - diode type and triode type, depending on whether the power supply is applied to the substrate (as in the former case) or to a perforated grid (as in the latter case).

[0013] Therefore, the method for manufacturing a SiC semiconductor element comprises the following steps: providing a SiC substrate having a SiC epitaxial layer on top; treating the SiC epitaxial layer by plasma immersion ion implantation (PIII) using a dopant of a first material. The method also comprises: thermally oxidizing the surface of the SiC epitaxial layer so that a thermal oxide layer (40) is grown; and etching the thermal oxide layer (40). The method further comprises: implanting a dopant of a second material in the SiC epitaxial layer so that a drain and a source are produced; activating the dopant by activation annealing; and depositing a metal gate.

[0014] The method for manufacturing a SiC semiconductor element comprises the optional step of performing an additional plasma immersion ion implantation using Si.

[0015] The method for manufacturing a SiC semiconductor element comprises the further optional step of performing plasma immersion ion implantation using Ar to pre-amorphize the SiC epitaxial layer before treating the SiC epitaxial layer by plasma immersion ion implantation (PIII) with a dopant of a first material.

[0016] By using the described method for manufacturing a SiC semiconductor element, it is possible to counteract the aforementioned adverse effects due to the specially performed plasma immersion ion implantation.

[0017] It is possible to reduce the interface state density D at the SiO2 / SiC interface itand subsequently improve the carrier mobility.

[0018] In addition, the optional step of Si PIII also improves carrier mobility. During oxidation, such Si-rich layers will be oxidized and the formation of C clusters will be minimized, resulting in increased carrier mobility in the channel of the SiC semiconductor element.

[0019] An additional step of Ar PIII enables making the channel region deeper.

[0020] A silicon carbide (SiC) semiconductor element comprises a SiC semiconductor substrate having a top surface and a bottom surface, and a SiC epitaxial layer having a top surface and a bottom surface. The SiC epitaxial layer is formed on the top surface of the SiC semiconductor substrate. The SiC semiconductor element further comprises a source and drain structure, a thermal oxide and a metal gate formed in the top surface of the SiC epitaxial layer, and a first region having a dopant of a first material, which first region may be a part of a channel. The thermal oxide covers the first region, at least a portion of the source structure, and at least a portion of the drain structure. Therefore, the metal gate is electrically insulated from the first region, the source structure, and the drain structure by the thermal oxide, and overlaps with the first region and at least a portion of the source and drain structure.

[0021] The SiC semiconductor component may optionally include a second region which is treated with Si by PIII.

[0022] The SiC semiconductor element may optionally include a SiC epitaxial layer that has been amorphized in advance with Ar.

[0023] The SiC semiconductor substrate is a 3C-SiC substrate, a 4H-SiC substrate, or a 6H-SiC substrate.

[0024] The SiC substrate is n-doped or p-doped, and the SiC epitaxial layer is n-doped or p-doped in the same manner as the SiC substrate.

[0025] The SiC semiconductor element can be used as a SiC transistor. For example, the SiC transistor can be an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET), a SiC junction field effect transistor (SiC-JFET) or a SiC bipolar junction transistor (SiC-BJT).

[0026] Finally, it should be pointed out that all proposed features and methods can be used individually but also in combinations of two or more.

[0027] The present disclosure relates to implanting dopants in a SiC semiconductor element XYZXYZ.

[0028] Since the described SiC semiconductor component can be manufactured by embodiments of the method, the described features and characteristics of the method are also disclosed with respect to the SiC semiconductor component, and vice versa. Therefore, the present disclosure comprises several aspects, wherein each feature described with respect to one of these aspects is also disclosed herein with respect to another aspect, even if the corresponding feature is not explicitly mentioned in the context of a particular aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Exemplary embodiments are explained below with the aid of schematic diagrams and reference numerals. The drawings show:

[0030] Figures 1a-1g The steps of manufacturing a SiC semiconductor element are shown.

[0031] Figure 2 shows the DLTS spectra of pristine and PIII-treated 4H-SiC,

[0032] Figure 3a , Figure 3b The transfer and output characteristics of the MOSFET are shown.

[0033] The accompanying drawings are included to provide further understanding. It will be understood that the embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale. The same reference numerals designate elements or components having the same function. To the extent that an element or component corresponds to one another in different figures in terms of its function, its description will not be repeated for each of the following figures. For clarity, an element may not appear with the corresponding reference numeral in all figures. DETAILED DESCRIPTION

[0034] Figure 1a to Figure 1g The steps of a method for producing a semiconductor component 10 are shown.

[0035] In this regard, terms such as "above", "below", "top", "upper" and "bottom" refer to orientations or directions as illustrated in the figures and relative to the stacking direction A. Thus, the height or thickness of the described elements is related to the stacking direction A, while the lateral direction B is oriented perpendicular to the stacking direction A (see FIG. Figure 1a to Figure 1g ).

[0036] exist Figure 1a In the embodiment, a SiC substrate 20 having a top surface 21 and a bottom surface 22 is provided. On the top surface 21 of the SiC substrate 20 is a SiC epitaxial layer 30 having a bottom surface 31 and a top surface 32. The bottom surface 31 of the SiC epitaxial layer 30 faces the top surface 21 of the SiC substrate 20. The SiC substrate 20 may be n-doped or p-doped with a concentration of at least 1e18 cm -3The SiC epitaxial layer 30 is doped in the same manner as the SiC substrate 20 and may also be n-doped or p-doped with a concentration of 1e14 cm -3 With 1e16cm -3 For example, the SiC substrate 20 may be a 3C-SiC substrate, a 4H-SiC substrate, or a 6H-SiC substrate. For example, in the case of a 3C-SiC epitaxial layer, the SiC substrate 20 may be replaced by a silicon (Si) substrate.

[0037] Figure 1b The SiC epitaxial layer 30 is processed by plasma immersion ion implantation (PIII) to produce a first region 33 in the SiC epitaxial layer 30, the first region having a dopant 35 of a first material. The doping concentration of the dopant 35 of the first material in the SiC epitaxial layer 30 is 1e16-1e20 cm -3 The dopant 35 for the first material of the n-doped semiconductor element 10 may be, for example, an element from the 2nd group (Be, Mg, Ca, Sr, Ba, Ra) or the 13th group (B, Al, Ga, In, Tl, Nh). Alternatively, the dopant 35 for the first material of the p-doped semiconductor element 10 may be, for example, an element from the 15th group (N, P, As, Sb, Bi, Mc) or the 16th group (O, S, Se, Te, Po, Lv). For example, for PIII, energies in the range of 1-30 keV and aluminum dopants may be used. The implantation is performed at room temperature RT (approximately 20° C.-22° C.) or at a temperature between 300° C. and 500° C.

[0038] After implanting the dopant 35 of the first material, Figure 1c An optional further PIII step is shown. For this PIII step, an energy in the range of 1-15 keV and silicon as further dopant 37 are used, thereby producing a second region 34 in the SiC epitaxial layer 30. The doping concentration of the dopant in the SiC epitaxial layer 30 is between 1e15 and 1e18 cm -3 The implantation is performed at room temperature RT or at a temperature between 300° C. and 500° C. In this way, during oxidation, such Si-rich layer 34 will be oxidized and the formation of C clusters will be minimized, resulting in an improved carrier mobility.

[0039] Figure 1dA manufacturing step after an implantation step of a dopant 35 of a first material (such as Al, for example) or a dopant 35 of a first material and silicon is shown. This step shows a thermal oxidation of the top surface 31 of the SiC epitaxial layer 30, so that a thermal oxide layer 40 of SiO2 grows on top of the SiC epitaxial layer 30. The oxide layer 40 has a top surface 41 and a bottom surface 42. A SiO2 / SiC interface 45 is created between the top surface 31 of the SiC epitaxial layer 30 and the bottom surface 42 of the thermal oxide layer 40. The thermal oxidation is performed at a temperature between 1100°C and 1400°C.

[0040] Interface state density D at the SiO2 / SiC interface 45 in a typical MOSFET standard implant it is approximately 1e12-1e13 cm -2 eV -1 If both Al and Si PIII are used, the interface state density D it Less than 1e12 cm -2 eV -1 , and the on-resistance R_on is reduced by 8-10%.

[0041] In a typical MOSFET with standard implantation, the carrier mobility in the channel is approximately 20-50 cm 2 / Vs. If both Al and Si PIII are used, the carrier mobility in the channel is higher than 100 cm 2 / Vs.

[0042] After standard channel implantation, the concentration of carbon vacancies (Vc) in the SiC epilayer is higher than 1e14 cm -3 If AlPIII is used, the concentration of carbon vacancies (Vc) is lower than 1e11 cm -3 If Si PIII is performed on top of Al PIII, the concentration of carbon vacancies (Vc) is even lower.

[0043] Additionally, before the SiC epitaxial layer 30 is treated by plasma immersion ion implantation (PIII) using the dopant 35 of the first material and / or Si, the SiC epitaxial layer 30 may be treated by plasma immersion ion implantation (PIII) using Ar at an energy in the range of 5-10 keV to pre-amorphize the SiC epitaxial layer 30. Ar PIII helps to make the channel deeper.

[0044] Figure 1e The thermal oxide layer 40 is shown, which is etched back at the edge of the thermal oxide layer 40 until the underlying SiC epitaxial layer 30 with the doped first region 33 is visible.

[0045] Figure 1f The implantation of a dopant 36 of a second material in the SiC epitaxial layer 30 is shown, so that a drain 50 and a source 60 are produced. The implantation takes place at RT or at a temperature between 300° C. and 500° C. The concentration of the dopant 36 of the second material is between 1e17 and 1e21 cm -3 The implantation may be performed at a concentration within the range of 1000°C to 1000°C, but at least one order of magnitude higher than the concentration of the dopant of the first material (e.g., Al) used in PIII. For example, the implantation may be an n+ implantation using an n-type dopant. The implantation is followed by an activation annealing at a temperature between 1600°C and 1700°C for 30 minutes. The activation annealing is a thermal treatment that compensates for implantation damage caused by the dopant.

[0046] exist Figure 1g In the step shown in FIG. 4 , a metal gate 50 is deposited on the top 41 of the etched-back thermal oxide layer 40 .

[0047] This is a basic lateral structure, but the disclosure of the embodiments also extends its application to vertical SiC MOSFET devices.

[0048] The SiC semiconductor element 10 may be used as a SiC transistor, for example, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a SiC junction field effect transistor (SiC-JFET), or a SiC bipolar junction transistor (SiC-BJT).

[0049] Figure 2 Fourier transformed deep level transient spectroscopy (FT-DLTS) spectra of pristine SiC (solid line) and PIII treated SiC (dashed line) are shown. Capacitance (pF) is plotted against temperature (K).

[0050] The idea is to use plasma immersion ion implantation (PIII) to form the channel. By using standard ion implantation on native SiC, several electrically active energy levels appear, such as EH1 (Ec-0.4eV), Z1 / 2 (Ec-0.65eV), EH3 (Ec-0.72eV), EH4 (Ec-0.8eV), EH5 (Ec-1.0eV) and EH6 / 7 (Ec-1.6eV). The concentration of these energy levels is between 1e13-1e15cm -3 range. These electron traps contribute to hindering carrier mobility in the channel. On the other hand, PIII does not lead to the formation of electrically active energy levels, except for two levels labeled ON1 and ON2, which do not have any effect on the device functionality. In this way, it is possible to allow charge carriers to flow seamlessly in the channel without any trapping effects from electron traps.

[0051] Figure 3a and Figure 3b Shown are simulated output and transfer characteristics of MOSFETs having channels formed by standard ion implantation (solid line) and PIII (dashed line).

[0052] Figure 3a It is shown that the simulated devices have the same threshold voltage (V_th). Therefore, the gain in on-resistance R_on is only due to the lower defect density.

[0053] Figure 3b The output characteristics when PIII is employed are shown. It can be seen that the curve for the PIII treated MOSFET (dashed line) shows an improvement over the standard ion implantation (solid line), which means that R_on has been reduced.

[0054] The embodiments shown in FIGS. 1 to 3 as stated represent exemplary embodiments of an improved SiC semiconductor component 10 and a method of manufacturing the same; therefore, they do not constitute a complete list of all embodiments. For example, the actual arrangement and method may differ in the SiC semiconductor component 10 from the illustrated embodiments.

[0055] Reference numerals

[0056] 10 SiC semiconductor components

[0057] 20 SiC substrate

[0058] 21 Top surface of SiC substrate

[0059] 22 Bottom surface of SiC substrate

[0060] 30 SiC epitaxial layer

[0061] 31 Top surface of SiC epitaxial layer

[0062] 32 Bottom surface of SiC epitaxial layer

[0063] 33 The first region of the SiC epitaxial layer

[0064] 34 Second region of SiC epitaxial layer

[0065] 35 Dopant of the first material

[0066] 36 Dopant of the second material

[0067] 37 Additional dopant Si

[0068] 40 Thermal Oxide Layer

[0069] 41 Top surface of thermal oxide layer

[0070] 42 Bottom surface of thermal oxide layer

[0071] 45 SiO2 / SiC interface

[0072] 50 Drain

[0073] 60 Source

[0074] 70 Metal Gate

Claims

1. A method for manufacturing a SiC semiconductor element (10), the method comprising the following steps: - providing a SiC substrate (20) having a SiC epitaxial layer (30) on top, - treating the SiC epitaxial layer (30) with a dopant (35) of a first material by plasma immersion ion implantation (PIII), - thermally oxidizing the top surface (31) of the SiC epitaxial layer (30) so as to grow a thermal oxide layer (40), - etching the thermal oxide layer (40), - implanting a dopant (36) of a second material into the SiC epitaxial layer (30) so as to produce a drain (50) and a source (60), - activating the dopant by activation annealing, and - Deposition of a metal gate (70).

2. The method for manufacturing a SiC semiconductor element (10) according to claim 1, wherein: The PIII is performed at room temperature RT or at a temperature between 300° C. and 500° C. using a dopant (35) of the first material at an energy in the range of 1-30 keV, the dopant of the first material having a doping concentration in the SiC epitaxial layer (30) being between 1e16 and 1e20 cm -3 within the range.

3. The method for manufacturing a SiC semiconductor element (10) according to claim 1 or 2, wherein: The implantation is performed at room temperature RT or at a temperature between 300° C. and 500° C. using a dopant (36) of the second material having a doping concentration in the SiC epitaxial layer (20) of 1e17-1e21 cm -3 , and wherein the doping concentration of the dopant (36) of the second material in the SiC epitaxial layer (20) is at least one order of magnitude higher than the doping concentration of the dopant (35) of the first material in the SiC epitaxial layer (20).

4. The method for manufacturing a SiC semiconductor element (10) according to claim 1, 2 or 3, wherein: - The activation annealing is performed at a temperature between 1600° C. and 1700° C. for 30 minutes.

5. The method for producing a SiC semiconductor component (10) according to any one of the preceding claims, the method comprising: - treating the SiC epitaxial layer (30) by further plasma immersion ion implantation (PIII) at room temperature RT or at a temperature between 300° C. and 500° C. with Si having a doping concentration in the SiC epitaxial layer (30) of 1e15-1e18 cm -3 within the range.

6. The method for producing a SiC semiconductor component (10) according to any one of the preceding claims, comprising: - before treating the SiC epitaxial layer (30) by plasma immersion ion implantation (PIII) with a dopant (35) of the first material, treating the SiC epitaxial layer (30) by plasma immersion ion implantation (PIII) using Ar at an energy in the range of 5-10 keV to pre-amorphize the SiC epitaxial layer (30).

7. A SiC semiconductor element (10), comprising: - SiC substrate (20), - A SiC epitaxial layer (30), comprising: a first region (33) treated with a dopant (35) of a first material by plasma immersion ion implantation (PIII), - a thermal oxide layer (40), - a drain electrode (50), - a source electrode (60), and - A metal gate (70).

8. The semiconductor component (10) according to claim 7, wherein: - The dopant (35) of the first material for PIII comes from the elements of group 2 (Be, Mg, Ca, Sr, Ba, Ra) or group 13 (B, Al, Ga, In, Tl, Nh).

9. The SiC semiconductor element (10) according to claim 8, wherein: The dopant (35) of the first material for PIII has an energy in the range of 1-30 keV and a doping concentration in the SiC epitaxial layer (30) of 1e16-1e20 cm -3 Al within the range of.

10. The SiC semiconductor element (10) according to claim 7, wherein: - The dopant (35) of the first material for PIII is from the group 15 elements (N, P, As, Sb, Bi, Mc) or the group 16 elements (O, S, Se, Te, Po, Lv).

11. The SiC semiconductor element (10) according to any one of claims 7 to 10, comprising: - A second region (34) treated with Si by PIII.

12. The SiC semiconductor element (10) according to claim 11, wherein: The Si from the second region (34) is doped at an energy in the range of 1-15 keV and at a doping concentration in the SiC epitaxial layer (30) of 1e15-1e18 cm -3 Injected within the range.

13. The SiC semiconductor element (10) according to claim 7, wherein: - implanting Ar into the SiC epitaxial layer (30) at an energy in the range of 5-10 keV to pre-amorphize the SiC epitaxial layer (30).

14. The SiC semiconductor element (10) according to any one of claims 7 to 13, wherein: - The SiC substrate (20) is a 3C-SiC substrate, a 4H-SiC substrate or a 6H-SiC substrate.

15. The SiC semiconductor element (10) according to any one of claims 7 to 14, wherein: The SiC substrate (20) is n-doped or p-doped and has a doping concentration of at least 1e18 cm -3 ,and The SiC epitaxial layer (30) is n-type doped or p-type doped in the same manner as the SiC substrate (30) and has a doping concentration of 1e14-1e16 cm -3 within the range.

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