Package including direct bonded metal substrate and cooling jacket, methods of forming package and direct bonded metal substrate

Abstract

A package includes a semiconductor die (15) disposed on a three-layer substrate (100). The three-layer substrate includes a ceramic layer (100-2) disposed between a top metal layer (100-2) and a bottom metal layer (10-3). The semiconductor die is disposed on the top metal layer. An array of mesas (10, 12) is defined in the bottom metal layer, grooves (11) between the mesas forming a path (P) for a cooling fluid to flow through a surface of the bottom metal layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application is a continuation of and claims priority to U.S. patent application No. 18 / 324,362 filed on May 26, 2023, the entire text of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to cooling systems for power electronics assemblies. Background Art

[0004] In many applications (e.g., in electric drive vehicles), effective thermal management of power electronics components, modules, or packages is required to increase power density and improve reliability. For example, electric vehicles and hybrid electric vehicles utilize high voltage battery packs or fuel cells that deliver high power DC current to drive vehicle motors, electric traction systems, and other vehicle systems. Among other things, these vehicles may include power electronics components (e.g., inverters) to convert DC current provided by, for example, the battery pack into AC current for use by the vehicle's electric motor and other electrical devices and systems. Power electronics components may include heat-generating semiconductor devices, such as insulated gate bipolar transistors (IGBTs) and fast recovery diodes (FRDs). The compact packaging of power electronics components creates thermal management challenges that need to be addressed for power-intensive systems. Summary of the invention

[0005] In a general aspect, a package includes a semiconductor die disposed on a three-layer substrate. The three-layer substrate includes a ceramic layer disposed between a top metal layer and a bottom metal layer. The semiconductor die is disposed on the top metal layer. An array of mesas is defined in the bottom metal layer, and grooves between the mesas form paths for a cooling fluid to flow through a surface of the bottom metal layer.

[0006] In a general aspect, a method includes forming a set of mesas in a bottom metal layer of a three-layer direct bond metal (DBM) substrate to increase the surface area of ​​the bottom metal layer. The method also includes placing a semiconductor die on the top metal layer of the three-layer DBM substrate and exposing the bottom metal layer of the three-layer DBM substrate through the bottom of a molded body encapsulating the semiconductor die.

[0007] In a general aspect, a direct bond metal (DBM) substrate includes a ceramic sheet, a top metal layer bonded to one side of the ceramic sheet, and a bottom metal layer bonded to an opposite side of the ceramic sheet. The bottom metal layer includes a set of mesas in a surface.

[0008] In one aspect, the bottom metal layer of the DBM substrate includes a mesa array having a plurality of mesas arranged in a row in the bottom metal layer. The mesas in the row have a length and a width in cross section and a top surface with a height of h. The DBM substrate also includes a corrugated conductive strip including a coupling portion and a bridging portion attached to the top surface of the mesas in the row. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A cross-sectional view of a three-layer substrate having a bottom layer including a mesa is schematically shown in accordance with the principles of the present disclosure.

[0010] Figure 2 A cross-sectional view of an example semiconductor device package according to the principles of the present disclosure is schematically shown, wherein a semiconductor die is disposed on Figure 1 on a three-layer substrate.

[0011] Figure 3 Schematically shows the attachment to Figure 2 A cooling jacket is provided on the bottom of a molded body of a semiconductor device package.

[0012] Figure 4 , Figure 5A , Figure 5B , Fig. 6A and Figure 6B Views of an example doubly bonded metal (DBM) substrate at different stages of construction are shown having a surface layer of mesas on the DBM substrate.

[0013] Figure 7 Shown in Fig. 6A and Figure 6B A backside plan view of an example semiconductor device package fabricated on a substrate of FIG.

[0014] Figure 8 Example methods for dissipating heat generated by a semiconductor die in a semiconductor device package are shown.

[0015] In the drawings that are not necessarily drawn to scale, similar reference symbols and / or alphanumeric identifiers may indicate similar and / or similar parts (elements, structures, etc.) in different views. The drawings illustrate various specific implementations discussed in the present disclosure by way of example and not limitation. Reference symbols and / or alphanumeric identifiers shown in one drawing may not be repeated for the same and / or similar elements in the related views in other drawings. Reference symbols and / or alphanumeric identifiers repeated in multiple figures may not be specifically discussed with respect to each of the figures in these figures, but are provided for the convenience of cross-references between related views. In addition, not all similar elements in the drawings are specifically referenced with reference symbols and / or alphanumeric identifiers when multiple instances of the element are shown. DETAILED DESCRIPTION

[0016] The present disclosure relates to a thermal management system for a power electronic device module. A power electronic device module (or subpackage) may, for example, include power electronic devices (e.g., silicon-controlled rectifiers (SCRs), insulated gate bipolar transistors (IGBTs), field effect transistors (FETs), etc.) to provide AC power to a load. The power electronic devices may be silicon-based or based on wide bandgap (WBG) semiconductors. The power electronic devices may generate heat, which may be removed in order to maintain the device at an acceptable operating temperature. For high power density applications (e.g., power density equal to or greater than 240kW), the requirements for efficient heat removal may be stringent. Specific implementations described herein may facilitate efficient heat removal.

[0017] In an example implementation, a power electronics module may include at least a semiconductor die (e.g., an IGBT and / or an FRD). The semiconductor die may be mounted on a top surface (e.g., an outer surface) of a substrate (e.g., a printed circuit board, a direct bond metal (DBM) substrate, a direct bond copper (DBC) substrate, etc.). One or more semiconductor dies may be packaged (e.g., encapsulated in a molding compound), for example, as a single-sided direct cooling (SSDC) power electronics module, with signal pins and power terminals extending from the module. The power electronics module may have a width and height along the surface of the substrate, and a thickness perpendicular (substantially perpendicular) to the substrate (in the direction of the semiconductor die mounted on the top surface of the substrate). In an example implementation, for an IGBT power electronics module, the height and width may be measured in centimeters, while the thickness may be in the range of a few millimeters or less.

[0018] In an SSDC package, heat generated by one or more semiconductor dies flows vertically through the substrate to be dissipated from the bottom surface of the substrate. In some cases, a heat sink (e.g., a base plate or a base plate with fins) may be attached to the bottom surface of the substrate to help disperse the heat generated in the power electronics module. The base plate with fins may include pin fins (i.e., fins shaped like pins). The power electronics module may be further configured with forced air and liquid cooling options to remove the heat generated in the power electronics module.

[0019] In an example implementation, the semiconductor die may be mounted on a three-layer substrate (e.g., a direct bond metal (DBM) substrate). The DBM substrate may include a thermally conductive but electrically insulating layer (e.g., a ceramic sheet or plate) sandwiched between a top layer and a bottom layer. The top layer and the bottom layer may be made of a metal or a metal alloy. The semiconductor die may be mounted on the top metal layer of the substrate. The bottom metal layer of the substrate may also be the bottom surface of the molded body of the package and exposed to the outside of the molded body of the package for heat dissipation. Heat dissipation through the exposed bottom surface may be achieved by radiation and / or by heat transfer to a cooling fluid (e.g., air, water, a water glycol mixture, etc.), which may be in contact with the exposed bottom surface. In an example implementation, a cooling jacket may be attached to the package or included in the package so that the cooling fluid flows through the exposed bottom surface. The cooling fluid may carry heat away from the exposed bottom surface. Under various heat transfer mechanisms (e.g., conduction or convection through a cooling fluid), the amount and rate of heat transfer from the exposed bottom surface can be proportional to the surface area of ​​the bottom surface that contacts the cooling fluid. A larger surface area of ​​the exposed bottom surface can result in greater heat transfer than heat transferred from a smaller surface area.

[0020] In accordance with principles of the present disclosure, in an example implementation, a surface of a substrate (eg, bottom metal layer) has mesas (eg, fins) to increase the surface area available for heat transfer from a semiconductor die mounted on the front side of the substrate.

[0021] In an example implementation, a mesa on a surface of a substrate (eg, a bottom metal layer) may include parallel grooves and mesas (eg, protrusions, fins) disposed on the surface (when viewed from above). The parallel grooves may be disposed between or defined between the mesas.

[0022] In some example implementations, a set of parallel grooves extending in one direction (e.g., the x-direction) on a surface may intersect with another set of parallel grooves extending in another direction (e.g., the y-direction). The ridges formed between the sets of parallel grooves may be arranged or patterned into an array of mesas. The mesas may, for example, have a square, rectangular, trapezoidal, or other shaped cross-section (when viewed from above) and a vertical height h (in the z-direction).

[0023] In an example implementation, a mesa on a surface of the substrate (eg, a bottom metal layer) may also include a conductive strip bonded to the surface (top surface of the mesa).

[0024] The conductive strip may have a corrugated shape, including portions that are connecting portions (e.g., flat portions) and bridging portions (e.g., curved portions), which together define a wave shape, for example. The conductive strip may be bonded to the top of a ridge (mesa) formed on the surface. In an example implementation, the corrugation of the conductive strip may include alternating grooves and ridges (when viewed from the side). In some implementations, the corrugation of the conductive strip may include a series of concave portions, a series of convex portions, or a series of alternating concave portions and convex portions.

[0025] Figure 1 A cross-sectional view of a three-layer substrate 100 having a bottom layer including mesas is shown in accordance with the principles of the present disclosure.

[0026] A three-layer substrate 100 (e.g., a DBM substrate) may, for example, include a thermally conductive but electrically insulating ceramic plate or sheet (e.g., layer 100-2) disposed between a top metal layer (e.g., layer 100-1) and a bottom metal layer (e.g., layer 100-3). The top metal layer (e.g., layer 100-1) may have a flat surface S1 and include one or more die attach pads (not shown) on which a semiconductor die may be mounted. In an example implementation, layer 100-3 includes a set of mesas 10. In an example implementation, a set of mesas 10 may be formed by parallel grooves (grooves 11) and protrusions or mesas (e.g., mesas 12) formed in a bottom surface (surface S) of layer 100-3. The parallel grooves and ridges may, for example, alternate in the x-direction. In an example implementation, a set of parallel grooves extending in one direction (e.g., the x-direction) on surface S may alternate with protrusions or ridges extending in another direction (e.g., the y-direction) on surface S. Figure 5A ) and another set of parallel grooves extending on the top of the groove. The mesas 12 (e.g., protrusions) formed between each set of intersecting parallel grooves can form a mesa pattern or a mesa array. The mesas 12 can, for example, have a cross-section (in the xy plane) of a square, rectangular, trapezoidal, or other shape. In addition, the mesas 12 can, for example, have a vertical height h (in the z direction). The mesas with height h can have a top surface T (also referred to as an outer surface).

[0027] In addition, the conductive strip 13 is bonded to the top surface T of the table (e.g., table 12). The conductive strip 13 can be, for example, a corrugated strip including a connecting portion (e.g., connecting portion 13a) and a bridging portion (e.g., bridging portion 13b). The connecting portion (e.g., connecting portion 13a) can be aligned with and bonded to the top surface T of the table (e.g., table 12). The bridging portion 13b can have a curved or wavy shape (e.g., a semi-cylindrical shape) extending over the groove 11 between adjacent connecting portions 13a. In some specific implementations, the connecting portion 13a can have a flat shape in some specific implementations. In some specific implementations, the connecting portion 13a can have a flat surface (e.g., a flat bottom surface B) so that they can be connected to the top surface T of the flat table 12.

[0028] In this implementation, the bridge portion 13b has a convex shape that protrudes in a direction away from the shape (or bottom surface) of the groove 11. In other words, the bridge portion 13b has a convex shape that protrudes in the same direction as the mesa 12 (e.g., protrudes away from the mesa). This makes the cavity defined by the groove 11 and the bridge portion 13b larger than when the conductive strip 13 is flat. Although not shown, in some implementations, the bridge portion 13b may not have a convex shape that protrudes in a direction away from the shape of the groove 11.

[0029] A layer 100 - 3 including a set of mesas 10 may provide a larger surface area for a cooling fluid flowing through the layer 100 - 3 than a flat planar layer (eg, a layer 100 - 3 without a set of mesas 10 ).

[0030] Figure 2 A cross-sectional view of an example semiconductor device package 200 is shown in accordance with the principles of the present disclosure, wherein a semiconductor die is disposed in Figure 1 On a three-layer substrate 100.

[0031] In the example semiconductor device package 200, layer 100-3 (including a set of mesas 10) provides a heat dissipation path for heat generated by the semiconductor die in the package. Figure 2 As shown in (e.g., semiconductor device package 200), a semiconductor die (e.g., semiconductor die 15) may be disposed on a top metal layer (e.g., layer 100-1) of a three-layer substrate 100. The semiconductor die may, for example, include an insulated gate bipolar transistor (IGBT), a fast recovery diode FRD, a silicon carbide power transistor, or any other type of device. The various dies 15 may be interconnected to each other, for example, by wire bonds 16 (e.g., aluminum wire bonds). Wire bonds 16 may also connect leads (e.g., leads 12, leads 13, leads 14) to the semiconductor die. The leads (e.g., lead 14) may be directly connected to layer 100-1 on which the semiconductor die is mounted.

[0032] In the example semiconductor device package 200, a semiconductor die (e.g., semiconductor die 15) and a portion of a substrate (e.g., three-layer substrate 100) may be encapsulated in a molded body 21. Leads (e.g., leads 11, 12, 13, and 14) may extend outside the molded body and form external terminals of the package. The bottom metal layer of the substrate (e.g., layer 100-3) may also be the bottom surface of the molded body of the package and may be exposed to the outside of the molded body of the package for heat dissipation.

[0033] In an example implementation, a cooling fluid jacket may be attached to the bottom of the molded body of the package to direct a cooling fluid (e.g., water, a water-ethylene glycol mixture, etc.) through the set of mesas 10 of the bottom metal layer (e.g., layer 100-3) of the three-layer substrate 100.

[0034] For example, Figure 3 A cooling jacket 300 is shown attached to the bottom of the molded body of the semiconductor device package 200. The cooling jacket 300 may include an input port (port 302) through which a cooling fluid may enter the cooling jacket and flow through the surface of the set of mesas 10 to absorb heat. The cooling jacket 300 may also include an output port (port 304) through which the cooling fluid may exit the cooling jacket after flowing through the surface of the set of mesas 10.

[0035] A cooling fluid flow (e.g., water, a water-glycol mixture, etc.) may enter the jacket through an input port, pass over or through a deck (e.g., a set of deck groups 10) on the power electronic module placed along the cooling fluid channels in the jacket to remove heat generated by the power electronic module, and exit the jacket through an output port. The flow of cooling fluid may be driven by a recirculation pump (not shown).

[0036] Figures 4 to 6B Shown are views of a double bonded metal (DBM) substrate (eg, tri-layer substrate 100) at different stages of constructing a set of mesas in a surface layer on the DBM substrate.

[0037] Figure 4A starting DMB substrate (e.g., three-layer substrate 100) at a first construction stage is shown, before a set of mesas are formed. The DMB substrate may include a top metal layer (e.g., layer 100-1) and a bottom metal layer (e.g., layer 100-3) bonded to the top and bottom sides of a thermally conductive electrically insulating layer (e.g., layer 100-2), respectively. Layer 100-2 may be made of a thermally conductive ceramic or epoxy material. The top metal layer (e.g., layer 100-1) and the bottom metal layer (e.g., layer 100-3) may be made of a metal or metal alloy (e.g., copper). In an example implementation, the top metal layer (e.g., layer 100-1) and the bottom metal layer (e.g., layer 100-3) may be electroplated copper layers.

[0038] Layer 100-1, layer 100-2, and layer 100-3 may have thicknesses T1, T2, and T3, respectively. In an example implementation, to fabricate a set of mesas (e.g., a set of mesas 10) configured as a cooling mechanism in a device package (e.g., semiconductor device package 200), the thickness T3 of layer 100-3 in the starting three-layer substrate 100 may be at least 1 mm.

[0039] Figure 5A shows a cross-sectional view of the three-layer substrate 100 after a second construction stage, and Figure 5B A plan view thereof is shown.

[0040] In a second structuring stage, the surface S of layer 100 - 3 is photolithographically patterned and a set of grooves (eg, grooves 11 ) are etched into layer 100 - 3 to form a pattern of mesas (pillars) (eg, pattern 50 of mesas 12 ).

[0041] like Figure 5A As shown in , a groove (eg, groove 11) may have a depth d (in the z direction) (in other words, the terrace may have a corresponding height h=h, Figure 2 ). The mesa may have a top surface (e.g., surface T) that may be, for example, the same as the original surface S of layer 100-3. In an example implementation, the depth d of the groove to which surface S of layer 100-3 is etched may be at least about half of the thickness T3 of layer 100-3 in starting three-layer substrate 100. For example, when the thickness T3 of layer 100-3 in starting three-layer substrate 100 is at least 1 mm, the depth d of the groove may be at least about 0.5 mm (in other words, the mesa may have a corresponding height h of at least about 0.5 mm).

[0042] In an example implementation, Figure 5BAs shown in , a table (e.g., table 12) may have a cross-section having a width W (in the x-direction) and a length L (in the y-direction). In an example implementation, the width W may be in the range of 2.0 mm to 4.0 mm (e.g., about 1.3 mm), and the length L may be in the range of 2.0 mm to 4.0 mm (e.g., about 2.5 mm).

[0043] A pattern of mesas (e.g., pattern 50) may include several mesas (e.g., mesas 12) arranged in rows (e.g., rows R1, R2, R3, R4) (e.g., extending in the x-direction) and columns (e.g., columns C1, C2, etc.) (e.g., extending in the y-direction).

[0044] Mesas in adjacent rows (eg, rows R1 and R2 ) may be separated by an inter-row distance (eg, distance IR ) (eg, the distance between columns R1 and R2 ).

[0045] Furthermore, adjacent mesas in a particular row (e.g., row R1) may be separated by an inter-column distance (e.g., distance IC) (e.g., the distance between columns C1 and C2). The mesas 12 in a particular row (e.g., row R1) may be arranged in a linear array with a pitch equal to the sum of the mesa width W and the inter-column distance IC.

[0046] The row spacing (e.g., distance IR) and column spacing (e.g., distance IC) may correspond to the width of the groove (groove 11) defining the mesa. In an example implementation, the row spacing (e.g., distance IR) may be, for example, between 1.0 mm and 3.0 mm (e.g., about 1.2 mm), and the column spacing (e.g., distance IC) may be, for example, between 1.0 mm and 3.0 mm (e.g., about 1.2 mm).

[0047] The grooves (e.g., grooves 11) that define the mesas (e.g., mesas 12) in pattern 50 can create a path P (e.g., a serpentine path, a zigzag path) for the cooling fluid to flow along the sides of the mesas in pattern 50. In an example implementation, the mesas in a row (e.g., row R1) can be offset by an offset distance (e.g., distance OD) (e.g., in the x-direction) relative to corresponding mesas in the next row (e.g., row R2). In an example implementation, the offset distance (e.g., distance OD) is, for example, between 1.0 mm and 3.0 mm (e.g., about 1.3 mm). Figure 5B As shown in , such offsetting of the mesas in one row from the mesas in the next row can result in a zigzag path (eg, path P) around the sides of the mesas for the cooling fluid to flow through the pattern 50 .

[0048] Fig. 6A shows a cross-sectional view of the three-layer substrate 100 after the third construction stage, and Figure 6B Its plan view is shown. Figure 6B It is a plan view, so the bridging portion (eg, bridging portion 13b) and the coupling portion (eg, coupling portion 13b) may not be easily seen, but are identified with labels.

[0049] In the third construction stage, a conductive strip (e.g., conductive strip 13) is bonded to the top surface of the mesas formed in a row (e.g., row R1, R2, R3, or R4) in layer 100-3. A separate conductive strip 13 may be used for each row. The separate conductive strips may have a length L (in the y direction, 1 / 2) equal to the length of the mesa. Figure 5B ) have the same or approximately the same width. In an example implementation, the conductive strip may be a strip made of aluminum. Fig. 6A As shown in , the conductive strip 13 may include a connecting portion (e.g., a connecting portion 13a) and a bridging portion (e.g., a bridging portion 13b). The connecting portion (e.g., the connecting portion 13a) may be aligned with and bonded to a top surface T of a mesa (e.g., mesa 12) in a row (e.g., row R1, R2, R3, or R4). The bridging portion 13b of the conductive strip 13 between two connecting portions (e.g., the connecting portions 13a) may extend over the groove 11 and form a bridge between the paired mesas. The bridging portion 13b may have a wavy shape (e.g., a semi-cylindrical shape) extending over the groove 11 between adjacent connecting portions 13a. As shown in Fig. 6A As shown in , the thickness TR of the conductive strip 13 may be in the range of about 0.1 mm to 0.4 mm (e.g., 0.2 mm). The bridge portion 13b of the attached conductive strip (e.g., conductive strip 13) may produce a set of mesas 10 whose mesa height CH (in the y direction) is greater than the height h of the mesa 12. In an example implementation, the mesa height CH may be at least 1.0 mm.

[0050] In addition, if Fig. 6A and Figure 6B As shown in FIG. 1 , for each pair of mesas 12 bridged by a conductive strip 13, the conductive strip 13 may have a width WR. In an example implementation, the width WR may be the same as the width of a row (e.g., Figure 5B The spacing of the mesas in row R1 of φ1 is the same (eg, about 1C+W). In an example implementation, the conductive strip width WR (for each bridged pair of mesas) may be at least 2.0 mm.

[0051] After forming a group of mesas 10 on the three-layer substrate 100, the substrate can be used to manufacture a semiconductor device package (eg, semiconductor device package 200, Figure 2In the semiconductor device package, the semiconductor die (e.g., semiconductor die 15) may be disposed on layer 100-1 of the three-layer substrate 100, interconnected using wire bonds, and connected to leads (e.g., leads 11, 12, 13, and 14) before the package is in the molded body 21 (e.g., as shown in FIG. Figure 2 ).

[0052] Figure 7 Shown in Fig. 6A and Figure 6B A backside plan view of a semiconductor device package 700 manufactured on a three-layer substrate 100 (under a cooling jacket (eg, cooling jacket 300 ( Figure 3 )) before being attached to the semiconductor device package 700). The semiconductor device package 700 may include a semiconductor die (eg, semiconductor die 15) disposed on the front side (top side) of the three-layer substrate 100 (at Figure 7 700 ). The semiconductor die may be encapsulated in the molded body 21, and external input / output signal leads (e.g., leads 710) connected to the semiconductor die may extend outside the molded body 21. The molded body 21 may be attached to a connector header (e.g., connector header 720), which may be used, for example, to mount the semiconductor device package 700 in a chassis or frame (e.g., of an automotive application).

[0053] In an example implementation, Figure 7 As shown in FIG. 1 , the bottom layer (ie, layer 100 - 3 ) of the three-layer substrate 100 is exposed through the bottom of the molded body 21 . Figure 7 Elements of a group of mesas 10 in layer 100-3 (e.g., conductive strips 13 and mesas 12) are shown, which can be exposed to a cooling fluid (air, water, water-glycol mixture, etc.) to remove heat generated by the semiconductor die in semiconductor device package 700. A cooling jacket can be attached to semiconductor device package 700 to flow a cooling fluid through the group of mesas 10. For visual clarity, the cooling jacket is not shown in FIG. Figure 7 Shown in.

[0054] Figure 8 An example method 800 for dissipating heat generated by a semiconductor die in a semiconductor device package is shown. The semiconductor die may be disposed on a three-layer direct bond metal (DBM) substrate and encapsulated in a molded body.

[0055] The method 800 includes forming a set of mesas in a bottom metal layer of a three-layer direct bond metal (DBM) substrate to increase a surface area of ​​the bottom metal layer (810). A semiconductor die may be disposed on a front side of the DBM substrate and encapsulated in a molding body.

[0056] The method 800 also includes exposing a bottom metal layer of the DBM substrate through a bottom of a molded body encapsulating the semiconductor die (820), and flowing a cooling fluid through the bottom metal layer to transfer heat generated by the semiconductor die to the cooling fluid (830).

[0057] In an example implementation, the bottom metal layer of the three-layer DBM substrate can be a copper layer (e.g., an electroplated copper layer at least 1.0 mm thick). Forming a set of mesas (810) in the bottom metal layer of the three-layer direct bond metal (DBM) substrate can include forming an array of mesas (pillars) in the bottom metal layer.

[0058] Forming the mesa may include etching a first set of parallel grooves in the bottom metal layer and etching a second set of parallel grooves that intersect the first set of grooves. The mesa (e.g., mesa 12) may have a rectangular cross-section (having a width W and a length L) and a top surface with a height h. The grooves may form channels in the bottom metal layer for allowing fluid to flow along and contact the sides of the mesa.

[0059] In an example implementation, the mesa array may include mesas (e.g., mesas 12) arranged in rows and columns on the bottom metal layer. Mesas in adjacent rows (e.g., rows R1 and R2) may be separated by a row spacing (e.g., distance IR). In addition, adjacent mesas in a particular row may be separated by a column spacing (e.g., distance IC).

[0060] In an example implementation, the row pitch (eg, distance IR) may be, for example, between 1.0 mm and 3.0 mm (eg, approximately 1.2 mm), and the column pitch (eg, distance IC) may be, for example, between 1.0 mm and 3.0 mm (eg, approximately 1.2 mm).

[0061] The grooves (e.g., grooves 11) defining the mesas (e.g., mesas 12) can create paths P for cooling fluid to flow along the sides of the mesas in the array of mesas. In an example implementation, the mesas in a row (e.g., row R1 in the x-direction) can be offset by an offset distance (e.g., distance OD) (e.g., in the x-direction) relative to corresponding mesas in the next row (e.g., row R2). In an example implementation, the offset distance (e.g., distance OD) is, for example, between 1.0 mm and 3.0 mm (e.g., about 1.3 mm). This offset of the mesas in one row and the next row can allow (e.g., Figure 5B ) to produce a zigzag path (e.g., path P) for cooling fluid to flow along and around the sides of mesas in the array of mesas. Forming a set of mesas (810) in a bottom metal layer of a three-layer direct bond metal (DBM) substrate may include forming a zigzag path around the sides of the mesas for cooling fluid to flow.

[0062] Forming a set of mesas (810) in the bottom metal layer of the three-layer direct bond metal (DBM) substrate may also include attaching a strip to the top surface of the mesas in the row. The strip may be, for example, a conductive strip (e.g., conductive strip 13). For example, the strip may have a length L (in the y direction, 100) equal to the length of the mesas in the row. Figure 5B ) (in other words, the strip width is the same or approximately the same as the length of the mesa perpendicular to the row direction). The conductive strip can be, for example, a corrugated strip including a connecting portion (e.g., connecting portion 13a) and a bridging portion (e.g., bridging portion 13b). Adhering the strip to the top surface of the mesa in a row can include aligning the connecting portion of the strip with the top surface T of the mesa (e.g., mesa 12) and bonding to the top surface. The bridging portion 13b between adjacent connecting portions 13a can have a wavy shape (e.g., a semi-cylindrical shape) extending over the groove between adjacent mesas in the row.

[0063] Exposing the bottom metal layer (820) of the DBM substrate through the bottom of the molded body encapsulating the semiconductor die may also include attaching a cooling jacket to the bottom of the molded body to enclose the bottom metal layer. In addition, flowing a cooling fluid through the bottom metal layer may include flowing a cooling fluid in the cooling jacket through a path along and around the sides of the mesas in the array of mesas in the bottom metal layer. Flowing the cooling fluid through the bottom metal layer may also include flowing the cooling fluid over and under conductive strips attached to the top surfaces of the mesas in the row.

[0064] In an example implementation, a method for heat removal may include flowing a cooling fluid through a cooling jacket to pass through paths along and around sides of mesas in an array of mesas in a bottom metal layer.

[0065] In an example implementation, the conductive strips (eg, metal strips) may be made of a metal or a metal alloy (eg, copper, aluminum, or an alloy).

[0066] Various specific implementations described herein are given only by way of example and are only for the purpose of illustration.It should also be understood that for the purpose of this disclosure, when an element such as a layer, a zone, a part or a substrate is mentioned on another element, mechanically connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected to another element, or coupled to another element, or one or more intermediate elements may be present.On the contrary, when an element is mentioned directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there is no intermediate element or layer.Although the term may not be used in the entire specific embodiment directly on ..., directly connected to ... or directly connected to ... but the element shown as being directly located on the element, directly connected or directly connected can be mentioned in this manner.The claims of the present application may be revised to narrate the exemplary relationship described in the specification and / or shown in the accompanying drawings.

[0067] As used in this specification, unless the context indicates otherwise, the singular may include the plural. In addition to the orientations shown in the drawings, spatially relative terms (e.g., above, above, above, below, below, below, below, etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent may include lateral adjacent or horizontal adjacent.

[0068] Some implementations may be implemented using various semiconductor processing and / or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.

[0069] Although certain features of the described embodiments have been described as described herein, those skilled in the art will now appreciate that many modifications, alternatives, variations, and equivalents are contemplated. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A package, comprising: A three-layer substrate (100), comprising a ceramic layer (100-2) disposed between a top metal layer (100-1) and a bottom metal layer (100-3); an array of mesas (10, 12) defined in the bottom metal layer, grooves (11) between the mesas forming paths (P) for fluid to flow through the surface of the bottom metal layer; as well as A semiconductor die (15) is disposed on the top metal layer.

2. The package according to claim 1, wherein: The mesas in the mesa array have a rectangular or square cross-section with a width ranging from 2.0 mm to 4.0 mm and a length ranging from 2.0 mm to 4.0 mm.

3. The package according to claim 1, wherein: The mesas in the array of mesas have top surfaces with a height of at least about 0.5 mm.

4. The package according to claim 1, further comprising: A molding body encapsulates the semiconductor die disposed on the top metal layer and encapsulates a portion of the three-layer substrate.

5. The package according to claim 4, wherein: The bottom metal layer is exposed through the bottom of the molded body.

6. The package according to claim 4, wherein: A cooling jacket is attached to the molded body over the bottom metal layer, the cooling jacket having an input port and an output port, the input port being configured to receive a cooling fluid to flow the cooling fluid through the bottom metal layer.

7. The package according to claim 1, wherein: The array of mesas disposed in the bottom metal layer includes mesas arranged in rows across the bottom metal layer, and the package further includes a ribbon attached to top surfaces of the mesas arranged in rows.

8. The package according to claim 7, wherein: The strips are electrically conductive strips with a thickness ranging from 0.1 mm to 0.4 mm.

9. The package according to claim 7, wherein: The strip is a corrugated strip comprising a coupling portion and a bridging portion.

10. The package according to claim 9, wherein: The coupling portion is aligned with and bonded to top surfaces of the mesas arranged in a row, and the bridging portion extends over the grooves between adjacent mesas arranged in a row.

11. A method comprising: forming a set of mesas in a bottom metal layer of a three-layer direct bond metal (DBM) substrate to increase a surface area of ​​the bottom metal layer (810); Disposing a semiconductor die on the top metal layer of the three-layer DBM substrate (820); as well as The bottom metal layer of the three-layer DBM substrate is exposed through a bottom of a molding body encapsulating the semiconductor die.

12. The method according to claim 11, wherein: The bottom metal layer of the three-layer DBM substrate is a copper layer having a thickness of at least 1.0 mm.

13. The method according to claim 11, wherein: Forming a set of mesas in the bottom metal layer of the three-layer DBM substrate includes forming an array of mesas in the bottom metal layer.

14. The method according to claim 13, wherein: Forming an array of mesas in the bottom metal layer includes etching a first set of parallel grooves in the bottom metal layer and etching a second set of parallel grooves intersecting the first set of parallel grooves.

15. The method according to claim 14, wherein: The etching includes defining paths for cooling fluid to flow through grooves along sides of mesas in the array of mesas.

16. The method according to claim 15, wherein: The mesa array includes mesas arranged in rows, and the mesas in one row are offset by an offset distance relative to corresponding mesas in a next row, and wherein the etching includes defining a serpentine path for cooling fluid to flow through grooves along and around sides of the mesas in the mesa array.

17. The method according to claim 15, wherein: The mesa array includes mesas arranged in rows, and wherein forming a group of mesas in the bottom metal layer of the three-layer DBM substrate includes attaching a ribbon to a top surface of the mesas arranged in rows.

18. The method according to claim 17, wherein: The strips are made of metal and have a width in a direction perpendicular to the direction of the rows that is the same as or approximately the same as the length of the mesas.

19. The method according to claim 17, wherein: The strip is a corrugated strip including a coupling portion and a bridging portion, and wherein attaching the strip to the top surfaces of the countertops arranged in a row includes aligning and bonding the coupling portion of the strip to the top surfaces of the countertops while the bridging portion extends over the grooves between adjacent countertops in the row.

20. The method according to claim 19, wherein: Attaching the strip to the top surfaces of the countertops arranged in a row further includes extending the bridging portion over the grooves between adjacent countertops in the row.

21. The method according to claim 15, wherein: Exposing the bottom metal layer of the three-layer DBM substrate through the bottom of the molded body further includes attaching a cooling jacket to the bottom of the molded body to enclose the bottom metal layer.

22. A direct bonded metal (DBM) substrate, comprising: Ceramic sheet (100-2); A top metal layer (100-1), the top metal layer being bonded to one side of the ceramic sheet; as well as A bottom metal layer (100-3) is bonded to an opposite side of the ceramic sheet, the bottom metal layer having a set of mesas in a surface.

23. The direct bonded metal (DBM) substrate according to claim 22, wherein: The bottom metal layer comprises: a mesa array having a plurality of mesas arranged in a row in the bottom metal layer, the mesas in the row having a length and a width in cross-section and having a top surface with a height h; and A corrugated conductive strip includes a coupling portion and a bridging portion attached to the top surfaces of the mesas in the row.

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