Power divider circuit for load modulation amplifier

Abstract

Embodiments of an amplifier circuit are disclosed. In some embodiments, the amplifier circuit includes a first driver circuit and a second driver circuit. The first driver circuit is connected between the input splitter circuit and the power divider circuit, the first driver circuit having a first bias point. The second driver circuit is connected between the input splitter circuit and the power divider circuit. The second driver circuit has a second bias point different from the first bias point. Further, a carrier amplifier circuit and a peaking amplifier circuit are connected to the power divider circuit.

Description

[0001] Related Applications

[0002] This application claims the benefit of provisional patent application serial number 63 / 435,544, filed on December 27, 2022, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to amplifiers and, more particularly, to power divider circuits for load modulated amplifiers. Background Art

[0004] Doherty amplifiers are popular because of their high efficiency at average output power as well as at maximum output power. Doherty amplifiers generally consist of a main amplifier (also called a carrier amplifier) ​​and an auxiliary amplifier (also called a peaking amplifier). The main amplifier and the auxiliary amplifier are biased differently so that the main amplifier always provides amplification of the radio frequency (RF) signal, while the auxiliary amplifier provides amplification only when the RF signal reaches a certain power level.

[0005] However, Doherty amplifiers can suffer from several problems. One of these problems is that when the Doherty amplifier is driven into compression, a gain imbalance occurs between the main amplifier and the auxiliary amplifier. This imbalance causes the main amplifier to be overdriven compared to the auxiliary amplifier at peak power. Over-compressing the main amplifier produces more harmonic content, which in turn results in greater intermodulation distortion and poor linearity. Summary of the invention

[0006] Embodiments described herein provide amplifier circuits that are operable to allocate power to a carrier amplifier circuit and a peaking amplifier circuit based on input power in a Doherty amplifier. Although embodiments are described in conjunction with a Doherty amplifier, other embodiments are not limited to this implementation. The present disclosure may be applied to other amplifiers, such as load modulated balanced amplifiers. In some cases, the power allocated to the carrier amplifier circuit is limited at higher power levels entering three (3) decibel (dB) compression, and the power allocated to the peaking amplifier circuit is increased at higher power levels. In a non-limiting, non-exclusive example, the power allocated to the carrier amplifier circuit is limited at higher power levels entering three (3) decibel (dB) compression, and the power allocated to the peaking amplifier circuit is increased at higher power levels when it reaches saturation.

[0007] In some embodiments, an amplifier circuit includes: a first driver circuit connected between an input splitter circuit and a power divider circuit, the first driver circuit having a first bias point; a second driver circuit connected between the input splitter circuit and the power divider circuit, the second driver circuit having a second bias point different from the first bias point; and a carrier amplifier circuit and a peaking amplifier circuit connected to the power divider circuit. In some embodiments, the first driver circuit is a class AB amplifier circuit; and the second driver circuit is a class C amplifier circuit. In some embodiments, the amplifier circuit is a Doherty amplifier circuit. In some embodiments, the amplifier circuit further includes the input splitter; and the power divider circuit. In some embodiments, the amplifier circuit further includes an amplifier connected to a first input terminal of the input splitter. In some embodiments, the amplifier circuit further includes a terminal impedance connected to a second input terminal of the input splitter. In some embodiments, the first driver circuit is connected to a first output terminal of the input splitter; and the second driver circuit is connected to a second output terminal of the input splitter. In some embodiments, the peaking amplifier circuit contributes power and changes the load state so that the peaking carrier amplifier circuit is load modulated from an effective match to a power match. In some embodiments, the amplifier circuit further includes a first phase shifter connected between the input splitter and the first driver circuit; a second phase shifter connected between the input splitter and the second driver circuit. In some embodiments, the amplifier circuit further includes a first balanced power amplifier (BPA) circuit connected to the power divider circuit. In some embodiments, the amplifier circuit further includes a second BPA circuit connected to the power divider circuit. In some embodiments, the amplifier circuit further includes a coupler circuit connected to the first BPA circuit and the second BPA circuit.

[0008] In some embodiments, an amplifier circuit includes: an input splitter circuit connected to a first phase shifter circuit and a second phase shifter circuit; a first driver circuit connected between the first phase shifter circuit and a power divider circuit, the first driver circuit having a first bias point; a second driver circuit connected between the second phase shifter circuit and the power divider circuit, the second driver circuit having a second bias point different from the first bias point; and a carrier amplifier circuit and a peaking amplifier circuit connected to the power divider circuit. In some embodiments, the first driver circuit is a class AB amplifier circuit; and the second driver circuit is a class C amplifier circuit. In some embodiments, the amplifier circuit is a Doherty amplifier circuit. In some embodiments, the amplifier circuit further includes the power divider circuit. In some embodiments, the amplifier circuit further includes an amplifier connected to a first input terminal of the input splitter. In some embodiments, the amplifier circuit further includes a terminal impedance connected to a second input terminal of the input splitter.

[0009] In some embodiments, an amplifier circuit includes: an input splitter circuit connected to a first driver circuit and a second driver circuit, the first driver circuit having a first bias point and the second driver circuit having a second bias point different from the first bias point; a power divider circuit connected to the first driver circuit and the second driver circuit; a first balanced power amplifier (BPA) circuit connected to the power divider circuit; a second BPA circuit connected to the power divider circuit; and a coupler circuit connected to the first circuit and the second BPA circuit. In some embodiments, the first driver circuit is a class AB amplifier circuit; and the second driver circuit is a class C amplifier circuit.

[0010] Those skilled in the art will appreciate the scope of the present disclosure and become aware of additional aspects thereof after reading the following detailed description of the preferred embodiments and the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] Figure 1 A block diagram showing a first amplifier circuit according to an embodiment of the present disclosure;

[0013] Figures 2A to 2C The present invention is shown in the embodiment of the present invention. Figure 1 Example input signals and output signals of the power divider circuit shown in;

[0014] Figure 3 According to an embodiment of the present disclosure, Figure 1 An example graph of signals received at the carrier amplifier and peaking amplifier shown in;

[0015] Figure 4 A block diagram showing a second amplifier circuit according to an embodiment of the present disclosure;

[0016] Figure 5 A graph showing the power in a signal output from a first driver circuit at a phase difference of ten (10) degrees and the power in a signal output from a first driver circuit at a phase difference of ten (10) degrees according to an embodiment of the present disclosure Figure 4 An example first graph of a curve of power in a signal output by a second driver circuit is shown in FIG.

[0017] Figure 6 A graph showing the power in a signal output from a first driver circuit at a phase difference of twenty (20) degrees and the power in a signal output from a second driver circuit at a phase difference of twenty (20) degrees according to an embodiment of the present disclosure. Figure 4 An example second graph of a curve of power in a signal output by a second driver circuit is shown in FIG.

[0018] Figure 7 A graph showing the power in a signal output from a first driver circuit at a phase difference of thirty (30) degrees and the power in a signal output from a first driver circuit at a phase difference of thirty (30) degrees according to an embodiment of the present disclosure Figure 4 An example third graph of a curve of power in a signal output by a second driver circuit is shown in FIG.

[0019] Figure 8 A graph showing the power in a signal output from a first driver circuit at a phase difference of forty (40) degrees and the power in a signal output from a second driver circuit at a phase difference of forty (40) degrees according to an embodiment of the present disclosure. Figure 4 An example fourth graph of a curve of power in a signal output by the second driver circuit is shown in FIG.

[0020] Fig. 9 A graph showing the power in a signal output from a first driver circuit at a phase difference of fifty (50) degrees and the power in a signal output from a first driver circuit at a phase difference of fifty (50) degrees according to an embodiment of the present disclosure Figure 4 An example fifth graph of a curve of power in a signal output by the second driver circuit is shown in FIG. 5 ;

[0021] Fig.10 A graph showing the power in a signal output from a first driver circuit at a phase difference of sixty (60) degrees and a power in a signal output from a second driver circuit at a phase difference of sixty (60) degrees according to an embodiment of the present disclosure. Figure 4 An example sixth graph of a curve of power in a signal output by the second driver circuit is shown in FIG. 6 ;

[0022] Fig.11 shows a block diagram of a third amplifier circuit according to an embodiment of the present disclosure;

[0023] Fig.12 a flowchart illustrating a method of operating an amplifier circuit according to an embodiment of the present disclosure; and

[0024] Fig.13 A block diagram illustrating an example user component that may include one or more amplifier circuits according to an embodiment. DETAILED DESCRIPTION

[0025] The embodiments set forth below represent information necessary to enable those skilled in the art to practice the embodiments and to illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will understand the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0026] It should be understood that although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items.

[0027] It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0028] It should be understood that although the terms "upper," "lower," "bottom," "middle," "middle," "top," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as an "upper" element, and similarly, a second element may be referred to as an "upper" element, depending on the relative orientation of these elements, without departing from the scope of the present disclosure.

[0029] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. It should also be understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It should be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0031] Embodiments are described herein with reference to schematic illustrations of embodiments of the present disclosure. In this way, the actual sizes of layers and elements may be different, and it is expected that they will be different from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. For example, a region illustrated or described as a square or rectangle may have circular or curved features, and a region shown as a straight line may have some irregularities. Therefore, the region illustrated in the drawings is schematic, and its shape is not intended to illustrate the precise shape of the region of the device, and is not intended to limit the scope of the present disclosure. In addition, for illustrative purposes, the size of a structure or region may be enlarged relative to other structures or regions, and therefore a structure or region is provided to illustrate the general structure of this theme, and may be drawn to scale or may not be drawn to scale. Common elements between the accompanying drawings may be shown in this article with common element numbers, and are not described subsequently.

[0032] Embodiments are described herein with reference to schematic illustrations of embodiments of the present disclosure. In this way, the actual sizes of layers and elements may be different, and it is expected that they will be different from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. For example, a region illustrated or described as a square or rectangle may have circular or curved features, and a region shown as a straight line may have some irregularities. Therefore, the region illustrated in the drawings is schematic, and its shape is not intended to illustrate the precise shape of the region of the device, and is not intended to limit the scope of the present disclosure. In addition, for illustrative purposes, the size of a structure or region may be enlarged relative to other structures or regions, and therefore a structure or region is provided to illustrate the general structure of this theme, and may be drawn to scale or may not be drawn to scale. Common elements between the accompanying drawings may be shown in this article with common element numbers, and are not described subsequently.

[0033] The power divider circuit 114 is connected between the first driver circuit 106 and the second driver circuit 108 and the carrier amplifier circuit 116 and the peaking amplifier circuit 118. The output of the first driver circuit 106 is connected to a first input of the power divider circuit 114, and the output of the second driver circuit 108 is connected to a second input of the power divider circuit 114. The first output of the power divider circuit 114 is connected to an input of the carrier amplifier circuit 116, and the second output of the power divider circuit 114 is connected to an input of the peaking amplifier circuit 118.

[0034] The output of carrier amplifier circuit 116 and the output of peaking amplifier circuit 118 are connected together at node 120. An input of output circuitry 122 is connected to node 120. Thus, the output of carrier amplifier circuit 116 and the output of peaking amplifier circuit 118 are connected to an input of output circuitry 122.

[0035] In some embodiments, input splitter circuit 102 is implemented as a hybrid splitter circuit and power divider circuit 114 is implemented as a hybrid divider circuit. Input circuit system 104 can be, for example, a radio frequency (RF) source connected to a digital-to-analog converter (DAC) circuit, where the output of the DAC circuit is connected to input splitter circuit 102 (or to amplifier circuit 112 if amplifier circuit 112 is included in first amplifier circuit 100). Output circuit system 122 can be an RF output circuit system. The RF output circuit system can include an RF system (e.g., an isolator circuit, a filter circuit, etc.) connected to an antenna.

[0036] The first driver circuit 106 and the second driver circuit 108 form a dual driver amplifier circuit 124. The first driver circuit 106 has a first bias state and the second driver circuit 108 has a second bias state, wherein the first bias state is different from the second bias state. In a non-limiting, non-exclusive example, the first driver circuit 106 is a class AB amplifier circuit and the second driver circuit 108 is a class C amplifier circuit. The first driver circuit 106 and the second driver circuit 108 can be different types of amplifier circuits with different bias states. For example, the first driver circuit 106 can be a class F amplifier circuit and the second driver circuit 108 can be a class C amplifier circuit. The first bias state is referred to herein as a first bias point, and the second bias state is referred to as a second bias point.

[0037] The dual driver amplifier circuit 124 is operable to provide gain and power levels for average power as well as peak power. In a non-limiting, non-exclusive example, the first driver circuit 106 provides gain and power levels for average power, while the second driver circuit 108 provides peak power. The power divider circuit 114 is operable to divide the input power received from the first driver circuit 106 and the second driver circuit 108 when the input power is swept between low power and high power. Sometimes, the power divider circuit 114 limits the power to the carrier amplifier circuit 116 to maintain the carrier amplifier circuit 116 in a fixed compression state, while providing an increased input power to the peaking amplifier circuit 118 to direct the peaking amplifier circuit 118 into a compression state. In a non-limiting, non-exclusive example, the compression state is a three (3) decibel (dB) compression state. The terminal impedance 110 is connected to one of the input terminals of the input splitter 102.

[0038] For example, at the average power of the first amplifier circuit 100, the carrier amplifier circuit 116 is the only amplifier circuit turned on and operating. Therefore, the input power is received at the carrier amplifier circuit 116. As the input power increases, the peaking amplifier circuit 118 turns on and an increasing input power level is received at the peaking amplifier circuit 118, while the input power received at the carrier amplifier circuit 116 is maintained at a given level to keep the carrier amplifier circuit 116 in compression. T.

[0039] In some embodiments, input splitter circuit 102 and power divider circuit 114 are implemented with the same components, but other embodiments are not limited to this configuration. One example of a component is a three (3) dB coupler circuit.

[0040] In other embodiments, the power divider circuit 114 is implemented with an input splitter circuit, a first driver circuit, a second driver circuit, and a power divider circuit. The power divider circuit 114 is similar to Figure 1 , the input splitter circuit 102, the first driver circuit 106, the second driver circuit 108, and the power divider circuit 114 are configured as shown in FIG. The bias of the first driver circuit 106 (e.g., a class AB amplifier) ​​and the bias of the second driver circuit 108 (e.g., a class C amplifier) ​​are selected and / or adjusted to set the distribution function of the power divider circuit 114 to a specific distribution between the carrier amplifier circuit 116 and the peaking amplifier circuit 118.

[0041] Figures 2A to 2C The present invention is shown in the embodiment of the present invention. Figure 1 Example input signals and output signals of the power divider circuit 114 are shown in FIG. Figures 2A to 2C In the embodiment, a first input signal is received from a first driver circuit 106 (e.g., a class AB amplifier), a second input signal is received from a second driver circuit 108 (e.g., a class C amplifier), a first output signal is received by a carrier amplifier circuit 116, and a second output signal is received by a peaking amplifier circuit 118.

[0042] exist Figure 2A , the first input signal 200 and the second input signal are not equal because only the first input signal 200 is present. The first input signal 200 is received at the first input (IN1) port of the power divider circuit 114, while no input signal is present at the second input (In2) port. The power divider circuit 114 equally divides the first input signal 200 into a first output signal 202 at the first output (Out1) port and a second output signal 204 at the second output (Out2) port. The first output signal 202 and the second output signal 204 have the same amplitude, but are phase-shifted by ninety (90) degrees. The first output signal 202 is provided to the carrier amplifier circuit 116, and the second output signal 204 is provided to the peaking amplifier circuit 118. In the illustrated embodiment, the first output signal 202 and the second output signal 204 are each negative three (-3) dB signals.

[0043] exist Figure 2A, the first input signal 200 and the second input signal are not equal because only the first input signal 200 is present. The first input signal 200 is received at the first input (IN1) port of the power divider circuit 114, while no input signal is present at the second input (In2) port. The power divider circuit 114 equally divides the first input signal 200 into a first output signal 202 at the first output (Out1) port and a second output signal 204 at the second output (Out2) port. The first output signal 202 and the second output signal 204 have the same amplitude, but are phase-shifted by ninety (90) degrees. The first output signal 202 is provided to the carrier amplifier circuit 116, and the second output signal 204 is provided to the peaking amplifier circuit 118. In the illustrated embodiment, the first output signal 202 and the second output signal 204 are each negative three (-3) dB signals.

[0044] Figure 2C Example input signals and output signals are shown where a first input signal 214 at a first input (In1) port has the same amplitude as a second input signal 216 at a second input (In2) port. In such an embodiment, there is no first output signal at the first output (Out1) port, and the second output (Out2) port outputs a second output signal 218. Thus, all power is provided to the peaking amplifier circuit 118. In the illustrated embodiment, the second output signal 218 is a positive three (+3) dB signal.

[0045] Figure 3 Graph 302 shows a signal received at peaking amplifier circuit 118 and at Figure 1 300 of a curve 304 of a signal received at the carrier amplifier circuit 116. Figure 1 As shown in , a signal is received from the power divider circuit 114. The vertical axis represents output power (in dB), and the horizontal axis represents input power (in dB).

[0046] Figure 3 Graph 302 shows a signal received at peaking amplifier circuit 118 and at Figure 1 300 of a curve 304 of a signal received at the carrier amplifier circuit 116. Figure 1 As shown in , a signal is received from the power divider circuit 114. The vertical axis represents output power (in dB), and the horizontal axis represents input power (in dB).

[0047] Figure 44 is a block diagram of a second amplifier circuit 400 according to an embodiment of the present disclosure. The second amplifier circuit 400 is similar to the first phase shifter (PS1) circuit 402 and the second phase shifter (PS2) circuit 404. Figure 1 4. The first amplifier circuit 100 shown in FIG. 4 is a first amplifier circuit 100. The PS1 circuit 402 is operable to shift the phase of the input signal on the signal line 406. The PS2 circuit 404 is operable to shift the phase of the input signal on the signal line 408. The PS1 circuit 402 and the PS2 circuit 404 are respectively used to control and adjust the phase difference between the signal on the signal line 410 and the signal on the signal line 412. The phase difference between the signal on the signal line 410 and the input signal on the signal line 412 can be used to control and adjust the distribution of power by the power divider circuit 114.

[0048] Figures 5 to 10 The signals input into the power divider circuit 114 are depicted at different phase differences between the signal on signal line 410 and the signal on signal line 412. The signal on signal line 410 is received by the carrier amplifier circuit 116, and the signal on signal line 412 is received by the peaking amplifier circuit 118. Figures 5 to 10 , the horizontal axis represents the power input to the first driver circuit 106 and the power input to the second driver circuit 108. The vertical axis represents the power output from the first driver circuit 106 to the signal line 410 and the power output from the second driver circuit 108 to the signal line 412.

[0049] Figure 5 A graph 502 showing the power in the signal output from the first driver circuit 106 and the power in the signal output from the first driver circuit 106 at a phase difference of ten (10) degrees according to an embodiment of the present disclosure. Figure 4 5 is an example of a curve 504 of the power in the signal output by the second driver circuit 108 shown in first graph 500. Curve 504 corresponds to curve 502 as input power increases, but the power output from the second driver circuit 108 (on signal line 412) increases faster at higher input power levels than the power output from the first driver circuit 106 (on signal line 410).

[0050] Figure 6 A graph 602 showing the power in the signal output from the first driver circuit 106 and the power in the signal output from the first driver circuit 106 at a phase difference of twenty (20) degrees according to an embodiment of the present disclosure. Figure 4 604 of the power in the signal output by the second driver circuit 108 is shown in FIG. 600. As the input power increases, the curve 604 corresponds to the curve 602, but the power in the curve 604 increases faster at higher input power levels than the power in the curve 602. Figure 5), the power in curve 602 increases more slowly at higher input power levels. Figure 5 In contrast, an increased phase shift of twenty (20) degrees causes the power in curve 604 to increase faster than the power in curve 504 and causes the difference between the power shown in curve 602 and the power in curve 604 to be greater than the difference between curve 502 and curve 504 .

[0051] Figure 7 A graph 702 showing the power in the signal output from the first driver circuit 106 and the power in the signal output from the first driver circuit 106 at a phase difference of thirty (30) degrees according to an embodiment of the present disclosure. Figure 4 704 of the power in the signal output by the second driver circuit 108 is shown in FIG. 700. As the input power increases, the power in curve 704 increases faster at higher input power levels than the power in curve 702 and compared to the previous curves 504 and 604. The power in curve 702 decreases slightly at higher input power levels. Also, compared to Figure 5 and 6 In comparison, an increased phase shift of thirty (30) degrees results in a greater difference between the power shown in curve 702 and the power in curve 704 than between curve 502 and curve 504 and between curve 602 and curve 604 .

[0052] Figure 8 A graph 802 showing the power in the signal output from the first driver circuit 106 and the power in the signal output from the first driver circuit 106 at a phase difference of forty (40) degrees according to an embodiment of the present disclosure. Figure 4 800 . As the input power increases, the power in curve 804 increases faster at higher input power levels than the power in curve 802 and compared to the previous curves 504 , 604 , and 704 . The power in curve 802 is less at higher input power levels than at lower input power levels. Also, compared to Figures 5 to 7 In contrast, an increased phase shift of forty (40) degrees results in a difference between the power shown in curve 802 and the power in curve 804 that is greater than Figures 5 to 7 The difference between the corresponding curves in .

[0053] Fig. 9 A graph 902 showing the power in the signal output from the first driver circuit 106 and the power in the signal output from the first driver circuit 106 at a phase difference of fifty (50) degrees according to an embodiment of the present disclosure. Figure 4904 of the power in the signal output by the second driver circuit 108 shown in FIG. 900. As the input power increases, the power in curve 904 increases faster at higher input power levels than the power in curve 902 and compared to the previous curves 504, 604, 704, and 804. The power in curve 902 is less at higher input power levels than at lower input power levels. Also, compared to Figures 5 to 8 In contrast, an increased phase shift of fifty (50) degrees results in a difference between the power shown in curve 902 and the power in curve 904 that is greater than Figures 5 to 8 The difference between the corresponding curves in .

[0054] Fig.10 A graph 1002 showing the power in the signal output from the first driver circuit 106 and the power in the signal output from the first driver circuit 106 at a phase difference of sixty (60) degrees according to an embodiment of the present disclosure. Figure 4 1000. As the input power increases, the power in curve 1004 increases faster at higher input power levels than the power in curve 1002 and compared to previous curves 504, 604, 704, 804, and 904. The power in curve 1002 is less at higher input power levels than at lower input power levels. Also, compared to Figures 5 to 9 In comparison, an increased phase shift of sixty (60) degrees results in a difference between the power shown in curve 1002 and the power in curve 1004 that is greater than Figures 5 to 9 The difference between the corresponding curves in .

[0055] Fig.11 A block diagram of a third amplifier circuit 1100 according to an embodiment of the present disclosure is shown. The example third amplifier circuit 1100 is an orthogonal load modulation balanced amplifier circuit. The carrier amplifier circuit 116 and the peaking amplifier circuit 118 are connected between the input splitter circuit 102 and the power divider circuit 114. The first balanced power amplifier (BPA) circuit 1102 and the second BPA circuit 1104 are connected between the power divider circuit 114 and the coupler circuit 1106.

[0056] Specifically, a first output of input splitter circuit 102 is connected to an input of carrier amplifier circuit 116, and a second output of input splitter circuit 102 is connected to an input of peaking amplifier circuit 118. An output of carrier amplifier circuit 116 is connected to a first input of power divider circuit 114. An output of peaking amplifier circuit 118 is connected to a second input of power divider circuit 114. A first output of power divider circuit 114 is connected to an input of first BPA circuit 1102, and a second output of power divider circuit 114 is connected to an input of second BPA circuit 1104. An output of first BPA circuit 1102 is connected to a first input of coupler circuit 1106. An output of second BPA circuit 1104 is connected to a second input of coupler circuit 1106.

[0057] The first load 1108 can be connected to the first input of the input splitter circuit 102. The input pin (Pin) is connected to the second input of the input splitter circuit 102. The second load 1110 can be connected to the first output of the coupler circuit 1106. The output pin (Pout) is connected to the second output of the coupler circuit 1106. The power divider circuit 114 is connected to the Figures 2A to 2C and Figure 4 The power divider circuit 114 in FIG. 1104 operates in a similar manner. The power divider circuit 114 divides power into the first BPA circuit 1102 and the second BPA circuit 1104 according to the input power.

[0058] Fig.12 A flow chart of a method of operating an amplifier circuit according to an embodiment of the present disclosure is shown. Initially, an input signal is received at an amplifier circuit as shown in block 1200. When the input signal is at a lower power level, power is allocated to the carrier amplifier circuit (block 1202). The power level in the input signal is increased at block 1204, and a determination is made at block 1206 whether a peaking amplifier circuit has been turned on based on the current power level of the input signal. If it is determined that the peaking amplifier circuit has not been turned on, the method returns to block 1202.

[0059] When it is determined at block 1206 that the peaking amplifier circuit is already on, the method continues at block 1208, where the power allocated to the carrier amplifier circuit is limited and increased power is allocated to the peaking amplifier circuit. The power level is reduced at block 1210, and it is determined at block 1212 whether the peaking amplifier circuit has been turned off based on the current power level. If it is determined that the peaking amplifier circuit has not been turned off (e.g., is still on), the method returns to block 1208. When it is determined at block 1212 that the peaking amplifier circuit has been turned off, the method continues at block 1202.

[0060] Fig.13A block diagram of an example user element that may include one or more amplifier circuits according to an embodiment is shown. The concepts described above may be implemented in various types of user elements 1300 such as mobile terminals, smart watches, tablet computers, computers, navigation devices, access points, and similar wireless communication devices that support wireless communications such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element 1300 will typically include a control system 1302, a baseband processor 1304, a transmitting circuit system 1306, a receiving circuit system 1308, an antenna switch circuit system 1310, a plurality of antennas 1312, and a user interface circuit system 1314. In a non-limiting example, as an example, the control system 1302 may be a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). In this regard, the control system 1302 may include at least a microprocessor, an embedded memory circuit, and a communication bus interface. The receiving circuit system 1308 receives radio frequency signals from one or more base stations via an antenna 1312 and through an antenna switch circuit system 1310. The low noise amplifiers and filters of the receive circuitry 1308 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) then downconverts the filtered received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0061] The baseband processor 1304 processes the digitized received signal to extract the information or data bits transmitted in the received signal. Such processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 1304 is typically implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0062] For transmission, the baseband processor 1304 receives digitized data, which may represent voice, data, or control information, from the control system 1302, and encodes the digitized data for transmission. The encoded data is output to the transmit circuit system 1306, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at the desired transmit frequency or frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission, and the modulated carrier signal is delivered to the antenna 1312 via the antenna switch circuit system 1310 to the antenna 1312. Multiple antennas 1312 and replicated transmit and receive circuit systems 1306, 1308 may provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0063] It is contemplated that any of the aforementioned aspects, and / or the various individual aspects and features described herein, may be combined to obtain additional advantages. Unless otherwise indicated herein, any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments.

[0064] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims below.

Claims

1. An amplifier circuit, comprising: a first driver circuit connected between the input splitter circuit and the power divider circuit, the first driver circuit having a first bias point; a second driver circuit connected between the input splitter circuit and the power divider circuit, the second driver circuit having a second bias point different from the first bias point; and A carrier amplifier circuit and a peaking amplifier circuit are connected to the power divider circuit.

2. The amplifier circuit according to claim 1, wherein: The first driver circuit is a class AB amplifier circuit; and The second driver circuit is a class C amplifier circuit.

3. The amplifier circuit of claim 1, wherein the amplifier circuit is a Doherty amplifier circuit.

4. The amplifier circuit according to claim 1, further comprising: the input splitter; as well as The power divider circuit.

5. The amplifier circuit according to claim 1, further comprising: An amplifier is connected to a first input terminal of the input splitter.

6. The amplifier circuit according to claim 5, further comprising: A terminal impedance is connected to the second input terminal of the input splitter.

7. The amplifier circuit according to claim 6, wherein: the first driver circuit being connected to a first output terminal of the input splitter; The second driver circuit is connected to a second output terminal of the input splitter.

8. The amplifier circuit of claim 1, wherein the peaking amplifier circuit contributes power and changes a load state such that the carrier amplifier circuit is load modulated from an effective match to a power match.

9. The amplifier circuit according to claim 1, further comprising: a first phase shifter connected between the input splitter and the first driver circuit; A second phase shifter is connected between the input splitter and the second driver circuit.

10. The amplifier circuit according to claim 1, further comprising: A first balanced power amplifier (BPA) circuit is connected to the power divider circuit.

11. The amplifier circuit according to claim 10, further comprising: A second BPA circuit is connected to the power divider circuit.

12. The amplifier circuit of claim 11 , further comprising: A coupler circuit is connected to the first BPA circuit and the second BPA circuit.

13. An amplifier circuit comprising: an input splitter circuit connected to the first phase shifter circuit and the second phase shifter circuit; a first driver circuit connected between the first phase shifter circuit and the power divider circuit, the first driver circuit having a first bias point; a second driver circuit connected between the second phase shifter circuit and the power divider circuit, the second driver circuit having a second bias point different from the first bias point; as well as A carrier amplifier circuit and a peaking amplifier circuit are connected to the power divider circuit.

14. The amplifier circuit of claim 13, wherein: The first driver circuit is a class AB amplifier circuit; and The second driver circuit is a class C amplifier circuit.

15. The amplifier circuit of claim 13, wherein the amplifier circuit is a Doherty amplifier circuit.

16. The amplifier circuit of claim 13, further comprising the power divider circuit.

17. The amplifier circuit of claim 13, further comprising: An amplifier is connected to a first input terminal of the input splitter.

18. The amplifier circuit of claim 17, further comprising: A terminal impedance is connected to the second input terminal of the input splitter.

19. An amplifier circuit comprising: an input splitter circuit connected to a first driver circuit and a second driver circuit, the first driver circuit having a first bias point and the second driver circuit having a second bias point different from the first bias point; a power divider circuit connected to the first driver circuit and the second driver circuit; a first balanced power amplifier (BPA) circuit connected to the power divider circuit; a second BPA circuit connected to the power divider circuit; as well as A coupler circuit is connected to the first BPA circuit and the second BPA circuit.

20. The amplifier circuit of claim 19, wherein: The first driver circuit is a class AB amplifier circuit; and The second driver circuit is a class C amplifier circuit.

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