Circuit for integrating current from high density sensor

Abstract

A circuit (300) includes a plurality of first stage integrators (106 (1, 1) to 106 (2, 1)). Each of the plurality of first stage integrators (106 (1, 1) to 106 (2, 1)) includes a first input (324), a second input (326), a third input (322), and an output (328). The first input (324) of each of the plurality of first stage integrators is coupled to a different one of the circuit inputs (304), the second input (326) is coupled to a first reference input, and the third input (322) is coupled to a second reference input, and the output (328) of each of the plurality of first stage integrators is coupled to the first input (324) of that first stage integrator. The circuit (300) includes a second stage integrator (108 (1)) including a first input (386) coupled to each of the first inputs of the plurality of first stage integrators, a second input (388) coupled to the first reference input, and an output (392) coupled to the first input (386) of the second stage integrator (108 (1)).

Description

Technical Field

[0001] The present description generally relates to circuits for integrating current from a sensor. Background Art

[0002] Image sensors are used to convert optical image information into electrical signals. Image sensors generate an electric current according to the amount of light incident on the sensor. Image sensors are used in, for example, electronic imaging devices, medical imaging devices, and thermal imaging devices.

[0003] Optical nanopore sensors are used to detect and characterize clinical biomarkers and for DNA / RNA sequencing.Optical nanopore sensors typically operate by detecting changes in ionic current through a nanopore.

[0004] The sensor system may include hundreds or even thousands of individual sensors (e.g., sensor elements). The individual sensors may be arranged, for example, in a two-dimensional array. Each sensor may be coupled to an electronic processing circuit via a conductor (e.g., a signal trace, a channel, a wire). The electronic processing circuit converts the current generated by the sensor into a voltage. The electronic processing circuit may include an amplifier that integrates the current and provides an output voltage representative of the current. A disadvantage of many amplifiers is that noise signals (e.g., flicker noise signals or thermal noise signals) that may be present at the input of the amplifier may be amplified and generated at the output of the amplifier. In addition, parasitic capacitances of the sensors and signal traces increase the noise signal.

[0005] As the noise signal increases, the signal-to-noise ratio (SNR) of the amplifier decreases. In order to reduce the noise signal and increase the SNR, a precision amplifier may be used to convert the current into a voltage. The precision amplifier may have a large bandwidth, high gain, and low noise, and may be implemented with multiple gain stages, each with several transistors. Therefore, the precision amplifier requires a relatively large area to be implemented in an integrated circuit or a semiconductor die, and draws a higher current. Because the sensor system may include thousands of sensors densely fabricated in an integrated circuit or a semiconductor die, and the individual sensors may be coupled to corresponding precision amplifiers, a high-density sensor system may occupy a relatively large area in an integrated circuit or a semiconductor die, and may draw a higher current, which increases power consumption. Summary of the invention

[0006] In one aspect, a circuit includes a plurality of circuit inputs. At least one of the plurality of circuit inputs is adapted to receive an input current. The circuit includes a first reference input adapted to receive a first reference voltage, and includes a second reference input adapted to receive a second reference voltage. The circuit includes a plurality of first-stage integrators. Each of the plurality of first-stage integrators includes a first input, a second input, a third input, and an output. The first input of each of the plurality of first-stage integrators is coupled to a different one of the circuit inputs, the second input is coupled to the first reference input, the third input is coupled to the second reference input, and the output of each of the plurality of first-stage integrators is coupled to the first input of the first-stage integrator through a first feedback path for the first-stage integrator. The circuit includes a second-stage integrator, the second-stage integrator including a first input, a second input, and an output. The first input of the second-stage integrator is coupled to each of the first inputs of the plurality of first-stage integrators, the second input of the second-stage integrator is coupled to the first reference input, and the output of the second-stage integrator is coupled to the first input of the second-stage integrator through a second feedback path.

[0007] In an additional aspect, the circuit includes a plurality of transfer switches. Each of the plurality of transfer switches includes a first terminal and a second terminal. The first terminal of each of the plurality of transfer switches is coupled to a different one of the first inputs of the plurality of first stage integrators, and the second terminal of each of the plurality of transfer switches is coupled to the first input of the second stage integrator.

[0008] In an additional aspect, the first feedback path of each of the plurality of first stage integrators comprises a first switch comprising a first terminal coupled to the output of such first stage integrator and comprising a second terminal. The first feedback path of each of the plurality of first stage integrators comprises a first feedback capacitor comprising a first terminal coupled to the first input of such first stage integrator and a second terminal coupled to the second terminal of the first switch.

[0009] In an additional aspect, each of the plurality of first stage integrators further includes a second switch including a first terminal coupled to the second terminal of the first feedback capacitor of such first stage integrator and a second terminal adapted to receive the second reference voltage.

[0010] In an additional aspect, a circuit includes a circuit input adapted to receive an input current, a first reference input adapted to receive a first reference voltage, and a second reference input adapted to receive a second reference voltage. The circuit includes a first stage integrator, the first stage integrator including a first input coupled to the circuit input, a second input coupled to the first reference input, a third input coupled to the second reference input, and an output coupled to the first input of the first stage integrator through a first feedback path. The circuit includes a changeover switch, the changeover switch including a first terminal coupled to the first input of the first stage integrator and including a second terminal. The circuit includes a second stage integrator, the second stage integrator including a first input coupled to the second terminal of the changeover switch, a second input coupled to the first reference input, and an output coupled to the first input of the second stage integrator through a third feedback path.

[0011] In an additional aspect, a circuit includes a circuit input adapted to receive an input current, a first reference input adapted to receive a first reference voltage, and a second reference input adapted to receive a second reference voltage. The circuit includes a first amplifier, the first amplifier including a first input coupled to the circuit input, a second input coupled to the first reference input, and including an output. The circuit includes a first switch, the first switch including a first terminal coupled to the output of the first amplifier and including a second terminal. The circuit includes a first feedback capacitor, the first feedback capacitor including a first terminal coupled to the first input of the first amplifier and a second terminal coupled to the second terminal of the first switch. The circuit includes a second switch, the second switch including a first terminal coupled to the second terminal of the first feedback capacitor and a second terminal coupled to the second reference input. The circuit includes a transfer switch, the transfer switch including a first terminal coupled to the first input of the first amplifier and including a second terminal. The circuit includes a second amplifier, the second amplifier including a first input coupled to the second terminal of the transfer switch, a second input coupled to the first reference input, and including an output. The circuit includes a second feedback capacitor, the second feedback capacitor including a first terminal coupled to the first input of the second amplifier and a second terminal coupled to the output of the second amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating an example sensor system.

[0013] Figure 2 is a block diagram illustrating a plurality of sensors coupled to respective first stage integrators coupled to second stage integrators.

[0014] Figure 3A , 3B and 3C are schematic diagrams illustrating example circuits.

[0015] Figure 4 Yes Description Figures 3A to 3C Timing diagram of the timing signals and voltages in a circuit.

[0016] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (in function and / or structure). DETAILED DESCRIPTION

[0017] Figure 1 1 is a block diagram of a system 100 illustrating an example. System 100 includes a plurality of sensors 104(1,1)-104(M,N) arranged in a two-dimensional array consisting of M rows and N rows. Sensor 104(1,1) refers to the sensor of row number 1 and column number 1, and sensor 104(M,N) refers to the sensor of row number M and column number N. The sensor can be, for example, a photodiode, a nanopore, or other type of sensor. The sensor can be used in an electronic imaging device, a medical imaging device, a thermal imaging device, and / or in a system for detecting and / or characterizing clinical biomarkers and DNA / RNA sequencing.

[0018] When energy (e.g., light) is incident on the sensors 104(1,1)-104(M,N), they generate charge according to the amount of incident energy. In some examples, the sensors 104(1,1)-104(M,N) are coupled to respective first stage integrators 106(1,1)-106(M,N), which may incorporate a corresponding sensor (e.g., Figure 1 ). Thus, each sensor may be coupled to a corresponding first stage integrator. The charge generated by each sensor is integrated by the corresponding first stage integrator.

[0019] System 100 includes second stage integrators 108(1)-108(N). Each second stage integrator may be coupled to a corresponding group (e.g., a column, such as Figure 1, or a row). For example, the second stage integrator 108(1) may be coupled to the first stage integrator of column number 1, and the second stage integrator 108(N) may be coupled to the first stage integrator of column number N. The charge integrated by the first stage integrator of column number 1 is transferred to the second stage integrator 108(1), and similarly, the charge integrated by the first stage integrator of column number N is transferred to the second stage integrator 108(N). In response to the charge transferred by the first stage integrator of column number 1, the second stage integrator 108(1) provides an output voltage representing the transferred charge to, for example, one input of the multiplexer 110. Similarly, in response to the charge transferred by the first stage integrator of column N, the second stage integrator 108(N) provides an output voltage representing the transferred charge to, for example, another input of the multiplexer 110.

[0020] In some examples, the output voltages provided by the second stage integrators 108(1) to 108(N) are multiplexed by a multiplexer (MUX) 110, and the multiplexed output voltages are provided to an analog-to-digital converter (ADC) 112. ADC 112 digitizes the output voltages and provides digital information (e.g., a digital code) representing the output voltages to a circuit system (e.g., a processor, a state machine, a logic circuit system, a memory, and / or a combination thereof), which may include software. The switching of MUX 110 may be controlled by a processor, logic circuit system, and / or control circuit system, which may be located on the same integrated circuit as MUX 110 or may be external to the integrated circuit.

[0021] Figure 2 1 is a block diagram illustrating sensors 104(1,1) to 104(M,1) of column number 1 coupled to respective first stage integrators 106(1,1) to 106(M,1), which are coupled to second stage integrators 108(1). In response to receiving incident energy (e.g., light), sensors 104(1,1) generate input currents I S1 The first stage integrator 106 (1, 1) receives the input current I from the sensor 104 (1, 1). S1 The charge output in the form of a current (e.g., the charge generated by the sensor 104 (1, 1) in response to the incident energy received) is integrated and the resulting integrated charge CH1 is output. Similarly, in response to the incident energy, the sensor 104 (M, 1) generates a charge, which is used as the input current I SM The first stage integrator 106 (M, 1) integrates the charge output by the sensor 104 (M, 1) into an input current I SM , and output the resulting integrated charge CH MThe second stage integrator 108 ( 1 ) generates an output voltage based on the current / integrated charge provided by the first stage integrators 106 ( 1 , 1 ) to 106 (M, 1 ).

[0022] In some examples, the first stage integrators 106(1,1) to 106(M,1) integrate the charge during corresponding integration periods and output the resulting integrated charge to the second stage integrator 108(1) during corresponding transfer periods. The integration periods may be different, or they may overlap in time. The transfer periods may be different, or they may overlap in time. The transfer periods may be delayed in time from the corresponding integration periods to allow the first stage integrators sufficient time to integrate the charge. As described in more detail below, the number of transfer periods (which may also be referred to as "transfer phases") may be any integer value (e.g., 2), and the number of integration periods (which may also be referred to as "integration phases") may be any integer value (e.g., 2).

[0023] Figure 3A is a schematic diagram of an example circuit 300. Circuit 300 includes examples of sensors 104(1,1) and 104(2,1), first stage integrators 106(1,1) and 106(2,1), and second stage integrator 108(1). Circuit 300 is configured to receive input currents from a plurality of sensors (e.g., sensors 104(1,1) and 104(2,1)) and provide output voltages based on the input currents.

[0024] Circuit 300 includes a first stage integrator 106(1,1) coupled to sensor 104(1,1), and includes a first stage integrator 106(2,1) coupled to sensor 104(2,1). Circuit 300 includes a second stage integrator 108(1) coupled to first stage integrators 106(1,1) and 106(2,1). Circuit 300 includes a first circuit input 304 adapted to be coupled to sensor 104(1,1), and includes a second circuit input 306 adapted to be coupled to sensor 104(2,1).

[0025] Sensor 104 (1,1) is powered by a current source I S1 and parallel resistor R S1 Modeling where the current is generated by the charge collected from the energy incident on the sensor. S1 The sensor resistor R includes a first terminal 310 coupled to the first circuit input 304 and includes a second terminal 312 coupled to a common potential 314 (eg, ground). S1 (e.g., between about 1 M ohm and about 1 G ohm) including coupling to I S1The first terminal 316 of the first terminal 310 of the sensor 104 (1, 1) is coupled to the first circuit input 304 via a signal trace T1 (eg, a conductor, a wire, a channel, and / or a circuit board trace). The parasitic capacitance C PAR_1 Can exist between signal trace T1 and common potential 314. Parasitic capacitance C PAR_1 Can represent the sum of sensor parasitic capacitance, signal trace parasitic capacitance, and any other parasitic capacitance.

[0026] The circuit 300 includes a circuit adapted to receive a first reference voltage V REF1 (eg, about 0V to about 1V) and includes a first reference input 320 adapted to receive a second reference voltage V REF2 A second reference input 322 (eg, approximately 0V to approximately 1.5V) is provided.

[0027] The first stage integrator 106(1,1) includes a first operational amplifier A1 including a first input 324 (e.g., an inverting input), a second input 326 (e.g., a non-inverting input), and an output 328. The first input 324 of A1 is coupled to the first circuit input 304, and the second input 326 of A1 is coupled to the first reference input 320.

[0028] The first stage integrator 106 (1,1) includes a switch S 11 (also referred to as the first switch), the switch includes a first terminal 330 coupled to the output 328 of the first operational amplifier A1 and includes a second terminal 332. The feedback capacitor C1 is connected to the output 328 of the first operational amplifier A1 via the switch S 11 The feedback capacitor C1 includes a first terminal 334 coupled to the first terminal 324 of A1 and includes a first terminal 334 coupled to the switch S 11 The second terminal 332 of the second terminal 336.

[0029] The first stage integrator 106 (1,1) includes a switch S 12 (also referred to as a second switch), the switch comprising a first terminal 340 coupled to the second terminal 336 of the feedback capacitor C1, and comprising a second terminal 342 coupled to the second reference input 322, the second reference input being adapted to receive a second reference voltage V REF2 The first stage integrator 106 (1, 1) includes a switching switch S T1 The changeover switch comprises a first terminal 344 coupled to the first input 324 of the first operational amplifier A1 and comprises a second terminal 346 .

[0030] The model of sensor 104 (2,1) includes a current source I S2, the current source includes a first terminal 350 and includes a second terminal 352 coupled to the common potential 314. In addition, the model of the sensor 104 (2, 1) includes a sensor resistor R S2 (e.g., between about 1 M ohm and about 1 G ohm), the sensor resistor includes a resistor coupled to I S2 The first terminal 354 of the first terminal 350 of FIG. 1 and includes a second terminal 356 coupled to the common potential 314. The sensor 104 (2, 1) is coupled to the second circuit input 306 via a signal trace T2 (eg, a conductor, a wire, a channel, and / or a circuit board trace). The parasitic capacitance C PAR_2 Can exist between signal trace T2 and common potential 314. Parasitic capacitance C PAR_2 Can represent the sum of sensor parasitic capacitance, signal trace parasitic capacitance, and any other parasitic capacitance.

[0031] The first stage integrator 106 (2, 1) includes a second operational amplifier A2, which includes a first input 360 (e.g., an inverting input) coupled to the second circuit input 306, a second input 362 (e.g., a non-inverting input) coupled to a third reference input 364, and includes an output 366. The third reference input 364 is suitable for receiving a first reference voltage V REF1 The first stage integrator 106 (2,1) includes a switch S 21 A feedback capacitor C2 is coupled between the output 366 of A2 and the first input 360 of A2. The feedback capacitor C2 includes a first terminal 372 coupled to the first terminal 360 of A2 and includes a second terminal 370 coupled to the switch S. 21 The second terminal 370 of the second terminal 374.

[0032] The first stage integrator 106 (2,1) includes a switch S 22 (also referred to as a fourth switch), the switch comprising a first terminal 376 coupled to a second terminal 374 of feedback capacitor C2, and comprising a second terminal 378 coupled to a second reference input 380, the second reference input being adapted to receive a second reference voltage V REF2 The first stage integrator 106 (2,1) includes a switching switch S T2 The changeover switch includes a first terminal 382 coupled to the first input 360 of the second operational amplifier A2 and includes a second terminal 384.

[0033] The circuit 300 includes a second-stage integrator 108 (1), which includes a first transfer switch S T1 and the second transfer switch S T2The third operational amplifier A3 is coupled to the first operational amplifier A1 and the second operational amplifier A2. The third operational amplifier A3 includes a switch S coupled to the corresponding T1 and S T2 The third operational amplifier A3 includes a second input 388 (eg, non-inverting input) coupled to a fifth reference input 390, which is adapted to receive a first reference voltage V REF1 The third operational amplifier A3 includes an output 392 that can be coupled to the ADC 112 via the multiplexer 110. A feedback capacitor C3 is coupled between the output 392 of A3 and the first input 386 of A3. The feedback capacitor C3 includes a first terminal 393 coupled to the first input 386 of A3, and includes a second terminal 394 coupled to the output 392 of A3. The second stage integrator 108(1) includes a reset switch S coupled between the first terminal 393 and the second terminal 394 of C3. RST .

[0034] In some examples, circuit 300 includes a timing control circuit CTRL (eg, a processor, logic circuitry, memory, state machine, and / or software) configured to provide a timing signal to switch S 11 , S 12 , S T1 , S 21 , S 22 and S T2 The timing control circuit CTRL may include a clock (not shown in FIG. 3 ) that provides a clock signal. In response, the timing control circuit CTRL provides a first timing signal at respective outputs 395 , 396 , and 397 . Second timing signal and the third timing signal Apply timing signal To control (eg, to open (make it non-conductive) or close (make it conductive)) the applicable switch S 11 , S 12 and S T1 , apply the timing signal To control the switch S 21 , S 22 and S T2 , and apply the timing signal To control the switch S RST .

[0035] In some examples, circuit 300 operates in two phases: (1) an integration phase; and (2) a transfer phase. In the integration phase, an input current from a sensor (e.g., sensor 104(1,1)) is received by its corresponding first-stage integrator (e.g., first-stage integrator 106(1,1)), and the sensor charge forming the input current is integrated during an integration period. In the transfer phase, the first-stage integrator (e.g., first-stage integrator 106(1,1)) transfers the resulting integrated charge to a second-stage integrator (e.g., second-stage integrator 108(1)) during a transfer period. The second-stage integrator (e.g., second-stage integrator 108(1)) provides an output voltage representing the transferred charge.

[0036] Similarly, during the integration phase, the input current from the sensor 104(2,1) is received by the first stage integrator 106(2,1), which integrates the charge forming the input current during an integration period. During the transfer phase, the first stage integrator 106(2,1) transfers the resulting integrated charge to the second stage integrator 108(1) during a transfer period. The second stage integrator 108(1) provides an output voltage representing the transferred charge.

[0037] Figure 3B The circuit 300 is illustrated during a first integration phase and a second integration phase. During the first integration phase, charge is integrated by the first stage integrator 106(1,1), and during the second integration phase, charge is integrated by the first stage integrator 106(2,1).

[0038] During the first integration phase, the first timing signal is asserted low (e.g., logic “0”, a low voltage, such as near ground). In response, switch S 11 closed (ie, conducting), but the switch S 12 and S T1 1,1) is disconnected (e.g., not conducting). Thus, the output 328 of the first operational amplifier A1 is coupled to the first input 324 of A1 via the feedback capacitor C1, thereby forming a feedback path. Due to the feedback path, the first input 324 of A1 is maintained at a virtual ground relative to the second input 326 of A1. The input current I from the sensor 104 (1,1) S1 flows into the feedback capacitor C1, and I S1 The charge of is integrated into the feedback capacitor C1 during the first integration period. T1 During the first integration phase, the first stage integrator 106 ( 1 , 1 ) is disconnected from the second stage integrator 108 ( 1 ).

[0039] Similarly, during the second integration phase, the second timing is asserted low. In response, switch S 21 Closed, but switch S 22 and S T2 Disconnected. Therefore, the output 366 of the second operational amplifier A2 is coupled to the first input 360 of A2 via the feedback capacitor C2, thereby forming a feedback path. Due to the feedback path, the first input 360 of A2 is maintained at a virtual ground relative to the second input 362 of A2. The input current I from the sensor 104 (2, 1) S2 flows into the feedback capacitor C2, and I S2 The charge is integrated into the feedback capacitor C2 during the second integration period. T2 During the second integration phase, the first stage integrator 106 ( 2 , 1 ) is disconnected from the second stage integrator 108 ( 1 ).

[0040] In some examples, the duration and / or start time of the first integration period and the second integration period may be different. In other examples, the first integration period and the second integration period may overlap (at least partially) in time.

[0041] Figure 3C The circuit 300 is illustrated during a first transfer phase and a second transfer phase. During the first transfer phase, the first timing signal is asserted high. In response, switch S 11 Open, but switch S 12 and S T1 Closed. Because S 11 is disconnected, so the output 328 of the first operational amplifier A1 is disconnected from the first input 324 of A1, thereby disconnecting the feedback path. 21 and S T1 are closed, so the feedback capacitor C1 is coupled to the second reference voltage V REF2 , and the first input 324 of A1 is coupled to the first input 386 of the third operational amplifier A3. As a result, the charge integrated into the feedback capacitor C1 is transferred to the feedback capacitor C3 in the first transfer period.

[0042] Similarly, during the second transfer phase, the second timing signal is asserted high. In response, switch S 21 Open, but switch S 22 and S T2 Closed. Because S 21 is disconnected, so the output 366 of the second operational amplifier A2 is disconnected from the first input 360 of A2, thereby disconnecting the feedback path. And, because S 22 and S T2 are closed, so the feedback capacitor C2 is coupled to the second reference voltage VREF2 , and the first input 360 of A2 is coupled to the first input 386 of the third operational amplifier A3. Therefore, the charge integrated into the feedback capacitor C2 is transferred to the feedback capacitor C3 in the second transfer cycle.

[0043] During the first transfer cycle, the feedback path formed by the feedback capacitor C1 is disconnected. Therefore, during the first transfer cycle, there is no virtual ground at the first input 324 of the first operational amplifier A1 relative to the second input 326 of A1, and the output voltage V O1 is no longer capacitively coupled to the first input 324 of A1. Therefore, due to the absence of a virtual ground, any noise that may be present at the second input 326 of A1 is not present at the first input 324 of A1, and any noise that may be present at the output 328 of A1 is not capacitively coupled to the first input 324 of A1. Therefore, during the first transfer phase, any noise from the first input 324 of A1 or any noise from the output 328 of A1 is not transferred to the third operational amplifier A3. Similarly, during the second transfer phase, any noise from the first input 360 of A2 or any noise from the output 366 of A2 is not transferred to the third operational amplifier A3.

[0044] In some examples, the duration and / or start time of the first transfer period and the second transfer period may be different. In other examples, the first transfer period and the second transfer period may overlap in time (at least partially).

[0045] During the integration phase, the first stage integrator 106 ( 1 , 1 ) temporarily stores the current from the input current I S1 The first stage integrator 106(1,1) transfers the charge to the second stage integrator 108(1) during the transfer phase. Also, during the transfer phase, the first stage integrator 106(1,1) transfers the charge from the parasitic capacitor C PAR_1 However, the first stage integrator 106 (1, 1) does not transfer the output voltage V O1 is transferred to the second stage integrator 108 (1). Therefore, any noise that may be present at the output 328 of A1 (e.g., the output voltage V 01The noise signal in the first stage integrator 108 (1) is not transferred to the second stage integrator 108 (1) and does not degrade the performance of the second stage integrator 108 (1). Therefore, the first operational amplifier A1 can be implemented as a low gain, low bandwidth amplifier, which requires fewer gain stages and transistors than those required for a high gain, large bandwidth amplifier. Similarly, the first stage integrator 106 (2, 1) can be implemented as a low gain, low bandwidth amplifier. Therefore, the described example allows A1 and A2 to be implemented as low gain, low bandwidth amplifiers without reducing the accuracy of data acquisition. There are several benefits to using low gain, low bandwidth amplifiers instead of high gain, large bandwidth amplifiers. Low gain, low bandwidth amplifiers consume much less power than high gain, large bandwidth amplifiers due to their relaxed noise specifications. And, because low gain, low bandwidth amplifiers have a smaller number of transistors, they are cheaper and require less area to implement in an integrated circuit or semiconductor die. If the system requires a very large number (e.g., 10K or 100K) of sensors or pixels, thereby increasing the number of first stage integrators, these advantages may become quite large.

[0046] In one example, the third operational amplifier A3 can be implemented as a high gain, large bandwidth amplifier with low noise (also known as a precision amplifier). Because A3 provides an output voltage V in response to the charge transferred from A1 and A2 OF , so any noise generated by A3 can also be transferred to the output voltage V OF Therefore, it is beneficial to implement A3 as a high gain, large bandwidth amplifier with low noise.

[0047] To ensure that the output voltage of A3 V OF is composed of a first-stage integrator (e.g., Figure 3C The feedback capacitor C3 is connected to the switch S before the transfer cycle. RST Reset. In some instances, the timing signal For control switch S RST Before the transfer cycle, is asserted high, which makes S RST Closed. Thus, the feedback capacitor C3 is short-circuited and discharged or reset. After C3 is reset, is asserted low, which makes S RST Therefore, in the next transfer cycle, the feedback capacitor C3 is charged only by the transferred charge from the first stage integrator, and therefore, the output voltage V of A3 OF represents the transferred charge. In some examples, feedback capacitor C3 can be reset to a known potential by coupling C3 to a known reference voltage.

[0048] In some examples, after the charge is transferred from the first operational amplifier A1 to the third operational amplifier A3 or from the second operational amplifier A2 to A3 and the output voltage V OF After the predetermined duration required for stabilization, the output voltage V OF Can be converted by analog-to-digital converter ( Figures 3A to 3C not described in the sampler) and digitized.

[0049] In some examples, charge from sensors 104(1,1) to 104(M,N) may be transferred sequentially in a frame. Thus, for example, charge may be transferred sequentially from sensors in column number 1, starting with sensor 104(1,1). After the charge transfer from the last sensor in column number 1 (e.g., sensor 104(M,1)), the next frame (e.g., column number 2) may be initiated and the process repeated.

[0050] In some examples, the sensors 104(1,1)-104(M,N), the first stage integrators 106(1,1)-106(M,N), and the second stage integrators 108(1)-108(N) may be implemented in an integrated circuit or semiconductor die. In some examples, the first stage integrators 106(1,1)-106(M,N) and the second stage integrators 108(1)-108(N) may be implemented in an integrated circuit that may be coupled to the sensors 104(1,1)-104(M,N) via external connections, signal traces, wires, or conductors. Other variations are possible within the scope of the present description.

[0051] Figure 4 1 shows the timing signals and voltages in the circuit 300 of the example. The x-axis represents time and the y-axis represents voltage. Initially, at time T0, the timing signal (indicated by reference numeral 404) and (indicated by reference numeral 408) is low, and the timing signal (indicated by reference numeral 412) is high. Therefore, the feedback capacitor C3 of the third operational amplifier A3 is reset. In some examples, C3 is reset to a known voltage (e.g., V R ). Although at time T0, switch S 11 and S 21 closed, but the output of operational amplifier A1, V O1 (indicated by reference numeral 416) and the output V of operational amplifier A2 O2 (indicated by reference numeral 420) are both zero because feedback capacitors C1 and C2 are not fully charged. At time T0, the output V OF (indicated by reference numeral 424) is at V R , because the feedback capacitor C3 is reset to V R .

[0052] At time T1, is asserted high. Therefore, switch S 11 Open, and switch S 21 and S T1 Therefore, C1 is coupled to the second reference voltage V REF2 , and the first input 324 of the first operational amplifier A1 is coupled to the first input 386 of the third operational amplifier A3. Therefore, at time T1, the charge from C1 is transferred to C3, and the output V OF starts to decrease. At time T2, V OF is stabilized and is sampled (indicated by reference numeral 428) and digitized by the ADC.

[0053] At time T3, the charge transfer from C1 to C3 is complete. is asserted low, and is asserted high. Therefore, C3 is reset to V R , and switch S 11 Therefore, the output voltage V OF Rising back to V R .

[0054] At time T4, is asserted high. Therefore, switch S 22 and S T2 Closed, but switch S 21 Therefore, at time T4, the charge transfer from C2 to C3 begins. At time T5, the output V OF Stable, and the ADC is V OF At time T6, the charge transfer from C2 to C3 is complete, and is asserted low. Therefore, V OF Ascend back into VR.

[0055] The circuits described herein may include one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources). The circuits may include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structures at the time of manufacture or after manufacture, for example, by an end user and / or a third party. While some examples may include certain elements implemented in an integrated circuit and other elements external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as being external to the integrated circuit may be included in the integrated circuit, and / or some of the features described as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0056] In this description, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B; or (b) in a second instance, if the intermediate component C does not substantially change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C, so that device B is controlled by device A via the control signal provided by device A. In addition, in this specification, a device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be performed by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnects of the device, or a combination thereof. In addition, in this specification, a circuit or device including certain components may actually be suitable for coupling to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be suitable for coupling to at least some of the passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0057] As used herein, the terms "terminal", "node", "interconnection" and "pin" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnection between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0058] While some examples show certain elements included in the integrated circuit and other elements external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0059] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, metal oxide silicon FETs ("MOSFETs") (e.g., n-channel MOSFETs (nMOSFETs) or p-channel MOSFETs (pMOSFETs)), bipolar junction transistors (BJTs, e.g., NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain extension mode devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0060] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as being external to the integrated circuit may be included in the integrated circuit, and / or some features described as being internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0061] Although some components may be described herein as belonging to a specific process technology, these components may be exchanged with components of other process technologies. The circuits described herein may be reconfigured to include replaced components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the impedance amount represented by the resistors shown. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in series or in parallel between two nodes identical to a single resistor or capacitor, respectively. Moreover, the use of the phrase "ground terminal" in this specification includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, universal grounding, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. Unless otherwise stated, "about", "roughly" or "substantially" before a value represents + / -10% of the stated value, or if the value is zero, represents a reasonable value range near zero.

[0062] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A circuit having a plurality of circuit inputs, at least one of the plurality of circuit inputs being adapted to receive an input current, the circuit having a first reference input adapted to receive a first reference voltage and having a second reference input adapted to receive a second reference voltage, the circuit comprising: a plurality of first stage integrators, each of the plurality of first stage integrators comprising a first input, a second input, a third input and an output, the first input of each of the plurality of first stage integrators being coupled to a different one of the circuit inputs, the second input being coupled to the first reference input, the third input being coupled to the second reference input, and the output of each of the plurality of first stage integrators being coupled to the circuit inputs; A first feedback path of a first stage integrator is coupled to said first input of the first stage integrator; and A second-stage integrator comprises a first input, a second input and an output, wherein the first input of the second-stage integrator is coupled to each of the first inputs of the plurality of first-stage integrators, the second input of the second-stage integrator is coupled to the first reference input, and the output of the second-stage integrator is coupled to the first input of the second-stage integrator through a second feedback path.

2. The circuit of claim 1 , further comprising a plurality of transfer switches, each of the plurality of transfer switches comprising a first terminal and a second terminal, the first terminal of each of the plurality of transfer switches being coupled to a different one of the first inputs of the plurality of first-stage integrators, and the second terminal of each of the plurality of transfer switches being coupled to the first input of the second-stage integrator.

3. The circuit of claim 1 , wherein the first feedback path comprises: a first switch including a first terminal coupled to the output of the first stage integrator and including a second terminal; and A first feedback capacitor includes a first terminal coupled to the first input of the first stage integrator and a second terminal coupled to the second terminal of the first switch.

4. The circuit of claim 3 , wherein each of the plurality of first stage integrators further comprises a second switch comprising a first terminal coupled to the second terminal of the first feedback capacitor of such first stage integrator and a second terminal adapted to receive the second reference voltage.

5. The circuit of claim 1 , wherein each of the plurality of first stage integrators further comprises a changeover switch including a first terminal coupled to the first input of the first stage integrator and a second terminal coupled to the first input of the second stage integrator.

6. The circuit of claim 1, wherein the second feedback path comprises a second feedback capacitor comprising a first terminal coupled to the first input of the second stage integrator and a second terminal coupled to the output of the second stage integrator.

7. The circuit of claim 1, wherein the second stage integrator comprises a reset switch including a first terminal coupled to the first input of the second stage integrator and a second terminal coupled to the output of the second stage integrator.

8. The circuit of claim 7, wherein the reset switch is configured to reset the second feedback capacitor.

9. A circuit having a circuit input adapted to receive an input current, the circuit having a first reference input adapted to receive a first reference voltage and having a second reference input adapted to receive a second reference voltage, the circuit comprising: a first stage integrator comprising a first input coupled to the circuit input, a second input coupled to the first reference input, a third input coupled to the second reference input, and an output coupled to the first input of the first stage integrator via a first feedback path; a changeover switch including a first terminal coupled to the first input of the first stage integrator and including a second terminal; and A second stage integrator includes a first input coupled to the second terminal of the changeover switch, a second input coupled to the first reference input, and an output coupled to the first input of the second stage integrator through a third feedback path.

10. The circuit of claim 9, wherein the first feedback path comprises: a first switch including a first terminal coupled to the output of the first stage integrator and including a second terminal; and A first feedback capacitor includes a first terminal coupled to the first input of the first stage integrator and a second terminal coupled to the second terminal of the first switch.

11. The circuit of claim 9, wherein the second feedback path comprises a second feedback capacitor comprising a first terminal coupled to the first input of the second stage integrator and a second terminal coupled to the output of the second stage integrator.

12. The circuit of claim 9, wherein the second stage integrator comprises a reset switch including a first terminal coupled to the first input of the second stage integrator and a second terminal coupled to the output of the second stage integrator.

13. A circuit having a circuit input adapted to receive an input current, the circuit having a first reference input adapted to receive a first reference voltage and having a second reference input adapted to receive a second reference voltage, the circuit comprising: a first amplifier comprising a first input coupled to the circuit input, a second input coupled to the first reference input, and comprising an output; a first switch including a first terminal coupled to the output of the first amplifier and including a second terminal; a first feedback capacitor comprising a first terminal coupled to the first input of the first amplifier and a second terminal coupled to the second terminal of the first switch; a second switch comprising a first terminal coupled to the second terminal of the first feedback capacitor and a second terminal coupled to the second reference input; a changeover switch including a first terminal coupled to the first input of the first amplifier and including a second terminal; a second amplifier comprising a first input coupled to the second terminal of the changeover switch, a second input coupled to the first reference input, and comprising an output; and A second feedback capacitor includes a first terminal coupled to the first input of the second amplifier and a second terminal coupled to the output of the second amplifier.

14. The circuit of claim 13, further comprising a reset switch comprising a first terminal coupled to the first terminal of the second feedback capacitor and a second terminal coupled to the second terminal of the second feedback capacitor.

15. A circuit having a plurality of circuit inputs, at least one of the plurality of circuit inputs being adapted to receive an input current, the circuit having a first reference input adapted to receive a first reference voltage and having a second reference input adapted to receive a second reference voltage, the circuit comprising: a plurality of first stage integrators, wherein each first stage integrator of the plurality of first stage integrators comprises a first input coupled to a different one of the circuit inputs, a second input coupled to the first reference input, a third input coupled to the second reference input, and an output coupled to the first input of such first stage integrator through a first feedback path; and A second stage integrator includes a first input coupled to the first input of each of the plurality of first stage integrators, a second input coupled to the first reference input, and an output coupled to the first input of the second stage integrator through a second feedback path.

16. The circuit of claim 15, wherein each of the plurality of first stage integrators further comprises a changeover switch including a first terminal coupled to the first input of such first stage integrator and a second terminal coupled to the first input of the second stage integrator.

17. The circuit of claim 15, further comprising a reset switch comprising a first terminal coupled to the first terminal of the second stage integrator and a second terminal coupled to the output of the second stage integrator.

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