Column-based memory (MRAM) embedded within embedded power rail within reverse power distribution network

Abstract

An apparatus comprising a backside power distribution network; a backside power rail joined to the backside power distribution network; and a backside contact via coupling a front end of at least one line transistor to the backside power rail; wherein the backside contact via includes a pillar-based memory device.

Description

Background Art

[0001] The exemplary embodiments described herein relate generally to semiconductor device design and integrated circuit design, and more particularly, to pillar-based memory (MRAM) embedded within a buried power rail within a backside power distribution network.

[0002] In some systems, there may be an integration of MRAM devices with TSVs, placing the MRAM far from the corresponding transistor. However, it is desirable to place the MTJ near the transistor to minimize RC delay for last level cache applications to replace eDRAM. Furthermore, in some systems, the MRAM device is not directly connected to the backside contacts connected to the transistor, but it may be advantageous to connect the MRAM directly to the backside contacts connected to the transistor, for example to improve upon that described by U.S. Patent 10,916,583 B2. Summary of the invention

[0003] In one aspect, an apparatus includes a backside power distribution network; a backside power rail coupled to the backside power distribution network; and a backside contact via coupling a front end of at least one line transistor to the backside power rail; wherein the backside contact via includes a pillar-based memory device.

[0004] In another aspect, a method includes forming a backside power distribution network; joining a backside power rail to the backside power distribution network; and forming a contact via coupling a front end of at least one line transistor to the backside power rail; wherein the contact via includes a pillar-based memory device.

[0005] On the other hand, an apparatus includes a transistor including a source or a drain; a backside contact coupled to the transistor; and a memory device formed at the back side of a wafer, the memory device including an electrode; wherein the electrode of the memory device is directly connected to the backside contact of the transistor.

[0006] In another aspect, a method includes forming a first sacrificial placeholder in a first region of a wafer below a source or drain region of at least one transistor in the first region; forming a second sacrificial placeholder in a second region of the wafer below a source or drain region of at least one transistor in the second region; wherein the first sacrificial placeholder is formed deeper in the wafer than the second sacrificial placeholder; flipping the wafer; removing the first sacrificial placeholder to form a first empty region; forming a first backside contact and electrode for a memory device in at least a portion of the first empty region, the first backside contact contacting the source or drain of at least one transistor in the first region; depositing and patterning a memory device in at least a portion of the first empty region; removing the second sacrificial placeholder to form a second empty region; and forming a second backside contact in at least a portion of the second empty region, the second backside contact contacting the source or drain of at least one transistor in the second region.

[0007] In another aspect, a semiconductor device includes a first region including a first backside contact to couple at least one transistor of the first region to a memory device of the first region and a second region including a second backside contact to couple at least one transistor of the second region to a backside power rail of the second region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The foregoing and other aspects of the exemplary embodiments will become more apparent in the following detailed description when read in conjunction with the accompanying drawings, in which:

[0009] Figure 1 depicts vias to buried power rails, which are part of the backside power distribution network;

[0010] Figure 2 A starting structure substrate with n capping layers of epitaxial silicon germanium / silicon stacks is depicted;

[0011] Figure 3 Nanosheet patterning is depicted;

[0012] Figure 4 Depicting the formation of STI layers and nanosheet stack fin exposure;

[0013] Figure 5 Depicts continued and completed FEOL integration;

[0014] Figure 6 depicts the MOL processing, which includes forming contacts to the source drain and vias to the buried power rail connections;

[0015] Figure 7 shows a cross-sectional view between the gates in the source-drain region;

[0016] Figure 8Depicts continued BEOL processing;

[0017] Fig. 9 depicts completion of BEOL processing and bonding to a carrier wafer;

[0018] Fig.10 Flipping the wafer is described;

[0019] Fig.11 Depicting starting substrate thinning and stopping on an etch stop layer;

[0020] Fig.12 depicting removal of an etch stop layer;

[0021] Fig.13 depicts etching and applying CMP to portions of the silicon layer to expose backside via contacts;

[0022] Fig.14 A recessed MRAM backside via contact is described;

[0023] Fig.15 depicts filling a backside via recess with one or more non-magnetic materials;

[0024] Fig.16 Describes the application of CMP susceptor materials;

[0025] Fig.17 Deposition of a hard mask is depicted;

[0026] Fig.18 MTJ patterning is depicted;

[0027] Fig.19 Depicts encapsulation / etch-back for protecting MTJ sidewalls and for exposing block shape;

[0028] Fig. 20 Depicts selective exfoliation of bar block shapes;

[0029] Fig.21 Depicts the use of ILD to perform fill followed by CMP;

[0030] Fig. 22 Depicted is backside ILD fill followed by buried power rail patterning and metallization;

[0031] Fig.23 The MRAM backside power distribution network is described;

[0032] Fig.24 Semiconductor devices are depicted;

[0033] Fig.25Depicts the logic and MRAM regions after nanosheet stack patterning, STI formation, gate patterning, BDI / spacer formation, nanosheet recessing, and internal spacer formation;

[0034] Fig.26 Placeholder patterning is depicted;

[0035] Fig. 27 depicts the use of a block mask to open up the MRAM region to increase the placeholder depth;

[0036] Fig.28 depicts the placeholder material filling;

[0037] Fig.29 The fabrication of a depression of placeholder material is depicted;

[0038] Fig.30 Depicts source / drain epitaxial formation, ILD deposition, and CMP;

[0039] Fig.31 Depicts dummy gate removal, SiGe removal, replacement HKMG formation, MOL / BEOL interconnect formation, and carrier wafer bonding;

[0040] Fig.32 depicts wafer flipping, substrate removal, and stopping on etch stop layer;

[0041] Fig.33 depicts etch stop layer and silicon removal;

[0042] Fig.34 Backside ILD deposition and CMP are depicted;

[0043] Fig.35 depicts the removal of exposed placeholders;

[0044] Fig.36 depicts forming contacts including silicide liner, adhesive liner, and metal fill;

[0045] Fig.37 depicts the fabrication of the backside contact recess;

[0046] Fig.38 Depicting filling of bottom electrode material for MRAM;

[0047] Fig.39 Depicted is the MRAM stack deposition;

[0048] Fig.40 Depicted is MRAM patterning via IBE;

[0049] Fig.41 Depicts MRAM protective spacer deposition and RIE;

[0050] Fig.42 depicts placeholder removal;

[0051] Fig.43 Backside contact fill and depression are depicted;

[0052] Fig.44 The formation of the dorsal track and dorsal interconnect formation are depicted;

[0053] Fig.45 is a logic flow diagram illustrating a method of forming a pillar-based memory device having buried power rails and a backside power distribution network; and

[0054] Fig.46 is a logic flow diagram illustrating a method of forming a semiconductor device. DETAILED DESCRIPTION

[0055] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. All of the embodiments described in this detailed description are exemplary embodiments provided to enable those skilled in the art to make or use the invention, rather than to limit the scope of the invention as defined by the claims.

[0056] A pillar-based memory (MRAM) embedded in a buried power rail within a backside power distribution network is described herein. Specifically, a semiconductor structure having a buried power rail and a backside power distribution network is described herein. The structure includes a contact via connecting a FEOL transistor to the backside power rail. A pillar-based memory device is formed within the contact via. The via may include a magnetic material (such as cobalt). The memory may be an MRAM device. The portion of the magnetic contact via that forms a bottom contact for the MRAM device has a non-magnetic conductive spacer (such as titanium nitride) between the MRAM device and the via. In other embodiments, the contact via may include a non-magnetic conductive material. Alternatively, the memory may be a PCM or a ReRAM.

[0057] Also described herein is a method of forming a pillar-based memory device within a buried power rail and a backside power distribution network.

[0058] Thus, the examples described herein relate to MRAM integrated on the backside of a wafer, wherein the backside power distribution network / buried power rail is located on the backside of the wafer. A non-magnetic bottom electrode contacts the MRAM device, which utilizes operation to avoid disturbances.

[0059] The device described herein has high value attributes and technical effects. Specifically, the structure forming the MRAM is very close to the corresponding transistor, which minimizes the RC delay. Possible applications are last-level caches, i.e., 14 nm, 7 nm, 5 nm, 3 nm technology nodes. No additional space is required because the structure can be integrated in existing unused space.

[0060] MRAM is an emerging memory technology that is integrated in older, current, and future technology nodes (14 nm and below). High-performance MRAM integration is severely challenged at 14 nm and below nodes due to the minimum vertical height. While in some systems, there can be heterogeneous integration of MRAM with TSVs, placing the MRAM far away from the corresponding transistors, the MTJ needs to be placed close to the transistor to minimize RC delays for last-level cache applications to replace eDRAM. Alternatives such as skipping the level between M1 and M3 have significant integration issues and also move the top contact away from the transistor.

[0061] The examples described herein place an MRAM pillar together with vias and a backside power distribution network for buried power rails. Portions of the magnetic contact vias (e.g., cobalt) are replaced with non-magnetic conductive spacers (e.g., titanium nitride) to form the bottom contact for the MRAM pillar.

[0062] Figure 1 1 is an example semiconductor device 100. Semiconductor device 100 is a through via buried power rail to backside power distribution network device. BEOL 104 is bonded to the surface of carrier wafer 102. Via 112 connects contact 108 to buried power rail 118. STI 114 is formed in the initial substrate, and buried power rail 118 is formed subsequently. Backside via 112 is formed within STI 114. Silicon 110 is the remaining silicon from the initial silicon substrate. Backside power distribution network 120 is formed on one side of buried power rail 118 and ILD 116. Source / drain contact 106 is coupled to source / drain 105, and source / drain contact 108 is coupled to source / drain 107.

[0063] Figure 2 A starting structure substrate with n capping epitaxial SiGe / Si stacks 216 is depicted. A sacrificial etch stop layer 204 is applied between the substrate 202 and the silicon layer 206. The sacrificial etch stop layer 204 may include BOX, silicon germanium (SiGe), or phosphorus-doped silicon (Si:P). Figure 2 In the example shown, the silicon / silicon germanium nanosheet stack 216 includes four layers of silicon germanium (silicon germanium 208, silicon germanium 210, silicon germanium 212, silicon germanium 214).

[0064] Figure 3 Nanoflake patterning is depicted. Several etches (etch 302, etch 304, etch 306, etch 308, etch 310, etch 312) are made in a structure having silicon 206 and silicon / silicon germanium nanoflake stack 216. As shown, hard masks (hard mask 314, hard mask 316, hard mask 318, hard mask 320, hard mask 322) are made on one side of the etched silicon / silicon germanium nanoflake stack 216.

[0065] Figure 4 Depicted is the formation of an STI layer and fin exposure. An STI layer 402 is formed on one side of the silicon layer 206 and within the etching (etch 302, etch 304, etch 306, etch 308, etch 310, etch 312). The hard masks (hard mask 314, hard mask 316, hard mask 318, hard mask 320, hard mask 322) are removed to expose the fins (fin 412, fin 414, fin 416, fin 418, fin 420).

[0066] Figure 5 Continuing and completing FEOL integration is described. ILD layer 502 is formed beside (eg, over) STI layer 402 and between epitaxial-based fins (fin 504 , fin 506 , fin 508 , fin 510 , fin 512 ).

[0067] Figure 6 The MOL process including forming contacts and VBPR connections to the source and drain is depicted. Multiple source / drain contacts (contact 604, contact 606, contact 608, contact 610, contact 612) are fabricated next to (e.g., above) the epitaxial-based fins (fin 504, fin 506, fin 508, fin 510, fin 512) within the ILD layer 502. Two vias (via 601, via 602) connect the source / drain contacts (contact 606, contact 610) to the silicon layer 206 through the ILD layer 502 and the STI layer 402.

[0068] Figure 7 A cross-sectional view between the gates in the source-drain region is shown. A dummy gate line 702 interrupted by a gate cutout 704 is shown, as well as additional source / drain contacts (contact 605, contact 607) and active device layer 706 spanning source / drain contacts 606, source / drain contacts 604 and dummy gate line 702. A cross-sectional view of source / drain contacts 606, vias 601, and source / drain contacts 607 is depicted.

[0069] Figure 8Continuation of BEOL processing is depicted. A layer of BEOL 802 is formed next to (e.g., above) source / drain contacts (contact 604, contact 606, contact 608, contact 610, contact 612). A plurality of vias (via 802, via 804, via 806, via 808, via 810, via 812) are formed within BEOL layer 802, wherein via 802 is formed on one side of source / drain contact 604, via 808 is formed on one side of source / drain contact 608, and via 812 is formed on one side of source / drain contact 612.

[0070] Fig. 9 Depicted is completion of BEOL processing and bonding to a carrier wafer. Another BEOL layer 902 is formed next to BEOL layer 802, which is located next to vias (via 802, via 804, via 806, via 808, via 810, via 812). BEOL layer 902 is bonded to carrier wafer 904.

[0071] Fig.10 Flipping (1002) the wafer 1004 is depicted so that the carrier wafer 900 that was previously on one side is on a different side, and the starting substrate 202 that was previously on a different side is on one side.

[0072] Fig.11 Depicted is starting substrate thinning and stopping on an etch stop layer (buried oxide, silicon germanium, phosphorus doped silicon).Substrate 202 is thinned and removed. Fig.12 Removal of etch stop layer 204 is depicted.

[0073] Fig.13 Depicted is etching and applying CMP to portions of silicon layer 206 to expose via contacts (contact 602, contact 601). Fig.13 shows an embodiment where the through-hole contact 601 is not recessed and the pedestal / MTJ (MTJ 2316 / MTJ 1802, cf. Fig.23 and Fig.18 ) is directly on the via contact 601 (e.g., a relatively Fig.13 With μ column 1504 Fig.23 ). The disadvantage of this embodiment is that if the through-hole contact 601 is made of a magnetic material (ie, cobalt), the MTJ stack (MTJ stack 2304, MTJ stack 2312, MTJ stack 1908, see Fig.23 ) to compensate for the magnetic field from the through hole 601. Fig.13 , through hole 601 is for the buried power rail (buried power rail 2308, reference Fig.23 ) through holes.

[0074] Fig.14 A recessed MRAM via contact 601 is depicted (e.g., the recess 1402 is greater than 10 nanometers). Thus, the via contact 601 is recessed. In this embodiment, the recessed MRAM via contact 601 prevents the MTJ (MTJ 1802, referenced to FIG. 1802 ) from being exposed to possible common contact metal (magnetic) in the via 601. Fig.18 ) magnetic field interference. Fig.14 Also depicted is the fabrication of wet-strippable patterned block shapes 1404 (ie, sacrificial SiN) fabricated on the surface of the STI layer 402 , portions of the silicon layer 206 , and the via contacts 602 .

[0075] Fig.15 Depicted is the filling of the via recess 1402 with one or more non-magnetic materials (titanium (Ti), titanium nitride (TiN), titanium alloy (Ta), titanium aluminum nitride (TaN), etc.) 1502. The one or more non-magnetic materials 1502 are also fabricated on the wet-strippable patterned block shapes 1404, the STI layer 402, and the silicon layer 206. The one or more non-magnetic materials 1502 within the recess 1402 form μ-pillars 1504.

[0076] Fig.16 The application of CMP pedestal material 1602 is depicted to ensure a smooth surface entering the MTJ deposition. This embodiment does not require the pedestal 2316 to be coplanar over the block shape (e.g., see item 1604). Fig.13 The illustrated embodiment without the recessed via contact 601 appears similar but without the μ-pillars 1504 formed using one or more non-magnetic materials 1502 .

[0077] Fig.17 Depicted is the deposition of a hard mask 1702 (eg, a patterned hard mask), and the fabrication of a RIE layer 1704 over the pedestal layer 1602 .

[0078] Fig.18 Patterning (IBE) is depicted to form MTJ 1802. Partially etched block shape 1404 prevents etching into vias (e.g., via 602), STI 402, and silicon 206 (if desired). Fig.18 As shown in FIG. 4 , two etches (etch 1804 , etch 1806 ) occur in STI 402 and silicon 206 .

[0079] Fig.19 Encapsulation / etch-back is depicted for protecting the MTJ sidewalls (sidewalls 1904, 1906) and for exposing the block shape 1404. Encapsulation spacers 1902 protect the sidewalls (sidewalls 1904, 1906) of the MTJ 1802. MRAM 1908 is formed.

[0080] Fig. 20 Depicted is selective etching (etch 2002) of block shapes 1404 without etching STI 402, silicon 206, at least a portion of silicon nitride encapsulation 1404, and via metal 602. Fig.21 Filling with ILD 2102 followed by CMP is depicted. Fig. 22 Backside ILD fill (fill 2102) is depicted, followed by buried power rail patterning and metallization (patterning and metallization 2202, patterning and metallization 2204, patterning and metallization 2206). Spacers 1902 around MTJ 1802 can be silicon boron carbon nitride (SiBCN), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxynitride (SiON), or other high quality silicon nitride (SiN) material, to which SiN block 1404 can be selectively etched. Block shape 1404 is a wet removable sacrificial SiN (e.g., silicon carbon nitride (SiCNH) or silicon nitride (SiNH) hydride). Wet removal is performed using dilute HF.

[0081] Fig.23 An MRAM backside power distribution network 2300 is depicted, including a backside power distribution network 2302 and an MRAM 2304. The MRAM backside power distribution network 2300 may be referred to as an MRAM buried power rail, an embedded MRAM buried power rail, or a memory buried power rail. The buried power rail 2308 is coupled to a via including via 601, μ-pillars 1504, and a pillared via 2312 including MRAM 1908. The buried power rail 2308 is also coupled to the backside power distribution network 2302. The via 601 and μ-pillars 1504 couple transistor 2314 to MRAM 1908. The pedestal 2316 is formed of the pedestal material / layer 1602.

[0082] This article also describes MRAM integration with self-aligned backside contacts. There is great interest in forming MRAM close to the S / D to increase speed. Backside direct contacts offer great opportunities to move MRAM very close to the device. However, there is a great risk that backside sputtering of the backside contact metal will reduce the MRAM yield.

[0083] In one embodiment, a method of forming a semiconductor device includes forming a sacrificial placeholder deeper than the S / D of a logic transistor under an MRAM transistor, flipping the wafer after MOL / BEOL fabrication, first removing the sacrificial placeholder in the MRAM region, forming a backside contact and bottom electrode for the MRAM in the empty placeholder region, depositing and patterning an MRAM stack, removing the sacrificial placeholder in the logic region, and forming a backside contact and backside interconnect. The method provides a promising solution for the integration of MRAM with self-aligned backside contacts.

[0084] The present invention also describes a semiconductor device including an MRAM formed at the back side of a wafer, wherein the bottom electrode of the MRAM is directly connected to the back side contact of a transistor. The back side contact is substantially aligned with the bottom electrode of the MRAM. The back side contact is substantially aligned with the S / D of the transistor. The back side contact is isolated from the gate metal by a BDI and an internal spacer. There is also a back side contact for the transistor in the logic area, wherein the back side contact in the logic area has an upper surface lower than the lower surface of the MRAM spacer.

[0085] Fig.24 A semiconductor device is depicted. Fig.24 Provided by U.S. Patent 10,916,583B2 Figure 3 C. The first ("front") substrate includes front back end layer 40 and device layer 4, and the second ("back") substrate includes back back end layer 52. Front back end layer 40 includes interconnect layer 38, interconnect layer 36, and interconnect layer 32. Device layer 4 includes ILD 28 and substrate 99. Back back end layer 52 includes substrate 50, interconnect layer 54, and interconnect layer 58.

[0086] The interconnect layer 38 includes an interconnect (bit line) 35 and an interconnect 34 connected to a reference layer of the interconnect layer 36. The interconnect layer 36 includes a SHE-MRAM 42, wherein the SHE-MRAM 42 includes a reference layer, a barrier layer, a free layer, and a spin filter. The spin filter of the interconnect layer 36 is bonded to the interconnect 34 of the interconnect layer 32. The interconnect 34 is shared with the interconnect layer 32 and the ILD 28, and is bonded to the gate 24 of the ILD 28. The gate 24 of the ILD 28 is bonded to the logic transistor 12 of the substrate 99, and the logic transistor 12 includes a source 16 and a drain 20.

[0087] The backside contact 2 of substrate 99 contacts logic transistor 12 and is coupled to interconnect 56 of substrate 50. STT-MRAM device 60 of interconnect layer 54 includes a reference layer, a barrier layer, and a free layer. The interconnect of interconnect layer 54 is bonded to interconnect 56 of interconnect layer 58, which also includes interconnect bit line 57. Fig.24 In FIG. 6 , the MRAM device 60 is not directly connected to the backside contact 2 . Fig.24 and Fig.44 In contrast to the semiconductor device shown in Fig.44 The semiconductor device shown in is the result of the semiconductor manufacturing method described herein. Fig.44 The MRAM device 4414 is shown connected directly to the backside contact 3602 .

[0088] Fig.25Depicted are a logic region 2501 of a wafer 2551 and an MRAM region 2502 of a wafer 2551 after nanosheet stack patterning, STI formation, gate patterning, BDI / spacer formation, nanosheet recessing, and internal space formation. The logic region 2501 includes a silicon substrate 2503, an etch stop layer 2505 (e.g., BOX, silicon oxide, or silicon germanium), and a silicon layer 2507. The logic region 2501 also includes a BDI layer 2509, a silicon layer 2515 for bonding a dummy gate 2517 to silicon germanium 2511, which is included in an internal spacer 2513. The spacer 2521 encapsulates the dummy gate 2517 and the hard mask 2519. Structure 2525 and structure 2527 are constructed similarly to structure 2523, including silicon germanium 2511, inner spacer 2513, silicon 2515, dummy gate 2517, hard mask 2519, and spacer 2521 (ie, include similar components).

[0089] The MRAM region 2502 includes a silicon substrate 2504, an etch stop layer 2506 (such as BOX, silicon oxide, or silicon germanium), and a silicon layer 2508. The MRAM region 2502 also includes a BDI layer 2510, a silicon layer 2516 for bonding a dummy gate 2518 to silicon germanium 2512, which is included in an inner spacer 2514. The spacer 2522 encapsulates the dummy gate 2518 and the hard mask 2520. The structures 2526 and 2528 are constructed similarly to the structure 2524, including the silicon germanium 2512, the inner spacer 2514, the silicon 2516, the dummy gate 2518, the hard mask 2520, and the spacer 2522 (i.e., including similar components).

[0090] Fig.26 Placeholder patterning is depicted, including applying an OPL layer 2601 within the logic region 2501 and applying an OPL layer 2602 within the MRAM region 2502, and etching a placeholder region 2603 within the BDI layer 2509 and, in some cases, etching the silicon layer 2507 of the logic region 2501, and etching a placeholder region 2604 within the BDI layer 2510 and, in some cases, etching the silicon layer 2508 of the MRAM region 2502.

[0091] Fig. 27 Depicted is the use of a block mask to open up the MRAM region 2502 to increase the placeholder depth of region 2604. The depth of the placeholder region 2604 for the MRAM is increased by approximately the amount shown by item 2702. Fig. 27 Also shown in FIG. 25 is the application of an OPL layer 2704 within the placeholder region 2603 of the logic region 2501 and between the structure 2523 and the structure 2525 . Fig. 27 Also shown in FIG. 2 is the removal of the OPL to create a placeholder region 2706 within the MRAM region 2502 .

[0092] Fig.28 A placeholder material fill is depicted (eg, titanium oxide (TiOx) or aluminum oxide (AlOx). Placeholder fill 2801 is applied in logic region 2501 , and placeholder fill 2802 is applied in MRAM region 2502 .

[0093] Fig.29 The fabrication of a recess of placeholder material, removing portions of placeholder fill 2801 and creating placeholder 2901 , and removing portions of placeholder fill 2802 and creating placeholder 2902 are depicted.

[0094] Fig.30 S / D epi formation, ILD deposition, and CMP are depicted. S / D epi 3001 and S / D epi 3003 are formed in logic region 2501, and S / D epi 3002 and S / D epi 3004 are formed in MRAM region 2502. S / D epi 3001 is formed in S / D region 3011, and S / D epi 3002 is formed in S / D region 3012. ILD 3005 is formed beside (e.g., above) S / D epi 3001, ILD 3007 is formed beside (e.g., above) S / D epi 3003, ILD 3006 is formed beside (e.g., above) S / D epi 3002, and ILD 3008 is formed beside (e.g., above) S / D epi 3004. Hard mask 2519 and hard mask 2520 are removed, as are the hard masks removed from structure 2525 , structure 2527 , structure 2526 , and structure 2528 .

[0095] Fig.31Depicted are dummy gate removal, silicon germanium removal, replacement high-k / metal gate (HKMG) formation, MOL / BEOL interconnect formation, and carrier wafer bonding. Specifically, dummy gate 2517 and dummy gate 2518 are removed, as are dummy gates from structures 2525, 2527, 2526, and 2528. Silicon germanium 2511 and silicon germanium 2512 are removed. HKMG 3107, HKMG 3109, HKMG 3111, HKMG 3108, HKMG 3110, and HKMG 3112 are formed to replace the removed dummy gates and silicon germanium. In the logic region 2501, BEOL 3103 is formed to bond the carrier wafer 3101 to an additional ILD layer 3113 formed next to (e.g., above) HKMG 3107, HKMG 3109, and HKMG 3111. BEOL 3103 is also bonded to contacts 3105 bonded to S / D epi 3003. Source / drain contacts 3105 are formed within ILD layer 3113 and ILD layer 3007. Similarly, in MRAM region 2502, BEOL 3104 is formed to bond carrier wafer 3102 to additional ILD layer 3114 formed beside (e.g., above) HKMG 3108, HKMG 3110, and HKMG 3112. BEOL 3104 is also bonded to source / drain contacts 3106, which are bonded to S / D epi 3004. Source / drain contacts 3106 are formed within ILD layer 3114 and ILD layer 3008.

[0096] Fig.32 Wafer flipping, substrate removal, and stopping on an etch stop layer are depicted. The logic region wafer is flipped (flip 3201) and the MRAM region wafer is flipped (flip 3202), resulting in flipped wafer 2551. Silicon substrate 2503 is removed (depicted as item 3203) from logic region 2501, and silicon substrate 2504 is removed (depicted as item 3204) from MRAM region 2502.

[0097] Fig.33 Etch stop layer and silicon removal are depicted. Specifically, silicon layer 2507 is removed (depicted as item 3301) from logic region 2501, and silicon layer 2508 is removed (depicted as item 3302) from MRAM region 2502. Etch stop layer 2505 is removed (depicted as item 3303) from logic region 2501, and etch stop layer 2506 is removed (depicted as item 3304) from MRAM region 2502.

[0098] Fig.34Backside ILD deposition and CMP are depicted. ILD layer 3401 is formed on the backside of logic region 2501, which is next to BDI layer 2509 to encapsulate placeholder 2901. ILD layer 3402 is formed on the backside of MRAM region 2502, which is next to BDI layer 2510 to encapsulate placeholder 2902. Fig.35 The exposed placeholder is depicted removed to form region 3502 .

[0099] Fig.36 Depicted is forming contacts 3602. Forming contacts 3602 includes application of a silicide liner (liner 3604, liner 3606), such as titanium and an adhesion liner titanium nitride (TiN) and a metal fill 3608, such as cobalt and CMP. Fig.37 The fabrication of the backside contact recess 3702 is depicted. Fig.38 Filling of the recess 3702 with a bottom electrode material for the MRAM to produce a bottom electrode 3802 is depicted. Fig.39 An MRAM stack deposition 3901 in the logic region 2501 and an MRAM stack deposition 3902 in the MRAM region 2502 are depicted.

[0100] Fig.40 MRAM patterning by IBE is depicted. In logic region 2501, MRAM stack deposition 3901 is removed and a portion of backside interlayer dielectric 3401 (represented by 4001) is removed. The benefit is that placeholder 2901 is buried in backside interlayer dielectric 3401 so that there is no post-sputtering. In MRAM region 2502, MRAM patterning includes creating region 4002 and region 4004 by removing a portion of backside interlayer dielectric 3402 and MRAM stack deposition 3902. A hard mask 4006 is applied to one side of the remaining portion of MRAM stack deposition 3902.

[0101] Fig.41 MRAM protection spacer deposition and RIE are depicted. MRAM protection spacers 4102 are formed on the sides of hard mask 4006, MRAM stack deposition 3902, and backside interlayer dielectric 3402. Etching backside interlayer dielectric 3402 creates regions 4104 and 4106. Fig.42 Placeholder removal is depicted to remove placeholder 2901 from logic region 2501 to generate region 4201 . Fig.43 Back side contact filling and recessing are depicted to generate back side contact 4301 and recess 4303.

[0102] Fig.44The formation of the backside rails and the backside interconnect formation are depicted. In the logic region 2501, the backside power rail 4401 is connected to the backside contact 4301 and to the via 4403 that joins the backside power rail 4401 to the backside interconnect 4405. The backside interlayer dielectric layer 3401 is enhanced (enhancement 4407) so that the backside interlayer dielectric layer (backside interlayer dielectric layer 3401, backside interlayer dielectric layer 4407) encapsulates the backside power rail 4401 and the via 4403. In the MRAM region 2502, the backside interlayer dielectric layer 3402 is enhanced (enhancement 4408). In the MRAM region 2502, vias 4404 connect the backside interconnect layer 4406 to the MRAM stack deposition 3902 through the backside interlayer dielectric layer (backside interlayer dielectric layer 3402, backside interlayer dielectric layer 4408) and the hard mask 4006. The backside interlayer dielectric layer (backside interlayer dielectric layer 3402, backside interlayer dielectric layer 4408) encapsulates the vias 4404, the hard mask 4006, the spacers 4102, the MRAM stack deposition 3902, the bottom electrode 3802, and at least a portion of the backside contact 3602. Also shown are the S / D 4410 of the transistor 4412, the S / D 4409 of the transistor 4411, and the memory device 4414. In Fig.44 , the MRAM device 4414 is directly connected to the backside contact 3602.

[0103] Fig.45 4500 is a logic flow diagram illustrating a method of forming a pillar-based memory device having a buried power rail and a backside power distribution network. At 4510, the method includes forming a backside power distribution network (backside power distribution network 2302). At 4520, the method includes joining a backside power rail (backside backside power rail 2308) to the backside power distribution network (backside power distribution network 2302). At 4530, the method includes forming a contact via (contact via 601, contact via 1504, contact via 2312) coupling a front end of at least one line transistor (line transistor 2314) to the backside power rail (backside backside power rail 2308). At 4540, the method includes wherein the contact via (contact via 601, contact via 1504, contact via 2312) includes a pillar-based memory device (1908).

[0104] Fig.464600 is a logic flow diagram illustrating a method of forming a semiconductor device. At 4610, the method includes forming a first sacrificial placeholder (sacrificial placeholder 2902) in a first region (region 2502) of a wafer (wafer 2551) below a source or drain region (source or drain region 3012) of at least one transistor (transistor 4412) in the first region (region 2502). At 4620, the method includes forming a second sacrificial placeholder (sacrificial placeholder 2901) in a second region (region 2501) of the wafer (wafer 2551) below a source or drain region (source or drain region 3011) of at least one transistor (transistor 4411) in the second region (region 2501). At 4630, the method includes wherein the first sacrificial placeholder (sacrificial placeholder 2902) is formed deeper within the wafer (wafer 2551) than the second sacrificial placeholder (sacrificial placeholder 2901). At 4640, the method includes flipping (flip 3201, flip 3202) the wafer (wafer 2551). At 4650, the method includes removing the first sacrificial placeholder (sacrificial placeholder 2902) to form a first empty region (region 3502). At 4660, the method includes forming a first backside contact (backside contact 3602) and an electrode (electrode 3802) for a memory device (memory device 4414) in at least a portion of the first empty region (region 3502), the first backside contact (backside contact 3602) contacting a source (source or drain 4410) or a drain (source or drain 4410) of at least one transistor (transistor 4412) of the first region (region 2502). At 4670, the method includes depositing and patterning a memory device (memory device 4414) in at least a portion of the first empty region (region 3502). At 4680, the method includes removing the second sacrificial placeholder (sacrificial placeholder 2901) to form a second empty region (region 4201). At 4690, the method includes forming a second backside contact (backside contact 4301) in at least a portion of the second empty region (4201), the second backside contact (backside contact 4301) contacting a source (source or drain 4409) or a drain (source or drain 4409) of at least one transistor (transistor 4411) of the second region (region 2501).

[0105] Now referring to all of the accompanying drawings, in one exemplary embodiment, an apparatus includes a backside power distribution network; a backside power rail that is joined to the backside power distribution network; and a backside contact via that couples a front end of at least one line transistor to the backside power rail; wherein the backside contact via includes a pillar-based memory device.

[0106] The portion of the backside contact via couples the source or drain to the memory device. The apparatus may also include a non-magnetic conductive spacer between the memory device and the portion of the backside contact via. The memory device may be directly connected to the portion of the backside contact via. The memory device may include at least one of: a magnetoresistive random access memory; a phase change memory; or a resistive random access memory.

[0107] In another embodiment, a method includes forming a backside power distribution network; joining a backside power rail to the backside power distribution network; and forming a contact via coupling a front end of at least one line transistor to the backside power rail; wherein the contact via includes a pillar-based memory device.

[0108] The method may also include forming a recess in the contact via; and filling the recess with at least one non-magnetic material to form a non-magnetic conductive spacer between the memory device and the non-recessed portion of the contact via. The method may also include forming a memory device, which is formed using a method including: applying at least one non-magnetic base material to a shallow trench isolation layer that encapsulates at least a portion of the contact via; depositing a hard mask to the non-magnetic base material; forming a magnetic channel node between the non-magnetic base material and the hard mask; and forming an encapsulation spacer along at least one wall of the magnetic channel node. The method may also include applying a block shape to the shallow trench isolation layer, wherein the block shape prevents etching into selected portions of the contact via, the shallow trench isolation layer, and the silicon layer. The memory device may include at least one of the following: a magnetoresistive random access memory; a phase change memory; or a resistive random access memory.

[0109] In another embodiment, an apparatus includes a transistor including a source or a drain; a backside contact coupled to the transistor; and a memory device formed at the backside of a wafer, the memory device including an electrode; wherein the electrode of the memory device is directly connected to the backside contact of the transistor.

[0110] The memory device may include at least one of the following: magnetoresistive random access memory; phase change memory; or resistive random access memory. The backside contact may be substantially aligned with an electrode of the memory device, and the backside contact may be substantially aligned with a source or drain of the transistor. The backside contact may be isolated from the gate metal of the transistor by a dielectric isolation layer and an internal spacer. The device may also include a logic region of a wafer, the logic region being different from a region of the wafer including the memory device; and a logic region transistor in the logic region, the logic region transistor being different from the transistor; and a logic region backside contact in the logic region, the logic region backside contact being different from the backside contact; wherein the logic region backside contact includes an upper surface, the upper surface being lower than a lower surface of a spacer in a region of the wafer including the memory device, the spacer being configured to isolate the backside contact from the gate metal of the transistor.

[0111] In an embodiment, a method includes forming a first sacrificial placeholder in a first region of a wafer, which is below the source or drain region of at least one transistor in the first region; forming a second sacrificial placeholder in a second region of the wafer, which is below the source or drain region of at least one transistor in the second region; wherein the first sacrificial placeholder is formed deeper in the wafer than the second sacrificial placeholder; flipping the wafer; removing the first sacrificial placeholder to form a first empty region; forming a first backside contact and electrode for a memory device in at least a portion of the first empty region, the first backside contact contacting the source or drain of at least one transistor in the first region; depositing and patterning a memory device in at least a portion of the first empty region; removing the second sacrificial placeholder to form a second empty region; and forming a second backside contact in at least a portion of the second empty region, the second backside contact contacting the source or drain of at least one transistor in the second region.

[0112] The method may also include coupling at least one transistor of the first region to a memory device using a first backside contact; and coupling the memory device to a back end of a wire interconnect using a through hole. The method may also include coupling at least one transistor of the second region to a backside power rail using a second backside contact; and coupling the backside power rail to a back end of the wire interconnect using a through hole. The first sacrificial placeholder may be formed deeper within the wafer than the second sacrificial placeholder, such that an upper surface of the second backside contact is lower than a lower surface of a spacer in a first region of the wafer including the memory device, the spacer being configured to isolate the first backside contact from a gate metal of at least one transistor of the first region. The memory device may include at least one of: a magnetoresistive random access memory; a phase change memory; or a resistive random access memory.

[0113] In another embodiment, a semiconductor device includes: a first region including a first backside contact to couple at least one transistor of the first region to a memory device of the first region; and a second region including a second backside contact to couple at least one transistor of the second region to a backside power rail of the second region.

[0114] The first backside contact may directly connect the source or drain of at least one transistor to an electrode of the memory device. The upper surface of the second backside contact may be lower than the lower surface of the spacer in the first region of the memory device, the spacer being configured to isolate the first backside contact from the gate metal of at least one transistor of the first region. The memory device may include at least one of the following: a magnetoresistive random access memory; a phase change memory; or a resistive random access memory. The semiconductor device may also include an electrode of the memory device, wherein the first backside contact is substantially aligned with the electrode of the memory device.

[0115] References to "computers", "processors", etc. should be understood to cover not only computers with different architectures (such as single / multi-processor architectures and sequential or parallel architectures), but also special-purpose circuits (such as field programmable gate arrays (FPGAs), application-specific circuits (ASICs), signal processing devices, and other processing circuit devices. References to computer programs, instructions, codes, etc. should be understood to cover software or firmware for programmable processors, such as the programmable content of hardware devices, whether instructions for a processor or configuration settings for a fixed-function device, gate array, or programmable logic device, etc.

[0116] The memory as described herein can be implemented using any suitable data storage technology, such as semiconductor-based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, non-volatile memory, transient memory, fixed memory, and removable memory. The memory(s) may include a database for storing data.

[0117] As used herein, circuitry may refer to the following: (a) hardware circuit implementations, such as implementations in analog and / or digital circuitry, and (b) combinations of circuitry and software (and / or firmware), such as (as applicable): (i) processor(s) or (ii) combinations of portions of processor(s) / software, including (multiple) digital signal processor(s), software, and (multiple) memories that work together to enable the device to perform various functions, and (c) circuitry, such as (multiple) microprocessors or portions of (multiple) microprocessors, that require software or firmware for operation, even if the software or firmware is not physically present. As a further example, as used herein, circuitry would also cover implementations of only a processor (or processors) or portions of a processor and its (or their) accompanying software and / or firmware. For example, circuitry would also cover a baseband integrated circuit or an application processor integrated circuit for a mobile phone or a similar integrated circuit in a server, cellular network device, or another network device, if applicable to the particular element.

[0118] A list of abbreviations that can be appended to each other or with other characters using, for example, dashes or hyphens ("-"):

[0119] ASIC: Application Specific Integrated Circuit

[0120] BDI: Bottom Dielectric Isolation

[0121] BEOL: Back-end of the line

[0122] BOX: Buried Oxide

[0123] CMP: Chemical Mechanical Planarization / Polishing

[0124] DHF: Diluted hydrofluoric acid

[0125] DRAM: Embedded Dynamic Random Access Memory

[0126] FEOL: Front End of Line

[0127] FPGA: Field Programmable Gate Array

[0128] HF: hydrofluoric acid

[0129] High-k: high dielectric constant

[0130] HKMG: high-k metal gate

[0131] IBE: Ion Beam Etching

[0132] ILD: Interlayer Dielectric

[0133] M: metal layer, such as M1, M3

[0134] MOL: Middle of the Line

[0135] MRAM: Magnetoresistive Random Access Memory

[0136] MTJ: Magnetic Channel Junction

[0137] OPL: Inorganic Planarization Layer

[0138] PCM: Phase Change Memory

[0139] RC: Resistor and Capacitor

[0140] ReRAM: Resistive Random Access Memory

[0141] RIE: Reactive Ion Etching

[0142] S / D: Source / Drain

[0143] SHE-MRAM: Spin Hall Effect MRAM

[0144] Si: Silicon

[0145] SiGe: Silicon Germanium

[0146] Si:P: Phosphorus-doped epitaxial silicon

[0147] sp: spacer

[0148] STI: Shallow Trench Isolation

[0149] STT: Rotational Transfer Torque

[0150] TSV: Through Silicon Via

[0151] VBPR: Via to buried power rail

[0152] In the above description, many specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, and techniques, in order to provide a thorough understanding of the exemplary embodiments disclosed herein. However, it will be understood by those of ordinary skill in the art that the exemplary embodiments disclosed herein may be practiced without these specific details. In addition, details of well-known structures or processing steps may have been omitted or may not be described in order to avoid obscuring the presented embodiments.

[0153] The description of the present invention has been presented for the purpose of illustration and description, but it is not intended to be exhaustive or limited in the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The embodiments are selected and described in order to best explain the principles and practical application of the invention, and in order to enable others of ordinary skill in the art to understand the various embodiments of the invention with various modifications that are suitable for the particular use under consideration.

Claims

1. A device comprising: Backside power distribution network; a backside power rail joined to the backside power distribution network; as well as a backside contact via coupling a front end of at least one line transistor to the backside power rail; Wherein the backside contact via comprises a pillar-based memory device. 2 . The apparatus of claim 1 , wherein a portion of the backside contact via couples a source or a drain to the memory device. 3 . The apparatus of claim 2 , further comprising a non-magnetic conductive spacer between the memory device and the portion of the backside contact via. 4 . The apparatus of claim 2 , wherein the memory device is directly connected to the portion of the backside contact via.

5. The apparatus of claim 1 , wherein the memory device comprises at least one of: Magnetoresistive random access memory; Phase change memory; or Resistive Random Access Memory.

6. A method comprising: forming a backside power distribution network; bonding a backside power rail to the backside power distribution network; as well as forming a contact via coupling a front end of at least one line transistor to the backside power rail; Wherein the contact via comprises a pillar-based memory device.

7. The method according to claim 6, further comprising: forming a recess in the contact through hole; as well as The recess is filled with at least one non-magnetic material to form a non-magnetic conductive spacer between the memory device and the non-recessed portion of the contact via.

8. The method of claim 6, further comprising forming the memory device, the memory device being formed using a method comprising: applying at least one non-magnetic base material to a shallow trench isolation layer encapsulating at least a portion of the contact via; depositing a hard mask onto the nonmagnetic base material; forming a magnetic tunneling junction between the nonmagnetic base material and the hard mask; as well as An encapsulation spacer is formed along at least one wall of the magnetic tunnel node.

9. The method according to claim 8, further comprising: A block shape is applied to the shallow trench isolation layer, wherein the block shape prevents etching into the contact via, the shallow trench isolation layer, and selected portions of the silicon layer.

10. The method of claim 6, wherein the memory device comprises at least one of: Magnetoresistive random access memory; Phase change memory; or Resistive Random Access Memory.

11. An apparatus comprising: A transistor, the transistor comprising a source or a drain; a backside contact coupled to the transistor; as well as a memory device formed at a backside of the wafer, the memory device comprising an electrode; wherein the electrode of the memory device is directly connected to the backside contact of the transistor.

12. The apparatus of claim 11, wherein the memory device comprises at least one of: Magnetoresistive random access memory; Phase change memory; or Resistive Random Access Memory.

13. The apparatus of claim 11, wherein the backside contact is substantially aligned with the electrode of the memory device, and wherein the backside contact is substantially aligned with the source or drain of the transistor.

14. The device of claim 11, wherein the backside contact is isolated from a gate metal of the transistor by a dielectric isolation layer and an internal spacer.

15. The apparatus according to claim 11, further comprising: a logic region of the wafer, the logic region being different from a region of the wafer including the memory device; as well as a logic region transistor in the logic region, the logic region transistor being different from the transistor; as well as a logic region backside contact within the logic region, the logic region backside contact being different from the backside contact; The logic region backside contact includes an upper surface that is lower than a lower surface of a spacer in the region of the wafer including the memory device, the spacer being configured to isolate the backside contact from a gate metal of the transistor.

16. A method comprising: forming a first sacrificial placeholder in a first region of the wafer, the first sacrificial placeholder being below a source or drain region of at least one transistor in the first region; forming a second sacrificial placeholder in a second region of the wafer, the second sacrificial placeholder being below a source or drain region of at least one transistor in the second region; wherein the first sacrificial placeholder is formed deeper in the wafer than the second sacrificial placeholder; turning over the wafer; removing the first sacrificial placeholder to form a first empty area; forming a first backside contact and an electrode for a memory device in at least a portion of the first empty region, the first backside contact contacting a source or a drain of the at least one transistor of the first region; depositing and patterning the memory device in at least a portion of the first empty region; removing the second sacrificial placeholder to form a second empty area; as well as A second backside contact is formed in at least a portion of the second empty region, the second backside contact contacting a source or a drain of the at least one transistor of the second region.

17. The method according to claim 16, further comprising: coupling the at least one transistor of the first region to the memory device using the first backside contact; as well as The memory device is coupled to the back end of the wire interconnect using vias.

18. The method according to claim 16, further comprising: coupling the at least one transistor of the second region to a backside power rail using the second backside contact; as well as Vias are utilized to couple the backside power rail to the back end of the wire interconnect.

19. The method of claim 16, wherein the first sacrificial placeholder is formed deeper within the wafer than the second sacrificial placeholder such that an upper surface of the second backside contact is lower than a lower surface of a spacer in the first region of the wafer including the memory device, the spacer being configured to isolate the first backside contact from a gate metal of the at least one transistor of the first region.

20. The method of claim 16, wherein the memory device comprises at least one of: Magnetoresistive random access memory; Phase change memory; or Resistive Random Access Memory.

21. A semiconductor device comprising: a first region, the first region comprising a first backside contact to couple at least one transistor of the first region to a memory device of the first region; as well as A second region includes a second backside contact to couple at least one transistor of the second region to a backside power rail of the second region.

22. The semiconductor device of claim 21, wherein the first backside contact directly connects a source or a drain of the at least one transistor to an electrode of the memory device.

23. The semiconductor device of claim 21 , wherein an upper surface of the second backside contact is lower than a lower surface of a spacer in the first region including the memory device, the spacer being configured to isolate the first backside contact from a gate metal of the at least one transistor of the first region.

24. The method of claim 16, wherein the memory device comprises at least one of: Magnetoresistive random access memory; Phase change memory; or Resistive Random Access Memory.

25. The semiconductor device according to claim 21, further comprising: An electrode of the memory device, wherein the first backside contact is substantially aligned with the electrode of the memory device.

Images