Method for depositing thick-layer silicon epitaxial wafer on ultrathin substrate for semiconductor power device

Abstract

The invention discloses a method for depositing a thick-layer silicon epitaxial wafer on an ultrathin substrate for a semiconductor power device. By comprehensively designing key process parameters different from traditional growth temperature, heating power, heating time, cooling time and the like, the induction defects of epitaxy such as stacking fault, dislocation, slip line, orange peel, back and edge crystal point adsorption and the like which are easily generated in the traditional process are overcome. The traditional technological process is simplified, the process is simple and convenient, the industrial continuous production cost is reduced, and batch deposition of thick-layer silicon epitaxial wafers on 6-inch and 8-inch ultrathin silicon substrates is realized. Good product parameter uniformity and five-point thickness non-uniformity lt are realized; and therefore, the requirements of the market in the industry on 6-inch and 8-inch ultrathin substrate thick-layer silicon epitaxial wafers can be met.

Description

Technical Field

[0001] The invention belongs to the field of deposition of semiconductor silicon epitaxial wafers on semiconductor substrates, and in particular relates to a method for depositing thick-layer silicon epitaxial wafers on ultra-thin substrates for semiconductor power devices. Background Art

[0002] Silicon epitaxial wafers are silicon wafers obtained by depositing semiconductor silicon epitaxial layers on silicon substrates. Semiconductor silicon single crystal thin film layers are epitaxially grown on polished silicon single crystal substrates through gas phase chemical reactions at high temperatures. By controlling the growth conditions, silicon epitaxial layers of different resistivities, thicknesses and types can be obtained, which are used to manufacture various silicon-based semiconductor power devices. High-voltage and large semiconductor power devices such as 1200V FRED, PIN, and IGBT semiconductor power device structures require a thicker silicon epitaxial layer of more than 120μm as a voltage-resistant functional layer. Based on the slot size requirements of conventional process carriers, conventional thickness silicon epitaxial wafers of (5~100)μm can also use conventional thickness silicon substrates specified in the corresponding national standards. However, for thicker silicon epitaxial layers far above 100μm, thinner silicon substrates must be used to ensure that the total thickness of the final silicon wafer can be placed in the slot of the process carrier without damage.

[0003] For example, the national standard stipulates that the thickness of the silicon substrate is (625±15)μm for 6-inch silicon substrates and (725±15)μm for 8-inch silicon substrates. However, the silicon epitaxial wafers used in high-voltage semiconductor power devices such as 1200V FRED, PIN, IGBT, etc. require a thicker silicon epitaxial layer of more than 120μm. Then, according to the total thickness requirements, ultra-thin 6-inch silicon substrates with a thickness of (525±15)μm or ultra-thin 8-inch silicon substrates with a thickness of (625±15)μm are selected for epitaxial growth to ensure that the thick silicon epitaxial layer formed on the silicon substrate can be placed in the card slot of the process carrier without damage. In addition, ultra-thin silicon substrates can save the time of the back thinning process in the subsequent device processing, further reducing the device manufacturing cost.

[0004] However, the ultra-thin silicon substrate increases the difficulty of controlling the film quality of the thick silicon epitaxial layer. The probability of epitaxial induced defects such as stacking faults, dislocations, slip lines, orange peels, and adsorption of crystal points on the back and edges is higher. This is because when the silicon wafer size reaches a larger size of 6 inches and 8 inches, the silicon substrate is more likely to have a serious position shift during the loading process and the heating process. The uncontrollable adhesion between the silicon substrate and the edge of the base pit causes the silicon epitaxial wafer to break easily, greatly increasing the breakage rate. In particular, the growth of thick silicon epitaxial layers is more likely to generate epitaxial induced defects such as stacking faults, dislocations, slip lines, orange peels, and adsorption of crystal points on the back and edges than conventional thin silicon epitaxial layers. Therefore, the growth of thick silicon epitaxial layers on ultra-thin silicon substrates has higher requirements on process parameters such as process temperature and growth rate, and is obviously more difficult.

[0005] At present, the process methods used for growing silicon epitaxial wafers on ultra-thin silicon substrates with thickness far lower than conventional ones are as follows: Chinese patent with publication number CN 104947183 A discloses a method for preparing a silicon epitaxial layer on a heavily doped thin phosphorus substrate for Schottky devices: a thin phosphorus silicon substrate is used instead of a silicon substrate of conventional thickness, and an intrinsic epitaxial layer is first grown, and the growth rate of the intrinsic layer is controlled at 1 μm / min, and then the doped epitaxial layer is grown, and the growth rate is controlled at 1.2 μm / min. The disadvantage is that two layers of silicon epitaxial layers with variable epitaxial growth rates are introduced, and the process is more complicated, which increases the control difficulty of mass industrial production. The Chinese patent with the publication number CN 106128938 A discloses a method for preparing thick epitaxial layers on thin Sb substrates for VDMOS devices. The thin Sb substrate is selected to replace the conventional thick silicon substrate. It is necessary to first grow a very thin intrinsic epitaxial layer on the silicon wafer, and the growth rate of the intrinsic epitaxial layer is controlled at 2.0~2.5μm / min, and then grow the doped epitaxial layer, and the growth rate of the doped epitaxial layer is controlled at 2.5~2.8μm / min, so as to achieve good control of the epitaxial growth of the thin Sb substrate and successfully prepare an epitaxial layer with good thickness uniformity and good edge crystal quality. However, the disadvantage is that the growth of the silicon epitaxial layer with two layers of epitaxial growth rate gradient is introduced, and the process is more complicated, which increases the control difficulty of mass industrial production.

[0006] At present, there is no publicly reported deposition method for growing a silicon epitaxial layer thicker than 100μm to form silicon epitaxial wafers for ultra-thin silicon substrates of 6 inches and 8 inches, which are much thinner than conventional thicknesses. Therefore, a deposition method for thick silicon epitaxial wafers of 6 inches and 8 inches ultra-thin substrates for semiconductor power devices with good parameter uniformity (five-point thickness non-uniformity <0.8%), simple process, and adaptability to industrial continuous production requirements is needed. Summary of the invention

[0007] In view of the existing technical conditions and existing problems, the present invention provides a method for depositing thick silicon epitaxial wafers on ultra-thin substrates for semiconductor power devices. The method solves the problem that the silicon epitaxial wafers grown by traditional silicon epitaxial furnaces using 6-inch and 8-inch ultra-thin silicon substrates need to adopt more complex process methods such as the growth of two-layer silicon epitaxial layers with variable epitaxial growth rates to overcome thermal stress, mechanical stress, silicon wafer deformation internal stress, etc., which affects industrial continuous production. The ultra-thin silicon substrate wafers deposited by this method achieve a five-point thickness non-uniformity of the silicon epitaxial layer of less than 0.8%, and overcome epitaxial induced defects such as no stacking faults, dislocations, slip lines, orange peels on the surface, and no crystal point adsorption on the back and edges.

[0008] The technical solution adopted by the present invention is: a method for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device comprises the following steps in sequence: S1. The temperature of the silicon epitaxial furnace reaction chamber is raised to 1120-1140°C, and hydrogen chloride and hydrogen are introduced to etch and clean the reaction chamber and the graphite base. The hydrogen chloride gas flow rate is 30-35 L / min, the hydrogen gas flow rate is 25-30 L / min, and the etching and cleaning time is 15-16 min.

[0009] S2. The silicon epitaxial furnace reaction chamber starts to cool down. After cooling to 300-350°C, wait for 300-360 seconds and then place the ultra-thin silicon substrate sheet in the sheet pit of the graphite base of the silicon epitaxial furnace reaction chamber to avoid serious displacement of the ultra-thin silicon substrate sheet.

[0010] S3. The silicon epitaxial furnace reaction chamber and the graphite base are heated from an initial temperature of 300-350°C. Power heating is first performed. The initial heating power is set to 20 kW, which is increased to 78-80 kW. The time is set to 480-540 sec. The temperature of the silicon epitaxial furnace reaction chamber is raised to 900-930°C. Then, the temperature is continued to rise while maintaining a constant power. Finally, the temperature of the silicon epitaxial furnace reaction chamber is raised to 1040-1060°C. Subsequently, the surface of the ultra-thin silicon substrate is baked. The baking time is set to 3-5 min.

[0011] S4, using hydrogen to carry trichlorosilane as a silicon growth source, growing a silicon epitaxial layer on the polished surface of the ultra-thin silicon substrate, the graphite pedestal speed is set to 3-4 r / min, and the acceleration of the graphite pedestal speed is set to 0.4-0.6 r / min 2, which is used to reduce the serious position deviation of the ultra-thin silicon substrate during the rotation of the graphite base. The hydrogen flow rate is 180~200 L / min, the trichlorosilane flow rate is 7~8 g / min, the silicon epitaxial layer growth temperature is 1020~1040℃, and the growth rate is set to 1.2~1.5μm / min, which is used to reduce the occurrence of cracks caused by the continuous accumulation of stress in the thick silicon epitaxial layer during the growth process; the target thickness of the silicon epitaxial layer is 125~135μm, and the target five-point thickness non-uniformity is <0.8%. When the target thickness of the silicon epitaxial layer is reached, a thick silicon epitaxial wafer is formed.

[0012] S5. Nitrogen is introduced into the silicon epitaxial furnace reaction chamber for purging. The nitrogen purge flow rate is 100-150 L / min. The nitrogen purge time is 10-15 min. The silicon epitaxial furnace reaction chamber is cooled to 300-350°C. The cooling time is 700-840 sec. Then, the thick silicon epitaxial wafer is taken out from the wafer pit of the graphite base of the silicon epitaxial furnace reaction chamber.

[0013] The silicon epitaxial furnace described in the present invention is a NAURA 630 silicon epitaxial furnace.

[0014] In step S2 of the present invention, the ultra-thin silicon substrate sheet is a 6-inch or 8-inch ultra-thin silicon substrate sheet, wherein the thickness specification of the 6-inch ultra-thin silicon substrate sheet is designed to be 525±15 μm, and the thickness specification of the 8-inch ultra-thin silicon substrate sheet is designed to be 625±15 μm.

[0015] In step S3 of the present invention, a slow heating design is adopted, and the total time for heating the silicon epitaxial furnace reaction chamber from the initial temperature to 1040-1060° C. is set to 800-1000 seconds, so as to reduce the situation in which the ultra-thin silicon substrate sheet is severely deformed and cracked during the heating process.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. The North Huachuang 630 flat-plate multi-wafer silicon epitaxial furnace is used, and the comprehensive design is different from the traditional key process parameters such as growth temperature, heating power, heating time, cooling time, etc.; it overcomes the traditional process that easily generates epitaxial defects such as stacking faults, dislocations, slip lines, orange peels, and back and edge crystal point adsorption.

[0017] 2. The traditional process has been simplified, the process is simple, the cost of industrial continuous production has been reduced, and batch deposition of thick silicon epitaxial wafers on 6-inch and 8-inch ultra-thin silicon substrates has been achieved.

[0018] 3. The product parameters have good uniformity, and the five-point thickness non-uniformity of the silicon epitaxial layer is less than 0.8%, meeting the market demand for 6-inch and 8-inch ultra-thin silicon substrate thick-layer silicon epitaxial wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of five-point thickness distribution of the silicon epitaxial layer produced in Example 1 of the present invention; Figure 2 A schematic diagram of five-point thickness distribution of a silicon epitaxial layer produced in Example 2 of the present invention; Figure 3 A schematic diagram of five-point thickness distribution of a silicon epitaxial layer produced in Example 3 of the present invention; Figure 4 A schematic diagram of five-point thickness distribution of a silicon epitaxial layer produced in Example 4 of the present invention; Figure 5 A schematic diagram of five-point thickness distribution of a silicon epitaxial layer produced in Example 5 of the present invention; Figure 6 Schematic diagram of five-point thickness distribution of the silicon epitaxial layer produced in Comparative Example 2 of the present invention. DETAILED DESCRIPTION

[0020] The technical solution of the present invention will be clearly and completely described below in conjunction with embodiments.

[0021] A method for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device comprises the following steps in sequence: S1. Using the NAURA 630 silicon epitaxial furnace, the temperature of the silicon epitaxial furnace reaction chamber was raised to 1120~1140℃, and hydrogen chloride and hydrogen were introduced to etch and clean the reaction chamber and graphite base. The hydrogen chloride gas flow rate was 30~35 L / min, the hydrogen gas flow rate was 25~30 L / min, and the etching and cleaning time was 15~16 min.

[0022] S2. The silicon epitaxial furnace reaction chamber begins to cool down. After cooling to 300-350°C, continue to wait for 300-360 seconds and then place the ultra-thin silicon substrate sheet in the sheet pit of the graphite base of the silicon epitaxial furnace reaction chamber in the center to avoid serious displacement of the ultra-thin silicon substrate sheet. The ultra-thin silicon substrate sheet is 6-inch or 8-inch, wherein the thickness specification of the 6-inch ultra-thin silicon substrate sheet is designed to be 525±15 μm, and the thickness specification of the 8-inch ultra-thin silicon substrate sheet is designed to be 625±15 μm.

[0023] The crystal orientation of 6-inch and 8-inch ultra-thin silicon substrates is <100> The resistivity is 1~4 Ω·cm, the oxygen content is 8~14ppma, the front side of the 6-inch and 8-inch ultra-thin silicon substrate is polished, the back side is covered with a 450~550 nm silicon dioxide back-sealing layer, and the edge removal is 0.8~1.0mm.

[0024] S3. The silicon epitaxial furnace reaction chamber and the graphite base are heated from the initial 300~350℃. First, power heating is performed. The initial heating power is set to 20kW and increased to 78~80 kW. The time required for power increase is set to 480~540 sec. The temperature of the silicon epitaxial furnace reaction chamber is raised to 900~930℃. Then, the temperature is continued to rise while maintaining a constant power. Finally, the temperature of the silicon epitaxial furnace reaction chamber is raised to 1040~1060℃. Then, the surface of the ultra-thin silicon substrate is baked. The baking time is set to 3~5min.

[0025] A slow heating design is adopted to set the total time for heating the silicon epitaxial furnace reaction chamber from the initial temperature to 1040~1060℃ to 800~1000sec, in order to reduce the possibility of severe deformation and cracking of the ultra-thin silicon substrate during heating.

[0026] S4, using hydrogen to carry trichlorosilane as a silicon growth source, growing a silicon epitaxial layer on the polished surface of an ultra-thin silicon substrate, the graphite pedestal speed is set to 3~4 r / min, and the acceleration of the graphite pedestal speed is set to 0.4~0.6 r / min 2 , which is used to reduce the serious position deviation of the ultra-thin silicon substrate during the rotation of the graphite base. The hydrogen flow rate is 180~200 L / min, the trichlorosilane flow rate is 7~8 g / min, the silicon epitaxial layer growth temperature is 1020~1040℃, and the growth rate is set to 1.2~1.5μm / min, which is used to reduce the occurrence of cracks caused by the continuous accumulation of stress in the thick silicon epitaxial layer during the growth process; the target thickness of the silicon epitaxial layer is 125~135μm, and the target five-point thickness non-uniformity is <0.8%. When the target thickness of the silicon epitaxial layer is reached, a thick silicon epitaxial wafer is formed.

[0027] S5. Nitrogen is introduced into the silicon epitaxial furnace reaction chamber for purging. The nitrogen purge flow rate is 100-150 L / min. The nitrogen purge time is 10-15 min. The silicon epitaxial furnace reaction chamber is cooled to 300-350°C. The cooling time is 700-840 sec. Then, the thick silicon epitaxial wafer is taken out from the wafer pit of the graphite base of the silicon epitaxial furnace reaction chamber.

[0028] By fully cooling the silicon epitaxial wafer, the thermal stress accumulated in the growth process of the silicon epitaxial wafer can be effectively released, significantly reducing the risk of cracking of the silicon epitaxial wafer.

[0029] Embodiment 1: The method of depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device of this embodiment is as follows: S1. The temperature of the silicon epitaxial furnace reaction chamber is raised to 1120°C. Hydrogen chloride and hydrogen are introduced to etch and clean the reaction chamber and graphite base. The hydrogen chloride gas flow rate is 35 L / min, the hydrogen gas flow rate is 25 L / min, and the etching and cleaning time is 15 min.

[0030] S2. The silicon epitaxial furnace reaction chamber begins to cool down. After cooling to 300°C, wait for 360 seconds and then place the 6-inch ultra-thin silicon substrate sheet in the center of the sheet pit of the graphite base of the silicon epitaxial furnace reaction chamber to avoid serious displacement of the ultra-thin silicon substrate sheet. The thickness specification of the 6-inch ultra-thin silicon substrate sheet is designed to be 525±15 μm.

[0031] S3. The silicon epitaxial furnace reaction chamber and the graphite base are heated from the initial temperature of 300°C. First, power heating is performed. The initial heating power is set to 20kW, which is increased to 78 kW. The time is set to 480 seconds, and the temperature of the silicon epitaxial furnace reaction chamber is raised to 900°C. Then, the temperature is continued to rise while maintaining a constant power, so that the temperature of the silicon epitaxial furnace reaction chamber is finally raised to 1040°C. The total time required for heating is 850 seconds. Subsequently, the surface of the 6-inch ultra-thin silicon substrate is baked, and the baking time is set to 3 minutes.

[0032] S4, using hydrogen to carry trichlorosilane as the silicon growth source, the silicon epitaxial layer is grown on the polished surface of a 6-inch ultra-thin silicon substrate. The graphite pedestal speed is set to 4 r / min, and the acceleration of the graphite pedestal speed is set to 0.4 r / min. 2 , used to reduce the serious position deviation of the 6-inch ultra-thin silicon substrate during the rotation of the graphite base, the hydrogen flow rate is 180 L / min, the trichlorosilane flow rate is 7g / min, the silicon epitaxial layer growth temperature is 1040℃, and the growth rate is set to 1.2μm / min, which is used to reduce the continuous accumulation of stress in the thick silicon epitaxial layer during the growth process and cause cracks; the target thickness of the silicon epitaxial layer is 125~135μm, and the target five-point thickness non-uniformity is <0.8%. When the target thickness of the silicon epitaxial layer is reached, a thick silicon epitaxial wafer is formed.

[0033] S5. Nitrogen is introduced into the silicon epitaxial furnace reaction chamber for purge. The nitrogen purge flow rate is 100 L / min. The nitrogen purge time is 10 min. The silicon epitaxial furnace reaction chamber is cooled to 300° C. The cooling time is 840 sec. Then, the thick silicon epitaxial wafer is taken out from the wafer pit of the graphite base of the silicon epitaxial furnace reaction chamber.

[0034] Example 1 The five test positions for the thickness of the silicon epitaxial wafer are the center point with the main reference facing upward and four points 6 mm above, below, left and right of the center point. The average thickness of the silicon epitaxial wafer is calculated based on the five test positions, as shown in FIG. Figure 1As shown, the thickness of the silicon epitaxial layer is 125.442μm, 126.225μm, 124.194μm, 125.113μm, and 125.176μm, respectively, with an average of 125.23μm. The five-point thickness non-uniformity is 0.58%, which meets the target standard of five-point thickness non-uniformity <0.8%, and there are no epitaxial induced defects such as stacking faults, dislocations, slip lines, orange peels on the surface, and no crystal point adsorption on the back and edges.

[0035] Embodiment 2: The method of depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device of this embodiment is as follows: S1. The temperature of the silicon epitaxial furnace reaction chamber is raised to 1120°C. Hydrogen chloride and hydrogen are introduced to etch and clean the reaction chamber and graphite base. The hydrogen chloride gas flow rate is 35 L / min, the hydrogen gas flow rate is 25 L / min, and the etching and cleaning time is 15 min.

[0036] S2. The silicon epitaxial furnace reaction chamber begins to cool down. After cooling to 300°C, wait for 300 seconds and then place the 6-inch ultra-thin silicon substrate sheet in the center of the sheet pit of the graphite base of the silicon epitaxial furnace reaction chamber to avoid serious displacement of the ultra-thin silicon substrate sheet. The thickness specification of the 6-inch ultra-thin silicon substrate sheet is designed to be 525±15 μm.

[0037] S3. The silicon epitaxial furnace reaction chamber and the graphite base are heated from the initial temperature of 300°C. First, power heating is performed. The initial heating power is set to 20kW, which is increased to 80 kW. The time is set to 480 seconds, and the temperature of the silicon epitaxial furnace reaction chamber is raised to 900°C. Then, the temperature is continued to rise while maintaining a constant power, so that the silicon epitaxial furnace reaction chamber is finally heated to 1040°C. The total time required for heating is 800 seconds. Subsequently, the surface of the 6-inch ultra-thin silicon substrate is baked, and the baking time is set to 3 minutes.

[0038] S4, using hydrogen to carry trichlorosilane as the silicon growth source, the silicon epitaxial layer is grown on the polished surface of a 6-inch ultra-thin silicon substrate. The graphite pedestal speed is set to 4 r / min, and the acceleration of the graphite pedestal speed is set to 0.4 r / min. 2 , which is used to reduce the serious position deviation of the 6-inch ultra-thin silicon substrate during the rotation of the graphite base. The hydrogen flow rate is 185L / min, the trichlorosilane flow rate is 7g / min, the silicon epitaxial layer growth temperature is 1040℃, and the growth rate is set to 1.25μm / min, which is used to reduce the occurrence of cracks caused by the continuous accumulation of stress in the thick silicon epitaxial layer during the growth process; the target thickness of the silicon epitaxial layer is 125~135μm, and the target five-point thickness non-uniformity is <0.8%. When the target thickness of the silicon epitaxial layer is reached, a thick silicon epitaxial wafer is formed.

[0039] S5. Nitrogen is introduced into the silicon epitaxial furnace reaction chamber for purge. The nitrogen purge flow rate is 100 L / min. The nitrogen purge time is 10 min. The silicon epitaxial furnace reaction chamber is cooled to 300° C. The cooling time is 840 sec. Then, the thick silicon epitaxial wafer is taken out from the wafer pit of the graphite base of the silicon epitaxial furnace reaction chamber.

[0040] Example 2 The five test positions of the thickness of the silicon epitaxial wafer are the center point with the main reference upward and four points 6 mm above, below, left and right of the center point. The average thickness of the silicon epitaxial wafer is calculated based on the five test positions, as shown in FIG. Figure 2 As shown, the thickness of the silicon epitaxial layer is 125.558μm, 126.512μm, 124.176μm, 125.265μm, and 125.372μm, respectively, with an average of 125.38μm. The five-point thickness non-uniformity is 0.66%, which meets the target standard of five-point thickness non-uniformity <0.8%, and there are no epitaxial induced defects such as stacking faults, dislocations, slip lines, orange peels on the surface, and no crystal point adsorption on the back and edges.

[0041] Embodiment 3: The method of depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device of this embodiment is as follows: S1. The temperature of the silicon epitaxial furnace reaction chamber is raised to 1120°C. Hydrogen chloride and hydrogen are introduced to etch and clean the reaction chamber and graphite base. The hydrogen chloride gas flow rate is 35 L / min, the hydrogen gas flow rate is 25 L / min, and the etching and cleaning time is 15 min.

[0042] S2. The silicon epitaxial furnace reaction chamber begins to cool down. After cooling to 300°C, wait for 360 seconds and then place the 6-inch ultra-thin silicon substrate sheet in the center of the sheet pit of the graphite base of the silicon epitaxial furnace reaction chamber to avoid serious displacement of the ultra-thin silicon substrate sheet. The thickness specification of the 6-inch ultra-thin silicon substrate sheet is designed to be 525±15 μm.

[0043] S3. The silicon epitaxial furnace reaction chamber and the graphite base are heated from the initial 300°C. First, power heating is performed. The initial heating power is set to 20kW, which is increased to 80kW. The time is set to 540sec, and the temperature of the silicon epitaxial furnace reaction chamber is raised to 900°C. Then, the temperature is continued to rise while maintaining a constant power, so that the temperature of the silicon epitaxial furnace reaction chamber is finally raised to 1040°C. The total time required for heating is 850sec. Then, the surface of the 6-inch ultra-thin silicon substrate is baked, and the baking time is set to 3min.

[0044] S4, using hydrogen to carry trichlorosilane as the silicon growth source, the silicon epitaxial layer is grown on the polished surface of a 6-inch ultra-thin silicon substrate. The graphite pedestal speed is set to 4 r / min, and the acceleration of the graphite pedestal speed is set to 0.6 r / min. 2, used to reduce the serious position deviation of the 6-inch ultra-thin silicon substrate during the rotation of the graphite base, the hydrogen flow rate is 190 L / min, the trichlorosilane flow rate is 8g / min, the silicon epitaxial layer growth temperature is 1040℃, and the growth rate is set to 1.4μm / min, which is used to reduce the continuous accumulation of stress in the thick silicon epitaxial layer during the growth process and cause cracks; the target thickness of the silicon epitaxial layer is 125~135μm, and the target five-point thickness non-uniformity is <0.8%. When the target thickness of the silicon epitaxial layer is reached, a thick silicon epitaxial wafer is formed.

[0045] S5. Nitrogen is introduced into the silicon epitaxial furnace reaction chamber for purge. The nitrogen purge flow rate is 100 L / min. The nitrogen purge time is 10 min. The silicon epitaxial furnace reaction chamber is cooled to 300° C. The cooling time is 840 sec. Then, the thick silicon epitaxial wafer is taken out from the wafer pit of the graphite base of the silicon epitaxial furnace reaction chamber.

[0046] Example 3 The five test positions of the thickness of the silicon epitaxial wafer are the center point with the main reference upward and four points 6 mm above, below, left and right of the center point. The average thickness of the silicon epitaxial wafer is calculated based on the five test positions, as shown in FIG. Figure 3 As shown, the thickness of the silicon epitaxial layer is 125.682μm, 126.711μm, 124.198μm, 125.361μm, and 125.422μm, respectively, with an average of 125.47μm. The five-point thickness non-uniformity is 0.71%, which meets the target standard of five-point thickness non-uniformity <0.8%, and there are no epitaxial induced defects such as stacking faults, dislocations, slip lines, orange peels on the surface, and no crystal point adsorption on the back and edges.

[0047] Embodiment 4: The method of depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device of this embodiment is as follows: S1. The temperature of the silicon epitaxial furnace reaction chamber is raised to 1120°C. Hydrogen chloride and hydrogen are introduced to etch and clean the reaction chamber and graphite base. The hydrogen chloride gas flow rate is 35 L / min, the hydrogen gas flow rate is 25 L / min, and the etching and cleaning time is 15 min.

[0048] S2. The silicon epitaxial furnace reaction chamber begins to cool down. After cooling to 300°C, wait for 360 seconds and then place the 6-inch ultra-thin silicon substrate sheet in the center of the sheet pit of the graphite base of the silicon epitaxial furnace reaction chamber to avoid serious displacement of the ultra-thin silicon substrate sheet. The thickness specification of the 6-inch ultra-thin silicon substrate sheet is designed to be 525±15 μm.

[0049] S3. The silicon epitaxial furnace reaction chamber and the graphite base are heated from the initial temperature of 300°C. First, power heating is performed. The initial heating power is set to 20kW, which is increased to 78 kW. The time is set to 480 seconds, and the temperature of the silicon epitaxial furnace reaction chamber is raised to 900°C. Then, the temperature is continued to rise while maintaining a constant power, so that the temperature of the silicon epitaxial furnace reaction chamber is finally raised to 1040°C. The total time required for heating is 850 seconds. Subsequently, the surface of the 6-inch ultra-thin silicon substrate is baked, and the baking time is set to 3 minutes.

[0050] S4, using hydrogen to carry trichlorosilane as the silicon growth source, the silicon epitaxial layer is grown on the polished surface of a 6-inch ultra-thin silicon substrate. The graphite pedestal speed is set to 4 r / min, and the acceleration of the graphite pedestal speed is set to 0.4 r / min. 2 , which is used to reduce the serious position deviation of the 6-inch ultra-thin silicon substrate during the rotation of the graphite base. The hydrogen flow rate is 195 L / min, the trichlorosilane flow rate is 8g / min, the silicon epitaxial layer growth temperature is 1040℃, and the growth rate is set to 1.45μm / min, which is used to reduce the continuous accumulation of stress in the thick silicon epitaxial layer during the growth process and cause cracks; the target thickness of the silicon epitaxial layer is 125~135μm, and the target five-point thickness non-uniformity is <0.8%. When the target thickness of the silicon epitaxial layer is reached, a thick silicon epitaxial wafer is formed.

[0051] S5. Nitrogen is introduced into the silicon epitaxial furnace reaction chamber for purge. The nitrogen purge flow rate is 100 L / min. The nitrogen purge time is 10 min. The silicon epitaxial furnace reaction chamber is cooled to 300° C. The cooling time is 840 sec. Then, the thick silicon epitaxial wafer is taken out from the wafer pit of the graphite base of the silicon epitaxial furnace reaction chamber.

[0052] Example 4 The five test positions for the thickness of the silicon epitaxial wafer are the center point with the main reference facing upward and four points 6 mm above, below, left and right of the center point. The average thickness of the silicon epitaxial wafer is calculated based on the five test positions, as shown in FIG. Figure 4 As shown, the thickness of the silicon epitaxial layer is 125.695μm, 126.825μm, 124.223μm, 125.473μm, and 125.655μm, respectively, with an average of 125.57μm. The five-point thickness non-uniformity is 0.73%, which meets the target standard of five-point thickness non-uniformity <0.8%, and there are no epitaxial induced defects such as stacking faults, dislocations, slip lines, orange peels on the surface, and no crystal point adsorption on the back and edges.

[0053] Embodiment 5: The method of depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device of this embodiment is as follows: S1. The temperature of the silicon epitaxial furnace reaction chamber is raised to 1120°C. Hydrogen chloride and hydrogen are introduced to etch and clean the reaction chamber and graphite base. The hydrogen chloride gas flow rate is 35 L / min, the hydrogen gas flow rate is 25 L / min, and the etching and cleaning time is 15 min.

[0054] S2. The silicon epitaxial furnace reaction chamber begins to cool down. After cooling to 300°C, wait for 360 seconds and then place the 6-inch ultra-thin silicon substrate sheet in the center of the sheet pit of the graphite base of the silicon epitaxial furnace reaction chamber to avoid serious displacement of the ultra-thin silicon substrate sheet. The thickness specification of the 6-inch ultra-thin silicon substrate sheet is designed to be 525±15 μm.

[0055] S3. The silicon epitaxial furnace reaction chamber and the graphite base are heated from the initial temperature of 300°C. First, power heating is performed. The initial heating power is set to 20kW, which is increased to 80 kW. The time is set to 540 seconds, and the temperature of the silicon epitaxial furnace reaction chamber is raised to 900°C. Then, the temperature is continued to rise while maintaining a constant power, so that the temperature of the silicon epitaxial furnace reaction chamber is finally raised to 1040°C. The total time required for heating is 850 seconds. Subsequently, the surface of the 6-inch ultra-thin silicon substrate is baked, and the baking time is set to 3 minutes.

[0056] S4, using hydrogen to carry trichlorosilane as the silicon growth source, the silicon epitaxial layer is grown on the polished surface of a 6-inch ultra-thin silicon substrate. The graphite pedestal speed is set to 4 r / min, and the acceleration of the graphite pedestal speed is set to 0.4 r / min. 2 , used to reduce the serious position deviation of the 6-inch ultra-thin silicon substrate during the rotation of the graphite base, the hydrogen flow rate is 200 L / min, the trichlorosilane flow rate is 7g / min, the silicon epitaxial layer growth temperature is 1040℃, and the growth rate is set to 1.3μm / min, which is used to reduce the occurrence of cracks caused by the continuous accumulation of stress in the growth process of the thick silicon epitaxial layer; the target thickness of the silicon epitaxial layer is 125~135μm, and the target five-point thickness non-uniformity is <0.8%. When the target thickness of the silicon epitaxial layer is reached, a thick silicon epitaxial wafer is formed.

[0057] S5. Nitrogen is introduced into the silicon epitaxial furnace reaction chamber for purge. The nitrogen purge flow rate is 100 L / min. The nitrogen purge time is 10 min. The silicon epitaxial furnace reaction chamber is cooled to 300° C. The cooling time is 840 sec. Then, the thick silicon epitaxial wafer is taken out from the wafer pit of the graphite base of the silicon epitaxial furnace reaction chamber.

[0058] Example 5 The five test positions for the thickness of the silicon epitaxial wafer are the center point with the main reference facing upward and four points 6 mm above, below, left and right of the center point. The average thickness of the silicon epitaxial wafer is calculated based on the five test positions, as shown in FIG. Figure 5As shown, the thickness of the silicon epitaxial layer is 125.727μm, 126.952μm, 124.324μm, 125.589μm, and 125.793μm, respectively, with an average of 125.67μm. The five-point thickness non-uniformity is 0.74%, which meets the target standard of five-point thickness non-uniformity <0.8%, and there are no epitaxial induced defects such as stacking faults, dislocations, slip lines, orange peels on the surface, and no crystal point adsorption on the back and edges.

[0059] Comparative Example 1: The difference between this comparative example and Example 5 is that the power at which the heating power in step S3 of this comparative example is increased from 20 kW is different. The power at which the heating power in step S3 of this comparative example is increased from 20 kW is set to 81 kW.

[0060] The edge of the silicon epitaxial wafer surface obtained in Comparative Example 1 has slip lines, which does not meet the requirements of the present invention.

[0061] Comparative Example 2: The difference between this comparative example and Example 5 is that the hydrogen flow rate in step S4 of this comparative example is different; the hydrogen flow rate of this comparative example is set to 205 L / min.

[0062] The five test positions of the thickness of the silicon epitaxial wafer prepared in Comparative Example 2 are the center point with the main reference upward and four points 6 mm above, below, left and right of the center point. The average thickness of the silicon epitaxial wafer is calculated based on the five test positions, as shown in FIG. Figure 6 As shown, the thickness of the silicon epitaxial layer is 125.802μm, 127.190μm, 124.332μm, 125.603μm, and 125.802μm, respectively, with an average value of 125.74μm, and the five-point thickness non-uniformity is 0.81%, which does not meet the target five-point thickness non-uniformity standard of <0.8%, and does not meet the requirements of the present invention.

[0063] Comparative Example 3: The difference between this comparative example and Example 5 is that the temperature reduction time in step S5 of this comparative example is different, and the temperature reduction time of this comparative example is set to 690 seconds.

[0064] The edge of the surface of the silicon epitaxial wafer prepared in Comparative Example 3 has slip lines, which does not meet the requirements of the present invention.

[0065] Comparative Example 4: The difference between this comparative example and Example 5 is that the growth temperature in step S4 of this comparative example is different. The growth temperature of the silicon epitaxial layer of this comparative example is set to 1050°C.

[0066] The silicon epitaxial wafer prepared in Comparative Example 4 has dislocation defects on its surface, which does not meet the requirements of the present invention.

[0067] Comparative Example 5: The difference between this comparative example and Example 5 is that the acceleration of the base speed in step S4 of this comparative example is different. The acceleration of the base speed of this comparative example is set to 0.7 r / min. 2 .

[0068] The silicon epitaxial wafer prepared in Comparative Example 5 has stacking fault defects at its edge, which does not meet the requirements of the present invention.

[0069] Comparative Example 6: The difference between this comparative example and Example 5 is that the continued waiting time after cooling in step S2 is different in this comparative example. The continued waiting time after cooling in this comparative example is set to 290 seconds.

[0070] The silicon epitaxial wafer prepared in Comparative Example 6 has stacking fault defects at its edge, which does not meet the requirements of the present invention.

[0071] Comparative Example 7: The difference between this comparative example and Example 5 is that the total time required for heating in step S3 of this comparative example is different, and the total time required for heating in this comparative example reaches 790 seconds.

[0072] The silicon epitaxial wafer prepared in Comparative Example 7 has slip line defects at its edge, which does not meet the requirements of the present invention.

[0073] Through the above five embodiments and seven comparative examples, it can be verified that, on the one hand, the present invention avoids the problem of serious position displacement of ultra-thin silicon substrates during the loading process and the heating process by designing key process parameters such as the waiting time after the cooling of the reaction chamber and the acceleration of the base rotation speed, thereby improving the film quality of thick silicon epitaxial layers deposited on ultra-thin silicon substrates, and effectively alleviating the adhesion problem between the silicon substrate and the edge of the base pit, greatly reducing the breakage rate. On the other hand, by designing key process parameters such as the heating power and the total heating time and the cooling time of the reaction chamber, the thermal stress accumulated in the silicon substrate during the heating stage and the epitaxial deposition process can be released in time.

[0074] The present invention has achieved remarkable results in batch deposition of thick silicon epitaxial wafers on 6-inch and 8-inch ultra-thin silicon substrates by comprehensively designing key process parameters such as growth temperature, heating power, heating time, and cooling time that are different from traditional ones, and has overcome the problems of easy generation of epitaxial defects such as stacking faults, dislocations, slip lines, orange peels, and adsorption of back and edge crystal points in thick silicon epitaxial wafers under traditional epitaxial deposition processes. The product parameters have good uniformity, and the five-point thickness non-uniformity is less than 0.8%, which is conducive to large-scale promotion and application.

[0075] The above five embodiments and seven comparative examples are all implementation cases of the present invention in the process of research and development, but the protection scope of the present invention is not limited thereto. Technicians in the relevant technical field should understand that any changes or substitutions that can be easily thought of by technicians in the relevant technical field within the technical scope disclosed by the present invention fall within the protection scope and disclosure scope of the present invention.

Claims

1. A method for depositing thick silicon epitaxial wafers on ultra-thin substrates for semiconductor power devices, characterized in that: The method comprises the following steps: S1. The temperature of the silicon epitaxial furnace reaction chamber is raised to 1120-1140°C, and hydrogen chloride and hydrogen are introduced to etch and clean the reaction chamber and the graphite base. The hydrogen chloride gas flow rate is 30-35 L / min, the hydrogen gas flow rate is 25-30 L / min, and the etching and cleaning time is 15-16 min. S2, the silicon epitaxial furnace reaction chamber starts to cool down, and after cooling down to 300-350° C., wait for 300-360 seconds and then place the ultra-thin silicon substrate in the center of the sheet pit of the graphite base of the silicon epitaxial furnace reaction chamber to avoid serious deviation of the placement position of the ultra-thin silicon substrate; S3, heating the silicon epitaxial furnace reaction chamber and the graphite susceptor from the initial 300-350°C, firstly performing power heating, initially setting the heating power to 20kW, increasing it to 78-80kW, setting the time to 480-540 seconds, correspondingly heating the silicon epitaxial furnace reaction chamber to 900-930°C, then maintaining a constant power and continuing to heat up, so that the silicon epitaxial furnace reaction chamber is finally heated to 1040-1060°C, and then baking the surface of the ultra-thin silicon substrate, and setting the baking time to 3-5min; S4, using hydrogen to carry trichlorosilane as a silicon growth source, growing a silicon epitaxial layer on the polished surface of the ultra-thin silicon substrate, the graphite pedestal speed is set to 3-4 r / min, and the acceleration of the graphite pedestal speed is set to 0.4-0.6 r / min 2 , used to reduce the serious position deviation of the ultra-thin silicon substrate during the rotation of the graphite base, the hydrogen flow rate is 180~200 L / min, the trichlorosilane flow rate is 7~8 g / min, the silicon epitaxial layer growth temperature is 1020~1040℃, and the growth rate is set to 1.2~1.5μm / min, which is used to reduce the occurrence of cracks caused by the continuous accumulation of stress in the thick silicon epitaxial layer during the growth process; the target thickness of the silicon epitaxial layer is 125~135μm, and the target five-point thickness non-uniformity is <0.8%. When the target thickness of the silicon epitaxial layer is reached, a thick silicon epitaxial wafer is formed; S5. Nitrogen is introduced into the silicon epitaxial furnace reaction chamber for purging. The nitrogen purge flow rate is 100-150 L / min. The nitrogen purge time is 10-15 min. The silicon epitaxial furnace reaction chamber is cooled to 300-350°C. The cooling time is 700-840 sec. Then, the thick silicon epitaxial wafer is taken out from the wafer pit of the graphite base of the silicon epitaxial furnace reaction chamber.

2. The method for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device according to claim 1, characterized in that: The silicon epitaxial furnace is a North Huachuang 630 model silicon epitaxial furnace.

3. The method for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device according to claim 1, characterized in that: In step S2, the ultra-thin silicon substrate sheet is a 6-inch or 8-inch ultra-thin silicon substrate sheet, wherein the thickness specification of the 6-inch ultra-thin silicon substrate sheet is designed to be 525±15 μm, and the thickness specification of the 8-inch ultra-thin silicon substrate sheet is designed to be 625±15 μm.

4. The method for depositing a thick silicon epitaxial wafer on an ultra-thin substrate for a semiconductor power device according to claim 1, characterized in that: In step S3, a slow heating design is adopted to set the total time for heating the silicon epitaxial furnace reaction chamber from the initial temperature to 1040-1060°C to 800-1000 seconds, so as to reduce the possibility of severe deformation and cracking of the ultra-thin silicon substrate during heating.

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