Chip test structure and chip test method
Through a chip testing structure that integrates stress testing and functional testing functions, the problems of complex chip testing process and frequent equipment replacement in the existing technology are solved, and the effect of simplifying the test process and saving costs is achieved.
Patent Information
- Application Number
- CN202510053878.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-13
- Publication Date
- 2025-04-22
AI Technical Summary
The existing chip testing process is complex, requiring multiple test structures for stress testing and functional testing, resulting in frequent equipment replacement and cumbersome testing steps.
It provides a chip testing structure, including a stress testing component, a functional testing component and an adapter, which can realize stress testing and functional testing of the chip to be tested without replacing the test equipment.
Simplifies the chip test process, reduces the number of equipment replacements, improves testing efficiency, and saves equipment costs.
Smart Images
Figure CN119861279A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip technology, and in particular to a chip testing structure and a chip testing method. Background Art
[0002] The chip manufacturing process is mainly divided into several steps: wafer fabrication, packaging, and testing. In order to avoid reliability failures when using the chip, the chip needs to be stress tested and functionally tested before it is officially shipped. Among them, the stress test mainly simulates the actual impact that may occur to the chip under test, such as temperature shock, acceleration shock, drop shock and other tests. The functional test places the chip under test on a printed circuit board (PCB), and the PCB is connected to an integrated circuit automatic tester (ATE) to test the reliability of the chip's function in a powered working state.
[0003] Currently, a chip is generally tested through multiple test structures. For example, a stress test structure may be used to perform a stress test on the chip, and then a functional test structure may be used to perform a functional test on the chip. This makes the chip testing process more complicated. Summary of the invention
[0004] The embodiments of the present application provide a chip testing structure and a chip testing method.
[0005] In the first aspect, an embodiment of the present application provides a chip testing structure, including a stress testing component, a functional testing component and a adapter component; the stress testing component includes a chip to be tested placement area and a first signal transmission component; the functional testing component includes a second signal transmission component and a third signal transmission component, and the second signal transmission component is electrically connected to the third signal transmission component; in a stress testing state, the stress testing component is connected to the adapter component; in a functional testing state, the stress testing component and the functional testing component are both connected to the adapter component, the first signal transmission component is connected to the chip to be tested in the chip to be tested placement area, the first signal transmission component is connected to the second signal transmission component, and the third signal transmission component is connected to an external functional testing device.
[0006] It can be understood that the chip testing structure provided in the embodiment of the present application can not only realize stress testing of the chip to be tested, but also realize functional testing of the chip to be tested. When performing stress testing and functional testing, there is no need to replace the testing equipment, which effectively simplifies the testing process.
[0007] In a possible implementation, the adapter assembly includes a fixing plate and a fourth signal transmission component; in a functional test state, a first end of the fourth signal transmission component is connected to the first signal transmission component, and a second end of the fourth signal transmission component is connected to the second signal transmission component.
[0008] In a possible implementation, the fixing plate is provided with a through hole, and the fourth signal transmission component passes through the through hole.
[0009] In a possible implementation, the fixing plate includes a first surface and a second surface, the first surface and the second surface are arranged opposite to each other, the fourth signal transmission component includes a first sub-signal transmission component and a second sub-signal transmission component, the first sub-signal transmission component and the second sub-signal transmission component are connected; the first sub-signal transmission component is arranged on the first surface, and the second sub-signal transmission component is arranged on the second surface; in a functional test state, the first sub-signal transmission component is connected to the first signal transmission component, and the second sub-signal transmission component is connected to the second signal transmission component.
[0010] In a possible implementation, the stress testing assembly includes a stress testing board, the stress testing board includes a third surface and a fourth surface, the third surface and the fourth surface are arranged opposite to each other; the chip to be tested placement area is located on the third surface, and the first signal transmission component is arranged on the fourth surface.
[0011] In a possible implementation, the number of the chip to be tested placement areas is one or more, and the first signal transmission component, the second signal transmission component, the third signal transmission component, and the fourth signal transmission component all include one or more groups of signal contact units.
[0012] In a possible implementation, the signal contact unit includes any one of a signal contact point, a signal contact block, a signal contact column, a signal contact needle, and a gold finger.
[0013] In a possible implementation, the functional test assembly includes a transfer test board, and the third signal transmission component is disposed on the transfer test board.
[0014] In a possible implementation, the adapter assembly includes a first fixing assembly, a second fixing assembly and a fixing plate; the first fixing assembly is used to fix the stress test assembly and the fixing plate, and the second fixing assembly is used to fix the functional test assembly and the fixing plate.
[0015] In one possible implementation, the stress testing component includes a stress testing board, and the functional testing component includes a transfer testing board; the first fixing component includes a first sub-fixed structure and a second sub-fixed structure, the first sub-fixed structure is arranged on the stress testing board, the second sub-fixed structure is arranged on the fixing board, and in the stress testing state, the first sub-fixed structure and the second sub-fixed structure are connected; the second fixing component includes a third sub-fixed structure and a fourth sub-fixed structure, the third sub-fixed structure is arranged on the fixing board, the fourth sub-fixed structure is arranged on the transfer testing board, and in the functional testing state, the first sub-fixed structure and the second sub-fixed structure are connected, and the third sub-fixed structure and the fourth sub-fixed structure are connected.
[0016] In one possible implementation, the adapter assembly includes a fixing plate, the first fixing assembly includes a first bolt assembly, the second fixing assembly includes a second bolt assembly, the stress testing assembly includes a stress testing plate, and the functional testing assembly includes an adapter testing plate; the stress testing plate is provided with a first screw hole group, the fixing plate is provided with a second screw hole group and a third screw hole group, and the adapter testing plate is provided with a fourth screw hole group. In the stress testing state, the first bolt assembly, the first screw hole group and the second screw hole group are matched and connected; in the functional testing state, the second bolt assembly, the third screw hole group and the fourth screw hole group are matched and connected.
[0017] In a possible implementation, the stress test component further includes a test circuit, which is arranged around the chip under test placement area; in a functional test state, the chip under test in the chip under test placement area is electrically connected to the test circuit.
[0018] In the second aspect, an embodiment of the present application provides a chip testing structure, including a stress testing component and a functional testing component; the stress testing component includes a stress testing board, on which a chip to be tested placement area is provided; the functional testing component includes a gold finger, which is connected to the stress testing board; in the functional testing state, the gold finger is connected to an external functional testing device.
[0019] It can be understood that the chip test structure provided in the embodiment of the present application can realize both stress testing of the chip to be tested and functional testing of the chip to be tested. When performing stress testing and functional testing, there is no need to replace the test equipment, which effectively simplifies the test process. The chip test structure provided in the embodiment of the present application is simple in structure and saves equipment costs.
[0020] In a third aspect, an embodiment of the present application provides a chip testing method, which is used for the test structure of any one of the first aspects above, and the method includes: when performing a stress test on the chip to be tested, placing the chip to be tested in the chip to be tested placement area, and connecting the stress testing component to the adapter component; when performing a functional test on the chip to be tested, placing the chip to be tested in the chip to be tested placement area, and connecting the stress testing component and the functional testing component to the adapter component, wherein the first signal transmission component is connected to the chip to be tested in the chip to be tested placement area, the first signal transmission component is connected to the second signal transmission component, the second signal transmission component is connected to the third signal transmission component, and the third signal transmission component is connected to an external functional testing device.
[0021] The chip testing method provided in the embodiment of the present application can realize both stress testing of the chip to be tested and functional testing of the chip to be tested. When performing stress testing and functional testing, there is no need to replace the testing equipment, which effectively simplifies the testing process. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 According to an embodiment of the present application, a schematic diagram of a chip test structure is shown;
[0023] Figure 2a According to an embodiment of the present application, a schematic diagram of a chip test structure is shown;
[0024] Figure 2b According to an embodiment of the present application, a schematic diagram of a chip test structure is shown;
[0025] Figure 3 According to an embodiment of the present application, a schematic diagram of a chip test structure is shown;
[0026] Figure 4 According to an embodiment of the present application, a schematic diagram of a chip test structure is shown;
[0027] Figure 5a and Figure 5b According to an embodiment of the present application, a schematic diagram of a third surface and a fourth surface of a stress testing plate 104 is shown;
[0028] Figure 6 According to an embodiment of the present application, a schematic diagram of a third surface of a stress testing plate 104 is shown;
[0029] Figure 7a and Figure 7b According to an embodiment of the present application, a schematic top view and a schematic side view of the transfer test board 203 are shown;
[0030] Figure 8According to an embodiment of the present application, a schematic diagram of a chip test structure is shown;
[0031] Fig. 9 According to an embodiment of the present application, a schematic diagram of a chip testing structure is shown. DETAILED DESCRIPTION
[0032] The embodiments of the present application provide a chip testing structure and a testing method.
[0033] As mentioned above, currently, a chip is generally tested through multiple test structures. For example, a stress test structure may be used to perform stress testing on a chip, and then a functional test structure may be used to perform functional testing on the chip, that is, each chip test generally only has a single function. For example, this makes the chip testing process more complicated.
[0034] For example, Figure 1 A schematic diagram of a chip test structure is shown. Figure 1 As shown, the chip test structure adopts a daisy chain design, and the chip test structure includes a PCB board 1001, and a plurality of interconnected solder balls 1003 are arranged on the PCB board 1001. During the test, the chip to be tested 101 is electrically connected to the PCB board 1001 through each solder ball 1003 (the arrow in the figure indicates the direction of the current path). The connectivity between the chip to be tested 101 and the PCB board 1001 is judged by the change of the solder ball impedance, that is, whether each solder ball fails is judged, and the functional test of the chip to be tested 101 is completed. However, this test structure can only perform functional testing on the chip to be tested, and cannot perform stress testing, that is, it is necessary to continue to use other stress test structures to perform stress testing on the chip to be tested, resulting in a more complicated chip testing process.
[0035] In order to solve the above problems, an embodiment of the present application provides a chip testing structure, which can implement both stress testing and functional testing of the chip to be tested.
[0036] Figure 2a A schematic diagram of a chip test structure according to an embodiment of the present application is shown. Figure 2a As shown, the chip test structure includes a stress test component 100, a functional test component 200 and a transfer component 300; the stress test component 100 includes a chip to be tested placement area for placing a chip to be tested 101 and a first signal transmission component 102, and the functional test component 200 includes a second signal transmission component 201 and a third signal transmission component 202, and the second signal transmission component 201 is electrically connected to the third signal transmission component 202.
[0037] Figure 2b A schematic diagram of a chip test structure under a stress test state is shown. Figure 2b As shown, in the stress test state, the stress test component 100 is connected to the adapter component 300. At this time, the functional test component 200 may not be assembled.
[0038] Figure 3 A schematic diagram of a chip test structure in a functional test state is shown. Figure 3 As shown, in the functional test state, the stress test component 100 and the functional test component 200 are both connected to the adapter component 300, the first signal transmission component 102 is connected to the chip under test 101 in the chip under test placement area, the first signal transmission component 102 is connected to the second signal transmission component 201, and the third signal transmission component 202 is connected to the external functional test device 400. Among them, the external functional test device 400 can be ATE.
[0039] It can be understood that the chip testing structure provided in the embodiment of the present application can not only realize stress testing of the chip 101 under test, but also realize functional testing of the chip 101 under test. When performing stress testing and functional testing, there is no need to replace the testing equipment, which effectively simplifies the testing process.
[0040] In some embodiments, the first signal transmission component 102, the second signal transmission component 201, and the third signal transmission component 202 all include a signal contact unit, and the signal contact unit includes any one of one or more signal contact points, one or more signal contact blocks, one or more signal contact columns, one or more signal contact needles, and one or more gold fingers. In some embodiments, the signal contact unit may also be other structures that can achieve signal transmission, which is not limited in the embodiments of the present application. For example, the first signal transmission component 102 is one or more signal contact points, the second signal transmission component 201 is one or more signal contact points, and the third signal transmission component 202 is one or more metal pins. Among them, the material of the signal contact unit such as the signal contact point, signal contact block, signal contact column, signal contact needle, gold finger, etc. can be any conductive material, such as metal material.
[0041] Figure 4 A schematic diagram of a chip test structure is shown. Figure 4 As shown, the adapter assembly 300 includes a fixing plate 302 and a fourth signal transmission component 301 ; in the functional test state, the first end of the fourth signal transmission component 301 is connected to the first signal transmission component 102 , and the second end of the fourth signal transmission component 301 is connected to the second signal transmission component 201 .
[0042] In some embodiments, the fourth signal transmission component 301 includes a signal contact unit, and the signal contact unit may be any one of a signal contact point, a signal contact block, a signal contact column, a signal contact needle, and a gold finger.
[0043] In some embodiments, Figure 4 As shown, the fixing plate 302 is provided with a through hole, and the fourth signal transmission component 301 passes through the fixing plate 302. For example, the fourth signal transmission component 301 can be one or more metal contact pins, and the fixing plate 302 is provided with one or more through holes matching the metal contact pins. The stress test assembly 100 includes a stress test board 104, and the functional test assembly 200 includes a transfer test board 203. The metal contact pin passes through the through hole on the fixing plate 302, and the first end of the metal contact pin is connected to the stress test board 104, and the second end of the metal contact pin is connected to the transfer test board 203, so that the signal can be transmitted between the stress test board 104 and the transfer test board 203.
[0044] In the embodiment of the present application, the fourth signal transmission component 301 can be any structure that can achieve signal conduction between the stress test board 104 and the transfer test board 203. The fourth signal transmission component 301 can be connected to the stress test board 104 and the transfer test board 203 through other conductors, or can be directly fixedly contacted.
[0045] In some embodiments, the fourth signal transmission component 301 may also include a first sub-signal transmission component and a second sub-signal transmission component, the first sub-signal transmission component and the second sub-signal transmission component are connected, and the fixing plate 302 includes a first surface and a second surface arranged opposite to each other; the first sub-signal transmission component is arranged on the first surface, and the second sub-signal transmission component is arranged on the second surface; in the functional test state, the first sub-signal transmission component is connected to the first signal transmission component 102, and the second sub-signal transmission component is connected to the second signal transmission component 201.
[0046] It can be understood that the first sub-signal transmission component and the second sub-signal transmission component can be connected in any form through a lead, a metal contact pin, etc. The first sub-signal transmission component and the second sub-signal transmission component can also be any one of one or more signal contact points, one or more signal contact blocks, one or more signal contact pillars, one or more signal contact pins, and one or more gold fingers.
[0047] In some embodiments, Figure 4 As shown, the stress test assembly 100 further includes a test circuit 103 , which is arranged around a chip under test placement area 105 ; in a functional test state, the chip under test 101 in the chip under test placement area is electrically connected to the test circuit 103 .
[0048] Figure 5a and Figure 5b Schematic diagrams of the third surface and the fourth surface of a stress test plate 104 are respectively shown, wherein Figure 5a and 5bAs shown, the stress test board 104 includes a third surface and a fourth surface, the third surface and the fourth surface are arranged opposite to each other, the chip placement area to be tested is arranged on the third surface, and the first signal transmission component 102 is arranged on the fourth surface.
[0049] It can be understood that in the embodiment of the present application, the chip under test placement area can be an area on the stress test board 104 where the chip under test 101 is placed. The area can be a partial surface area of the stress test board 104, or a structure such as a groove opened in the stress test board to accommodate the chip under test 101, which is not limited in the embodiment of the present application.
[0050] In some embodiments, Figure 5b As shown, the first signal transmission component 102 may include a plurality of signal contacts.
[0051] In some embodiments, Figure 5a As shown, the test circuit 103 is arranged around the chip placement area for placing the chip 101 under test; in the functional test state, the chip 101 under test in the chip placement area is electrically connected to the test circuit 103. The test circuit 103 can cooperate with the chip 101 under test to simulate the working state of the chip.
[0052] In some embodiments, the test circuit 103 may also be referred to as a peripheral device, and the test circuit 103 may include devices such as resistors, capacitors, or inductors. In some embodiments, to ensure that the chip can work properly, the layout design of the test circuit 103 may be a preset distance from the test chip, for example, more than 1 mm, and the number of devices in the test circuit 103 may be limited to less than a preset threshold, so as to avoid the test circuit 103 from affecting the chip stress test.
[0053] In some embodiments, the chip under test placement area can be arranged at the center of the stress test board 104, so that the stress level of different chips under test can be ensured to be consistent during the test. In some embodiments, when testing is required, the chip under test 101 and the test circuit 103 can be welded on the stress test board 104 through the SMT process. That is, the chip test structure provided in the embodiment of the present application may not include the test circuit 103.
[0054] In some embodiments, the test circuit 103 may be pre-welded on the stress test board 104, and when testing, the chip 101 to be tested is welded to the test circuit 103, and the chip 101 to be tested is welded to the stress test board 104. That is, the chip test structure provided in the embodiment of the present application may include the test circuit 103.
[0055] In some embodiments, the number of the chip under test placement areas is one or more, that is, it can accommodate one or more chips under test 101. Correspondingly, the first signal transmission component 102, the second signal transmission component 201, and the fourth signal transmission component 301 all include one or more groups of signal contact units to correspond to each chip under test 101.
[0056] For example, Figure 6 A schematic diagram of the third surface of the stress test board 104 is shown. Figure 6 As shown, the number of the chip under test placement areas for placing the chip under test 101 is 4, the first signal transmission component 102, the second signal transmission component 201, and the fourth signal transmission component 301 all include 4 groups of signal contact units, and the number of the test circuits 103 is also 4.
[0057] Figure 7a and Figure 7b The third surface (i.e., top view) and the side view of the transfer test board 203 are respectively shown. Figure 7a and 7b As shown, the third signal transmission component 202 is disposed on the transfer test board 203; the third signal transmission component 202 can be a plurality of metal pins.
[0058] In some embodiments, the adapter assembly 300 includes a first fixing assembly, a second fixing assembly and a fixing plate 302 ; the first fixing assembly is used to fix the stress test assembly 100 and the fixing plate 302 , and the second fixing assembly is used to fix the functional test assembly 200 and the fixing plate 302 .
[0059] It is understandable that the first fixing assembly can be any structure that can fix the stress test assembly 100 and the fixing plate 302. For example, the first fixing assembly can be a clamping assembly, a bolt assembly, a pressure head assembly, etc., which is not limited in the embodiment of the present application.
[0060] The second fixing component may be any structure that can fix the functional test component 200 and the fixing plate 302. For example, the second fixing component may be a clamping component, a bolt component, a pressure head component, etc., which is not limited in the embodiment of the present application.
[0061] In some embodiments, the first fixing assembly is used to fix the stress testing assembly 100 and the fixing plate 302 , thereby preventing different external conditions from affecting the chip stress test.
[0062] In some embodiments, the first fixing assembly includes a first sub-fixing structure and a second sub-fixing structure, the first sub-fixing structure is arranged on the stress testing board 104 of the stress testing assembly 100, and the second sub-fixing structure is arranged on the fixing plate 302, and in the stress testing state, the first sub-fixing structure and the second sub-fixing structure are connected.
[0063] In some embodiments, the second fixed component includes a third sub-fixed structure and a fourth sub-fixed structure, the third sub-fixed structure is arranged on the fixed plate 302, and the fourth sub-fixed structure is arranged on the transfer test board 203 of the functional test component 200, and in the functional test state, the first sub-fixed structure and the second sub-fixed structure are connected, and the third sub-fixed structure and the fourth sub-fixed structure are connected.
[0064] For example, the first fixing structure and the second fixing structure in the first fixing assembly can be two snap-fitting parts of a buckle, so that the stress test assembly 100 and the fixing plate 302 can be connected by a buckle. Or the first fixing structure and the second fixing structure in the first fixing assembly can be a slot and a protruding mechanism, so that the stress test assembly 100 and the fixing plate 302 can be connected by a slot and a protruding mechanism.
[0065] In some embodiments, the adapter assembly 300 includes a fixing plate 302, the first fixing assembly includes a first bolt assembly, the second fixing assembly includes a second bolt assembly, the stress testing plate 104 has a first screw hole group, the fixing plate 302 has a second screw hole group and a third screw hole group, and the adapter test plate 203 has a fourth screw hole group. In the stress testing state, the first bolt assembly, the first screw hole group and the second screw hole group are matched and connected; in the functional testing state, the second bolt assembly, the third screw hole group and the fourth screw hole group are matched and connected.
[0066] In some embodiments, the first screw hole group, the second screw hole group, and the third screw hole group may each include one or more screw holes, wherein the number of screw holes in the first screw hole group and the second screw hole group is the same, and the number of screw holes in the second screw hole group and the third screw hole group is the same. The embodiment of the present application does not limit the number of screw holes in the first screw hole group, the second screw hole group, and the third screw hole group.
[0067] In some embodiments, the first screw hole group may be disposed at an edge of the stress testing board 104 , and the third screw hole group may be disposed at an edge of the adapter testing board 203 .
[0068] In some embodiments, Figure 5a-Figure 6 As shown in , the number of screw holes 105 in the first screw hole group can be 4.
[0069] In some embodiments, the stress test board 104 and the transfer test board 203 can both be PCB boards, and the transfer test board 203 can also be replaced by a printed circuit (Flexible Printed Circuit, FPC) or a flexible cable or other structures for achieving signal connection and conduction.
[0070] Figure 8 FIG. 2 is a schematic diagram showing another chip test structure according to an embodiment of the present application. Figure 8 As shown, the chip test structure includes a stress test component 100 and a functional test component 200; the stress test component 100 and the functional test component 200 are connected;
[0071] The stress test component 100 includes a stress test board 104 , on which a chip-to-be-tested placement area is disposed; the functional test component 200 includes a gold finger, which is connected to the stress test board.
[0072] In some embodiments, the extension direction of the gold finger may be parallel to the length extension direction of the stress test board, so that the gold finger is not damaged during the stress test.
[0073] It can be understood that the connection method between the gold finger and the stress test board can be any method such as welding, and the embodiment of the present application is not limited thereto.
[0074] In some embodiments, Figure 8 As shown, the stress test assembly 100 further includes a test circuit 103, which is arranged around the chip under test placement area 105; in the functional test state, the chip under test 101 in the chip under test placement area is electrically connected to the test circuit 103. The structural design of the stress test assembly 100 can be referred to FIG. Figure 7b The structure described in will not be repeated here.
[0075] In some embodiments, the gold finger structure can be connected to ATE in a functional test state.
[0076] In some embodiments, Figure 8 The chip test structure shown does not need to set up a transfer component and a transfer test board, which can further simplify the construction of the chip test structure. Figure 8 The chip test structure shown can be applied to chips with a small number of signals and simple functions. The stress test board can be directly connected to the ATE test using the gold finger structure.
[0077] In some embodiments, the shape, size, thickness of the stress test board 104, the position of the screw holes on the stress test board 104 or the position of the chip to be tested 101 can be designed according to the stress test accuracy or reliability requirements and the test quantity requirements.
[0078] Fig. 9 A schematic diagram of a chip test structure is shown. Fig. 9As shown, the chip test structure includes a PCB board 1001, and the PCB board 1001 includes a placement area for the chip to be tested and peripheral devices. The PCB board 1001 is provided with a pin 1002, and the pin 1002 is vertically arranged with the PCB board 1001. Specifically, one end of the pin 1002 is inserted and fixed in the through hole of the PCB board 1001, and the other end of the pin 1002 extends out of the PCB board 1001 and is connected to the integrated circuit automatic test machine, thereby realizing the electrical connection between the device to be tested, the peripheral devices, the pin 1002 and the ATE. Among them, the peripheral devices (such as capacitors, inductors, resistors, etc.) can cooperate with the chip to be tested 101 to simulate the working state of the chip. It can be understood that Fig. 9 The solution shown can also perform stress testing on the chip. However, since one end of the pin 1002 extends out of the PCB board 1001, in some cases, the pin 1002 is easily damaged when performing a stress test (such as a drop test) on the chip 101 to be tested. Once the pin 1002 is damaged, it will be impossible to perform a functional test on the chip 101 to be tested. Therefore, the pin 1002 is replaced with Figure 8 The gold finger in the embodiment can effectively avoid the occurrence of this problem due to the planar structure of the gold finger, and implement stress testing and functional testing of the chip to be tested 101 through a chip test structure.
[0079] Embodiments of the present application Figure 2a-Figure 8 The provided chip testing structure can implement both stress testing and functional testing of the chip 101 under test. When performing stress testing and functional testing, there is no need to replace the testing equipment, which effectively simplifies the testing process.
[0080] Embodiments of the present application Figure 2a-Figure 8 The provided chip test structure can accurately test the damage status of specific functional modules inside the chip to be tested based on peripheral devices and ATE, that is, perform precise functional testing, and can perform stress testing, and the test structure is simple.
[0081] The present application embodiment provides a chip testing method for Figure 2a-Figure 7bThe chip testing structure tests the chip to be tested, and the method includes: when performing stress testing on the chip to be tested, the chip to be tested is placed in a chip to be tested placement area, and the stress testing component is connected to the adapter component to perform stress testing on the chip to be tested; when performing functional testing on the chip to be tested, the chip to be tested is placed in the chip to be tested placement area, and the stress testing component, the functional testing component and the adapter component are connected, wherein the first signal transmission component is connected to the chip to be tested in the chip to be tested placement area, the first signal transmission component is connected to the second signal transmission component, the second signal transmission component is connected to the third signal transmission component, and the third signal transmission component is connected to an external functional testing device to realize functional testing of the chip to be tested.
[0082] The present application embodiment provides a chip testing method for Figure 8 The chip testing structure tests the chip to be tested, and the method includes: when performing stress testing on the chip to be tested, the chip to be tested is placed in a chip to be tested placement area to perform stress testing on the chip to be tested; when performing functional testing on the chip to be tested, the chip to be tested is placed in the chip to be tested placement area, and the gold fingers in the functional testing component are connected to an external functional testing device to perform functional testing on the chip to be tested.
[0083] The chip testing method provided in the embodiment of the present application can realize both stress testing of the chip to be tested and functional testing of the chip to be tested. When performing stress testing and functional testing, there is no need to replace the testing equipment, which effectively simplifies the testing process.
[0084] In summary, the chip testing structure provided in the embodiment of the present application can not only realize stress testing of the chip to be tested, but also realize functional testing of the chip to be tested. When performing stress testing and functional testing, there is no need to replace the testing equipment, which effectively simplifies the testing process.
[0085] In addition, the embodiments of the present application take into account both stress reliability testing and chip function testing of the chip, which is more conducive to evaluating the stress risk level and function of the chip.
[0086] In addition, the embodiments of the present application do not require the use of additional testing equipment and expensive hardware, thus saving equipment costs.
[0087] In addition, the embodiments of the present application are closer to the actual application scenarios of customers using chips, which facilitates the early discovery of possible stress reliability risks and chip function problems, helps to avoid risks and optimize designs in the early chip design stage, and improves chip reliability and quality.
[0088] It should be noted that, as used in the specification and the appended claims of this application, the singular expressions "a", "an", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless the context clearly indicates otherwise. It should also be understood that in the embodiments of the present application, "one or more" means one, two or more than two.
[0089] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.
[0090] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.
Claims
1. A chip testing structure, characterized in that: Including stress test components, functional test components and switching components; The stress test assembly includes a chip placement area to be tested and a first signal transmission component; The functional test assembly comprises a second signal transmission component and a third signal transmission component, wherein the second signal transmission component is electrically connected to the third signal transmission component; In the stress test state, the stress test component is connected to the adapter component; In the functional test state, the stress test component and the functional test component are both connected to the adapter component, the first signal transmission component is connected to the chip to be tested in the chip to be tested placement area, the first signal transmission component is connected to the second signal transmission component, and the third signal transmission component is connected to an external functional test device.
2. The chip test structure according to claim 1, characterized in that: The adapter assembly includes a fixing plate and a fourth signal transmission component; In the function test state, the first end of the fourth signal transmission component is connected to the first signal transmission component, and the second end of the fourth signal transmission component is connected to the second signal transmission component.
3. The chip test structure according to claim 2, characterized in that: The fixing plate is provided with a through hole, and the fourth signal transmission component passes through the through hole.
4. The chip test structure according to claim 2, characterized in that: The fixing plate includes a first surface and a second surface, the first surface and the second surface are arranged opposite to each other, the fourth signal transmission component includes a first sub-signal transmission component and a second sub-signal transmission component, the first sub-signal transmission component and the second sub-signal transmission component are connected; The first sub-signal transmission component is disposed on the first surface, and the second sub-signal transmission component is disposed on the second surface; In a functional test state, the first sub-signal transmission component is connected to the first signal transmission component, and the second sub-signal transmission component is connected to the second signal transmission component.
5. The chip test structure according to claim 2, characterized in that: The stress testing assembly includes a stress testing plate, the stress testing plate includes a third surface and a fourth surface, and the third surface and the fourth surface are arranged opposite to each other; The chip-to-be-tested placement area is located on the third surface, and the first signal transmission component is disposed on the fourth surface.
6. The chip test structure according to any one of claims 2 to 5, characterized in that: The number of the chip-to-be-tested placement areas is one or more, and the first signal transmission component, the second signal transmission component, the third signal transmission component, and the fourth signal transmission component each include one or more groups of signal contact units.
7. The chip test structure according to claim 6, characterized in that: The signal contact unit includes any one of a signal contact point, a signal contact block, a signal contact column, a signal contact needle, and a gold finger.
8. The chip test structure according to any one of claims 1 to 5, characterized in that: The functional test assembly includes a transfer test board, and the third signal transmission component is arranged on the transfer test board.
9. The chip test structure according to any one of claims 1 to 5, characterized in that: The adapter assembly includes a first fixing assembly, a second fixing assembly and a fixing plate; The first fixing assembly is used to fix the stress test assembly and the fixing plate, and the second fixing assembly is used to fix the functional test assembly and the fixing plate.
10. The chip test structure according to claim 9, characterized in that: The stress test assembly includes a stress test board, and the functional test assembly includes a transfer test board; The first fixing assembly includes a first sub-fixing structure and a second sub-fixing structure, the first sub-fixing structure is arranged on the stress test board, the second sub-fixing structure is arranged on the fixing board, and in the stress test state, the first sub-fixing structure and the second sub-fixing structure are connected; The second fixing assembly includes a third sub-fixing structure and a fourth sub-fixing structure, the third sub-fixing structure is arranged on the fixing plate, the fourth sub-fixing structure is arranged on the transfer test board, and in a functional test state, the first sub-fixing structure is connected to the second sub-fixing structure, and the third sub-fixing structure is connected to the fourth sub-fixing structure.
11. The chip test structure according to claim 9, characterized in that: The adapter assembly includes a fixing plate, the first fixing assembly includes a first bolt assembly, the second fixing assembly includes a second bolt assembly, the stress test assembly includes a stress test plate, and the functional test assembly includes an adapter test plate; The stress test plate is provided with a first screw hole group, the fixing plate is provided with a second screw hole group and a third screw hole group, and the transfer test plate is provided with a fourth screw hole group. In a stress test state, the first bolt assembly, the first screw hole group and the second screw hole group are connected in a cooperative manner; In a functional test state, the second bolt assembly, the third screw hole group and the fourth screw hole group are connected in a cooperative manner.
12. The chip test structure according to any one of claims 1 to 5, characterized in that: The stress test assembly further includes a test circuit, and the test circuit is arranged around the chip to be tested placement area; In the functional test state, the chip under test in the chip under test placement area is electrically connected to the test circuit.
13. A chip testing method, characterized in that: For the chip test structure according to any one of claims 1 to 12, the method comprises: When performing stress testing on the chip to be tested, the chip to be tested is placed in the chip to be tested placement area, and the stress testing component is connected to the adapter component; When performing a functional test on the chip to be tested, the chip to be tested is placed in the chip to be tested placement area, and the stress test component, the functional test component and the adapter component are connected, wherein the first signal transmission component is connected to the chip to be tested in the chip to be tested placement area, the first signal transmission component is connected to the second signal transmission component, the second signal transmission component is connected to the third signal transmission component, and the third signal transmission component is connected to the external functional test device.