A laser measurement circuit based on FPGA and its measurement method

Abstract

The present invention relates to the field of laser measurement technology, and in particular to a FPGA-based laser measurement circuit and a measurement method thereof. The circuit comprises a laser emission circuit, a first voltage threshold configuration circuit, a second voltage threshold configuration circuit, and an FPGA. The method comprises: generating an emission feedback signal and a reception signal by the laser emission circuit; when the laser emission circuit generates the emission feedback signal, if the difference between the voltage value of a first input signal point and the voltage value of a first detection signal point is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width; when the laser emission circuit generates the emission feedback signal, if the difference between the voltage value of a second input signal point and the voltage value of a second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse with a pulse width that varies with a signal strength ratio; and performing distance detection by the FPGA based on the first positive pulse and the second positive pulse. The present invention can improve ranging accuracy, stability, and anti-interference capability, and reduce costs.

Description

Technical Field

[0001] The present invention relates to the technical field of laser measurement, and in particular to a laser measurement circuit based on FPGA and a measurement method thereof. Background Art

[0002] In fields such as industrial production, construction, and geological exploration, the demand for measurement accuracy is becoming increasingly demanding. Traditional measurement methods such as rulers, tape measures, and levels have limitations in accuracy, efficiency, and safety, prompting the emergence of laser measurement technology. With the development of industry, automated equipment is becoming increasingly sophisticated. With technological advancements, laser measurement technology is moving towards higher precision, smaller size, greater intelligence, and greater networking. For example, the emergence of new measurement devices such as 3D laser scanners and lidar has revolutionized the measurement field.

[0003] Traditional laser measurement technology uses a dedicated TDC (time-to-digital converter) chip combined with an MCU. TDC measurement requires that the received signal be passed through a high-speed comparator to output a STOP signal. However, high-speed comparators have high propagation delays and are expensive, which can affect measurement accuracy. Summary of the Invention

[0004] In view of this, the purpose of the embodiments of the present invention is to provide an FPGA-based laser measurement circuit and a measurement method thereof to solve one or more technical problems existing in the prior art and provide at least one beneficial option or create conditions.

[0005] On the one hand, an embodiment of the present invention provides a laser measurement circuit based on FPGA, wherein the laser measurement circuit includes a laser emission circuit, a first voltage threshold configuration circuit, a second voltage threshold configuration circuit, and an FPGA;

[0006] The laser emitting circuit includes a transmitting feedback signal terminal and a receiving signal terminal, the transmitting feedback signal terminal is connected to a first voltage threshold configuration circuit, and the receiving signal terminal is connected to a second voltage threshold configuration circuit; the laser emitting circuit is used to generate a transmitting feedback signal and a receiving signal, the transmitting feedback signal is a negative pulse with a fixed pulse width, and the receiving signal is a negative pulse with a pulse width that varies with signal strength; the transmitting feedback signal is input into the first voltage threshold configuration circuit via the transmitting feedback signal terminal, and the receiving signal is input into the second voltage threshold configuration circuit via the receiving signal terminal;

[0007] The first input signal point and the first detection signal point of the first voltage threshold configuration circuit are connected to two pins of the FPGA correspondingly. When the laser emission circuit generates a transmission feedback signal, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the transmission feedback signal.

[0008] The second input signal point and the second detection signal point of the second voltage threshold configuration circuit are connected to two other pins of the FPGA correspondingly. When the laser emission circuit generates a transmission feedback signal, if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse whose pulse width changes with the ratio of the signal strength, and the second positive pulse corresponds to the received signal.

[0009] The FPGA performs distance detection based on the first positive pulse and the second positive pulse.

[0010] Optionally, the first voltage threshold configuration circuit configures the voltage threshold of the first input signal point to be a first DC voltage value, and configures the voltage value of the first detection signal point to be a second DC voltage value;

[0011] The first voltage threshold configuration circuit is configured to obtain a voltage value of the first input signal point by superimposing the voltage value of the transmit feedback signal and the first DC voltage value;

[0012] If the difference between the voltage value of the first input signal point and the second DC voltage value is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width.

[0013] Optionally, the first voltage threshold configuration circuit includes a first voltage dividing circuit and a second voltage dividing circuit;

[0014] The voltage dividing end of the first voltage dividing circuit is connected to the transmission feedback signal end and the first input signal point respectively, and the voltage dividing end of the second voltage dividing circuit is connected to the first detection signal point;

[0015] The voltage dividing end of the first voltage dividing circuit provides a third DC voltage value, and the voltage value of the first input signal point is obtained by adding the third DC voltage value and the voltage value of the transmission feedback signal end; the voltage dividing end of the second voltage dividing circuit provides a second DC voltage value to the first detection signal point;

[0016] When the difference between the voltage value of the first input signal point and the second DC voltage value is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width.

[0017] Optionally, the first voltage divider circuit includes a first resistor and a second resistor, one end of the first resistor is connected to the first power supply terminal, the other end of the first resistor is respectively connected to the transmission feedback signal terminal, the first input signal point, and one end of the second resistor, and the other end of the second resistor is grounded;

[0018] The second voltage divider circuit includes a third resistor and a fourth resistor, one end of the third resistor is connected to the second power supply end, the other end of the third resistor is respectively connected to the transmission feedback signal end and one end of the fourth resistor, and the other end of the fourth resistor is grounded.

[0019] Optionally, the first voltage threshold configuration circuit further includes a first filtering circuit and a second filtering circuit, the first filtering circuit includes a first capacitor and a second capacitor, and the first capacitor, the second capacitor and the second resistor are connected in parallel;

[0020] The first voltage threshold configuration circuit further includes the second filtering circuit including a third capacitor and a fourth capacitor, and the third capacitor, the fourth capacitor and the fourth resistor are connected in parallel.

[0021] Optionally, the second voltage threshold configuration circuit configures the voltage threshold of the second input signal point to be a third DC voltage value, and configures the voltage value of the second detection signal point to be a fourth DC voltage value;

[0022] The second voltage threshold configuration circuit is configured to obtain a voltage value of the second input signal point by superimposing the voltage value of the received signal and a third DC voltage value;

[0023] If the difference between the voltage value of the second input signal point and the fourth DC voltage value is greater than the difference threshold, the FPGA detects a second positive pulse with a fixed pulse width.

[0024] Optionally, the second voltage threshold configuration circuit includes a third voltage dividing circuit and a fourth voltage dividing circuit;

[0025] The voltage dividing end of the third voltage dividing circuit is connected to the signal receiving end and the second input signal point respectively, and the voltage dividing end of the fourth voltage dividing circuit is connected to the second detection signal point;

[0026] The voltage dividing end of the third voltage dividing circuit provides a third DC voltage value, and the voltage value of the second input signal point is obtained by adding the third DC voltage value and the voltage value of the signal receiving end; the voltage dividing end of the fourth voltage dividing circuit provides a fourth DC voltage value to the second detection signal point;

[0027] When the difference between the voltage value of the second input signal point and the fourth DC voltage value is greater than the difference threshold, the FPGA detects a second positive pulse with a fixed pulse width.

[0028] Optionally, the third voltage divider circuit includes an eighth resistor and a ninth resistor, one end of the eighth resistor is connected to the third power supply terminal, the other end of the eighth resistor is respectively connected to the signal receiving terminal, the second input signal point, and one end of the ninth resistor, and the other end of the ninth resistor is grounded;

[0029] The fourth voltage divider circuit includes a tenth resistor and an eleventh resistor, one end of the tenth resistor is connected to the fourth power supply end, the other end of the tenth resistor is respectively connected to the signal receiving end and one end of the eleventh resistor, and the other end of the eleventh resistor is grounded.

[0030] Optionally, the first voltage threshold configuration circuit further includes a third filtering circuit and a fourth filtering circuit, the third filtering circuit includes a seventh capacitor and an eighth capacitor, and the seventh capacitor, the eighth capacitor and the ninth resistor are connected in parallel;

[0031] The fourth filtering circuit includes a ninth capacitor and a tenth capacitor, and the ninth capacitor, the tenth capacitor and the tenth resistor are connected in parallel.

[0032] On the other hand, an embodiment of the present invention provides an FPGA-based laser measurement method, which is applied to any of the above-mentioned FPGA-based laser measurement circuits, and the method includes the following steps:

[0033] S100, generating a transmission feedback signal and a reception signal by the laser transmission circuit, the transmission feedback signal being input into a first voltage threshold configuration circuit via a transmission feedback signal terminal, and the reception signal being input into a second voltage threshold configuration circuit via a reception signal terminal; wherein the transmission feedback signal is a negative pulse with a fixed pulse width, and the reception signal is a negative pulse with a pulse width that varies with signal strength;

[0034] S200, when the laser emitting circuit generates a transmission feedback signal, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the transmission feedback signal; when the laser emitting circuit generates a transmission feedback signal, if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse with a pulse width that varies with a ratio of signal strengths, and the second positive pulse corresponds to the received signal;

[0035] S300 , performing distance detection based on the first positive pulse and the second positive pulse by the FPGA.

[0036] Embodiments of the present invention provide the following advantageous effects: The embodiment provided by the present invention generates a transmit feedback signal and a receive signal through a laser transmission circuit. The transmit feedback signal is configured as a negative pulse with a fixed pulse width. If the difference between the voltage value at the first input signal point and the voltage value at the first detection signal point is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, corresponding to the transmit feedback signal. The receive signal is configured as a negative pulse with a pulse width that varies with signal strength. If the difference between the voltage value at the second input signal point and the voltage value at the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse with a pulse width that varies with the ratio of signal strengths, corresponding to the receive signal. The FPGA performs distance detection based on the first and second positive pulses. The FPGA processes the receive signal in real time and accurately calculates pulse width variations, thereby improving measurement accuracy, reducing costs, and achieving efficient and intelligent laser measurement. The FPGA replaces the traditional comparator plus TDC (time-to-digital converter) chip solution, uses a laser transmission circuit to generate the transmit feedback signal and receive signal, and combines the first and second voltage threshold configuration circuits with the FPGA. This not only improves ranging accuracy, stability, and anti-interference capabilities, but also reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 This is a schematic structural diagram of a FPGA-based laser measurement circuit provided by an embodiment of the present invention;

[0039] Figure 2 is a circuit schematic diagram of a first voltage threshold configuration circuit in an embodiment of the present invention;

[0040] Figure 3 is a circuit schematic diagram of a second voltage threshold configuration circuit in an embodiment of the present invention;

[0041] Figure 4 The figure is a flowchart of the steps of a laser measurement method based on FPGA provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0043] It should be noted that although the device schematics illustrate a modular division and the flowcharts illustrate a logical sequence, in some cases, the steps shown or described may be performed in a different order than the modular division in the device or the sequence in the flowcharts. The terms "first," "second," and so on in the specification, claims, and drawings are used to distinguish similar items and are not necessarily used to describe a specific order or precedence.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0045] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0046] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. In other words, these functional entities may be implemented in software, in one or more hardware charging modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0047] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0048] The TDC measurement unit in related art is triggered by the STOP1 signal and stops when it receives the STOP2 signal. Between the STOP1 and STOP2 signals, the signal passes through gates within the chip. Each gate has a fixed propagation delay. The TDC measurement unit determines the time interval between the STOP1 and STOP2 signals by counting the number of gates the signal passes through.

[0049] The present invention is applied to short-distance visible laser ranging, which requires high laser measurement accuracy. FPGA has the characteristics of high speed, high precision, high stability and reliability. It can realize real-time processing of various signals in the laser ranging system, improve ranging accuracy, stability and anti-interference ability.

[0050] The present invention aims to improve the accuracy of laser ranging and reduce the effects of temperature drift. To this end, the present invention provides an FPGA-based laser measurement circuit and measurement method. This circuit uses an FPGA to replace the traditional comparator plus TDC (time-to-digital converter) chip solution. A laser transmission circuit generates transmission feedback signals and received signals, and is combined with a first voltage threshold configuration circuit, a second voltage threshold configuration circuit, and an FPGA. This circuit not only improves ranging accuracy, stability, and anti-interference capabilities, but also reduces costs.

[0051] like Figure 1 As shown, an embodiment of the present invention provides an FPGA-based laser measurement circuit, the laser measurement circuit including a laser emission circuit, a first voltage threshold configuration circuit, a second voltage threshold configuration circuit and an FPGA;

[0052] The laser emitting circuit includes a transmitting feedback signal terminal and a receiving signal terminal, the transmitting feedback signal terminal is connected to a first voltage threshold configuration circuit, and the receiving signal terminal is connected to a second voltage threshold configuration circuit; the laser emitting circuit is used to generate a transmitting feedback signal and a receiving signal, the transmitting feedback signal is a negative pulse with a fixed pulse width, and the receiving signal is a negative pulse with a pulse width that varies with signal strength; the transmitting feedback signal is input into the first voltage threshold configuration circuit via the transmitting feedback signal terminal, and the receiving signal is input into the second voltage threshold configuration circuit via the receiving signal terminal;

[0053] The first input signal point and the first detection signal point of the first voltage threshold configuration circuit are connected to two pins of the FPGA correspondingly. When the laser emission circuit generates a transmission feedback signal, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the transmission feedback signal.

[0054] The second input signal point and the second detection signal point of the second voltage threshold configuration circuit are connected to two other pins of the FPGA correspondingly. When the laser emission circuit generates a transmission feedback signal, if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse whose pulse width changes with the ratio of the signal strength, and the second positive pulse corresponds to the received signal.

[0055] The FPGA performs distance detection based on the first positive pulse and the second positive pulse.

[0056] refer to Figure 1 , Figure 1 The circuit includes an FPGA and a voltage threshold configuration circuit. STOP1+ is a transmission feedback signal. The transmission feedback signal STOP1+ is a negative pulse with a fixed pulse width of 5ns and an amplitude of about -1V. STOP2+ is a receiving signal. The amplitude of the receiving signal STOP2+ is a negative pulse of about -1V, and the pulse width changes with the signal strength.

[0057] The first input signal point STOP1N is configured to a DC voltage of 1.3V through the first voltage threshold configuration circuit, and the first detection signal point STOP1P is configured to a DC voltage of 0.8V. When there is no transmission feedback signal, the potential detected by the FPGA is a low level. When the transmission feedback signal is input to the FPGA through the first input signal point STOP1N, the FPGA detects the first positive pulse, and the pulse width of the first positive pulse is fixed.

[0058] Similarly, the second input signal point STOP2N is configured to a DC voltage of 1.3V and the second detection signal point STOP2P is configured to a DC voltage of 0.8V through the second voltage threshold configuration circuit. When there is no received signal, the potential detected by the FPGA is a low level. When the received signal generated by the laser emission circuit is input to the FPGA through the second input signal point STOP2N, the FPGA detects a second positive pulse, and the pulse width of the second positive pulse changes with the signal strength ratio.

[0059] It should be noted that since the pulse width of the transmitted feedback signal is fixed, the signal at the first input signal point also has a fixed pulse width, and the first positive pulse also has a fixed pulse width. Since the pulse width of the received signal varies with signal strength, the pulse width of the signal at the second input signal point also varies with signal strength, and the second positive pulse also varies with signal strength. The FPGA detects distance by comparing the time difference between the rising edge of the first positive pulse and the rising edge of the second positive pulse, and accurately calibrates the detected distance using the pulse width of the second positive pulse. The present invention ensures signal stability and detection accuracy through precise voltage division and filtering designs.

[0060] In some embodiments, the first voltage threshold configuration circuit configures the voltage threshold of the first input signal point to be a first DC voltage value, and configures the voltage value of the first detection signal point to be a second DC voltage value;

[0061] The first voltage threshold configuration circuit is configured to obtain a voltage value of the first input signal point by superimposing the voltage value of the transmit feedback signal and the first DC voltage value;

[0062] If the difference between the voltage value of the first input signal point and the second DC voltage value is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width.

[0063] It should be noted that if the difference between the voltage value of the first input signal point and the second DC voltage value is less than or equal to the difference threshold, the potential detected by the FPGA is a low level. This ensures the accuracy and stability of distance detection. The difference threshold can be flexibly adjusted according to actual application requirements to optimize detection sensitivity and anti-interference capabilities. Through the pulse width detection mechanism, the FPGA can efficiently handle complex signal environments, ensuring accurate and real-time data acquisition.

[0064] like Figure 2 As shown, in some embodiments, the first voltage threshold configuration circuit includes a first voltage divider circuit and a second voltage divider circuit;

[0065] The voltage dividing end of the first voltage dividing circuit is connected to the transmission feedback signal end and the first input signal point respectively, and the voltage dividing end of the second voltage dividing circuit is connected to the first detection signal point;

[0066] The voltage dividing end of the first voltage dividing circuit provides a third DC voltage value, and the voltage value of the first input signal point is obtained by adding the third DC voltage value and the voltage value of the transmission feedback signal end; the voltage dividing end of the second voltage dividing circuit provides a second DC voltage value to the first detection signal point;

[0067] It should be noted that the third DC voltage value is precisely adjusted to ensure that the voltage value at the first input signal point is within the ideal range, for example, 0.3V to 1.5V, thereby improving the FPGA's detection sensitivity to the first positive pulse. Simultaneously, the stability design of the second voltage divider circuit effectively reduces the impact of external interference on the second DC voltage value, further enhancing the reliability and accuracy of distance detection. This dual voltage divider circuit design enables the FPGA to stably identify signals in complex environments, ensuring real-time and accurate data processing. The FPGA achieves high-precision distance detection through precise time difference measurement and pulse width calibration.

[0068] When the difference between the voltage value of the first input signal point and the second DC voltage value is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width.

[0069] It should be noted that the ground terminal of the first voltage divider circuit and the ground terminal of the second voltage divider circuit are grounded together, and the power supply terminal of the first voltage divider circuit and the power supply terminal of the second voltage divider circuit are respectively connected to the power supply terminal; the difference threshold is 0.5V; the voltage comparison circuit built into the FPGA compares the voltage value of the first input signal point with the second DC voltage value. If the difference exceeds 0.5V, the pulse width detection logic is triggered, and the FPGA records the pulse time and combines the built-in clock to accurately calculate the distance. This design effectively filters out noise, ensures stable and reliable measurement results, and is suitable for a variety of complex environments. Through this precise voltage comparison and pulse width detection mechanism, the FPGA can complete distance calculation within milliseconds, improve the system's response speed and measurement accuracy, and meet the needs of high-precision applications.

[0070] In some embodiments, the first voltage divider circuit includes a first resistor and a second resistor, one end of the first resistor is connected to the first power supply terminal, the other end of the first resistor is respectively connected to the transmission feedback signal terminal, the first input signal point, and one end of the second resistor, and the other end of the second resistor is grounded;

[0071] The second voltage divider circuit includes a third resistor and a fourth resistor, one end of the third resistor is connected to the second power supply end, the other end of the third resistor is respectively connected to the transmission feedback signal end and one end of the fourth resistor, and the other end of the fourth resistor is grounded.

[0072] It should be noted that the first power supply terminal is grounded via a fifth capacitor, and the second power supply terminal is grounded via a sixth capacitor. In some embodiments, the capacitance of the fifth and sixth capacitors is set to 0.1 μF. The fifth and sixth capacitors filter out power supply noise, improving circuit stability. By optimizing the capacitor configuration, the purity of the voltage signal is ensured, thereby improving the detection accuracy of the FPGA and the overall performance of the system.

[0073] In some embodiments, the first voltage threshold configuration circuit further includes a first filtering circuit and a second filtering circuit, the first filtering circuit includes a first capacitor and a second capacitor, and the first capacitor, the second capacitor and the second resistor are connected in parallel;

[0074] The first voltage threshold configuration circuit further includes the second filtering circuit including a third capacitor and a fourth capacitor, and the third capacitor, the fourth capacitor and the fourth resistor are connected in parallel.

[0075] It should be noted that a fifth resistor is connected between the first input signal point and the transmission feedback signal terminal, a sixth resistor is connected between the first input signal point and the voltage divider terminal of the first voltage divider circuit, and a seventh resistor is connected between the first detection signal point and the voltage divider terminal of the second voltage divider circuit. The fifth, sixth, and seventh resistors all function as current limiters.

[0076] like Figure 3 As shown, in some embodiments, the second voltage threshold configuration circuit configures the voltage threshold of the second input signal point to be a third DC voltage value, and configures the voltage value of the second detection signal point to be a fourth DC voltage value;

[0077] The second voltage threshold configuration circuit is configured to obtain a voltage value of the second input signal point by superimposing the voltage value of the received signal and a third DC voltage value;

[0078] If the difference between the voltage value of the second input signal point and the fourth DC voltage value is greater than the difference threshold, the FPGA detects a second positive pulse with a fixed pulse width.

[0079] It should be noted that if the difference between the voltage value of the second input signal point and the fourth DC voltage value is less than or equal to the difference threshold, the potential detected by the FPGA is a low level, and the FPGA will not detect a pulse value.

[0080] In some embodiments, the second voltage threshold configuration circuit includes a third voltage divider circuit and a fourth voltage divider circuit;

[0081] The voltage dividing end of the third voltage dividing circuit is connected to the signal receiving end and the second input signal point respectively, and the voltage dividing end of the fourth voltage dividing circuit is connected to the second detection signal point;

[0082] The voltage dividing end of the third voltage dividing circuit provides a third DC voltage value, and the voltage value of the second input signal point is obtained by adding the third DC voltage value and the voltage value of the signal receiving end; the voltage dividing end of the fourth voltage dividing circuit provides a fourth DC voltage value to the second detection signal point;

[0083] When the difference between the voltage value of the second input signal point and the fourth DC voltage value is greater than the difference threshold, the FPGA detects a second positive pulse with a fixed pulse width.

[0084] It should be noted that the grounding end of the third voltage-dividing circuit and the grounding end of the fourth voltage-dividing circuit are grounded together, the power supply end of the first voltage-dividing circuit and the power supply end of the second voltage-dividing circuit are respectively connected to the power supply end; the difference threshold is 0.5V.

[0085] In some embodiments, the third voltage divider circuit includes an eighth resistor and a ninth resistor, one end of the eighth resistor is connected to the third power supply terminal, the other end of the eighth resistor is respectively connected to the signal receiving terminal, the second input signal point, and one end of the ninth resistor, and the other end of the ninth resistor is grounded;

[0086] The fourth voltage divider circuit includes a tenth resistor and an eleventh resistor, one end of the tenth resistor is connected to the fourth power supply end, the other end of the tenth resistor is respectively connected to the signal receiving end and one end of the eleventh resistor, and the other end of the eleventh resistor is grounded.

[0087] It should be noted that the third power supply terminal is grounded via an eleventh capacitor, and the fourth power supply terminal is grounded via a twelfth capacitor.

[0088] In some embodiments, the first voltage threshold configuration circuit further includes a third filtering circuit and a fourth filtering circuit, the third filtering circuit includes a seventh capacitor and an eighth capacitor, and the seventh capacitor, the eighth capacitor and the ninth resistor are connected in parallel;

[0089] The fourth filtering circuit includes a ninth capacitor and a tenth capacitor, and the ninth capacitor, the tenth capacitor and the tenth resistor are connected in parallel.

[0090] It should be noted that a twelfth resistor is also connected between the second input signal point and the receiving signal end, a thirteenth resistor is also connected between the second input signal point and the voltage divider end of the third voltage divider circuit, and a fourteenth resistor is also connected between the second detection signal point and the voltage divider end of the fourth voltage divider circuit.

[0091] like Figure 4 As shown, an embodiment of the present invention provides an FPGA-based laser measurement method, which is applied to the FPGA-based laser measurement system in any of the above embodiments. The method includes the following steps:

[0092] S100, generating a transmission feedback signal and a reception signal by the laser transmission circuit, the transmission feedback signal being input into a first voltage threshold configuration circuit via a transmission feedback signal terminal, and the reception signal being input into a second voltage threshold configuration circuit via a reception signal terminal; wherein the transmission feedback signal is a negative pulse with a fixed pulse width, and the reception signal is a negative pulse with a pulse width that varies with signal strength;

[0093] S200, when the laser emitting circuit generates a transmission feedback signal, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the transmission feedback signal; when the laser emitting circuit generates a transmission feedback signal, if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse with a pulse width that varies with a ratio of signal strengths, and the second positive pulse corresponds to the received signal;

[0094] S300 , performing distance detection based on the first positive pulse and the second positive pulse by the FPGA.

[0095] It can be seen that the contents of the above circuit embodiments are all applicable to the present method embodiments. The functions specifically implemented by the present method embodiments are the same as those of the above circuit embodiments, and the beneficial effects achieved are also the same as those achieved by the above circuit embodiments.

[0096] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one location or distributed across multiple network units. Some or all of the charging modules may be selected to achieve the objectives of this embodiment based on actual needs.

[0097] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional charging modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0098] The terms "first," "second," "third," "fourth," and the like (if any) in the specification of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the application described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product, or apparatus.

[0099] It should be understood that in this application, "at least one (item)" means one or more, and "more" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or plural.

[0100] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0101] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0102] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0103] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store programs, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0104] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A laser measurement circuit based on FPGA, characterized in that: The laser measurement circuit includes a laser emitting circuit, a receiving circuit, a first voltage threshold configuration circuit, a second voltage threshold configuration circuit and an FPGA; The laser emitting circuit includes a transmitting feedback signal terminal and a receiving signal terminal, wherein the transmitting feedback signal terminal is connected to a first voltage threshold configuration circuit, and the receiving signal terminal is connected to a second voltage threshold configuration circuit; the laser emitting circuit is used to generate a transmitting feedback signal and a receiving signal, wherein the transmitting feedback signal is a negative pulse with a fixed pulse width, and the receiving signal is a negative pulse with a pulse width that varies with signal strength; The transmission feedback signal is input into the first voltage threshold configuration circuit via the transmission feedback signal terminal, and the reception signal is input into the second voltage threshold configuration circuit via the reception signal terminal; The first input signal point and the first detection signal point of the first voltage threshold configuration circuit are connected to two pins of the FPGA correspondingly. When the laser emission circuit generates a transmission feedback signal, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than the difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the transmission feedback signal. The second input signal point and the second detection signal point of the second voltage threshold configuration circuit are connected to two other pins of the FPGA correspondingly. When the laser emission circuit generates a transmission feedback signal, if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse whose pulse width changes with the ratio of the signal strength, and the second positive pulse corresponds to the received signal. The FPGA performs distance detection based on the first positive pulse and the second positive pulse.

2. The laser measurement circuit according to claim 1, characterized in that The first voltage threshold configuration circuit configures the voltage threshold of the first input signal point to be a first DC voltage value, and configures the voltage value of the first detection signal point to be a second DC voltage value; The first voltage threshold configuration circuit is configured to obtain a voltage value of the first input signal point by superimposing the voltage value of the transmit feedback signal and the first DC voltage value; If the difference between the voltage value of the first input signal point and the second DC voltage value is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width.

3. The laser measurement circuit according to claim 2, characterized in that: The first voltage threshold configuration circuit includes a first voltage dividing circuit and a second voltage dividing circuit; The voltage dividing end of the first voltage dividing circuit is connected to the transmission feedback signal end and the first input signal point respectively, and the voltage dividing end of the second voltage dividing circuit is connected to the first detection signal point; The voltage dividing end of the first voltage dividing circuit provides a third DC voltage value, and the voltage value of the first input signal point is obtained by superimposing the third DC voltage value and the voltage value of the transmission feedback signal end; The voltage dividing end of the second voltage dividing circuit provides a second DC voltage value to the first detection signal point; When the difference between the voltage value of the first input signal point and the second DC voltage value is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width.

4. The laser measurement circuit according to claim 3, characterized in that: The first voltage divider circuit includes a first resistor and a second resistor, one end of the first resistor is connected to the first power supply terminal, the other end of the first resistor is respectively connected to the transmission feedback signal terminal, the first input signal point and one end of the second resistor, and the other end of the second resistor is grounded; The second voltage divider circuit includes a third resistor and a fourth resistor, one end of the third resistor is connected to the second power supply end, the other end of the third resistor is respectively connected to the transmission feedback signal end and one end of the fourth resistor, and the other end of the fourth resistor is grounded.

5. The laser measurement circuit according to claim 4, characterized in that: The first voltage threshold configuration circuit further includes a first filtering circuit and a second filtering circuit, the first filtering circuit includes a first capacitor and a second capacitor, and the first capacitor, the second capacitor and the second resistor are connected in parallel; The first voltage threshold configuration circuit further includes the second filtering circuit including a third capacitor and a fourth capacitor, and the third capacitor, the fourth capacitor and the fourth resistor are connected in parallel.

6. The laser measurement circuit according to claim 1, characterized in that: The second voltage threshold configuration circuit configures the voltage threshold of the second input signal point to be a third DC voltage value, and configures the voltage value of the second detection signal point to be a fourth DC voltage value; The second voltage threshold configuration circuit is configured to obtain a voltage value of the second input signal point by superimposing the voltage value of the received signal and a third DC voltage value; If the difference between the voltage value of the second input signal point and the fourth DC voltage value is greater than the difference threshold, the FPGA detects a second positive pulse with a fixed pulse width.

7. The laser measurement circuit according to claim 6, characterized in that: The second voltage threshold configuration circuit includes a third voltage dividing circuit and a fourth voltage dividing circuit; The voltage dividing end of the third voltage dividing circuit is connected to the signal receiving end and the second input signal point respectively, and the voltage dividing end of the fourth voltage dividing circuit is connected to the second detection signal point; The voltage dividing end of the third voltage dividing circuit provides a third DC voltage value, and the voltage value of the second input signal point is obtained by adding the third DC voltage value and the voltage value of the signal receiving end; the voltage dividing end of the fourth voltage dividing circuit provides a fourth DC voltage value to the second detection signal point; When the difference between the voltage value of the second input signal point and the fourth DC voltage value is greater than the difference threshold, the FPGA detects a second positive pulse with a fixed pulse width.

8. The laser measurement circuit according to claim 7, characterized in that: The third voltage divider circuit includes an eighth resistor and a ninth resistor, one end of the eighth resistor is connected to the third power supply terminal, the other end of the eighth resistor is respectively connected to the signal receiving terminal, the second input signal point and one end of the ninth resistor, and the other end of the ninth resistor is grounded; The fourth voltage divider circuit includes a tenth resistor and an eleventh resistor, one end of the tenth resistor is connected to the fourth power supply end, the other end of the tenth resistor is respectively connected to the signal receiving end and one end of the eleventh resistor, and the other end of the eleventh resistor is grounded.

9. The laser measurement circuit according to claim 8, characterized in that: The first voltage threshold configuration circuit further includes a third filtering circuit and a fourth filtering circuit, the third filtering circuit includes a seventh capacitor and an eighth capacitor, and the seventh capacitor, the eighth capacitor and the ninth resistor are connected in parallel; The fourth filtering circuit includes a ninth capacitor and a tenth capacitor, and the ninth capacitor, the tenth capacitor and the tenth resistor are connected in parallel.

10. A laser measurement method based on FPGA, characterized in that: Applied to the FPGA-based laser measurement circuit according to any one of claims 1 to 9, the method comprises the following steps: S100, generating a transmission feedback signal and a reception signal by the laser transmission circuit, the transmission feedback signal being input into a first voltage threshold configuration circuit via a transmission feedback signal terminal, and the reception signal being input into a second voltage threshold configuration circuit via a reception signal terminal; wherein the transmission feedback signal is a negative pulse with a fixed pulse width, and the reception signal is a negative pulse with a pulse width that varies with signal strength; S200, when the laser emitting circuit generates a transmission feedback signal, if the difference between the voltage value of the first input signal point and the voltage value of the first detection signal point is greater than a difference threshold, the FPGA detects a first positive pulse with a fixed pulse width, and the first positive pulse corresponds to the transmission feedback signal; when the laser emitting circuit generates a transmission feedback signal, if the difference between the voltage value of the second input signal point and the voltage value of the second detection signal point is greater than the difference threshold, the FPGA detects a second positive pulse with a pulse width that varies with a ratio of signal strengths, and the second positive pulse corresponds to the received signal; S300 , performing distance detection based on the first positive pulse and the second positive pulse by the FPGA.

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