Manufacturing method of array substrate, array substrate, display panel and display device

Abstract

The invention discloses a manufacturing method of an array substrate, the array substrate, a display panel and a display device, and relates to the technical field of display.The manufacturing method of the array substrate comprises the steps that a substrate, an insulating material and a metal material are provided; depositing a metal material on the surface of the substrate to form a first metal layer; etching the first metal layer, and forming a first data line and a grid electrode on the surface, corresponding to the non-opening region, of the substrate; depositing an insulating material on the surfaces of the grid electrode, the first data line and the substrate to form a grid electrode insulating layer; and removing the gate insulating layer formed on the surface, corresponding to the opening region, of the substrate. According to the display panel, the gate insulating layer of the opening area of the array substrate is removed, so that interference generated after a light source passes through the gate insulating layer is reduced, the problems that the brightness of a picture of the display panel is not uniform and colors have deviation are solved, and the display effect of the display panel and the use experience of a user are improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a method for manufacturing an array substrate, an array substrate, a display panel and a display device. Background Art

[0002] As a widely used display technology, the working principle of liquid crystal display panel is based on the optical anisotropy of liquid crystal material. The arrangement state of liquid crystal molecules is changed by external electric field, thereby controlling the transmittance of light and realizing the function of image display. Liquid crystal display panel includes light source, array substrate, liquid crystal molecule layer and color film substrate. Among them, the array substrate includes substrate and data lines, thin film transistors (TFT), pixel electrodes and common electrodes deposited on the surface of the substrate. The data lines, thin film transistors (TFT), pixel electrodes and common electrodes are separated by insulating layers to ensure the normal operation of the circuit.

[0003] The light emitted by the light source will be transmitted and reflected when passing through different film layers, thus causing the interference effect of light. Since there are many film layers stacked on the substrate surface of the array substrate, the light will interfere multiple times when passing through the array substrate. Some light will constructively interfere between the interfaces of different film layers, enhancing the light intensity of certain wavelengths; while some light will destructively interfere, weakening the light intensity of the corresponding wavelengths. This interference effect will not only cause uneven brightness of the display screen, but also cause color deviation, affecting the overall display quality of the liquid crystal display panel and the user experience. Summary of the invention

[0004] The main purpose of the present invention is to provide a method for manufacturing an array substrate, an array substrate, a display panel and a display device, aiming to solve the problem of uneven brightness and color deviation of the displayed image caused by multiple interferences when light passes through the array substrate.

[0005] To achieve the above object, the present invention provides a method for manufacturing an array substrate, comprising the steps of:

[0006] providing a substrate;

[0007] Depositing a metal material on the surface of the substrate to form a first metal layer;

[0008] Etching the first metal layer, and forming a first data line and a gate on the surface of the substrate corresponding to the non-opening area;

[0009] Depositing an insulating material on the surface of the gate, the first data line and the substrate to form a gate insulating layer;

[0010] The gate insulating layer formed on the surface of the substrate corresponding to the opening area is removed.

[0011] In one embodiment of the present invention, after the step of removing the gate insulating layer formed on the surface of the substrate corresponding to the opening area, the step includes:

[0012] removing the gate insulating layer formed on the surface of the first data line;

[0013] On the surface of the substrate corresponding to the opening area 、 Depositing the metal material on the surface of the first data line and the surface of the gate insulating layer to form a second metal layer;

[0014] The portion of the second metal layer corresponding to the opening area is etched to form a second data line on the surface of the first data line, and a source electrode and a drain electrode are formed on the surface of the gate insulating layer.

[0015] In one embodiment of the present invention, the step of etching a portion of the second metal layer corresponding to the opening area to form a second data line on the surface of the first data line and forming a source electrode and a drain electrode on the surface of the gate insulating layer comprises:

[0016] Depositing the insulating material on a surface of the substrate, a surface of the second data line, a surface of the gate insulating layer, a surface of the source electrode, and a surface of the drain electrode to form a first insulating layer;

[0017] The first insulating layer formed on the surface of the substrate corresponding to the opening area is removed.

[0018] In one embodiment of the present invention, after the step of removing the first insulating layer formed on the surface of the substrate corresponding to the opening area, the step includes:

[0019] forming a planar layer on a surface of the substrate corresponding to the opening area and a surface of the first insulating layer;

[0020] A common electrode, a second insulating layer and a pixel electrode are sequentially formed on the surface of the planar layer.

[0021] The present invention further provides an array substrate, the array substrate comprising:

[0022] substrate;

[0023] A thin film transistor, wherein the thin film transistor is disposed on a surface of the substrate corresponding to the non-opening area, and the thin film transistor comprises a gate electrode, a gate insulating layer, a semiconductor layer, a drain electrode, and a source electrode which are sequentially stacked on the surface of the substrate;

[0024] a data line, the data line being disposed on a surface of the substrate corresponding to the non-opening area and electrically connected to the thin film transistor; and

[0025] A first insulating layer is disposed in the non-opening area and is located on a surface of the thin film transistor and a surface of the data line.

[0026] In an embodiment of the present invention, the data line includes a first data line and a second data line, the first data line is disposed on the surface of the substrate, and the second data line is disposed on the surface of the first data line.

[0027] In one embodiment of the present invention, the second data line, the source electrode and the drain electrode are formed in the same metal layer.

[0028] In one embodiment of the present invention, the first data line is located within the orthographic projection of the second data line on the first data line, and both sides of the second data line in the width direction extend along both sides of the first data line in the width direction and both contact the substrate.

[0029] The present invention also proposes a display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate as described above, wherein the array substrate and the color filter substrate are combined to form a liquid crystal box, the liquid crystal layer is filled in the liquid crystal box and is located between the array substrate and the color filter substrate.

[0030] The present invention further provides a display device, comprising a backlight module and the display panel as described above, wherein the display panel is arranged on the light emitting side of the backlight module.

[0031] The manufacturing method of the array substrate proposed by the present invention includes first depositing a metal material on the surface of the substrate to form a first metal layer, then patterning the first metal layer, etching the first metal layer, and then forming a first data line and a gate at the non-opening area corresponding to the array substrate. Then, an insulating material is deposited on the gate, the first data line and the surface of the substrate, and a gate insulating layer is formed on the surface thereof, and the gate insulating layer isolates the gate from the first data line and the drain and source of the thin film transistor. Finally, the gate insulating layer of the array substrate in the opening area is removed to reduce the interference of the light source after passing through the gate insulating layer, thereby improving the problem of uneven brightness and color deviation of the display panel, and improving the display effect of the display panel and the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0033] Figure 1A schematic structural diagram of an embodiment of an array substrate provided by the present invention;

[0034] Figure 2 for Figure 1 Section view along AA;

[0035] Figure 3 for Figure 1 Sectional view along BB;

[0036] Figure 4 for Figure 1 A cross-sectional view of another embodiment of the array substrate along the line BB;

[0037] Figure 5 A flow chart of an embodiment of a method for manufacturing an array substrate provided by the present invention;

[0038] Figure 6 for Figure 5 A flow chart after the step of removing the gate insulating layer formed on the surface of the substrate corresponding to the opening area;

[0039] Figure 7 for Figure 6 A flow chart after the steps of forming a second data line, a source electrode and a drain electrode;

[0040] Figure 8 for Figure 7 The flowchart is after the step of removing the surface of the substrate corresponding to the opening area to form the first insulating layer.

[0041] Description of Figure Numbers:

[0042] 1. array substrate; 10. substrate; 21. gate; 22. first data line; 30. gate insulating layer; 41. source; 42. drain; 43. second data line; 44. semiconductor layer; 50. first insulating layer; 60. planar layer; 70. common electrode; 80. second insulating layer; 90. pixel electrode; 100. opening area; 200. non-opening area.

[0043] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0046] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0047] The present invention provides a method for manufacturing an array substrate 1. The array substrate 1 may be a FFS (Fringe Field Switching) structure, a VA (Vertical Alignment) structure, an IPS (In-Plane Switching) structure, etc. The inventive concept proposed in this application can be applied to the above-mentioned various structures. In the FFS structure, the IGZO (Indium Gallium Zinc Oxide) oxide product has more film layers stacked on the array substrate 1, and light is more likely to interfere. Therefore, this application takes the IGZO oxide product in the FFS structure as an example to explain the method for manufacturing the array substrate 1, and other structures are not explained one by one.

[0048] Combination Figures 1 to 5 As shown, in one embodiment of the present invention, a method for manufacturing an array substrate 1 comprises the steps of:

[0049] Providing a substrate 10;

[0050] S10: depositing a metal material on the surface of the substrate 10 to form a first metal layer;

[0051] S20: etching the first metal layer, and forming a first data line 22 and a gate 21 on the surface of the substrate 10 corresponding to the opening area 100;

[0052] S30: depositing an insulating material on the surface of the gate 21 , the first data line 22 and the substrate 10 to form a gate insulating layer 30 ;

[0053] S40 : removing the gate insulating layer 30 formed on the surface of the substrate 10 corresponding to the opening area 100 .

[0054] In this embodiment, the material of the substrate 10 can be a transparent material such as glass or plastic, so that the backlight source of the subsequent display panel can pass through the substrate 10. The insulating material can be silicon dioxide, silicon nitride or other suitable inorganic insulating materials, which have good insulation performance and stability. The metal material can be selected from metals with good conductivity such as aluminum, copper, molybdenum, etc. to ensure that the first metal layer has good conductivity.

[0055] When forming the first metal layer on the surface of the substrate 10 , a physical vapor deposition (PVD) or chemical vapor deposition (CVD) method may be used to deposit a metal material on the surface of the substrate 10 to form the first metal layer.

[0056] After the first metal layer is deposited, it is necessary to pattern the first metal layer to form the circuit pattern required by the array substrate 1. Specifically, a pre-designed first metal layer mask is placed on the surface of the first metal layer, and a wet etching or dry etching technique is used to etch the first metal layer corresponding to the mask window, thereby transferring the pattern of the mask to the first metal layer, and forming the first data line 22 and the gate 21 in the non-opening area 200. Of course, the first metal layer can also be patterned by photolithography and etching processes, for example, a photoresist is coated on the surface of the first metal layer, and then the photoresist layer is exposed, developed, and patterned; then the first metal layer is etched again, and the portion blocked by the photoresist layer is retained to form the first data line 22 and the gate 21, and the first metal layer exposed in the photoresist layer opening area 100 is etched away, thereby achieving patterning of the first metal layer.

[0057] After etching is completed, the array substrate 1 needs to be cleaned. Pure water or organic solvents can be used for cleaning to remove the residues of the first metal layer, while improving the surface adhesion of the first metal layer and the substrate 10, thereby improving the connection strength between the first metal layer, the substrate 10 and the film layer thereon.

[0058] The gate 21 is used to receive the scanning signal and turn on the thin film transistor according to the cycle of the scanning signal. Since the thin film transistor is arranged in the non-opening area 200 and the gate 21 is made of metal material, the gate 21 will block the propagation of light. Therefore, the gate 21 is arranged in the non-opening area 200, which is convenient for connecting the gate line 21 with the thin film transistor while avoiding affecting the area of ​​the display area of ​​the display panel (that is, increasing the aperture ratio of the display panel).

[0059] The first data line 22 is connected to the source electrode 41 of the thin film transistor, and transmits the voltage signal and the image signal to the pixel electrode 90 in each pixel unit to display the image.

[0060] After the first metal layer is patterned, an insulating material is then deposited on the surface of the gate 21, the first data line 22, and the surface of the opening area 100 corresponding to the substrate 10 to form a gate insulating layer 30. Specifically, the insulating material is deposited on the surface of the substrate 10 and the first metal layer by using methods such as chemical vapor deposition (CVD) or atomic layer deposition technology (ALD) to form the gate insulating layer 30. The material of the gate insulating layer 30 is SiNx (silicon nitride) or SiOx (silicon oxide). SiNx and SiOx have a high dielectric constant, which can improve the insulation performance between the first metal layer and other film layers, and between the gate 21 and the first data line 22 in the first metal layer, and improve the breakdown voltage. In addition, SiNx and SiOx have good light transmittance, which can reduce the absorption and reflection of light.

[0061] Although the material of the gate insulating layer 30 has good light transmittance, light will interfere with each other between different film layers. Therefore, after the gate insulating layer 30 is deposited, the gate insulating layer 30 of the array substrate 1 in the opening area 100 needs to be removed. The specific steps of removing the gate insulating layer 30 are as follows:

[0062] First, a mask plate with a specific pattern is prepared, and the window on the mask plate corresponds to the opening area 100 of the array substrate 1. The mask plate is placed on the gate insulating layer 30 so that the portion of the gate insulating layer 30 located in the opening area 100 is exposed.

[0063] Then, a dry etching process is used to select a suitable etching gas (such as a fluorine-based gas) for etching according to the material of the gate insulating layer 30. The advantage of dry etching over wet etching is its high precision and controllability. It can accurately remove the gate insulating layer 30 in the opening area 100 and cause less damage to the surrounding film structure. During the etching process, the etching process can be optimized by adjusting parameters such as gas flow, pressure and power to obtain the required etching depth and width. Of course, in other embodiments, an etching barrier layer can also be applied to the surface of the gate insulating layer 30 in the non-opening area 200, and the gate insulating layer 30 in the non-opening area 200 can be etched away by a wet etching process.

[0064] After the etching is completed, the substrate 10 and the film structures deposited on the surface of the substrate 10 are cleaned to remove the residual etching products and impurities. After the cleaning is completed, other film layers are deposited, such as the planar layer 60, the electrode layer, etc.

[0065] The manufacturing method of the array substrate 1 proposed in the present application removes the gate insulating layer 30 of the array substrate 1 in the opening area 100 to reduce the interference caused when the light source passes through the gate insulating layer 30, thereby improving the problems of uneven brightness and color deviation of the display panel, and improving the display effect of the display panel and the user experience.

[0066] Combination Figure 3 , Figure 4 as well as Figure 6 As shown, in one embodiment of the present invention, after the step of removing the gate insulating layer 30 formed on the surface of the substrate 10 corresponding to the opening area 100, the following steps are included:

[0067] S50: removing the gate insulating layer 30 formed on the surface of the first data line 22;

[0068] S60: depositing a metal material on the surface of the substrate 10 corresponding to the opening area 100 , the surface of the first data line 22 , and the surface of the gate insulating layer 30 to form a second metal layer;

[0069] S70 : etching the portion of the second metal layer corresponding to the opening area 100 to form the second data line 43 on the surface of the first data line 22 , and forming the source electrode 41 and the drain electrode 42 on the surface of the gate insulating layer 30 .

[0070] In this embodiment, when the gate insulating layer 30 formed on the surface of the substrate 10 corresponding to the opening area 100 is removed, the gate insulating layer 30 formed on the surface of the first data line 22 may be removed at the same time to reduce the number of process steps.

[0071] The step of depositing the second metal layer can be achieved by physical vapor deposition (PVD) or chemical vapor deposition (CVD). For example, PVD technology can be used to control the deposition rate and the thickness of the second metal layer by adjusting parameters such as sputtering power, pressure of the working gas, and deposition time.

[0072] Then, the second metal layer is patterned. Specifically, the second metal layer is etched using a wet etching or dry etching technique to form the required second data line 43, source 41, and drain 42. In this process, a mask plate can be set, and then the mask plate is covered on the surface of the second metal layer, and then the pattern of the mask plate is transferred to the second metal layer by dry etching; or a photoresist etching barrier layer can be formed on the surface of the second metal layer by photolithography and etching processes, and then the second metal layer exposed in the photoresist etching barrier layer window is etched by a wet etching process. The specific steps can refer to the above-mentioned etching steps for the first metal layer, and no further description is given here.

[0073] Since the data line is made of metal, it will block the transmission of light, resulting in a decrease in the aperture ratio of the display panel. Therefore, it is necessary to design the width of the data line to be smaller to increase the aperture ratio. However, reducing the width of the data line will increase the impedance of the data line. The larger impedance causes mischarging or insufficient charging of each pixel of the display panel, resulting in poor uniformity of display quality. Therefore, it is necessary to increase the thickness of the data line. The present application etches the gate insulating layer 30 on the surface of the first data line 22, and then deposits the second metal layer on the surface of the first metal layer, so that the opening area 100 forms two metal lines superimposed on each other, that is, the second data line 43 covers the first data line 22, thereby increasing the overall thickness of the data line and improving the above-mentioned problem of poor uniformity of display quality.

[0074] After the second metal layer is patterned, a source 41 and a drain 42 are formed in the non-opening area 200. The source 41 and the drain 42 are respectively connected to the semiconductor layer 44 (the semiconductor layer 44 is formed on the surface of the gate insulating layer 30 corresponding to the gate 21 before the second metal layer is deposited), and are responsible for transmitting and receiving current signals.

[0075] Combination Figure 4 and Figure 7 As shown, in one embodiment of the present invention, after etching the portion of the second metal layer corresponding to the opening area 100 to form the second data line 43 on the surface of the first data line 22 and forming the source 41 and the drain 42 on the surface of the gate insulating layer 30, the steps include:

[0076] S80: depositing an insulating material on the surface of the substrate 10 , the surface of the second data line 43 , the surface of the gate insulating layer 30 , the surface of the source electrode 41 , and the surface of the drain electrode 42 to form a first insulating layer 50 ;

[0077] S90 : removing the first insulating layer 50 formed on the surface of the substrate 10 corresponding to the opening area 100 .

[0078] In this embodiment, the step of depositing the first insulating layer 50 can be achieved by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The material of the first insulating layer 50 is SiNx (silicon nitride) / SiOx (silicon oxide). The first insulating layer 50 is mainly used to isolate the second metal layer and other functional layers, and to isolate the metal traces patterned in the second metal layer to prevent short circuits between these film layers or traces.

[0079] Although the material of the first insulating layer 50 also has good light transmittance, due to the different materials between different film layers, light will interfere with each other. Therefore, after the deposition of the first insulating layer 50 is completed, the first insulating layer 50 corresponding to the opening area 100 of the substrate 10 needs to be removed. The specific steps of removing the first insulating layer 50 are as follows:

[0080] First, a mask with a specific pattern is prepared, the pattern on the mask corresponding to the opening area 100 of the array substrate 1. Then the mask is placed on the first insulating layer 50 so that the portion of the first insulating layer 50 located in the opening area 100 is exposed.

[0081] Then, a dry etching process is used and a suitable etching gas is selected according to the material of the first insulating layer 50 to perform etching, so as to remove the first insulating layer 50 in the opening area 100 and retain the first insulating layer 50 in the non-opening area 200 .

[0082] After the etching is completed, each film layer structure deposited on the surface of the substrate 10 is cleaned to remove the residual etching products and impurities.

[0083] The present application further reduces the number of interferences that occur when light passes through the array substrate 1 by removing the first insulating layer 50 located in the opening area 100, making the brightness of the display panel more uniform and the color performance more consistent, significantly improving the user's visual experience. In addition, the first insulating layer 50 located in the non-opening area 200 is retained to maintain good insulation performance between the layers.

[0084] Combination Figures 2 to 4 as well as Figure 8 As shown, in one embodiment of the present invention, after removing the surface of the substrate 10 corresponding to the opening area 100 to form the first insulating layer 50, the step includes:

[0085] S100 : forming a planarization layer 60 on a surface of the substrate 10 corresponding to the opening region 100 and a surface of the first insulating layer 50 ;

[0086] S110 : forming a common electrode 70 , a second insulating layer 80 and a pixel electrode 90 in sequence on the surface of the planar layer 60 .

[0087] In this embodiment, the step of depositing the planar layer 60 can be achieved by chemical vapor deposition (CVD) or spin coating. The main function of the planar layer 60 is to fill the grooves formed when the film layers on the surface of the substrate 10 are formed, and to provide a flat base on the side of the planar layer 60 away from the substrate 10, so that the common electrode 70, the second insulating layer 80 and the pixel electrode 90 formed subsequently are more uniform and consistent.

[0088] The material of the planar layer 60 is PFA (Perfluoroalkoxy) or polyimide (PI), etc. PFA has good high temperature resistance, chemical stability, insulation and light transmittance, so it can play a good protective role and electrical isolation role for each film layer of the array substrate 1, and can also ensure the light transmittance effect of the array substrate 1.

[0089] Then, a layer of transparent conductive material, such as indium tin oxide (ITO) or zinc oxide (ZnO), is deposited on the planar layer 60 by physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form a common electrode 70. The common electrode 70 is used to provide a uniform electric field in the entire display area to control the arrangement of liquid crystal molecules.

[0090] Then, a layer of insulating material, such as silicon dioxide (SiO2) or silicon nitride (SiNx), is deposited on the common electrode 70 to form a second insulating layer 80. The main function of the second insulating layer 80 is to isolate the common electrode 70 and the pixel electrode 90 to prevent a short circuit between the common electrode 70 and the pixel electrode 90. Compared with SiO2, silicon nitride generally has a higher dielectric strength and a lower dielectric constant, which helps to further reduce the parasitic capacitance between circuits and improve the signal transmission speed. In addition, SiNx has excellent moisture resistance, can effectively block moisture and other corrosive gases, and provide better protection for electronic components. Therefore, in one embodiment, the material of the second insulating layer 80 is silicon nitride (SiNx) to improve the protective effect of the second insulating layer 80 on each film layer of the array substrate 1, as well as the insulation effect between the common electrode 70 and the pixel electrode 90.

[0091] Finally, a layer of transparent conductive material, such as indium tin oxide (ITO) or zinc oxide (ZnO), is deposited again on the second insulating layer 80 to form a pixel electrode 90. The pixel electrode 90 is connected to the drain electrode 42 of the thin film transistor, and forms a parallel electric field with the common electrode 70, thereby adjusting the arrangement of the liquid crystal layer to adjust the display effect of the display panel. Specifically, a through hole is etched on the surface of the flat layer 60 to expose the drain electrode 42 of the thin film transistor in the through hole, and the first insulating layer 50 is deposited to extend to the side wall of the through hole, and then the pixel electrode 90 is deposited in the through hole and electrically connected to the drain electrode 42.

[0092] The present invention further provides an array substrate 1, which is manufactured by the above manufacturing method. The specific steps of the manufacturing method can refer to the introduction in the above embodiment, and no further description is given here.

[0093] Among them, combined Figure 1 and Figure 2As shown, in one embodiment of the present invention, the array substrate 1 has an opening area 100 and a non-opening area 200, and the array substrate 1 includes a substrate 10, a thin film transistor, a data line and a first insulating layer 50; the thin film transistor is arranged on the surface of the substrate 10 corresponding to the non-opening area 200, and the thin film transistor includes a gate 21, a gate insulating layer 30, a semiconductor layer 44, a drain 42 and a source 41 stacked in sequence on the surface of the substrate 10; the data line is arranged on the surface of the substrate 10 corresponding to the non-opening area 200, and is electrically connected to the thin film transistor; the first insulating layer 50 is arranged in the non-opening area 200, and is located on the surface of the thin film transistor and the surface of the data line.

[0094] In this embodiment, the gate 21 is used to receive the scanning signal and control the opening and closing of the thin film transistor; the gate insulating layer 30 isolates the gate 21 from the semiconductor layer 44, the gate 21 from the drain 42 and the source 41 to prevent short circuits between them; the semiconductor layer 44 is IGZO oxide or other semiconductor materials, which is used to form the channel region of the thin film transistor; the source 41 and the drain 42 are respectively connected to the data line and the pixel electrode 90, responsible for transmitting and receiving current signals. The data line is arranged on the surface of the substrate 10 located in the non-opening area 200, and is electrically connected to the thin film transistor, and is used to transmit the image signal and the voltage signal to the pixel unit. This array substrate 1 prevents the thin film transistor from interfering with the transmission of light by arranging the thin film transistor in the non-opening area 200.

[0095] In addition, the gate insulating layer 30 located in the opening area 100 is removed so that the gate insulating layer 30 is only arranged in the non-opening area 200, thereby reducing the number of film layers in the opening area 100 and reducing the number of interferences that occur when light passes through the array substrate 1, thereby improving the brightness uniformity and color consistency of the display panel.

[0096] The gate insulating layer 30 and the first insulating layer 50 are made of silicon dioxide (SiO2) or silicon nitride (SiNx). The first insulating layer 50 is mainly used to isolate the thin film transistor and other functional layers to prevent short circuits between them. In addition, the first insulating layer 50 located in the opening area 100 is removed, and only the first insulating layer 50 covering the surface of the thin film transistor and the data line is retained, which further reduces the number of film layers in the opening area 100, reduces the number of times light interference occurs, and improves the brightness uniformity and color consistency of the display panel.

[0097] The width of the first insulating layer 50 coated on the surface of the data line is greater than the width of the data line, and the first insulating layer 50 in the opening area 100 between the two data lines is removed, that is, the data line is wrapped between the first insulating layer 50 and the substrate 10. Since the data line is made of metal material and is located in the non-opening area 200, it cannot transmit light, so the first insulating layer 50 disposed on the surface of the data line will not increase the number of light interferences, and the first insulating layer 50 can protect the data line.

[0098] Combination Figure 3 and Figure 4 As shown, in one embodiment of the present invention, the data line includes a first data line 22 and a second data line 43 . The first data line 22 is disposed on the surface of the substrate 10 , and the second data line 43 is disposed on the surface of the first data line 22 .

[0099] In this embodiment, the data lines of the array substrate 1 include a first data line 22 and a second data line 43, and the first data line 22 and the second data line 43 are sequentially formed through two deposition processes. The first data line 22 is arranged on the surface of the substrate 10 and is the same layer of metal as the gate 21, while the second data line 43 is arranged on the surface of the first data line 22 and is the same layer of metal routing as the drain 42 and the source 41. This design can use a single deposition and etching process to achieve the formation of two or more metal routings, thereby reducing the processing cost.

[0100] Since the metal routing will affect the aperture ratio, the line width of the data line needs to be designed to be narrower, which leads to an increase in the resistance of the data line. The resistance can be reduced by increasing the metal film thickness of the routing, but since the first data line 22 and the gate 21 are the same layer of metal, increasing the thickness of the first data line 22 will also increase the overall thickness of the metal layer, which will lead to an increase in production costs. Therefore, the present invention adopts a double-layer metal routing design of the first data line 22 and the second data line 43. This double-layer metal routing structure can not only reduce the impedance of the data line, thereby improving the mischarging, insufficient charging and other quality problems caused by excessive routing impedance, but also the setting of the second data line 43 does not increase the thickness of the first metal layer, which can reduce production costs.

[0101] Combination Figure 2-Figure 4As shown, in one embodiment of the present invention, the second data line 43 and the source 41 and the drain 42 are the same metal layer. Therefore, when processing the array substrate 1, the second data line 43, the source 41 and the drain 42 can be formed at the same time through one metal deposition and patterning, which reduces the number of processing and forming times and reduces the production cost. At the same time, the present application adopts a double-layer data line routing design scheme, which can increase the overall thickness of the data line. Since the newly added second data line 43 and the source 41 and the drain 42 are the same metal layer, the design scheme reduces the impedance of the data line while not increasing the overall thickness of the array substrate 1.

[0102] Combination Figure 3 and Figure 4 As shown, in one embodiment of the present invention, the first data line 22 is located within the positive projection of the second data line 43 on the first data line 22, and both sides of the second data line 43 in the width direction extend along the two side surfaces in the width direction of the first data line 22 and both contact the substrate 10.

[0103] In this embodiment, the cross section of the first data line 22 is a trapezoid, and the line width of the first data line 22 on the side facing away from the substrate 10 is smaller than the line width on the side facing the substrate 10, and the angle between the two side surfaces of the first data line 22 and the substrate 10 is an acute angle. The width of the second data line 43 is greater than the width of the first data line 22, and the cross section of the second data line 43 is stepped and spans the surface of the first data line 22. Since the thicker data line is steeper on both sides along the width direction, cracks or gaps are prone to occur when depositing other film layers. The structural design of the present application not only increases the overall thickness of the data line, but also reduces the overall slope of the data line, so as to facilitate the deposition of other film layers on the surface of the data line, thereby improving the reliability of the array substrate 1.

[0104] The present invention also proposes a display panel, which includes an array substrate 1, a liquid crystal layer and a color film substrate. The specific structure of the array substrate 1 refers to the above-mentioned embodiment. Since the display panel adopts all the technical solutions of all the embodiments of the above-mentioned array substrate 1, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here one by one.

[0105] The array substrate 1 and the color filter substrate are combined to form a liquid crystal box. The liquid crystal layer is filled in the liquid crystal box and is located between the array substrate 1 and the color filter substrate. The color filter substrate includes a color filter and a glass substrate. The color filter includes filters of three colors: red, green, and blue, for realizing color display. The liquid crystal layer is arranged between the array substrate 1 and the color filter substrate. The liquid crystal molecules in the liquid crystal layer can change the arrangement direction under the action of the electric field, thereby controlling the transmittance of light. Since the present application reduces the number of film layers in the opening area 100 of the array substrate 1, thereby reducing the number of light interferences, the display effect of the display panel is improved.

[0106] The present invention also proposes a display device, which includes a backlight module and a display panel. The specific structure of the display panel refers to the above-mentioned embodiment. Since the display device adopts all the technical solutions of all the above-mentioned display panel embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here one by one.

[0107] The display device may be a display panel arranged on the light-emitting side of the backlight module, and the light emitted by the backlight module passes through the array substrate 1, the liquid crystal layer, and the color film substrate in sequence to display the picture. The display device may be a variety of electronic devices, such as televisions, computer monitors, mobile phones, and tablet computer screens. Since the present application reduces the number of film layers in the opening area 100 of the array substrate 1, thereby reducing the number of light interferences, the display effect of the display device is improved.

[0108] The above description is only an exemplary embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the technical concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing an array substrate, characterized in that: Includes steps: providing a substrate; Depositing a metal material on the surface of the substrate to form a first metal layer; Etching the first metal layer, and forming a first data line and a gate on the surface of the substrate corresponding to the non-opening area; Depositing an insulating material on the surface of the gate, the first data line and the substrate to form a gate insulating layer; The gate insulating layer formed on the surface of the substrate corresponding to the opening area is removed.

2. The method for manufacturing an array substrate according to claim 1, wherein: After the step of removing the gate insulating layer formed on the surface of the substrate corresponding to the opening area, the following steps are included: removing the gate insulating layer formed on the surface of the first data line; Depositing the metal material on a surface of the substrate corresponding to the opening area, a surface of the first data line, and a surface of the gate insulating layer to form a second metal layer; The portion of the second metal layer corresponding to the opening area is etched to form a second data line on the surface of the first data line, and a source electrode and a drain electrode are formed on the surface of the gate insulating layer.

3. The method for manufacturing an array substrate according to claim 2, wherein: After the step of etching the portion of the second metal layer corresponding to the opening area to form a second data line on the surface of the first data line and forming a source electrode and a drain electrode on the surface of the gate insulating layer, the step includes: Depositing the insulating material on the surface of the substrate, the surface of the second data line, the surface of the gate insulating layer, the surface of the source electrode, and the surface of the drain electrode to form a first insulating layer; The first insulating layer formed on the surface of the substrate corresponding to the opening area is removed.

4. The method for manufacturing an array substrate according to claim 3, wherein: After the step of removing the first insulating layer formed on the surface of the substrate corresponding to the opening area, the step further comprises: forming a planar layer on a surface of the substrate corresponding to the opening area and a surface of the first insulating layer; A common electrode, a second insulating layer and a pixel electrode are sequentially formed on the surface of the planar layer.

5. An array substrate, characterized in that: The array substrate comprises: substrate; A thin film transistor, wherein the thin film transistor is disposed on a surface of the substrate corresponding to the non-opening area, and the thin film transistor comprises a gate electrode, a gate insulating layer, a semiconductor layer, a drain electrode, and a source electrode stacked in sequence on the surface of the substrate; a data line, the data line being disposed on a surface of the substrate corresponding to the non-opening area and electrically connected to the thin film transistor; and A first insulating layer is disposed in the non-opening area and is located on a surface of the thin film transistor and a surface of the data line.

6. The array substrate according to claim 5, characterized in that: The data line includes a first data line and a second data line. The first data line is arranged on the surface of the substrate, and the second data line is arranged on the surface of the first data line.

7. The array substrate according to claim 6, characterized in that: The second data line, the source electrode and the drain electrode are formed in the same metal layer.

8. The array substrate according to claim 6, wherein: The first data line is located within the orthographic projection of the second data line on the first data line, and both sides of the second data line in the width direction extend along both side surfaces in the width direction of the first data line and both contact the substrate.

9. A display panel, characterized in that: The display panel includes a color filter substrate, a liquid crystal layer and an array substrate as described in any one of claims 5 to 8, wherein the array substrate and the color filter substrate are combined to form a liquid crystal box, and the liquid crystal layer is filled in the liquid crystal box and is located between the array substrate and the color filter substrate.

10. A display device, characterized in that: The display device comprises a backlight module and the display panel as claimed in claim 9, wherein the display panel is arranged on the light emitting side of the backlight module.

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