Direct-current power supply device based on FPGA control and dynamic power-on method

Abstract

The invention relates to the field of power supplies, in particular to a direct-current power supply device based on FPGA control and a dynamic power-on method, and the direct-current power supply device comprises a control module, a digital-to-analog converter and a power output module. Wherein the control module comprises a timer, a memory and a waveform calculation module, and the timer and the waveform calculation module are both connected with the memory; the digital-to-analog converter is in communication connection with the memory; the input end of the power output module is connected with the digital-to-analog converter, and the output end of the power output module is connected with a load. According to the invention, various voltage value sequences can be calculated according to user settings, the power-on period can be flexibly adjusted to provide stable output voltage meeting load requirements, and both flexibility and output stability are achieved.

Description

Technical Field

[0001] The present invention relates to the field of power supply, and in particular to a direct current power supply device based on FPGA control and a dynamic power-on method. Background Art

[0002] In the operating environment of modern electronic equipment, ordinary DC constant voltage power supplies are widely used to power various load circuits. However, they have obvious defects in the startup phase. When the power is turned on, since the load end is often equipped with energy storage capacitors, these capacitors need to be quickly charged in the initial state to reach the normal working voltage level. This process will cause a huge instantaneous current. The peak value of this instantaneous current often far exceeds the normal current range that the load circuit can withstand, which inevitably causes the load circuit to trigger the overcurrent alarm mechanism, seriously affecting the normal startup process of the equipment, and may even cause irreversible damage to sensitive components in the load circuit, reducing the stability and reliability of the entire electronic system.

[0003] Furthermore, if a fixed soft-start function is simply added during the power supply design phase, although it can alleviate the problem of excessive instantaneous current to a certain extent, this will cause new contradictions. For some loads with special startup characteristics, the fixed soft-start mode cannot flexibly adapt to their diverse needs. For some loads that have strict requirements on the startup speed, the startup speed will be excessively restricted in this fixed mode, and it will not be able to reach the normal working state within the specified time, which will greatly reduce the operating efficiency of the entire equipment and fail to meet the high performance requirements in actual application scenarios, limiting the effective application of power supplies in some specific fields.

[0004] In fact, the existing power supply products on the market generally have the problem of insufficient compatibility when facing various special loads. Specifically, when the power supply starts up too fast, for those special loads with limited starting current tolerance, the excessive starting current will cause huge pressure on the internal circuit components, shorten the service life of the components, and even directly cause failures; and when the power supply starts up too slowly, it is difficult to meet the requirements of some special loads with precise time requirements for the starting speed, causing these loads to fail to complete the startup process within the expected time, thus affecting the coordinated work of the entire system and failing to exert the performance that the load should have, which greatly restricts the stable operation and efficient working ability of electronic equipment in complex working environments. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a DC power supply device based on FPGA control and a dynamic power-on method. The DC power supply device based on FPGA control includes:

[0006] A control module, the control module comprising a timer, a memory and a waveform calculation module, the timer and the waveform calculation module are both connected to the memory;

[0007] a digital-to-analog converter, the digital-to-analog converter being communicatively connected to the memory;

[0008] A power output module, wherein the input end of the power output module is connected to the digital-to-analog converter, and the output end of the power output module is connected to a load.

[0009] In one embodiment of the present invention, the control module further includes an enable port, and the power output module is connected to the enable port.

[0010] In one embodiment of the present invention, the control module further includes a serial peripheral interface, and the digital-to-analog converter is communicatively connected to the memory via the serial peripheral interface.

[0011] In one embodiment of the present invention, the memory is a FIFO buffer.

[0012] Based on the above DC power supply device, the present invention also provides a first dynamic power-on method, which comprises the following steps:

[0013] S1: turning on the enable port of the power output module, receiving a power-on enable signal from the control module through the enable port, and putting the power output module into a working state;

[0014] S2: Calculate different voltage value sequences and their corresponding DAC value sequences according to the maximum voltage set by the user and the time required to reach the maximum voltage;

[0015] S3: performing digital-to-analog conversion on the DAC value sequence regularly according to a power-on cycle set in advance to obtain an analog voltage value;

[0016] S4: Based on the analog voltage value, an output voltage that meets the load working requirements is obtained. After the output voltage rises to the target voltage value according to the set voltage value sequence, the analog voltage value is no longer updated, so that the output voltage is maintained at the target voltage value to power the load.

[0017] In one embodiment of the present invention, the voltage value sequence is a linear function power-on waveform sequence or a quadratic function power-on waveform sequence;

[0018] When the voltage value sequence is a linear function power-on waveform sequence, according to the maximum voltage V set by the user max And the time T required to reach the maximum voltage, calculate the time from 0V to the maximum voltage V max In the climbing phase, the voltage value sequence V at each time node t out :

[0019]

[0020] When the voltage value sequence is a quadratic function power-on waveform sequence, according to the maximum voltage V set by the user max And the time T required to reach the maximum voltage, calculate the time from 0V to the maximum voltage V max In the climbing phase, the voltage value sequence V at each time node t out :

[0021]

[0022] In one embodiment of the present invention, the power-on period is adjusted by adjusting a trigger period of a timer.

[0023] Based on the above DC power supply device, the present invention also provides a second dynamic power-on method, which includes the following steps:

[0024] S1: Calculate different voltage value sequences and their corresponding DAC value sequences according to the maximum voltage set by the user and the time required to reach the maximum voltage;

[0025] S2: performing digital-to-analog conversion processing on the DAC value sequence regularly according to the power-on cycle set in advance to obtain an analog voltage value;

[0026] S3: turning on the enable port of the power output module, and receiving a power-on enable signal from the control module through the enable port;

[0027] S4: Based on the power-on enable signal, the power output module processes the analog voltage value to obtain an output voltage that meets the load working requirements. After the output voltage rises to the target voltage value according to the set voltage value sequence, the analog voltage value is no longer updated, so that the output voltage remains at the target voltage value to power the load.

[0028] In one embodiment of the present invention, the voltage value sequence is a linear function power-on waveform sequence or a quadratic function power-on waveform sequence;

[0029] When the voltage value sequence is a linear function power-on waveform sequence, according to the maximum voltage V set by the user max And the time T required to reach the maximum voltage, calculate the time from 0V to the maximum voltage V max In the climbing phase, the voltage value sequence V at each time node t out :

[0030]

[0031] When the voltage value sequence is a quadratic function power-on waveform sequence, according to the maximum voltage V set by the user max And the time T required to reach the maximum voltage, calculate the time from 0V to the maximum voltage V max In the climbing phase, the voltage value sequence V at each time node t out :

[0032]

[0033] The present invention also provides a computer storage medium, characterized in that the computer storage medium stores a computer software product, and the computer software product includes several instructions for enabling a computer device to execute the dynamic power-on method.

[0034] The above technical solution of the present invention has the following advantages compared with the prior art:

[0035] 1. High power-on flexibility, providing a variety of voltage value sequences, including linear function, quadratic function sequence and user-specified sequence. Users can also set key parameters to meet the requirements of different loads for voltage rise characteristics, and can also change the power-on speed by adjusting the timer trigger cycle.

[0036] 2. The power supply is highly stable, and the power-on process is carried out in an orderly and step-by-step manner to avoid current shock and voltage mutation. The power-off process is also smooth and orderly to reduce failures.

[0037] 3. It has a wide range of applicability and can be adapted to a variety of electronic devices. It is easy to integrate and expand. With FPGA control chip as the core, it can be easily integrated with other systems by utilizing its programmability, and is also convenient for subsequent upgrades and function expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein:

[0039] Figure 1 It is a structural schematic diagram of a DC power supply device based on FPGA control provided in one embodiment of the present invention;

[0040] Figure 2 This is a first dynamic power-on method process intention provided in an embodiment of the present invention;

[0041] Figure 3 This is a second dynamic power-on method process provided in an embodiment of the present invention;

[0042] Explanation of the reference numerals in the specification: 10. control module; 11. timer; 12. memory; 13. waveform calculator; 14. enable port; 15. serial peripheral interface; 20. digital-to-analog converter; 30. power output module. DETAILED DESCRIPTION

[0043] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0044] Embodiment 1

[0045] See also Figure 1 As shown, the present invention provides a DC power supply device based on FPGA control and a dynamic power-on method. The DC power supply device based on FPGA control includes: a control module 10, a digital-to-analog converter 20 and a power output module 30;

[0046] The control module 10 includes a timer 11, a memory 12 and a waveform calculation module 13, and both the timer 11 and the waveform calculation module 13 are connected to the memory 12;

[0047] The digital-to-analog converter 20 is communicatively connected with the memory 12;

[0048] The input end of the power output module 30 is connected to the digital-to-analog converter 20 , and the output end thereof is connected to a load.

[0049] Furthermore, the control module 10 is an FPGA control chip, which also includes an enable port 14. The power output module 30 is connected to the enable port 14. The FPGA control chip sends a power-on enable signal to the power output module 30 through the enable port 14, so that the power output module 30 enters an operational state and prepares for subsequent voltage output.

[0050] The waveform calculation module 13 calculates the voltage value sequence from 0V to the specified voltage and its corresponding DAC value sequence according to user requirements, that is, sets the maximum voltage Vmax and the time T to reach the voltage according to the load characteristics to meet the requirements of different loads for voltage rise speed and curve shape.

[0051] Preferably, the memory 12 is a FIFO buffer, and the calculated DAC value sequence is stored in the FIFO buffer in sequence to ensure orderly transmission of data.

[0052] Furthermore, the control module 10 further includes a serial peripheral interface 15 , namely, an SPI interface, and the digital-to-analog converter 20 is communicatively connected with the memory 12 via the serial peripheral interface 15 .

[0053] After the timer 11 is started, the FPGA control chip will periodically take out the DAC value sequence from the FIFO buffer and transmit the data to the digital-to-analog converter 20 through the SPI interface.

[0054] The digital-to-analog converter 20 converts the received digital signal into an analog voltage value, and the power output module 30 outside the FPGA control chip converts these analog voltage values ​​into actual output voltages for the load. In the voltage climbing stage, the voltage is gradually increased according to the set voltage value sequence, and the voltage is kept stable after the climbing is completed, providing a stable working voltage for the load.

[0055] If you need to adjust the power-on speed, you can do so by modifying the timer trigger period. Shortening the trigger period can speed up the update of the DAC sequence value, thereby making the voltage rise faster; extending the trigger period will slow down the voltage rise. This flexibility enables the technical solution to adapt to the power-on speed requirements of different loads. For example, for some loads that are sensitive to voltage shocks, a slower power-on speed can be used, while for loads that need to start quickly, the power-on process can be accelerated.

[0056] Embodiment 2

[0057] Based on the DC power supply device of the first embodiment, the present invention also provides a first dynamic power-on method. Figure 2 As shown, the specific steps include:

[0058] S1: The control module 10 turns on the enable port of the power output module 30, receives a power-on enable signal from the control module 10 through the enable port, and puts the power output module 30 into a working state;

[0059] S2: according to the maximum voltage set by the user and the time required to reach the maximum voltage, the waveform calculator 13 calculates different voltage value sequences and their corresponding DAC value sequences, and stores the DAC value sequences in the memory 12;

[0060] S3: According to the power-on cycle set in advance, the control module 10 periodically takes out the DAC value sequence from the memory 12, and the digital-to-analog converter 20 performs digital-to-analog conversion on the DAC value sequence to obtain an analog voltage value;

[0061] S4: Based on the analog voltage value, an output voltage that meets the load working requirements is obtained through the power output module 30, until the output voltage rises to the target voltage value according to the set voltage value sequence, the analog voltage value is no longer updated, so that the output voltage remains at the target voltage value to power the load.

[0062] Furthermore, the voltage value sequence is a linear function power-on waveform sequence or a quadratic function power-on waveform sequence, or may be other user-specified power-on waveform sequences;

[0063] When the voltage value sequence is a linear function power-on waveform sequence, according to the maximum voltage V set by the user max And the time T required to reach the maximum voltage, calculate the time from 0V to the maximum voltage V max In the climbing phase, the voltage value sequence V at each time node t out :

[0064]

[0065] When the voltage value sequence is a quadratic function power-on waveform sequence, according to the maximum voltage V set by the user max And the time T required to reach the maximum voltage, calculate the time from 0V to the maximum voltage V max In the climbing phase, the voltage value sequence V at each time node t out :

[0066]

[0067] Furthermore, the power-on period is adjusted by adjusting the trigger period of the timer 11. Through this adjustment mechanism, the user is provided with the ability of autonomous adjustment under different working environments and load requirements.

[0068] For example, in some scenarios where the startup time requirement is not high but more emphasis is placed on reducing electromagnetic interference and reducing circuit heat loss, the trigger period of timer 11 can be appropriately extended to make the voltage rise more gentle and slow; in emergency situations where the equipment needs to be put into operation quickly or in application scenarios with high requirements for startup efficiency, shortening the trigger period can achieve fast power-on, thereby improving the overall response speed and utilization efficiency of the equipment, making the power control technology widely applicable to various complex and changeable actual working conditions.

[0069] In addition, when the power needs to be turned off, the FPGA control chip first turns off the enable port of the power output module 30, and then calculates the DAC value corresponding to the 0V voltage through the waveform calculation module 13. The FPGA control chip takes the value out of the FIFO buffer and transmits it to the digital-to-analog converter 20 through the SPI interface, so that the power output module 30 is restored to the initial power-off state.

[0070] Embodiment 3

[0071] Based on the DC power supply device in the first embodiment, the present invention also provides a second dynamic power-on method, the process of which is as follows: Figure 3When the required power-on speed is faster than the method in the second embodiment, this method can be used, and the specific steps are as follows:

[0072] S1: Calculating different voltage value sequences and their corresponding DAC value sequences by the waveform calculator 13 according to the maximum voltage set by the user and the time required to reach the maximum voltage;

[0073] S2: According to the power-on cycle set in advance, the control module 10 periodically takes out the DAC value sequence from the memory 12, and the digital-to-analog converter 20 performs digital-to-analog conversion on the DAC value sequence to obtain an analog voltage value;

[0074] S3: the control module 10 turns on the enable port of the power output module 30, receives a power-on enable signal from the control module 10 through the enable port, and puts the power output module 30 into a working state;

[0075] S4: Based on the power-on enable signal, the power output module 30 processes the analog voltage value, and obtains an output voltage that meets the load working requirements through the power output module 30, until the output voltage rises to the target voltage value according to the set voltage value sequence. The analog voltage value is no longer updated, so that the output voltage remains at the target voltage value to power the load.

[0076] Furthermore, the voltage value sequence is a linear function power-on waveform sequence or a quadratic function power-on waveform sequence, or may be other user-specified power-on waveform sequences;

[0077] When the voltage value sequence is a linear function power-on waveform sequence, according to the maximum voltage V set by the user max And the time T required to reach the maximum voltage, calculate the time from 0V to the maximum voltage V max In the climbing phase, the voltage value sequence V at each time node t out :

[0078]

[0079] When the voltage value sequence is a quadratic function power-on waveform sequence, according to the maximum voltage V set by the user max And the time T required to reach the maximum voltage, calculate the time from 0V to the maximum voltage V max In the climbing phase, the voltage value sequence V at each time node t out :

[0080]

[0081] In addition, when the power needs to be turned off, the FPGA control chip first turns off the enable port of the power output module 30, and then calculates the DAC value corresponding to the 0V voltage through the waveform calculation module 13. The FPGA control chip takes the value out of the FIFO buffer and transmits it to the digital-to-analog converter 20 through the SPI interface, so that the power output module 30 is restored to the initial power-off state.

[0082] Embodiment 4

[0083] The present invention also provides a computer storage medium, characterized in that the computer storage medium stores a computer software product, and the computer software product includes several instructions for enabling a computer device to execute the dynamic power-on method described in Example 2 or Example 3.

[0084] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0085] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0086] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0087] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0088] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A DC power supply device based on FPGA control, characterized in that: include: A control module, the control module comprising a timer, a memory and a waveform calculation module, the timer and the waveform calculation module are both connected to the memory; a digital-to-analog converter, the digital-to-analog converter being communicatively connected to the memory; A power output module, wherein the input end of the power output module is connected to the digital-to-analog converter, and the output end of the power output module is connected to a load.

2. The DC power supply device based on FPGA control according to claim 1, characterized in that: The control module further comprises an enable port, and the power output module is connected to the enable port.

3. The DC power supply device based on FPGA control according to claim 1, characterized in that: The control module further comprises a serial peripheral interface, and the digital-to-analog converter is communicatively connected with the memory via the serial peripheral interface.

4. The DC power supply device based on FPGA control according to claim 1, characterized in that: The memory is a FIFO buffer.

5. A dynamic power-on method, characterized in that: Applied to the DC power supply device according to any one of claims 1 to 4, the power-on method comprises the following steps: S1: turning on the enable port of the power output module, receiving a power-on enable signal from the control module through the enable port, and putting the power output module into a working state; S2: Calculate different voltage value sequences and their corresponding DAC value sequences according to the maximum voltage set by the user and the time required to reach the maximum voltage; S3: performing digital-to-analog conversion on the DAC value sequence regularly according to a power-on cycle set in advance to obtain an analog voltage value; S4: Based on the analog voltage value, an output voltage that meets the load working requirements is obtained. After the output voltage rises to the target voltage value according to the set voltage value sequence, the analog voltage value is no longer updated, so that the output voltage is maintained at the target voltage value to power the load.

6. The dynamic power-on method according to claim 5, characterized in that: The voltage value sequence is a linear function power-on waveform sequence or a quadratic function power-on waveform sequence; When the voltage value sequence is a linear function power-on waveform sequence, according to the maximum voltage V set by the user max And the time T required to reach the maximum voltage, calculate the time from 0V to the maximum voltage V max In the climbing phase, the voltage value sequence V at each time node t out : When the voltage value sequence is a quadratic function power-on waveform sequence, according to the maximum voltage V set by the user max And the time T required to reach the maximum voltage, calculate the time from 0V to the maximum voltage V max In the climbing phase, the voltage value sequence V at each time node t out :

7. The dynamic power-on method according to claim 5, characterized in that: The power-on period is adjusted by adjusting the trigger period of the timer.

8. A dynamic power-on method, characterized in that: Applied to the DC power supply device according to any one of claims 1 to 4, the power-on method comprises the following steps: S1: Calculate different voltage value sequences and their corresponding DAC value sequences according to the maximum voltage set by the user and the time required to reach the maximum voltage; S2: performing digital-to-analog conversion processing on the DAC value sequence regularly according to the power-on cycle set in advance to obtain an analog voltage value; S3: turning on the enable port of the power output module, and receiving a power-on enable signal from the control module through the enable port; S4: Based on the power-on enable signal, the power output module processes the analog voltage value to obtain an output voltage that meets the load working requirements. After the output voltage rises to the target voltage value according to the set voltage value sequence, the analog voltage value is no longer updated, so that the output voltage remains at the target voltage value to power the load.

9. The dynamic power-on method according to claim 8, characterized in that: The voltage value sequence is a linear function power-on waveform sequence or a quadratic function power-on waveform sequence; When the voltage value sequence is a linear function power-on waveform sequence, according to the maximum voltage V set by the user max And the time T required to reach the maximum voltage, calculate the time from 0V to the maximum voltage V max In the climbing phase, the voltage value sequence V at each time node t out : When the voltage value sequence is a quadratic function power-on waveform sequence, according to the maximum voltage V set by the user max And the time T required to reach the maximum voltage, calculate the time from 0V to the maximum voltage V max In the climbing phase, the voltage value sequence V at each time node t out :

10. A computer storage medium, characterized in that: The computer storage medium stores a computer software product, and the computer software product includes several instructions for enabling a computer device to execute the dynamic power-on method described in any one of claims 5 to 9.

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