Memory read-write device, data writing method, data reading method and related device

Abstract

The embodiment of the invention provides memory read-write equipment, a data writing method, a data reading method and related equipment, the memory read-write equipment comprises a CXL controller and an RAID engine, the CXL controller comprises a plurality of first ports and at least one second port, and the RAID engine is connected with the at least one second port. Each first port is used for being connected with at least one first memory, the second port is used for being connected with at least one second memory, the first memories are used for storing application data blocks, and the second memories are used for storing verification data blocks; the CXL controller is used for performing fragmentation processing on to-be-written data to obtain a plurality of application data blocks, and respectively writing the plurality of application data blocks into the first memories connected with the plurality of first ports; and the RAID engine is used for encoding the plurality of application data blocks to obtain a verification data block, and storing the verification data block into a second memory corresponding to the at least one second port. The method can improve the reliability of the memory.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of server technology, and in particular to a memory read-write device, a data writing method, a data reading method, and related devices. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, memory manufacturing technology is constantly improving.

[0003] Currently, memory is rapidly evolving towards high frequency, high density, low power consumption, and low cost. However, due to the characteristics of high density or high speed of memory, the probability of failure during memory operation is increasing, resulting in poor memory reliability. Summary of the invention

[0004] The embodiments of the present application provide a memory read-write device, a data writing method, a data reading method and related devices to solve the problem of low memory reliability.

[0005] In a first aspect, an embodiment of the present application provides a memory read / write device, including: a CXL controller and a RAID engine, wherein the CXL controller includes a plurality of first ports and at least one second port, wherein:

[0006] The RAID engine is connected to the at least one second port, each of the first ports is used to connect to at least one first memory, the second port is used to connect to at least one second memory, the first memory is used to store application data blocks, and the second memory is used to store check data blocks;

[0007] The CXL controller is used to slice the data to be written to obtain a plurality of the application data blocks, and write the plurality of application data blocks into the first memories connected to the plurality of the first ports respectively; or, according to the storage location of the target application data block to be read, obtain the target application data block from the first memory connected to the corresponding first port;

[0008] The RAID engine is used for encoding the multiple application data blocks to obtain check data blocks, storing the check data blocks in the second memory corresponding to at least one of the second ports, and recovering the erroneous target application data blocks when the target application data blocks read by the CXL controller are erroneous.

[0009] In the above scheme, the memory read-write device may include a CXL controller and a RAID engine, the CXL controller may be connected to at least one first memory and at least one second memory, and the RAID engine may be connected to at least one second memory. The CXL controller may read and write multiple application data blocks in the first memory. The RAID engine may encode multiple application data blocks to obtain verification data blocks, and store the verification data blocks in the second memory. If there is a memory failure in the application data block read by the CXL controller, the RAID engine may repair the data block with the memory failure. Through the above memory read-write device, multi-bit memory failures may be repaired to repair faulty data, thereby improving memory reliability and further improving the reliability of electronic devices using the memory read-write device.

[0010] In a possible implementation, the RAID engine includes a cache and a codec, wherein the codec is connected to the cache and the at least one second port respectively;

[0011] The cache is used to store the multiple application data blocks obtained by the CXL controller through slicing;

[0012] The codec is used to encode the multiple application data blocks stored in the cache to obtain the check data block, and after the multiple application data blocks are written into the first memory, store the check data block in the second memory corresponding to at least one of the second ports; or, when the target application data block read by the CXL controller is erroneous, recover the erroneous target application data block.

[0013] In the above scheme, the RAID engine may include a cache and a codec, and the RAID engine may encode the application data block through the codec and recover the erroneous target application data block, thereby achieving the purpose of the RAID engine encoding multiple application data blocks and recovering the erroneous target application data block. At the same time, the embodiment of the present application stores multiple application data blocks in the first memory after obtaining the multiple application data blocks, and then stores the verification data after obtaining the verification data according to the multiple application data blocks. This step-by-step storage method can improve the data storage speed and effectively reduce the data writing delay compared to waiting for the verification data to be obtained according to the multiple application data blocks and then storing the multiple application data blocks together with the verification data.

[0014] In a possible implementation, the CXL controller includes a processing core, the processing core is connected to the plurality of first ports respectively, and the processing core is also connected to the cache;

[0015] The processing core is used to slice the data to be written to obtain the multiple application data blocks, store the multiple application data blocks in the cache, and write the multiple application data blocks in parallel in the first memories corresponding to the multiple first ports.

[0016] In the above solution, the CXL controller may include a processing core, and the CXL controller may perform slicing processing on the data to be written through the processing core, thereby achieving the purpose of performing slicing processing on the data to be written.

[0017] In a possible implementation, the CXL controller is further configured to determine whether there is an erroneous data block in the target application data block that has been read, and if so, send a recovery instruction to the RAID engine;

[0018] The RAID engine is used to read the check data block from the second memory corresponding to at least one of the second ports through the codec according to the recovery instruction, and perform recovery processing on the erroneous target application data block according to the check data block.

[0019] In the above solution, if there is an erroneous data block in the target application data block read by the CXL controller, the RAID engine can recover the erroneous data block, so that the data security and reliability are higher.

[0020] In a possible implementation, the RAID engine is disposed in the CXL controller.

[0021] In the above solution, the RDIA engine may also be arranged in the CXL controller, so that the arrangement flexibility of the RAID engine is higher.

[0022] In a possible implementation, the CXL controller is a CXL switch controller in a CXL switch device, or the CXL controller is a CXL memory controller in a CXL memory device;

[0023] If the CXL controller is a CXL switch controller, the first port is used to connect the first memory through a first CXL memory controller, and the second port is used to connect the second memory through a second CXL memory controller, wherein the first CXL memory controller and the second CXL memory controller are CXL memory controllers in the CXL memory device;

[0024] If the CXL controller is a CXL memory controller, the first port is used to connect to the first memory, and the second port is used to connect to the second memory.

[0025] In the above solution, the CXL controller may be a CXL switch controller in a CXL switch device, or the CXL controller may be a CXL memory controller in a CXL memory device, so that the CXL controller has better flexibility.

[0026] In a second aspect, an embodiment of the present application provides a data writing method, which is applied to a memory read-write device, wherein the memory read-write device includes a CXL controller and a RAID engine, wherein the CXL controller includes a plurality of first ports and at least one second port, and the RAID engine is connected to the at least one second port, wherein the method includes:

[0027] The CXL controller obtains data to be written, slices the data to be written to obtain a plurality of application data blocks, writes the plurality of application data blocks into first memories corresponding to the plurality of first ports respectively, and writes the plurality of application data blocks into the RAID engine;

[0028] The RAID engine encodes the multiple application data blocks to obtain verification data blocks, and stores the verification data blocks in a second memory corresponding to the at least one second port.

[0029] In the above scheme, the CXL controller can obtain the data to be written, can slice the data to be written to obtain multiple application data blocks, and can store the multiple application data blocks in the first memory corresponding to the multiple first ports. The RAID engine can encode the multiple application data blocks to obtain the verification data blocks, and can store the verification data blocks in the second memory corresponding to at least one second port. Through the above scheme, the multiple application data blocks can be verified by the RAID engine, thereby improving the reliability of the first memory. In addition, the CXL controller can slice the data to be written into multiple application data blocks, and can write multiple application data blocks to the first memory in parallel through multiple channels, so that the memory write bandwidth is large, the write speed is fast, and the write performance is good.

[0030] In a possible implementation, the data to be written is processed in slices, including:

[0031] Based on a preset number, the data to be written is sliced ​​to obtain a preset number of application data blocks; or,

[0032] Based on the preset size, the data to be written is segmented to obtain a plurality of application data blocks, and the size of each application data block is equal to the preset size.

[0033] In the above scheme, the data to be written can be processed in slices according to a preset number, or the data to be written can be processed in slices according to a preset size, so that the flexibility of the slice processing is high.

[0034] In a possible implementation, the number of the application data blocks is equal to the number of the first memories; and storing the multiple application data blocks in the first memories corresponding to the multiple first ports includes:

[0035] An application data block is stored in parallel in the same storage location in each first memory.

[0036] In the above solution, the CXL controller can write multiple application data blocks to the first memory in parallel through multiple channels, so that the memory write bandwidth is larger, the write speed is faster, and the write performance is better.

[0037] In a possible implementation, the RAID engine stores the check data block in a second memory corresponding to the at least one second port, including:

[0038] After the CXL controller writes the multiple application data blocks into the first memories corresponding to the multiple first ports respectively, the RAID engine stores the check data block into the second memory corresponding to the at least one second port.

[0039] In the above scheme, the verification data can be stored after multiple application data blocks are stored in the first memory. This step-by-step storage method can increase the data storage speed and effectively reduce the data writing delay compared to waiting for the verification data to be obtained based on multiple application data blocks and then storing the multiple application data blocks together with the verification data.

[0040] In a third aspect, an embodiment of the present application provides a data reading method, which is applied to a memory read-write device, wherein the memory read-write device includes a CXL controller and a RAID engine, wherein the CXL controller includes a plurality of first ports and at least one second port, and the RAID engine is connected to the at least one second port, wherein the method includes:

[0041] The CXL controller receives a data read request from a central processing unit (CPU), wherein the data read request includes a storage location of a target application data block to be read;

[0042] The CXL controller reads the target application data block from the first memory corresponding to the plurality of first ports according to the data read request, and determines whether there is an error data block in the target application data block;

[0043] When an error data block exists in the target application data block, the CXL controller requests the RAID engine to read a check data block from a second memory corresponding to the at least one second port, and recover the error data block according to the check data block to obtain a correct data block corresponding to the error data block;

[0044] The CXL controller sends the correct target application data block to the CPU.

[0045] In the above scheme, if there is no error data block in the target application data block read by the CXL controller, the CXL controller can directly send the target application data block to the CPU. If there is an error data block in the target application data block read by the CXL controller, the RAID engine can read the check data block from the second memory corresponding to the second port, and can recover the error data block according to the check data block to obtain the correct data block corresponding to the error data block. Through the above method, the RAID engine can recover the error application data block obtained from the first memory, thereby improving the reliability of the first memory.

[0046] In a possible implementation, the CXL controller reads the target application data block from the first memory corresponding to the plurality of first ports according to the data read request, including:

[0047] The CXL controller reads a target application data block from each first memory in parallel according to the storage location.

[0048] In the above solution, the CXL controller can read multiple application data blocks in parallel, so that the data reading speed is faster.

[0049] In a possible implementation, the recovering the erroneous data block according to the check data block includes:

[0050] The RAID engine decodes the remaining application data blocks except the erroneous data block according to the verification data to obtain a correct data block corresponding to the erroneous data block.

[0051] In the above solution, the RAID engine can decode the remaining application data blocks except the erroneous data blocks according to the verification data, thereby achieving the purpose of recovering the erroneous data.

[0052] In a fourth aspect, an embodiment of the present application provides a CXL memory device, the CXL memory device comprising a memory read / write device, a plurality of first memories and a second memory, the memory read / write device comprising a CXL controller and a RAID engine, the CXL controller comprising a plurality of first ports and at least one second port, wherein:

[0053] The RAID engine is connected to the at least one second port, each of the first ports is used to connect to one of the first memories, the second port is used to connect to one of the second memories, the first memory is used to store application data blocks, and the second memory is used to store check data blocks;

[0054] The CXL controller is used to slice the data to be written to obtain a plurality of the application data blocks, and write the plurality of application data blocks into the first memories connected to the plurality of the first ports respectively; or, according to the storage location of the target application data block to be read, obtain the target application data block from the first memory connected to the corresponding first port;

[0055] The RAID engine is used for encoding the multiple application data blocks to obtain check data blocks, storing the check data blocks in the second memory corresponding to at least one of the second ports, and recovering the erroneous target application data blocks when the target application data blocks read by the CXL controller are erroneous.

[0056] In the above scheme, the memory read-write device of the CXL memory device may include a CXL controller and a RAID engine, the CXL controller may be connected to at least one first memory and at least one second memory, and the RAID engine may be connected to at least one second memory. The CXL controller may read and write multiple application data blocks in the first memory. The RAID engine may encode multiple application data blocks to obtain verification data blocks, and store the verification data blocks in the second memory. If there is a memory failure in the application data block read by the CXL controller, the RAID engine may repair the data block with the memory failure. Through the above CXL memory device, multi-bit memory failures may be repaired to repair faulty data, thereby improving memory reliability and further improving the reliability of electronic devices using the memory read-write device.

[0057] In a fifth aspect, an embodiment of the present application provides a CXL switching device, the CXL switching device comprising a CXL controller and a RAID engine, the CXL controller comprising a plurality of first ports and at least one second port, wherein:

[0058] The RAID engine is connected to the at least one second port, each of the first ports is used to connect to a first CXL storage device, the second port is connected to a second CXL storage device, the first CXL storage device is used to store application data blocks, and the second CXL storage device is used to store check data blocks;

[0059] The CXL controller is used to slice the data to be written to obtain a plurality of the application data blocks, and write the plurality of application data blocks into the first CXL storage devices connected to the plurality of the first ports respectively; or, according to the storage location of the target application data block to be read, obtain the target application data block from the first CXL storage device connected to the corresponding first port;

[0060] The RAID engine is used for encoding the multiple application data blocks to obtain check data blocks, storing the check data blocks in the second CXL storage device corresponding to at least one of the second ports, and recovering the erroneous target application data blocks when the target application data blocks read by the CXL controller are erroneous.

[0061] In the above scheme, the memory read-write device of the CXL switching device may include a CXL controller and a RAID engine. The CXL controller includes multiple first ports and at least one second port. Each first port is used to connect to a first CXL storage device, and the second port is connected to a second CXL storage device. The RAID engine can be connected to at least one second port. The CXL controller can read and write multiple application data blocks in the first CXL storage device. The RAID engine can encode multiple application data blocks to obtain verification data blocks, and store the verification data blocks in the second CXL storage device. If the application data block read by the CXL controller has a memory fault, the RAID engine can repair the data block with the memory fault. Through the above CXL switching device, multi-bit memory faults can be repaired to repair faulty data, thereby improving memory reliability and further improving the reliability of electronic devices using the memory read-write device. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0063] Figure 1 A schematic diagram of the relationship between memory evolution and memory attributes provided in an embodiment of the present application;

[0064] Figure 2 A schematic diagram of the relationship between memory evolution and memory production line interception rate provided in an embodiment of the present application;

[0065] Figure 3A A schematic diagram of the architecture of a memory read-write system provided in an embodiment of the present application;

[0066] Figure 3B A schematic diagram of the architecture of another memory read-write system provided in an embodiment of the present application;

[0067] Figure 4 A schematic diagram of the architecture of a memory read-write device provided in an embodiment of the present application;

[0068] Figure 5 A schematic diagram of a connection between a memory read / write device and a memory provided in an embodiment of the present application;

[0069] Figure 6 A schematic diagram of the architecture of another memory read-write device provided in an embodiment of the present application;

[0070] Fig. 7A A schematic diagram of the architecture of another memory read-write device provided in an embodiment of the present application;

[0071] Figure 7B A schematic diagram of the architecture of another memory read-write device provided in an embodiment of the present application;

[0072] Figure 8 A schematic diagram of a data writing method provided in an embodiment of the present application;

[0073] Fig. 9 A flowchart of a data reading method provided in an embodiment of the present application;

[0074] Fig.10 A schematic diagram of a connection between a memory read / write device and a first CXL memory controller and a second CXL memory controller provided in an embodiment of the present application;

[0075] Fig.11 A schematic diagram of another connection between a memory read / write device and a memory provided in an embodiment of the present application;

[0076] Fig.12 A schematic diagram of connection between another memory read / write device provided in an embodiment of the present application and a first CXL memory controller and a second CXL memory controller;

[0077] Fig.13 A schematic diagram of a flow chart of another data writing method provided in an embodiment of the present application;

[0078] Fig.14 A flowchart of another data reading method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0079] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the embodiments of the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims. Hereinafter, at least one is one or more.

[0080] The embodiments of the present application involve memory. To facilitate understanding, the memory is first described in detail.

[0081] Memory is also called internal memory or main memory, which is installed in the memory slot on the motherboard of the computing device. Memory can be used to store the operation data of the processor. For example, memory can be random access memory (RAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), dual inline memory modules (DIMM), persistent memory (PMEM), or double data rate synchronous dynamic random access memory (DDR).

[0082] With the improvement of memory manufacturing technology, memory density is getting higher and higher, transmission rate is getting higher and higher, power consumption is getting lower and lower, and memory is gradually possessing properties such as high density, high speed and low power consumption.

[0083] Next, we take DDR as an example to explain the relationship between memory evolution and memory attributes. Figure 1 As shown, Figure 1 A schematic diagram of the relationship between memory evolution and memory attributes provided in an embodiment of the present application. Figure 1 , Figure 1 The horizontal axis may be the type of memory, for example, the memory may be DDR, DDR2, DDR3, DDR4, and DDR5; Figure 1 The vertical axis can be the physical size of the memory or the transfer rate of the memory.

[0084] like Figure 1 As shown in the figure, in the process of memory evolution from DDR to DDR5, the physical size of memory has gradually evolved from 100nm to less than 10nm, that is, the density of memory is getting higher and higher. In the process of memory evolution from DDR to DDR5, the transmission rate of memory has gradually evolved from 400Mbps to 6400Mbps, that is, the transmission rate of memory is getting higher and higher. In addition, in the process of memory evolution from DDR to DDR5, the operating voltage of memory has also gradually decreased (not shown in the figure). Generally speaking, the operating voltage of DDR is about 2.5V, while the operating voltage of DDR5 is about 1.1V. It can be seen that memory is evolving towards high density, high speed and low power consumption.

[0085] However, due to the characteristics of memory such as high density or high speed, the production reliability and operation reliability of memory are getting worse and worse.

[0086] like Figure 2 As shown, Figure 2 A schematic diagram of the relationship between memory evolution and memory production line interception rate provided in an embodiment of the present application. Figure 2 , Figure 2 The horizontal axis can be the year or the physical size of the memory; Figure 2 The vertical axis can be the memory production line interception rate.

[0087] like Figure 2 As shown in the figure, the physical size of the memory in 2018 can be 25nm, the physical size of the memory in 2019 can be 20nm, the physical size of the memory in 2020 can be 18nm, the physical size of the memory in 2021 can be 16nm, and the physical size of the memory in 2022 can be 14nm. It can be seen that with the evolution of memory, the physical size of the memory is gradually reduced. However, as the physical size of the memory is gradually reduced, the production line interception rate of the memory gradually increases from 4413PPM to 48000PPM. It can be seen that with the evolution of memory, the production reliability of memory is getting worse and worse.

[0088] In addition, due to the characteristics of high density or high speed of memory, errors are prone to occur during the operation of memory. For example, errors can be single-bit errors and multi-bit errors. Although the error checking and correction (ECC) technology of memory can automatically correct some single-bit errors, there are still some errors (for example, multi-bit errors) that cannot be automatically corrected. Errors that cannot be automatically corrected will cause memory failures, resulting in poor operating reliability of the memory, and further cause poor operating reliability of the server, which is prone to cause server downtime and other situations.

[0089] In the related art, in order to improve the operational reliability of the memory, a redundant memory can be set, and data can be backed up through the redundant memory to improve the memory reliability. For example, for any memory, another redundant memory of the memory can be set, and the redundant memory can be used to back up the data of the memory. However, in this solution, the memory generally corrects the fault through ECC technology. For multi-bit faults that cannot be corrected by ECC technology, there is still a high probability of causing memory failure, resulting in low memory reliability.

[0090] In view of this, an embodiment of the present application provides a memory read-write device, and a data writing method and a data reading method applied to the memory read-write device to solve the problem of low memory reliability.

[0091] The memory read-write device provided in the embodiment of the present application can be set up with a disk array (Redundant Arrays of Independent Disks, RAID) engine. The RAID engine can repair multi-bit memory failures, thereby improving memory reliability. The Compute Express Link (CXL) controller of the memory read-write device connects multiple memories and uses multiple memories in parallel, so that the memory read-write bandwidth is large and the read-write performance is good. In addition, there is no redundant memory in the multiple memories connected to the CXL controller. Compared with the setting of redundant memory, the memory read-write device provided in the embodiment of the present application can improve the space utilization of the memory.

[0092] It should be noted that the RAID engine can support at least one RAID level. The RAID level can support data slicing technology, data verification technology, and technology for setting verification memory. Among them, data verification includes but is not limited to exclusive OR (XOR) verification, and the verification memory can be a memory used only to store data verification results. The RAID level can be a standard RAID level, a non-standard RAID level, or a combined RAID level. For example, the RAID level can be RAID3, RAID5, RAID6, or RAID50, etc.

[0093] For ease of understanding, the following Figure 3A-3B The memory reading and writing system involved in the embodiment of the present application is described.

[0094] Figure 3A This is a schematic diagram of the architecture of a memory read-write system provided in an embodiment of the present application. Figure 3A The memory read / write system may include a computing device and a CXL memory device. The computing device may be communicatively connected with the CXL memory device.

[0095] The computing device may be a server, a computer, a mobile phone, a graphics processing unit (GPU) server, an artificial intelligence (AI) server, or other computing device with data processing capabilities.

[0096] The CXL memory device may be an extended memory device of a computing device. The CXL memory device may include a memory read / write device and a memory. It should be noted that the number of memories may be one or more, and this embodiment of the application does not limit this.

[0097] The memory read / write device may include a CXL controller and a RAID engine. The CXL controller may be a CXL memory controller in a CXL memory device.

[0098] Optionally, the RAID engine may also be disposed in the CXL controller.

[0099] In the above memory read-write system, the computing device can write data into the memory through the memory read-write device, or the computing device can read data from the memory through the memory read-write device.

[0100] Figure 3B This is a schematic diagram of another memory read-write system provided in an embodiment of the present application. Figure 3B The memory read / write system may include a computing device, a CXL switch device, and a CXL memory device. The computing device may be communicatively connected with the CXL memory device via the CXL switch device.

[0101] The computing device may be a server, computer, mobile phone, GPU server, AI server or other computing device with data processing capabilities.

[0102] The CXL memory device may be an extended memory device of a computing device. The CXL memory device may include a CXL memory controller and a memory. It should be noted that the number of memories may be one or more, and this embodiment of the application does not limit this.

[0103] The CXL switch device may include a memory read / write device. The memory read / write device may include a CXL controller and a RAID engine. The CXL controller may be a CXL switch controller in the CXL switch device.

[0104] Optionally, the RAID engine may also be disposed in the CXL controller.

[0105] In the above memory read-write system, the computing device may write data to the memory of the CXL memory device through the CXL switch device, or the computing device may read data from the memory of the CXL memory device through the CXL switch device.

[0106] It should be noted that Figure 3A-3B A detailed description of the memory read and write devices in Figure 4 - Figure 7 embodiment, and Figure 10-12 The embodiments are not described in detail here.

[0107] The technical solutions of the embodiments of the present application are described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0108] Figure 4 This is a schematic diagram of the architecture of a memory read-write device provided in an embodiment of the present application. Figure 4The memory read / write device may include a CXL controller and a RAID engine, and the CXL controller and the RAID engine may be connected via a wired or wireless method.

[0109] The CXL controller includes a plurality of first ports and at least one second port. For example, the plurality of first ports may be first port 1, first port 2, ..., and first port n, and the second port may be second port i, where n and i are integers greater than or equal to 1.

[0110] The first port is used to connect to at least one first memory, and the second port is used to connect to at least one second memory.

[0111] In this embodiment, each first port can be connected to one or more first memories, and each second port can be connected to one or more second memories; wherein, a plurality means two or more than two.

[0112] The multiple first memories are used to store multiple application data blocks, and the second memory is used to store the verification data block.

[0113] The multiple application data blocks may be multiple application data blocks obtained after the CXL controller performs segmentation processing on the data to be written.

[0114] The data to be written can be Figure 3A or Figure 3B The computing data of the computing device in the.

[0115] It should be noted that, in this embodiment, each application data block can be stored in a different first memory.

[0116] Optionally, in this embodiment, the CXL controller may include a processing core. The CXL controller may perform slicing processing on the data to be written through the processing core to obtain a plurality of application data blocks. The processing core may be connected to at least one first port to send the application data blocks to at least one first memory through the at least one first port.

[0117] The CXL controller may be a CXL memory expander chip, a CXL memory expander controller, or a CXL memory expander pooling chip; or, the CXL controller may be a CXL switch controller.

[0118] The verification data block may be verification data obtained by encoding multiple application data blocks.

[0119] The RAID engine is connected to at least one second port.

[0120] In this embodiment, the CXL controller is used to read and write multiple application data blocks in the first memory corresponding to the multiple first ports; the RAID engine is used to encode the multiple application data blocks to obtain verification data blocks, and store the verification data blocks in the second memory corresponding to at least one second port, and when the application data blocks read by the CXL controller are erroneous, recover the erroneous data blocks.

[0121] That is, when the memory read / write device writes data to the memory, the CXL controller can process the data to be written into multiple application data blocks, store multiple application data blocks in the first memory, and send multiple application data blocks to the RAID engine; the RAID engine can encode the application data blocks to obtain verification data blocks, and store the verification data blocks in the second memory. When the memory read / write device reads data from the memory, if the application data block read by the CXL controller is wrong, the RAID engine can recover the wrong data block according to the verification data to obtain the corresponding correct data block.

[0122] In this embodiment, the CXL controller can slice the data to be written. The RAID engine can encode multiple application data blocks processed by the CXL controller without slicing the data to be written, so that the RAID engine has a lower overhead and a faster processing speed.

[0123] The memory read-write device provided in this embodiment may include a CXL controller and a RAID engine. The CXL controller may be connected to multiple first memories and at least one second memory, and the RAID engine may be connected to at least one second memory. The CXL controller may read and write multiple application data blocks in the first memory. The RAID engine may encode multiple application data blocks to obtain verification data blocks, and store the verification data blocks in the second memory. If there is a memory fault in the application data block read by the CXL controller, the RAID engine may repair the data block with the memory fault. For example, if there is a multi-bit fault in the application data block read by the CXL controller, the RAID engine may repair the application data block with the multi-bit fault to obtain the correct application data block. Through the above-mentioned memory read-write device, multi-bit memory faults can be repaired to repair faulty data, thereby improving memory reliability and further improving the reliability of electronic devices using the memory read-write device.

[0124] Next, combine Figure 5 , taking each first port connected to a first memory and each second port connected to a second memory as an example, the connection relationship between the memory read-write device and the memory (the first memory and the second memory) is described.

[0125] Figure 5A schematic diagram of the connection between a memory read / write device and a memory provided in an embodiment of the present application. Figure 5 ,exist Figure 4 On the basis of, the first port 1 can be connected to the first memory 1, the first port 2 can be connected to the first memory 2, ..., the first port n can be connected to the first memory n, and the second port i can be connected to the second memory i. Wherein, n and i are integers greater than or equal to 1.

[0126] Depend on Figure 5 It can be seen that, in this embodiment, each first port can be connected to a first memory, and each second port can be connected to a second memory.

[0127] In this embodiment, the CXL controller, the RAID engine, the first memory 1, the first memory 2, ..., the first memory n, and the second memory i may constitute a CXL memory device; or, the CXL controller, the first memory 1, the first memory 2, ..., the first memory n, and the second memory i may constitute a CXL memory device.

[0128] It should be noted that Figure 5 Examples in Figure 4 Based on the embodiment, the connection relationship between the memory read-write device and the memory is described. For a detailed introduction to the memory read-write device, please refer to Figure 4 The embodiments are not described in detail here.

[0129] Based on any of the above embodiments, the RAID engine may include a cache and a codec. Figure 6 , the memory reading and writing device provided in the embodiment of the present application is further explained.

[0130] Figure 6 This is a schematic diagram of the architecture of another memory read-write device provided in an embodiment of the present application. Figure 6 ,exist Figure 4 Based on the invention, the RAID engine includes a cache and a codec, wherein the codec is respectively connected with the cache and the at least one second port.

[0131] The cache may be a general random access memory (RAM), a static random access memory (SRAM), or a cache. In this embodiment, the cache may be connected to the CXL controller to obtain and store the application data block from the CXL controller. The codec may be a data verification device. In this embodiment, the codec may encode multiple application data blocks to obtain verification data blocks.

[0132] Optionally, the codec supports multi-channel parallel encoding of multiple application data blocks, so that the encoding speed of the codec is faster.

[0133] In this embodiment, the CXL controller is specifically used to slice the data to be written to obtain multiple application data blocks, store the multiple application data blocks in the cache, and write the application data blocks respectively in the first memories corresponding to the multiple first ports; the codec is used to encode the multiple application data blocks to obtain verification data blocks, and write the verification data blocks in the second memory corresponding to at least one second port.

[0134] Specifically, when the memory read / write device writes data to the memory, the CXL controller can slice the data to be written to obtain multiple application data blocks; the CXL controller can also store multiple application data blocks in parallel to the first memory and the cache, so that the codec can obtain multiple application data blocks from the cache and encode and decode multiple application data blocks. The codec can encode multiple application data blocks in the cache in parallel to obtain verification data. Encoding multiple application data blocks in parallel can increase the encoding speed of the codec; the codec can also store the verification data in the second memory. It can be understood that the present application stores multiple application data blocks in the first memory after obtaining them, and stores the verification data after obtaining verification data according to multiple application data blocks. This step-by-step storage method can improve the data storage speed and effectively reduce the data writing delay compared to waiting for verification data to be obtained according to multiple application data blocks, and then storing multiple application data blocks together with verification data.

[0135] During the above data writing process, the memory read-write device can first store multiple application data blocks to the first memory. After obtaining the verification data, the memory read-write device can then store the verification data to the second memory, so that multiple application data and verification data can be asynchronously written into the memory (first memory and second memory), avoiding the situation where multiple application data and verification data are synchronously stored, resulting in a low application data storage speed.

[0136] In this embodiment, the CXL controller is further used to determine whether there is an erroneous data block among the multiple application data blocks that have been read, and if so, send a recovery instruction to the RAID engine; the RAID engine is used to read a check data block from a second memory corresponding to at least one second port according to the recovery instruction, and recover the erroneous data block according to the check data block.

[0137] Specifically, when the memory read / write device reads data from the memory, the application data blocks can be read from the multiple first memories through the CXL controller. If there is an erroneous data block in the data blocks read by the CXL controller, the CXL controller can send a recovery instruction to the RAID engine. The RAID engine can obtain the check data blocks corresponding to the multiple application data blocks according to the recovery instruction, and recover the erroneous data blocks according to the check data.

[0138] It should be noted that, in this embodiment, the first memory may support ECC technology, and the first memory may recover single-bit data errors through ECC technology. In this embodiment, the error data block read by the memory read / write device may be a data block that the first memory cannot recover through ECC technology. For example, the error data block may be an application data block with multi-bit data errors.

[0139] Optionally, the RAID engine may obtain check data blocks corresponding to the multiple application data blocks through a codec, and decode the remaining data blocks except the error data blocks according to the check data to obtain correct data blocks corresponding to the error data blocks.

[0140] In the memory read-write device provided in this embodiment, the RAID engine includes a cache and a codec. When the memory read-write device writes data, the cache can store multiple application data blocks; the codec can encode multiple application data blocks to obtain verification data blocks. When the memory read-write device reads data, if an error data block is read, the codec can recover the error data block according to the verification data block to obtain the correct data block. Through the above-mentioned memory read-write device, application data blocks with multi-bit failures can be recovered, which improves memory reliability and further improves the reliability of electronic devices using the memory read-write device.

[0141] Based on any of the above embodiments, the RAID engine may also be arranged in the CXL controller, and the CXL controller may further include a processing core. Figure 7A-7B , the memory reading and writing device provided in the embodiment of the present application is further explained.

[0142] Fig. 7A This is a schematic diagram of the architecture of another memory read-write device provided in an embodiment of the present application. Fig. 7A The memory read / write device may include a CXL controller, and the CXL controller may include a RAID engine and a processing core.

[0143] The CXL controller further includes a plurality of first ports and at least one second port. For example, the plurality of first ports may be first port 1, first port 2, ..., and first port n, and the second port may be second port i, where n and i are integers greater than or equal to 1.

[0144] The processing cores may be connected to the plurality of first ports and the RAID engine respectively.

[0145] The processing core may perform slicing processing on the data to be written to obtain multiple application data blocks. The processing core may send the multiple application data blocks to the at least one first memory through the at least one first port. The processing core may also send the multiple application data blocks to the RAID engine.

[0146] The RAID engine is connected to at least one second port.

[0147] It should be noted that Fig. 7A Examples in Figure 4 Based on the embodiment, the location of the RAID engine is changed. In addition, Fig. 7A In an embodiment, the CXL controller may further include a processing core, and the processing core may be used to perform slicing processing on the data to be written. Fig. 7A For more information about memory read and write devices, see Figure 4 The embodiments are not described in detail here.

[0148] Figure 7B This is a schematic diagram of the architecture of another memory read-write device provided in an embodiment of the present application. Figure 7B ,exist Fig. 7A Based on this, the RAID engine can also include a cache and a codec.

[0149] The processing cores may be connected to the cache.

[0150] The codec is connected to the buffer and at least one second port respectively.

[0151] It should be noted that Figure 7B For more information about memory read and write devices, see Figure 6 Embodiment, or Fig. 7A The embodiments are not described in detail here.

[0152] It should be noted that Figure 6 , Fig. 7A and Figure 7B In the memory read / write device shown, each first port can be connected to one or more first memories, and each second port can be connected to one or more second memories; wherein a plurality is two or more. The schematic diagram of the connection relationship between the memory read / write device and the memory (the first memory and the second memory) can be seen in Figure 5 The embodiments are not described in detail here.

[0153] Based on any of the above embodiments, the present application also provides a data writing method applied to the memory read-write device described in any of the above embodiments. Figure 8, the data writing method provided in the embodiment of the present application is described.

[0154] Figure 8 A flowchart of a data writing method provided in an embodiment of the present application. Figure 8 , the method may include:

[0155] S801, obtaining data to be written.

[0156] The data writing method provided in this embodiment is applied to Figure 4-Figure 6 , Fig. 7A ,or Figure 7B Any memory read / write device shown.

[0157] In this embodiment, the CXL control device may obtain the data to be written.

[0158] The data to be written can be: Figure 3A or Figure 3B The computing data of the computing device in the.

[0159] The CXL controller may obtain the data to be written from the computing device. Optionally, the CXL controller may obtain the data to be written from a central processing unit (CPU) of the computing device.

[0160] S802: Slice the data to be written to obtain multiple application data blocks.

[0161] In this embodiment, the CXL controller may perform segmentation processing on the data to be written to obtain multiple application data blocks.

[0162] Optionally, a processing core may be provided in the CXL controller, and the CXL controller may perform slicing processing on the data to be written through the processing core to obtain multiple application data blocks.

[0163] In this embodiment, the CXL controller may perform slicing processing on the data to be written based on a preset number or a preset size.

[0164] The preset number may be a preset number of shards. The preset size may be a preset size of shards. The preset number of shards may be a number of shards that a user pre-sets in a computing device according to storage requirements; the preset size of shards may be a size of shards that a user pre-sets in a computing device according to storage requirements.

[0165] In one example, the CXL controller may segment the data to be written based on a preset number to obtain a preset number of application data blocks.

[0166] In this example, the CXL controller may divide the data to be written into a preset number of application data blocks of equal size.

[0167] For example, assuming that the preset number is 4 and the size of the data to be written is 1024 MB, the CXL controller may divide the data to be written into 4 application data blocks of the same size, and the size of the application data block is 256 MB.

[0168] In another example, the CXL controller may segment the data to be written based on a preset size to obtain multiple application data blocks, and the size of each application data block is equal to the preset size.

[0169] In this example, the CXL controller may divide the data to be written into a plurality of application data blocks of a preset size.

[0170] For example, assuming that the preset size is 256 MB and the size of the data to be written is 1024 MB, the CXL controller may divide the data to be written into application data blocks of 256 MB in size, and the number of application data blocks is 4.

[0171] S803: Store the multiple application data blocks in the first memories corresponding to the multiple first ports.

[0172] In this embodiment, the CXL controller may store a plurality of application data blocks in first memories corresponding to a plurality of first ports, wherein one application data block is correspondingly stored in the first memory corresponding to one first port.

[0173] Optionally, a processing core may be provided in the CXL controller. The CXL controller may store the plurality of application data blocks in the first memories corresponding to the plurality of first ports through the processing core.

[0174] In this embodiment, the number of application data blocks is equal to the number of first memories. The CXL controller may store one application data block in parallel to the same storage location in each first memory.

[0175] Specifically, the CXL controller may store each application data block in parallel in a different first memory.

[0176] For example, assuming that the number of application data blocks and first memories is 4, the CXL controller may store one application data block in parallel to the same position of each first memory.

[0177] It should be noted that, in this embodiment, the CXL controller supports memory interleaving technology. The CXL controller can use memory interleaving to store multiple application data blocks in multiple first memories in parallel through multiple channels to improve the bandwidth of the first memories.

[0178] It should be noted that, in this embodiment, the first memory is not improved, and the first memory still supports ECC technology. That is, when writing application data blocks, each first memory can perform ECC verification on the corresponding application data blocks, and can also store the verification data obtained by the ECC verification.

[0179] S804: Encode multiple application data blocks to obtain verification data blocks.

[0180] In this embodiment, the RAID engine may perform encoding processing on multiple application data blocks to obtain verification data blocks.

[0181] In this embodiment, the RAID engine may include a cache and a codec. The CXL controller may store multiple application data blocks in the cache in parallel while storing multiple application data blocks in the first memory.

[0182] The codec may encode the multiple application data blocks in the buffer to obtain a verification data block.

[0183] Optionally, the codec supports multi-channel parallelism and performs encoding processing on multiple application data blocks, so that the encoding speed of the codec is faster.

[0184] Optionally, before the RAID engine performs encoding processing on the multiple application data blocks, the RAID engine may receive the multiple application data blocks sent by the CXL controller or a processing core of the CXL controller.

[0185] S805. Store the verification data block in a second memory corresponding to at least one second port.

[0186] In this embodiment, the RAID engine may store the check data block in a second memory corresponding to at least one second port.

[0187] In this embodiment, after the RAID engine obtains the check data block, it can store the check data block in the second memory. Further, the position of the check data block in the second memory is the same as the position of each application data block in the first memory, so as to store data quickly.

[0188] In this embodiment, after the CXL controller stores multiple application data blocks in multiple first memories, the RAID engine stores the check data blocks in the second memory. In other words, the memory read / write device asynchronously stores multiple application data blocks and check data blocks in the memory (first memory and second memory), avoiding the situation where multiple application data and check data are stored synchronously, resulting in a low storage speed of application data.

[0189] In the data writing method provided in this embodiment, the CXL controller can obtain the data to be written, can slice the data to be written to obtain multiple application data blocks, and can store the multiple application data blocks in the first memory corresponding to the multiple first ports. The RAID engine can encode the multiple application data blocks to obtain the verification data blocks, and can store the verification data blocks in the second memory corresponding to at least one second port. Through the above method, the multiple application data blocks can be verified by the RAID engine, thereby improving the reliability of the first memory. In addition, the CXL controller can slice the data to be written into multiple application data blocks, and can write multiple application data blocks to the first memory in parallel through multiple channels, so that the memory write bandwidth is large, the write speed is fast, and the write performance is good.

[0190] Based on any of the above embodiments, the present application also provides a data reading method applied to the memory reading and writing device described in any of the above embodiments. Fig. 9 , the data reading method provided in the embodiment of the present application is described.

[0191] Fig. 9 A flowchart of a data reading method provided in an embodiment of the present application. Fig. 9 , the method may include:

[0192] S901: Receive a data read request, where the data read request includes a storage location of a target application data block to be read.

[0193] The data reading method provided in this embodiment is applied to Figure 4-Figure 6 , Fig. 7A ,or Figure 7B Any memory read / write device shown.

[0194] In this embodiment, the CXL controller may receive a data read request.

[0195] In this embodiment, the data read request can be Figure 3A or Figure 3B The data read request is sent by the computing device in the embodiment of the present invention. Optionally, the data read request may be a data read request sent by a CPU of the computing device.

[0196] It should be noted that the number of the target application data blocks to be read may be one or more, which is not limited in this embodiment.

[0197] S902: Read a target application data block from a first memory corresponding to a first port according to a data read request.

[0198] In this embodiment, the CXL controller may read the target application data block from the first memory corresponding to the first port according to the data read request.

[0199] In this embodiment, each application data block can be stored in a first memory. If the number of target application data blocks to be read is one, the CXL controller can read the target application data block from a corresponding first memory according to the storage location in the data read request. If the number of target application data blocks to be read is multiple, the CXL controller can read multiple target application data blocks from the corresponding multiple first memories in parallel according to the storage location in the data read request.

[0200] It should be noted that, in this embodiment, the CXL controller supports memory interleaving technology. The CXL controller can read multiple target application data blocks from multiple first memories in parallel through multiple channels using memory interleaving to increase the bandwidth of the first memories and improve the data reading rate.

[0201] S903: Determine whether there is an error data block in the target application data block.

[0202] In this embodiment, the CXL controller may determine whether there is an error data block in the target application data block.

[0203] If yes, execute S904;

[0204] If not, execute S906.

[0205] In this embodiment, the first memory is not improved, and the first memory still supports the ECC technology and the cyclic redundancy check (CRC) technology. That is, when writing an application data block, each first memory can perform an ECC check and / or a CRC check on the corresponding application data block, and can store the check data obtained by the ECC check and / or the CRC check.

[0206] Correspondingly, for any first memory, when the CXL controller reads an application data block in the first memory, it can determine whether the application data block is an erroneous data block according to the ECC check data and / or the CRC check data.

[0207] It should be understood that if the application data block is determined to be an error data block based on the ECC check data and the CRC check data, the data error in the error data block is an error that cannot be repaired by the first memory using the ECC technology and the CRC technology. For example, the data error in the error data block may be a multi-bit data error.

[0208] S904: Read the verification data block and the auxiliary application data blocks corresponding to the verification data block except the target application data block.

[0209] In this embodiment, the RAID engine may read the check data block and the auxiliary application data blocks corresponding to the check data block except the target application data block.

[0210] Specifically, the RAID engine may read the check data block from the second memory corresponding to the at least one second port, and may read the auxiliary application data block from the CXL controller.

[0211] The verification data block may be a verification data block of a target application data block corresponding to the data read request, which is generated by the DAID engine.

[0212] It should be noted that the check data block can be generated by the DAID engine based on multiple application data blocks. Among the multiple application data blocks, the remaining data blocks except the error data block can be auxiliary application data blocks corresponding to the check data block. The number of auxiliary application data blocks can be one or more, that is, the multiple application data blocks include the error data block (target application data block) and multiple auxiliary application data blocks.

[0213] In this embodiment, the CXL controller may send a recovery instruction to the RAID engine, so that the RAID engine may read the check data block from the second memory according to the recovery instruction. The recovery instruction may include the auxiliary application data block.

[0214] Optionally, before the CXL controller sends the recovery instruction to the DAID engine, it may obtain the auxiliary application data block. It should be noted that the CXL controller may read the auxiliary application data block according to the storage location of the auxiliary application data block.

[0215] S905. Perform recovery processing on the error data block according to the check data block and the auxiliary application data block to obtain a correct data block corresponding to the error data block.

[0216] In this embodiment, the RAID engine can perform recovery processing on the error data block according to the check data block and the auxiliary application data block to obtain the correct data block corresponding to the error data block.

[0217] In this embodiment, the RAID engine decodes the auxiliary application data block according to the check data block to obtain a correct data block corresponding to the error data block.

[0218] Exemplarily, assuming that the target data blocks are four application data blocks corresponding to the check data blocks, and there is an error data block among the four application data blocks obtained by the CXL controller, the RAID can decode the remaining three application data blocks according to the check data to obtain the correct data block corresponding to the error data block.

[0219] Optionally, if the RAID engine is not provided on the CXL controller, the RAID engine may send the restored correct application data block to the CXL controller.

[0220] S906. Send the correct target application data block to the CPU.

[0221] In this embodiment, the CXL controller may send the correct target application data block to the CPU.

[0222] In this embodiment, the correct target application data block includes the following two situations:

[0223] Case 1: If the number of target application data blocks is one and the target application data block is a correct application data block, the correct target application data block sent by the CXL controller to the CPU is an application data block directly obtained by the CXL controller from the first memory. Alternatively, if the number of target application data blocks is multiple and each target application data block is a correct application data block, the correct target application data block sent by the CXL controller to the CPU is an application data block directly obtained by the CXL controller from multiple first memories.

[0224] Case 2: The number of target application data blocks is one, and the target application data block is an erroneous data block. The correct target application data block sent by the CXL controller to the CPU is the correct data block obtained by recovering the target application data block through the RAID engine. Alternatively, the number of target application data blocks is multiple, the first part of the multiple target application data blocks are all correct application data blocks, and the second part of the multiple target application data blocks are all erroneous data blocks. The correct target application data block sent by the CXL controller to the CPU includes the correct data block obtained by recovering the first part of the application data blocks and the second part of the application data blocks through the RAID engine.

[0225] In case 1, there is no error data block in the target application data blocks obtained by the CXL controller from the first memory.

[0226] In this case, the CXL controller can directly send one or more correct application data blocks to the CPU. Optionally, when there are multiple target application data blocks, the CXL controller can first combine and process the multiple correct target application data blocks to obtain the data to be sent, and then send the data to be sent to the CPU.

[0227] In case 2, there is an erroneous data block in the target application data block obtained by the CXL controller from the first memory.

[0228] In this case, the CXL controller may send a correct data block obtained by recovering an erroneous data block through the RAID engine to the CPU; or the CXL controller may send a correct data block obtained by recovering the first part of the application data block and the second part of the application data block through the RAID engine to the CPU. Optionally, when there are multiple target application data blocks, the CXL controller may first combine the first part of the application data block and the correct data block obtained by recovering the second part of the application data block through the RAID engine to obtain the data to be sent, and send the data to be sent to the CPU.

[0229] In the data reading method provided in this embodiment, the CXL controller can receive a data reading request, and can read the target application data block from the first memory corresponding to the multiple first ports according to the data reading request. If there is no error data block in the target application data block read by the CXL controller, the CXL controller can directly send the target application data block to the CPU. If there is an error data block in the target application data block read by the CXL controller, the RAID engine can read the check data block from the second memory corresponding to the second port, and can recover the error data block according to the check data block to obtain the correct data block corresponding to the error data block. Through the above method, the RAID engine can recover the error application data block obtained from the first memory, thereby improving the reliability of the first memory.

[0230] Based on any of the above embodiments, each first port of the memory read / write device can also be connected to the first memory through the first CXL memory controller, and each second port of the memory read / write device can also be connected to the second memory through the second CXL memory controller. Figure 10-12 , further explanation of memory reading and writing devices.

[0231] Fig.10 A schematic diagram of the connection between a memory read / write device and a first CXL memory controller and a second CXL memory controller provided in an embodiment of the present application.

[0232] See also Fig.10 The first port of the memory read / write device may be connected to a first CXL memory controller, and the first CXL memory controller may be used to connect to at least one first memory.

[0233] The second port of the memory read / write device may be connected to a second CXL memory controller, and the second CXL memory controller may be used to connect to at least one second memory.

[0234] In this embodiment, the CXL controller may be a CXL switch controller in a CXL switch device.

[0235] The first CXL memory controller and the second CXL memory controller may be a CXL memory expander chip, a CXL memory expander controller, or a CXL memory pooling chip.

[0236] It should be noted that Figure 6 The description of the memory read-write device in the embodiment is in Fig.10 The embodiments still apply. Fig.10 For an introduction to the memory read / write device in the embodiment, please refer to Figure 6 The embodiments are not described in detail here.

[0237] Next, combine Fig.11 , taking each first CXL memory controller connected to multiple first memories and each second CXL memory controller connected to multiple second memories as an example, the connection relationship between the memory read / write device and the memory (first memory and second memory) is described.

[0238] Fig.11 This is a schematic diagram of another memory read / write device and memory connection provided in an embodiment of the present application. Fig.11 ,exist Fig.10 On the basis of, the first CXL memory controller 1 can be connected to m first memories, the first CXL memory controller 2 can be connected to m first memories, ..., the first CXL memory controller n can be connected to m first memories, and the second CXL memory controller i can be connected to m second memories, where m and i are integers greater than or equal to 1.

[0239] Depend on Fig.11 It can be seen that in this embodiment, each first port can be connected to one or more first memories through a first CXL memory controller, and each second port can be connected to one or more second memories through a second CXL memory controller.

[0240] In this embodiment, the first CXL memory controller 1, the first CXL memory controller 2, ..., the first CXL memory controller n, the second CXL memory controller i, the first memories connected to the first memory controllers, and the second memories connected to the second memories may constitute a CXL memory device.

[0241] In this embodiment, each first CXL memory controller and the first memory connected to the first CXL memory controller may constitute a first CXL storage device, and each second CXL memory controller and the second memory connected to the second CXL memory controller may constitute a second CXL storage device.

[0242] Exemplarily, a first CXL memory controller 1 and a first memory connected to the first CXL memory controller 1 may constitute a first CXL memory device 1. A first CXL memory controller 2 and a first memory connected to the first CXL memory controller 2 may constitute a first CXL memory device 2. A first CXL memory controller n and a first memory connected to the first CXL memory controller n may constitute a first CXL memory device n. A second CXL memory controller i and a second memory connected to the second CXL memory controller i may constitute a second CXL memory device i.

[0243] It should be noted that Fig.11 Examples in Fig.10 Based on the embodiment, the connection relationship between the memory read-write device and the memory is described. For a detailed introduction to the memory read-write device, please refer to Fig.10 The embodiments are not described in detail here.

[0244] exist Fig.10 Based on the embodiment, the RAID engine can also be set in the CXL controller. Fig.12 , the memory reading and writing device provided in the embodiment of the present application is further explained.

[0245] Fig.12 A schematic diagram of another memory read / write device provided in an embodiment of the present application and a first CXL memory controller and a second CXL memory controller. Fig.12 , the memory read-write device may include a CXL controller, and the CXL controller may include a RAID engine.

[0246] The CXL controller includes a plurality of first ports and at least one second port. For example, the plurality of first ports may be first port 1, first port 2, ..., and first port n, and the second port may be second port i, where n and i are integers greater than or equal to 1.

[0247] The first port may be connected to a first CXL memory controller, and the second port may be connected to a second CXL memory controller. The RAID engine may be connected to at least one second port.

[0248] It should be noted that Fig.12 Examples in Fig.10 On the basis of the previous example, only the setting position of the RAID engine was changed. Fig.12 For more information about memory read and write devices, see Fig.10 The embodiments are not described in detail here.

[0249] It should be noted that Fig.12In the memory read / write device shown, each first CXL memory controller can be connected to one or more first memories, and each second CXL memory controller can be connected to one or more second memories; wherein a plurality is two or more. The connection relationship diagram of the memory read / write device and the memory (first memory and second memory) can be seen in Fig.11 The embodiments are not described in detail here.

[0250] in addition, Figure 10-12 The CXL controller in the embodiment may also include a processing core. For the case where the CXL controller includes a processing core, see Fig. 7A and Figure 7B The embodiments are not described in detail here.

[0251] exist Figure 10-12 Based on this, the embodiment of the present application also provides an application Figure 10-12 The data writing method of the memory read-write device described in the embodiment. Fig.13 , the data writing method provided in the embodiment of the present application is described.

[0252] Fig.13 This is a flowchart of another data writing method provided in an embodiment of the present application. Fig.13 , the method may include:

[0253] S1301, obtaining data to be written.

[0254] S1302: Slice the data to be written to obtain multiple application data blocks.

[0255] It should be noted that the specific implementation method of S1301-S1302 can be found in S801-S802 and will not be repeated here.

[0256] S1303: Send multiple application data blocks to first CXL memory controllers corresponding to the multiple first ports.

[0257] In this embodiment, the CXL controller may send a plurality of application data blocks to the first CXL memory controllers corresponding to the plurality of first ports.

[0258] Specifically, the number of the plurality of first ports is the same as the number of the plurality of application data blocks. The CXL controller may send one application data block to the first CXL memory controller corresponding to each first port.

[0259] In this embodiment, the CXL controller can send multiple application data blocks to multiple first CXL memory controllers in parallel through multiple channels to improve the data writing speed. For example, the CXL controller can send multiple application data blocks to K first CXL memory controllers in parallel through multiple channels, and the writing speed performance of the CXL controller can be improved by K times.

[0260] S1304. Store the application data block in the first memory.

[0261] In this embodiment, after receiving the application data block, each first CXL memory controller may store the application data block in the corresponding first memory. It should be understood that the number of first memories corresponding to each first CXL memory controller may be one or more, wherein the number may be two or more.

[0262] It should be noted that each first CXL memory controller stores the application data block in the first memory in the same manner. In the following, any first CXL memory controller is taken as an example to describe the manner in which the first CXL memory controller stores the application data block in the first memory.

[0263] In this embodiment, the first CXL memory controller can be connected to one or more first memories. If the first CXL memory controller is connected to one first memory, the first CXL memory controller can directly store the application data block in the first memory. If the first CXL memory controller is connected to multiple first memories, the first CXL memory controller can use memory interleaving and multi-channel parallel storage of application data blocks in the first memory to further improve the bandwidth of the first memory. For example, the CXL controller can send multiple application data blocks to K first CXL memory controllers in parallel through multiple channels, and each first CXL memory controller can store application data blocks to x first memories in parallel through multiple channels, so the write performance of the CXL controller can be improved by xK times.

[0264] S1305. Encode multiple application data blocks to obtain verification data blocks.

[0265] S1306. Store the verification data block in a second memory corresponding to at least one second port.

[0266] It should be noted that the specific implementation method of S1305-S1306 can be found in S804-S805 and will not be repeated here.

[0267] In the data writing method provided in this embodiment, the CXL controller can obtain the data to be written, can slice the data to be written to obtain multiple application data blocks, and can send the multiple application data blocks to multiple first CXL memory controllers in parallel and through multiple channels. After each first CXL memory controller receives the application data block sent by the CXL controller, it can store the application data block to the first memory in parallel and through multiple channels. The RAID engine can encode the multiple application data blocks to obtain the verification data blocks, and can store the verification data blocks in the second memory corresponding to at least one second port. Through the above method, the multiple application data blocks can be verified by the RAID engine, thereby improving the reliability of the first memory. The CXL controller can slice the data to be written into multiple application data blocks, and can send the multiple application data blocks to multiple first CXL memory controllers in parallel and through multiple channels, so that the memory write bandwidth is large and the write performance is good. In addition, each first CXL memory controller can also store the application data blocks to the first memory in parallel and through multiple channels, thereby further improving the write performance of the memory.

[0268] exist Figure 10-12 Based on this, the embodiment of the present application also provides an application Figure 10-12 The data reading method of the memory read-write device described in the embodiment. Fig.14 , the data reading method provided in the embodiment of the present application is described.

[0269] Fig.14 This is a flow chart of another data reading method provided in an embodiment of the present application. Fig.14 , the method may include:

[0270] S1401. Receive a data read request, where the data read request includes a storage location of a target application data block to be read.

[0271] It should be noted that the specific implementation method of S1401 can be found in S901 and will not be repeated here.

[0272] S1402: Send a data read request to the first CXL memory controller.

[0273] In this embodiment, the CXL controller may send a data read request to the first CXL memory controller.

[0274] Specifically, the CXL controller may determine one or more corresponding first CXL memory controllers according to the target application data block to be read, and send data read requests to the determined one or more first CXL memory controllers respectively. In this embodiment, if there are multiple first CXL memory controllers, the CXL controller may send data read requests to the multiple first CXL memory controllers in parallel through multiple channels to increase the data read speed.

[0275] S1403. Read a target application data block from the first memory according to the data read request.

[0276] In this embodiment, the first CXL memory controller that receives the data read request may read the target application data block from the corresponding first memory. It should be understood that the first CXL memory controller that receives the data read request may correspond to one or more first memories.

[0277] It should be noted that each first CXL memory controller reads the target application data block in the same manner. In the following, any first CXL memory controller is taken as an example to illustrate the manner in which the first CXL memory controller reads the target application data block.

[0278] In this embodiment, the first CXL memory controller can be connected to one or more first memories. If the first CXL memory controller is connected to one first memory, the first CXL memory controller can directly read the target application data block from the corresponding first memory. If the first CXL memory controller is connected to multiple first memories, the first CXL memory controller can read the target application data block from the corresponding multiple first memories respectively in a memory interleaving manner and multi-channel parallel, so as to further improve the bandwidth of the first memory and improve the data reading rate.

[0279] S1404: Determine whether there is an error data block in the target application data block.

[0280] If not, execute S1405;

[0281] If so, execute S1406.

[0282] In this embodiment, each first CXL memory controller can determine whether the target application data block read by itself includes an erroneous data block. If the target application data blocks read by each first CXL memory controller are all correct application data blocks, S1405 is executed; if the target application data blocks read by any first CXL memory controller include an erroneous application data block, S1406 is executed.

[0283] In this embodiment, the first memory is not improved, and the first memory still supports the ECC technology and the CRC technology. That is, when writing an application data block, each first memory can perform an ECC check and / or a CRC check on the corresponding application data block, and can store the check data obtained by the ECC check and / or the CRC check.

[0284] Correspondingly, for any first memory, when the first CXL memory controller reads an application data block in the first memory, it can determine whether the application data block is an erroneous data block according to the ECC check data and / or the CRC check data.

[0285] It should be understood that if the application data block is determined to be an error data block based on the ECC check data and the CRC check data, the data error in the error data block is an error that cannot be repaired by the first memory using the ECC technology and the CRC technology. For example, the data error in the error data block may be a multi-bit data error.

[0286] S1405 . Send the target application data block to the CXL controller.

[0287] In this embodiment, each first CXL memory controller may send the target application data block read by itself to the CXL controller.

[0288] In this embodiment, if all the first CXL memory controllers read the correct target application data blocks, each first CXL memory controller may send the target application data block it has read to the CXL controller.

[0289] It should be noted that S1409 can be executed after S1405.

[0290] S1406: The first CXL memory controller whose read target data blocks are all correct data blocks sends the read target application data blocks to the CXL controller; the first CXL memory controller whose read target data blocks have error data blocks sends a read error response to the CXL controller.

[0291] In this embodiment, if there is an erroneous application data block in the target data block read by the first CXL memory controller, a read error response may be sent to the CXL controller so that the CXL controller may instruct the RAID engine to recover the erroneous data block.

[0292] S1407, read the verification data block, and the auxiliary application data blocks corresponding to the verification data block except the target application data block.

[0293] S1408. Perform recovery processing on the error data block according to the check data block and the auxiliary application data block to obtain a correct data block corresponding to the error data block.

[0294] It should be noted that the specific implementation method of S1407-S1408 can be found in S904-S905 and will not be repeated here.

[0295] S1409. Send the correct target application data block to the CPU.

[0296] In this embodiment, the CXL controller may send the correct target application data block to the CPU.

[0297] In this embodiment, the correct target application data block includes the following two situations:

[0298] Case 1: If the number of target application data blocks is one and the target application data block is a correct application data block, the correct target application data block sent by the CXL controller to the CPU is an application data block directly obtained by the first CXL memory controller from the corresponding first memory. Alternatively, if the number of target application data blocks is multiple and each target application data block is a correct application data block, the correct target application data block sent by the CXL controller to the CPU may be application data blocks obtained by multiple first CXL memory controllers from the corresponding first memory.

[0299] Case 2: The number of target application data blocks is one, and the target application data block is an erroneous data block. The correct target application data block sent by the CXL controller to the CPU is the correct data block obtained by recovering the target application data block through the RAID engine. Alternatively, the number of target application data blocks is multiple, the first part of the multiple target application data blocks are all correct application data blocks, and the second part of the multiple target application data blocks are all erroneous data blocks. The correct target application data block sent by the CXL controller to the CPU includes the correct data block obtained by recovering the first part of the application data blocks and the second part of the application data blocks through the RAID engine.

[0300] In case 1, the target application data blocks read from the first memory by the first CXL memory controller do not contain error data blocks.

[0301] In this case, the CXL controller can directly send one or more correct application data blocks to the CPU. Optionally, when there are multiple target application data blocks, the CXL controller can first combine all correct application data blocks to obtain data to be sent, and send the data to be sent to the CPU.

[0302] In case 2, there are error data blocks in the target application data blocks read by the first CXL memory controller from the first memory.

[0303] In this case, the CXL controller may send a correct data block obtained by recovering an erroneous data block through the RAID engine to the CPU; or the CXL controller may send a correct data block obtained by recovering the first part of the application data block and the second part of the application data block through the RAID engine to the CPU. Optionally, when there are multiple target application data blocks, the CXL controller may first combine all correct application data blocks to obtain data to be sent, and send the data to be sent to the CPU.

[0304] In the data reading method provided in this embodiment, the CXL controller can receive a data reading request and can send a data reading request to at least one first CXL memory controller. At least one first CXL memory controller can read the target application data block from the corresponding first memory according to the data reading request, can determine whether there is an error data block in the read target application data block, and can send the read correct application data block to the CXL controller. If there is no error data block in the target application data block read by at least one first CXL memory controller, the CXL controller can directly send multiple target application data blocks to the CPU. If there is an error data block in the target application data block read by at least one first CXL memory controller, the RAID engine can read the check data block from the second memory corresponding to the second port, and can recover the error data block according to the check data block to obtain the correct data block corresponding to the error data block. Through the above method, the RAID engine can recover the error application data block obtained from the first memory, thereby improving the reliability of the first memory.

[0305] The present application embodiment provides a CXL memory device, the CXL memory device includes a memory read / write device, a plurality of first memories and a second memory, the memory read / write device includes a CXL controller and a RAID engine, the CXL controller includes a plurality of first ports and at least one second port, wherein:

[0306] The RAID engine is connected to the at least one second port, each of the first ports is used to connect to one of the first memories, the second port is used to connect to one of the second memories, the first memory is used to store application data blocks, and the second memory is used to store check data blocks;

[0307] The CXL controller is used to slice the data to be written to obtain a plurality of the application data blocks, and write the plurality of application data blocks into the first memories connected to the plurality of the first ports respectively; or, according to the storage location of the target application data block to be read, obtain the target application data block from the first memory connected to the corresponding first port;

[0308] The RAID engine is used for encoding the multiple application data blocks to obtain check data blocks, storing the check data blocks in the second memory corresponding to at least one of the second ports, and recovering the erroneous target application data blocks when the target application data blocks read by the CXL controller are erroneous.

[0309] The CXL memory device provided in this embodiment can be used to execute the data writing method and the data reading method shown in the above method embodiments. The implementation principles and technical effects are similar and will not be described in detail here.

[0310] The embodiment of the present application provides a CXL switching device, the CXL switching device includes a CXL controller and a RAID engine, the CXL controller includes a plurality of first ports and at least one second port, wherein:

[0311] The RAID engine is connected to the at least one second port, each of the first ports is connected to a first CXL storage device, each of the second ports is connected to a second CXL storage device, the first CXL storage device is used to store application data blocks, and the second CXL storage device is used to store check data blocks;

[0312] The CXL controller is used to slice the data to be written to obtain a plurality of the application data blocks, and write the plurality of application data blocks into the first CXL storage devices connected to the plurality of the first ports respectively; or, according to the storage location of the target application data block to be read, obtain the target application data block from the first CXL storage device connected to the corresponding first port;

[0313] The RAID engine is used for encoding the multiple application data blocks to obtain check data blocks, storing the check data blocks in the second CXL storage device corresponding to at least one of the second ports, and recovering the erroneous target application data blocks when the target application data blocks read by the CXL controller are erroneous.

[0314] The CXL switching device provided in this embodiment can be used to execute the data writing method and the data reading method shown in the above method embodiments. The implementation principles and technical effects are similar and will not be described in detail here.

[0315] All or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned memory (storage medium) includes: read-only memory (English: read-only memory, abbreviated: ROM), RAM, flash memory, hard disk, solid state drive, magnetic tape (English: magnetic tape), floppy disk (English: floppy disk), optical disc (English: optical disc) and any combination thereof.

[0316] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable terminal device to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0317] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0318] These computer program instructions can also be loaded onto a computer or other programmable terminal device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0319] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the embodiments of the present application are also intended to include these modifications and variations.

[0320] In the embodiments of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the element. The term "or" and its variations may refer to "and / or". In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. In the embodiments of the present application, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, A and / or B, which may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0321] After considering the invention disclosed in the specification and practice, those skilled in the art will easily think of other embodiments of the present application. The embodiments of the present application are intended to cover any variation, use or adaptive change of the embodiments of the present application, which follows the general principles of the embodiments of the present application and includes common knowledge or conventional technical means in the technical field that are not disclosed in the embodiments of the present application.

Claims

1. A memory reading and writing device, characterized in that: include: A CXL controller and a RAID engine, wherein the CXL controller comprises a plurality of first ports and at least one second port, wherein: The RAID engine is connected to the at least one second port, each of the first ports is used to connect to at least one first memory, the second port is used to connect to at least one second memory, the first memory is used to store application data blocks, and the second memory is used to store check data blocks; The CXL controller is used to slice the data to be written to obtain a plurality of the application data blocks, and write the plurality of application data blocks into the first memories connected to the plurality of the first ports respectively; or, according to the storage location of the target application data block to be read, obtain the target application data block from the first memory connected to the corresponding first port; The RAID engine is used for encoding the multiple application data blocks to obtain check data blocks, storing the check data blocks in the second memory corresponding to at least one of the second ports, and recovering the erroneous target application data blocks when the target application data blocks read by the CXL controller are erroneous.

2. The memory read-write device according to claim 1, characterized in that: The RAID engine includes a cache and a codec, wherein the codec is connected to the cache and the at least one second port respectively; The cache is used to store the multiple application data blocks obtained by the CXL controller through slicing; The codec is used to encode the multiple application data blocks stored in the cache to obtain the check data block, and after the multiple application data blocks are written into the first memory, store the check data block in the second memory corresponding to at least one of the second ports; or, when the target application data block read by the CXL controller is erroneous, recover the erroneous target application data block.

3. The memory reading and writing device according to claim 2, characterized in that: The CXL controller comprises a processing core, the processing cores are respectively connected to the plurality of first ports, and the processing cores are also connected to the cache; The processing core is used to slice the data to be written to obtain the multiple application data blocks, store the multiple application data blocks in the cache, and write the multiple application data blocks in parallel in the first memories corresponding to the multiple first ports.

4. The memory reading and writing device according to claim 2, characterized in that: The CXL controller is further used to determine whether there is an erroneous data block in the target application data block that has been read, and if so, send a recovery instruction to the RAID engine; The RAID engine is used to read the check data block from the second memory corresponding to at least one of the second ports through the codec according to the recovery instruction, and perform recovery processing on the erroneous target application data block according to the check data block.

5. The memory reading and writing device according to any one of claims 1 to 4, characterized in that: The RAID engine is disposed in the CXL controller.

6. The memory reading and writing device according to any one of claims 1 to 5, characterized in that: The CXL controller is a CXL switch controller in a CXL switch device, or the CXL controller is a CXL memory controller in a CXL memory device; If the CXL controller is a CXL switch controller, the first port is used to connect the first memory through a first CXL memory controller, and the second port is used to connect the second memory through a second CXL memory controller, wherein the first CXL memory controller and the second CXL memory controller are CXL memory controllers in the CXL memory device; If the CXL controller is a CXL memory controller, the first port is used to connect to the first memory, and the second port is used to connect to the second memory.

7. A data writing method, characterized in that: Applied to a memory read-write device, the memory read-write device includes a CXL controller and a RAID engine, the CXL controller includes a plurality of first ports and at least one second port, the RAID engine is connected to the at least one second port, and the method includes: The CXL controller obtains data to be written, slices the data to be written to obtain a plurality of application data blocks, writes the plurality of application data blocks into first memories corresponding to the plurality of first ports respectively, and writes the plurality of application data blocks into the RAID engine; The RAID engine encodes the multiple application data blocks to obtain verification data blocks, and stores the verification data blocks in a second memory corresponding to the at least one second port.

8. The method according to claim 7, characterized in that The RAID engine stores the check data block in a second memory corresponding to the at least one second port, including: After the CXL controller writes the multiple application data blocks into the first memories corresponding to the multiple first ports respectively, the RAID engine stores the check data block into the second memory corresponding to the at least one second port.

9. A data reading method, characterized in that: Applied to a memory read-write device, the memory read-write device includes a CXL controller and a RAID engine, the CXL controller includes a plurality of first ports and at least one second port, the RAID engine is connected to the at least one second port, and the method includes: The CXL controller receives a data read request from a central processing unit (CPU), wherein the data read request includes a storage location of a target application data block to be read; The CXL controller reads the target application data block from the first memory corresponding to the plurality of first ports according to the data read request, and determines whether there is an error data block in the target application data block; When an error data block exists in the target application data block, the CXL controller requests the RAID engine to read a check data block from a second memory corresponding to the at least one second port, and recover the error data block according to the check data block to obtain a correct data block corresponding to the error data block; The CXL controller sends the correct target application data block to the CPU.

10. A CXL memory device, characterized in that: The CXL memory device includes a memory read / write device, a plurality of first memories and a second memory, the memory read / write device includes a CXL controller and a RAID engine, the CXL controller includes a plurality of first ports and at least one second port, wherein: The RAID engine is connected to the at least one second port, each of the first ports is used to connect to one of the first memories, the second port is used to connect to one of the second memories, the first memory is used to store application data blocks, and the second memory is used to store check data blocks; The CXL controller is used to slice the data to be written to obtain a plurality of the application data blocks, and write the plurality of application data blocks into the first memories connected to the plurality of the first ports respectively; or, according to the storage location of the target application data block to be read, obtain the target application data block from the first memory connected to the corresponding first port; The RAID engine is used for encoding the multiple application data blocks to obtain check data blocks, storing the check data blocks in the second memory corresponding to at least one of the second ports, and recovering the erroneous target application data blocks when the target application data blocks read by the CXL controller are erroneous.

11. A CXL switching device, characterized in that: The CXL switching device comprises a CXL controller and a RAID engine, wherein the CXL controller comprises a plurality of first ports and at least one second port, wherein: The RAID engine is connected to the at least one second port, each of the first ports is connected to a first CXL storage device, each of the second ports is connected to a second CXL storage device, the first CXL storage device is used to store application data blocks, and the second CXL storage device is used to store check data blocks; The CXL controller is used to slice the data to be written to obtain a plurality of the application data blocks, and write the plurality of application data blocks into the first CXL storage devices connected to the plurality of the first ports respectively; or, according to the storage location of the target application data block to be read, obtain the target application data block from the first CXL storage device connected to the corresponding first port; The RAID engine is used for encoding the multiple application data blocks to obtain check data blocks, storing the check data blocks in the second CXL storage device corresponding to at least one of the second ports, and recovering the erroneous target application data blocks when the target application data blocks read by the CXL controller are erroneous.

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