Memory management method and memory controller

Abstract

The invention provides a memory management method and a memory controller thereof. The method comprises the following steps: acquiring a first voltage value of a first data reading operation; setting the first voltage value and the first reading parameter to an integrated reading module; when the integrated reading module executes the first data reading operation, obtaining a second voltage value of a second data reading operation in parallel; and in response to completion of the first data reading operation, setting a second voltage value and a second reading parameter to the integrated reading module to execute a second data reading operation. By integrating the reading steps and realizing parallel processing, the data reading efficiency of the storage device in the error processing process is remarkably improved.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a memory management method and a memory controller thereof. Background Art

[0002] In modern storage technology, rewritable non-volatile memory (NAND Flash) has been widely used in storage devices such as solid-state drives (SSDs). During the operation of the storage device, data reading errors may occur. At this time, an error handling mechanism is required to ensure the correct reading of data.

[0003] In the traditional error handling process, the firmware needs to perform special processing on the erroneous data. One important step is to adjust the read voltage of the NAND Flash to ensure that the correct data can be read. However, this process involves multiple steps, including setting the voltage value, checking whether the set voltage value is correct, reading the original data on the NAND Flash, and transmitting the data. These steps are not only cumbersome to operate, but also take a lot of time during execution, thus affecting the overall read and write performance of the storage device. Summary of the invention

[0004] The present disclosure provides a memory management method and a memory controller thereof to solve the technical problem that the error handling process in the prior art takes a long time.

[0005] One or more embodiments of the present invention provide a memory management method, which is applicable to a storage device equipped with a rewritable non-volatile memory module. The method includes: obtaining a first voltage value of a first data read operation corresponding to first data; setting the first voltage value and a first read parameter corresponding to the first data to an integrated read module, so as to perform the first data read operation via the integrated read module; while performing the first data read operation, obtaining a second voltage value of a second data read operation corresponding to second data in parallel; and in response to the completion of the first data read operation, setting the second voltage value and a second read parameter corresponding to the second data to the integrated read module, so as to perform the second data read operation via the integrated read module.

[0006] In one or more embodiments of the present invention, the first read parameter includes one or more of the following: a target physical address of the first data in the rewritable non-volatile memory module; a first data length of the first data; physical page size information of the first data; a read mode identifier of the first data; an error detection parameter of the first data; and metadata of the first data.

[0007] In one or more embodiments of the present invention, the method further includes: if the first data reading operation fails, obtaining another first voltage value for re-reading the first data, wherein the another first voltage value is different from the first voltage value; and setting the another first voltage value and the first reading parameter to the integrated reading module to re-execute the first data reading operation via the integrated reading module.

[0008] In one or more embodiments of the present invention, during the execution of the first data reading operation: if the first data reading operation fails, the execution of the second data reading operation is suspended until it is confirmed that the first data reading operation is successfully completed.

[0009] In one or more embodiments of the present invention, the method further includes: storing the first voltage value and the corresponding first reading result used each time the first data reading operation is performed; and determining an optimal voltage value for reading the first data based on the first voltage value and the first reading result.

[0010] In one or more embodiments of the present invention, determining the optimal voltage value includes: recording multiple first voltage values ​​and corresponding multiple first read error bit numbers; and using a specific first voltage value corresponding to the least first read error bit number as the optimal voltage value.

[0011] In one or more embodiments of the present invention, the integrated read module performs the first data read operation including: sending a read command sequence to the rewritable non-volatile memory module based on the first voltage value and the first read parameter; and obtaining the read first data from the rewritable non-volatile memory module.

[0012] In one or more embodiments of the present invention, the integrated read module includes: a parameter configuration module for storing the first voltage value and the first read parameter; a command generation module for generating a read command sequence for the rewritable non-volatile memory module according to the first voltage value and the first read parameter; an execution module for sending the read command sequence to the rewritable non-volatile memory module and receiving the first data read; and a status feedback module for storing execution status information of the first data read operation.

[0013] In one or more embodiments of the present invention, the rewritable non-volatile memory module includes multiple storage planes, each storage plane has a corresponding register group and command queue; and the integrated read module is configured to perform parallel parameter setting for the reading operation of the second data located in different storage planes when executing the first data reading operation.

[0014] In one or more embodiments of the present invention, the method further includes: determining whether the first data and the second data are located in different storage planes; and in response to the first data and the second data being located in different storage planes, triggering execution of the second data reading operation before the first data reading operation is completed.

[0015] One or more embodiments of the present invention provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to a connection interface circuit of the storage device to electrically connect to a host system. The processor is configured to: obtain a first voltage value of a first data read operation corresponding to first data; set the first voltage value and a first read parameter corresponding to the first data to an integrated read module to perform the first data read operation via the integrated read module; when the integrated read module performs the first data read operation, obtain a second voltage value of a second data read operation corresponding to second data in parallel; and in response to the completion of the first data read operation, set the second voltage value and a second read parameter corresponding to the second data to the integrated read module to perform the second data read operation via the integrated read module.

[0016] Based on the above, the memory management method provided by the present disclosure integrates multiple conventional reading steps into a unified interface, effectively reducing the time for the firmware to execute redundant codes. At the same time, by calculating the voltage value required for the next reading operation in parallel while executing the current data reading operation, the parallel processing of the data reading process is realized, and the data reading efficiency in the error handling process is optimized, thereby enhancing the working efficiency of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0018] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention;

[0019] Figure 2 is a flowchart of a memory management method according to an embodiment of the present disclosure;

[0020] Figure 3is a schematic diagram of an integrated reading module according to an embodiment of the present disclosure;

[0021] Figure 4 is a sequence diagram of a data reading operation between a processor, an integrated reading module and a rewritable non-volatile memory module according to an embodiment of the present disclosure;

[0022] Figure 5 is a timing diagram of multiple data reading operations according to an embodiment of the present disclosure;

[0023] Figure 6 is a timing diagram of multiple data reading operations according to another embodiment of the present disclosure;

[0024] Figure 7 FIG. 4 is a timing diagram of multiple data reading operations according to yet another embodiment of the present disclosure.

[0025] Description of Figure Numbers

[0026] 10: Host system

[0027] 20: Storage device

[0028] 110: processor (second processor)

[0029] 120: Host memory

[0030] 130: Data transmission interface circuit

[0031] 210: Memory Controller

[0032] 211: Processor (first processor)

[0033] 212: Data management circuit

[0034] 213: Memory interface control circuit

[0035] 214: Buffer memory

[0036] 220: Rewritable non-volatile memory module

[0037] 230: Connecting interface circuit

[0038] S210-S240: Step 300: Integrate the reading module

[0039] 310: Parameter configuration module

[0040] 320: Command generation module

[0041] 330: Execution module

[0042] 340: Status feedback module

[0043] S401-S406, S410-S413, S420-S423: Steps

[0044] A41: Arrow

[0045] CV1, CV1.1: Steps to obtain the first read voltage

[0046] SR1, SR1.1: Steps to set up the first read operation

[0047] TR1, TR1.1: Execute the first read operation

[0048] CV2: Step to obtain the second read voltage

[0049] SR2: Steps to set up the second read operation

[0050] TR2: Perform the second read operation

[0051] CV3: Step to obtain the third read voltage

[0052] SR3: Steps to set up the third read operation

[0053] TR3: Execute the third read operation

[0054] T1, T2, T3: time points

[0055] TR1.2: Perform another first read operation

[0056] CV1.2: Steps to obtain another first read voltage

[0057] SR1.2: Steps for setting up another first read operation

[0058] CV1.2: Step of obtaining another first read voltage in advance

[0059] TR2: Perform the second read operation DETAILED DESCRIPTION

[0060] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0061] Figure 1 FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention. Figure 1, the host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In the present embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In the present embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0062] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0063] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0064] In this embodiment, the number of the data transmission interface circuit 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless manner. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device or a low power consumption Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.

[0065] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use the fast non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol to transmit data.

[0066] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0067] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0068] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10 .

[0069] In more detail, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the storage device 20 operates, these control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in this embodiment, the control instructions / program codes can be further executed to perform data reading operations to implement the memory management method for the error handling program provided by the present invention. The control instructions / program codes corresponding to the memory management method can also be implemented as a circuit unit in the form of hardware to implement the memory management method provided by the present invention.

[0070] It is worth mentioning that in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present invention is not limited thereto.

[0071] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0072] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., the write operation is performed according to the write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more storage units in the one or more physical units), and the read data is written to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., the read operation is performed according to the read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0073] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also called programming) operation, a read operation or an erase operation on the rewritable non-volatile memory module 220 .

[0074] In addition, the data to be written to the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will transmit a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in the read instruction sequence, information such as the read identification code, memory address, and physical address will be included.

[0075] In addition, the memory controller 210 establishes a logical to physical address mapping table (Logical To Physical address mapping table) and a physical to logical address mapping table (Physical To Logical address mapping table) to record the mapping relationship between the logical address of the logical unit (e.g., logical block, logical page) configured for the rewritable non-volatile memory module 220 and the physical address (physical address) of the physical unit (e.g., physical erase unit / physical block, physical page). In other words, the memory controller 210 can search for the physical unit mapped by a logical unit (e.g., search for the physical page mapped by a logical page; search for the physical address mapped by a logical address) through the logical to physical address mapping table (also called the logical to physical mapping table), and the memory controller 210 can search for the logical unit mapped by a physical unit (e.g., search for the logical page mapped by a physical page; search for the logical address mapped by a physical address) through the physical to logical address mapping table (also called the physical to logical mapping table).

[0076] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data for managing the storage device 20 (e.g., various mapping tables, voltage adjustment level lists, read voltage lists, read results), so that the processor 211 can quickly access the data, instructions or system data from the buffer memory 216.

[0077] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213 ) and is used to store user data sent by the host system 10 .

[0078] In the present embodiment, each memory grain (chip) of the multiple memory grains of the rewritable non-volatile memory module 220 has multiple planes, and each plane has multiple physical blocks. Each physical block includes multiple physical programming units (also called physical pages). Each physical page has multiple storage cells (also called physical bytes or bytes), and each storage cell corresponds to a physical address. The physical address is used to record the physical location of the data stored in the storage cell. It should be noted that the present invention is not limited to the size of each physical page and logical page. The size of each byte is 8 bits, which is used to store data of 8 bit values.

[0079] Figure 2The present invention is a flowchart of a memory management method according to an embodiment of the present invention.

[0080] In one embodiment, please refer to Figure 2 In step S210 , the memory controller 210 obtains a first voltage value corresponding to a first data read operation of first data.

[0081] Specifically, when the storage device 20 needs to read data, the memory controller 210 first determines a first voltage value required for reading the first data. The first voltage value can be obtained by algorithm calculation to ensure that data is correctly read from the rewritable non-volatile memory module 220.

[0082] Next, in step S220 , the memory controller 210 sets the first voltage value and a first read parameter corresponding to the first data to an integrated read module, so as to perform the first data read operation on the rewritable non-volatile memory module 220 via the integrated read module.

[0083] Among them, the first read parameter may include the target physical address of the first data in the rewritable non-volatile memory module 220, the first data length of the first data, the physical page size information of the first data, the read mode identifier of the first data, the error detection parameters of the first data and the metadata of the first data.

[0084] In one embodiment, the memory controller 210 may flexibly configure specific content of the first reading parameter according to different application scenarios and reading requirements.

[0085] Specifically, the target physical address is used to accurately locate the storage location of the first data in the rewritable non-volatile memory module 220, ensuring that the read operation can access the correct data area. The first data length parameter indicates the amount of data to be read, so that the memory controller 210 can accurately allocate the cache space required for the read operation. The physical page size information reflects the physical storage characteristics of the rewritable non-volatile memory module 220, which helps the memory controller 210 optimize the data reading strategy. The read mode identifier is used to indicate the specific mode of the current read operation, such as whether error checking is required or whether it is a continuous read mode. The error detection parameter contains verification information for ensuring data integrity, so that the memory controller 210 can promptly detect and handle possible data errors. In addition, the metadata may also contain auxiliary information such as the timestamp and access rights of the data, which has corresponding effects on various data management and read control.

[0086] Next, in step S230 , when the integrated read module performs the first data read operation, the memory controller 210 concurrently obtains a second voltage value of a second data read operation corresponding to second data.

[0087] Thus, through this parallel processing mechanism, the memory controller 210 starts preparing the voltage value required for the next read operation while executing the current read operation, thereby improving the data read efficiency.

[0088] In one embodiment, the memory controller 210 triggers the integrated read module to perform the first data read operation based on a variety of conditions. For example, when the host system 10 sends a read request, the memory controller 210 checks the priority and urgency of the request. If it is a high priority request, the memory controller 210 will immediately trigger the integrated read module to perform the read operation. In addition, when the memory controller 210 detects that the data in the rewritable non-volatile memory module 220 may have a bit flip risk, it will also actively trigger the read operation to ensure the integrity of the data. Alternatively, when performing maintenance tasks such as data verification, the memory controller 210 may also need to trigger the integrated read module to perform a read operation. It is worth mentioning that after receiving the trigger signal, the integrated read module will first verify whether the set parameters are valid to ensure that the read operation can proceed normally.

[0089] Then, in step S240, in response to the completion of the first data read operation, the memory controller 210 sets the second voltage value and the second read parameter corresponding to the second data to the integrated read module to perform the second data read operation on the rewritable non-volatile memory module 220 via the integrated read module.

[0090] It is worth mentioning that in this embodiment, the memory controller 210 integrates the conventional multiple reading steps into a unified interface and adopts a parallel processing mechanism, which significantly reduces the time for the firmware to execute redundant codes. In addition, since the necessary parameters of the second data reading operation are ready during the execution of the first data reading operation, the second data reading operation can be started immediately after the first data reading operation is completed, further optimizing the overall reading process.

[0091] In addition, in a specific implementation of this embodiment, the memory controller 210 may determine whether to continue to execute the second data read operation by monitoring the execution status of the first data read operation. If the first data read operation fails, the memory controller 210 may need to re-execute the first data read operation using a different voltage value, and the execution of the second data read operation may be suspended at this time.

[0092] In one embodiment, when the memory controller 210 performs a read operation through the integrated read module, it monitors the execution status of each operation in real time. If it is detected that the first data read operation fails, the memory controller 210 immediately activates a data recovery mechanism.

[0093] Specifically, the memory controller 210 first obtains another first voltage value for re-reading the first data according to a preset voltage adjustment algorithm. This other first voltage value is different from the first voltage value used previously, and is usually appropriately adjusted according to the failure cause to increase the possibility of successful reading.

[0094] In more detail, after obtaining another first voltage value, the memory controller 210 sets the voltage value together with the original first read parameters to the integrated read module. These first read parameters including information such as the target physical address remain unchanged because the read target is still the same first data. Subsequently, the memory controller 210 re-executes the first data read operation through the integrated read module.

[0095] It is worth mentioning that in one embodiment, during the re-reading process, the memory controller 210 will simultaneously manage the execution status of the second data read operation. Since the failure of the first data read operation may indicate a potential data integrity problem, the memory controller 210 will suspend the execution of the second data read operation.

[0096] Thus, through the above-mentioned pause mechanism, the storage controller continues to execute the second data reading operation until it confirms that the first data reading operation is successfully completed, so as to ensure the reliability and accuracy of data reading. Only after confirming that the first data has been successfully read, the memory controller 210 will resume executing the second data reading operation. This strategy can not only effectively prevent the spread of errors, but also ensure the orderly progress of data reading operations.

[0097] In some embodiments, the memory controller 210 may set a maximum number of retries to avoid falling into an infinite retry loop in certain extreme cases. In addition, the voltage value used during each retry may follow a specific adjustment mode, such as gradually increasing or decreasing, to improve the retry efficiency.

[0098] Figure 3 is a schematic diagram of an integrated reading module according to an embodiment of the present disclosure.

[0099] In one embodiment, please refer to Figure 3 The integrated read module 300 is configured to execute the data read instruction issued by the memory controller 210. The integrated read module 300 includes a parameter configuration module 310, a command generation module 320, an execution module 330 and a status feedback module 340.

[0100] Specifically, in one embodiment, the parameter configuration module 310 is used to store various read parameters received from the memory controller 210. These parameters include a first voltage value and a first read parameter, wherein the first read parameter may include a target physical address, data length, physical page size information, a read mode identifier, an error detection parameter, and metadata, etc. The parameter configuration module 310 manages and stores these parameters in a unified manner, and provides necessary configuration information for subsequent read operations.

[0101] In one embodiment, the command generation module 320 generates a read command sequence for the rewritable non-volatile memory module 220 according to the parameter information stored in the parameter configuration module 310. These command sequences include complete read operation instructions, such as a command to set a read voltage value, a command to perform data reading, and a command for data transmission. The command generation module 320 ensures that the generated command sequence meets the communication protocol requirements of the rewritable non-volatile memory module 220.

[0102] In one embodiment, the execution module 330 is responsible for sending the read command sequence generated by the command generation module 320 to the rewritable non-volatile memory module 220, and receiving the data returned from the rewritable non-volatile memory module 220. The execution module 330 manages the entire data transmission process to ensure the correct execution of the command and the reliable transmission of the data.

[0103] In one embodiment, the status feedback module 340 is used to store the execution status information of the read operation, including whether the operation is successfully completed, whether an error occurs, etc. Such status information will be fed back to the memory controller 210 in a timely manner, so that the memory controller 210 can understand the execution status of the read operation in a timely manner and take corresponding processing measures when necessary.

[0104] In another embodiment, the memory controller 210 may take corresponding processing measures according to the different execution states fed back by the state feedback module 340. Specifically, when the state feedback module 340 feeds back that the first data read operation fails, the memory controller 210 may take the following processing measures: First, the memory controller 210 analyzes the cause of the failure, for example, checking whether the data read error is caused by an inappropriate read voltage value. If it is confirmed that the problem is the voltage value, the memory controller 210 selects another voltage value from the voltage adjustment gear list in the buffer memory 214, and re-executes the read operation through the integrated read module 300.

[0105] In more detail, if the status feedback module 340 reports that multiple consecutive reads using different voltage values ​​have failed, the memory controller 210 may initiate a more complex error recovery mechanism. For example, the memory controller 210 may record all the attempted voltage values ​​and their corresponding read results, and analyze these data to find the best read voltage value. At the same time, the memory controller 210 may also update the voltage adjustment gear list in the buffer memory 214, adding the newly discovered valid voltage value to the list to optimize future read operations.

[0106] In addition, when the status feedback module 340 reports that a certain storage area frequently has read errors, the memory controller 210 may record this information in the buffer memory 214 for evaluating the reliability (e.g., error frequency) of the storage area. If the error frequency exceeds a preset threshold, the memory controller 210 may actively initiate a data migration operation to transfer the data stored in the area to a more reliable storage area, thereby preventing possible data loss.

[0107] It is worth mentioning that the memory controller 210 also optimizes the parallel processing strategy according to the report of the status feedback module 340. For example, when it is found that certain specific types of read errors occur regularly, the memory controller 210 may adjust the scheduling strategy of the parallel read operation to avoid executing parallel operations in these error-prone situations, thereby improving the overall read reliability.

[0108] It is worth mentioning that the modular design of the integrated read module 300 not only improves the maintainability of the code, but also realizes the standardized processing of the read operation. By integrating multiple read steps into a unified interface, the operation process of the memory controller 210 is simplified, and the efficiency of data reading is improved. In addition, this design also supports a parallel processing mechanism, allowing the parameters of the next read operation to be prepared while the current read operation is being executed.

[0109] In some embodiments, the submodules of the integrated reading module 300 communicate with each other through standardized internal interfaces, and this design makes it easier to upgrade and maintain the modules. For example, when it is necessary to support a new reading mode or optimize a specific type of reading operation, only the corresponding submodule needs to be modified without affecting the normal operation of other modules.

[0110] In another embodiment, the integrated read module 300 achieves efficient data read operations by working in coordination with various components of the storage device 20 .

[0111] Specifically, after receiving the read instruction from the memory controller 210, the parameter configuration module 310 will obtain the required parameters from the buffer memory 214. For example, when a data read operation with error handling needs to be performed, the parameter configuration module 310 first reads the voltage adjustment gear list from the buffer memory 214 to determine the appropriate read voltage value. At the same time, the parameter configuration module 310 will also obtain the physical address information of the target data through the logic-to-physical address mapping table of the memory controller 210, thereby ensuring accurate positioning of the data to be read.

[0112] In some embodiments, the command generation module 320 generates a command sequence that complies with the communication protocol of the rewritable non-volatile memory module 220 according to the information provided by the parameter configuration module 310 and in cooperation with the memory interface control circuit 213. For example, when the read voltage value needs to be adjusted, the command generation module 320 generates a complete sequence including a voltage setting command, a voltage verification command, and a data reading command. These command sequences are formatted via the memory interface control circuit 213 to ensure that the rewritable non-volatile memory module 220 can correctly identify and execute them.

[0113] In some embodiments, during the data transmission phase, the execution module 330 coordinates the data transmission process through the data management circuit 212. After the execution module 330 sends a read command sequence, the data management circuit 212 is responsible for managing the flow of data read from the rewritable non-volatile memory module 220. For example, during the error handling process, if the same data needs to be read multiple times using different voltage values, the execution module 330 will cooperate with the data management circuit 212 to temporarily store the data read each time in the buffer memory 214 for subsequent data comparison and analysis.

[0114] In some embodiments, the state feedback module 340 maintains real-time state communication with the processor 211. When the execution module 330 completes a read operation, the state feedback module 340 will record the execution result in the read result list of the buffer memory 214. By checking these state information, the processor 211 can timely determine whether the read operation needs to adjust the voltage value and re-execute. For example, if the state feedback module 340 reports that the read operation fails, the processor 211 will immediately obtain a new voltage value from the buffer memory 214 and start a new round of read operations through the parameter configuration module 310.

[0115] It is worth mentioning that this modular design allows the integrated reading module 300 to fully utilize the functions of each component of the storage device 20, and simplifies the operation process through a unified interface. For example, when processing an error handling request, the processor 211 only needs to send a read instruction to the integrated reading module 300, and subsequent complex operations such as parameter acquisition, command generation, and data transmission will be completed by the various sub-modules of the integrated reading module 300, which greatly reduces the burden on the processor 211.

[0116] Figure 4 It is a sequence diagram of a data reading operation between a processor, an integrated reading module and a rewritable non-volatile memory module according to an embodiment of the present disclosure.

[0117] In one embodiment, please refer to Figure 4 , which shows the interaction timing between the processor 211, the integrated reading module 300 and the rewritable non-volatile memory module 220 when performing a data reading operation.

[0118] Specifically, in step S401, the processor 211 first obtains a first voltage value of a first data read operation. Next, in step S402, the processor 211 sets the first voltage value and the first read parameter to the integrated read module 300 to perform the first data read operation (S410). While performing the first data read operation, the processor 211 obtains a second voltage value of a second data read operation in parallel in step S403, which embodies the parallel processing mechanism of the present disclosure.

[0119] In another embodiment, the processor 211 uses a specific processing mechanism to optimize the data reading operation when executing steps S402 and S403. Specifically, in step S402, the processor 211 first obtains the configuration information of the first reading parameter from the buffer memory 214. These configuration information include the target physical address of the first data in the rewritable non-volatile memory module 220, the length of the first data, page size information, read mode identification, error detection parameters, and metadata. The processor 211 transmits these parameters together with the obtained first voltage value to the parameter configuration module 310 of the integrated reading module 300 for unified configuration. At the same time, the processor 211 will mark the status of these parameters in the buffer memory 214 to track the execution of the read operation later.

[0120] When executing step S403, the processor 211 will immediately start the calculation process of the second voltage value without waiting for the first data reading operation to be completed. More specifically, the processor 211 will determine the appropriate voltage value for the second data reading operation based on the preset voltage adjustment algorithm and the voltage adjustment gear list stored in the buffer memory 214. This parallel processing mechanism enables the processor 211 to make full use of the execution time of the first data reading operation and prepare the key parameters (such as the second voltage value) required for the second data reading operation in advance.

[0121] Next, after receiving the setting of the processor 211, the integrated read module 300 triggers and executes the first data read operation S410. Then in step S411, the integrated read module 300 generates and sends a first read command sequence to the rewritable non-volatile memory module 220. The rewritable non-volatile memory module 220 performs the corresponding read operation and returns the first data in step S412. After receiving the data, the integrated read module 300 transmits the first data to the processor 211 in step S413.

[0122] In another embodiment, when the integrated reading module 300 executes steps S411 to S413, the data reading operation is completed through the collaborative work of various functional modules within it. Specifically, in step S411, the command generation module 320 first generates a complete first read command sequence according to the first voltage value and the first read parameter stored in the parameter configuration module 310. This command sequence includes multiple specific operation instructions such as a command to set the voltage value, a command to verify the voltage value, and a command to read data. Subsequently, the execution module 330 sends these command sequences to the rewritable non-volatile memory module 220 according to a specific timing sequence. In step S412, when the rewritable non-volatile memory module 220 completes the data reading, the execution module 330 is responsible for receiving the returned first data. The execution module 330 will perform a preliminary integrity verification on the received data to ensure that no errors occur during the data transmission process. At the same time, the state feedback module 340 will record the state information of data reception in real time for reference by the processor 211.

[0123] In step S413, the execution module 330 transmits the verified first data to the processor 211, and the status feedback module 340 generates a detailed operation status report, including the complete execution of the read operation, the data transmission status, and any abnormal conditions that may occur. This information is transmitted to the processor 211 so that it can timely understand the execution result of the read operation and decide on subsequent operations.

[0124] In another embodiment, the execution module 330 verifies the first data at multiple levels. Specifically, the execution module 330 first checks the integrity of the data, and ensures that the data is not damaged or lost during transmission through mechanisms such as checksums. In addition, the execution module 330 also verifies whether the format of the data meets expectations, including whether the data length is correct and whether the data structure is complete. If any abnormality is found, the execution module 330 immediately reports the error status to the processor 211 through the status feedback module 340.

[0125] Next, in step S404 , the processor 211 determines whether the first data reading operation is successfully completed.

[0126] If the first data read operation is successfully completed, the processor 211 sets the second voltage value and the second read parameter to the integrated read module 300 in step S405 to perform the second data read operation. The integrated read module 300 then starts the second data read operation in step S420, and generates and sends a second read command sequence to the rewritable non-volatile memory module 220 in step S421. After performing the read operation, the rewritable non-volatile memory module 220 returns the second data in step S422, and the integrated read module 300 transmits the second data to the processor 211 in step S423. Finally, in step S406, the processor 211 determines whether the second data read operation is successfully completed.

[0127] In another embodiment, the memory controller 210 implements a complete voltage value optimization mechanism. Specifically, when the memory controller 210 performs multiple read operations on the first data, the processor 211 stores the first voltage value used each time and its corresponding read results in the buffer memory 214. These read results contain detailed data correctness information, such as the number of error bits detected in each read operation.

[0128] In more detail, the processor 211 will establish a voltage value performance table to record each first voltage value tried and its corresponding number of read error bits. For example, when the voltage value V1 is used, 50 error bits may be detected, when the voltage value V2 is used, 30 error bits may be detected, and when the voltage value V3 is used, 20 error bits may be detected. The processor 211 analyzes these data and determines the voltage value that produces the least number of error bits as the optimal voltage value.

[0129] In practical applications, the processor 211 may perform multiple rounds of testing to ensure the reliability of the results. For example, multiple read operations may be performed for each voltage value to reduce the impact of accidental factors by taking the average number of error bits. In addition, the processor 211 will also store the determined optimal voltage value in the buffer memory 214 to form a voltage optimization database. This database not only records the specific voltage value, but also contains the corresponding usage scenario information, such as the storage area where the data is located, the temperature conditions during reading, etc., to provide a reference for subsequent read operations.

[0130] It is worth mentioning that the memory controller 210 will also consider the stability of the read operation when determining the optimal voltage value. Specifically, if a voltage value generates the least number of error bits in a certain read, but the results of multiple tests fluctuate greatly, the processor 211 may select a voltage value with more overall stability as the optimal voltage value. This strategy ensures that the read operation can maintain high reliability under different conditions.

[0131] In some embodiments, the processor 211 may periodically update the voltage optimization database to adapt to performance changes of the storage device during use. For example, when it is found that the optimal voltage value of a storage area begins to deviate from the historical record, a new round of voltage value optimization process may be triggered.

[0132] In some embodiments, the processor 211 may dynamically adjust the parameters of the second data read operation according to the execution state of the first data read operation. For example, if it is found that the first data read operation has a higher success rate at a certain voltage value, the processor 211 may adjust the second voltage value accordingly to improve the success rate of the second data read operation.

[0133] In another embodiment, please refer to Figure 4 As shown by arrow A41, the processor 211 further performs an iterative data reading process. Specifically, when the processor 211 determines in step S404 that the first data reading operation is not successfully completed, the processor 211 will start the iterative reading mechanism. In this case, the processor 211 will re-execute step S401 to obtain another first voltage value, and set the voltage value and the first reading parameter to the integrated reading module 300 again through step S402 to try to re-read the first data. This iterative process may continue until the first data is successfully read or the preset retry limit is reached.

[0134] In more detail, the processor 211 may select another first voltage value based on different strategies. For example, the processor 211 may calculate a new voltage value by a preset voltage adjustment algorithm according to the result of the previous read operation. Alternatively, the processor 211 may select the next voltage value to be tried from the voltage value sequence pre-stored in the buffer memory 214. This iterative reading mechanism ensures that in the case of a first read failure, there is still a chance to successfully read the data by adjusting the voltage value.

[0135] However, in another embodiment, even if the first data read operation has been successfully completed, under certain conditions, the processor 211 may continue to perform additional read operations. For example, when the processor 211 detects that the number of error bits in the current read result is close to the acceptable upper limit, even if the data can be successfully corrected, the processor 211 may choose to use another voltage value to perform additional read attempts in order to obtain a better read result. This optimization mechanism is particularly suitable for application scenarios with high data reliability requirements.

[0136] It is worth mentioning that when performing these additional read operations, the processor 211 will weigh the relationship between the improvement in read quality and the time overhead. For example, if the number of error bits in the current read result is already low, or the system is under high load, the processor 211 may choose to skip the additional read attempt and directly perform the next data read operation. This flexible strategy enables the memory controller 210 to achieve a good balance between read performance and data reliability.

[0137] Figure 5 FIG. 4 is a timing diagram of multiple data reading operations according to an embodiment of the present disclosure.

[0138] In one embodiment, please refer to Figure 5 , which shows the timing flow of the memory controller 210 performing multiple data read operations.

[0139] For example, at time point T1, the memory controller 210 first executes step CV1 corresponding to the first data: obtaining a first read voltage (also called a first voltage value). Subsequently, in step SR1, a first read operation corresponding to the first data is set based on the first read voltage. Next, the memory controller 210 triggers and executes the first read operation TR1. It is worth noting that during the execution of the first read operation TR1, the memory controller 210 begins to execute step CV2 of obtaining a second read voltage (also called a second voltage value) corresponding to the second data, and sets a second read operation corresponding to the second data based on the second read voltage in step SR2, which embodies the parallel processing mechanism of the present disclosure.

[0140] In more detail, when the time point T2 is reached, the first read operation TR1 is completed, and the memory controller 210 immediately triggers and executes the second read operation TR2. At the same time, the memory controller 210 executes step CV3 of obtaining a third read voltage (also called a third voltage value) corresponding to the third data, and sets a third read operation corresponding to the third data based on the third read voltage in step SR3. This design ensures that at any time, the subsequent read operation can be executed in succession to the previous read operation (because the corresponding necessary parameters are ready).

[0141] When the second read operation TR2 is completed at time point T3, the memory controller 210 immediately triggers and executes the third read operation TR3. This continuous operation mode presents a pipelined data reading process, in which the preparation and execution of each read operation form an efficient overlapping execution mode.

[0142] It is worth mentioning that Figure 5 The timing arrangement in FIG. 1 shows an ideal situation, that is, each read operation can be successfully completed. This parallel processing mechanism significantly improves the data reading efficiency because the voltage value and related parameters required for the next read operation can always be prepared before the current read operation is completed. For example, during the time period from T1 to T2, the memory controller 210 performs the first read operation TR1 while completing steps CV2 and SR2, thereby ensuring that the second read operation TR2 can be immediately started at time T2.

[0143] However, in the case where the previous read operation is not successfully completed, the memory management method provided by the present disclosure will also have a corresponding execution process, see Figure 6 , Figure 7 Description of the corresponding embodiments.

[0144] Figure 6 FIG. 4 is a timing diagram of multiple data reading operations according to another embodiment of the present disclosure.

[0145] In another embodiment, please refer to Figure 6 , which shows the processing flow when the first data read operation fails. In this case, the memory controller 210 will take specific measures to ensure reliable reading of data.

[0146] For example, at time point T1, the memory controller 210 first executes the step of obtaining the first read voltage (such as step CV1.1), and then sets the first read operation based on the first read voltage in step SR1.1. Then, the memory controller 210 triggers and executes another first read operation TR1.1. It is worth noting that during the execution of another first read operation TR1.1, the memory controller 210 starts to execute the step CV2 of obtaining the second read voltage, and sets the second read operation based on the second read voltage in step SR2, which reflects the parallel processing mechanism of the present disclosure.

[0147] Next, at time point T2, after another first read operation TR1.1 is completed, the memory controller 210 detects that the operation has not been successfully completed. In this case, although the memory controller 210 has prepared for the second data read operation through steps CV2 and SR2, the memory controller 210 will give priority to the first data read problem. Therefore, the memory controller 210 will immediately execute the step CV1.2 of obtaining another first read voltage, and set another first read operation based on the another first read voltage in step SR1.2.

[0148] This priority processing mechanism is reflected in that the memory controller 210 temporarily puts aside the originally planned second data read operation and instead performs another read attempt TR1.2 for the first data. This design ensures that a new read operation will not be hastily started before the current data read problem is resolved. It is worth noting that although the preparation work (CV2 and SR2) for the second data read operation has been completed, its execution will be postponed until it is confirmed that the first data can be successfully read.

[0149] In addition, at time point T3, the memory controller 210 will determine the subsequent operation according to the execution result of TR1.2. If another first read operation TR1.2 still fails, the memory controller 210 may continue to try a new voltage value; and if TR1.2 is successfully completed, the second data read operation TR2 prepared previously may be started.

[0150] It is worth mentioning that Figure 6 The timing arrangement in reflects the flexibility and reliability of the present disclosure in handling read failures. By timely adjusting the read strategy and ensuring that the current data read problem is solved, the memory controller 210 can maintain the efficiency of the read operation as much as possible while ensuring data reliability. This mechanism is particularly suitable for application scenarios with high requirements for data integrity, such as data recovery operations during error handling.

[0151] Figure 7FIG. 4 is a timing diagram of multiple data reading operations according to yet another embodiment of the present disclosure.

[0152] In another embodiment, please refer to Figure 7 , which shows the data reading process using the preventive preparation mechanism of the memory controller 210. This embodiment particularly emphasizes that during the execution of the first data reading operation, another set of reading parameters that may be required are prepared in advance, thereby further optimizing the time efficiency of the reading operation.

[0153] Specifically, at time point T1, the memory controller 210 first performs a step CV1.1 of acquiring a first read voltage, and sets a first read operation based on the voltage in step SR1.1. Subsequently, during the execution of another first read operation TR1.1, the memory controller 210 not only performs a step CV2 of acquiring a second read voltage and a corresponding setting step SR2, but also preliminarily performs a step CV1.2 of acquiring another first read voltage and a corresponding setting step SR1.2.

[0154] In more detail, the advantage of this preventive preparation mechanism is that when reaching the time point T2, if another first read operation TR1.1 fails to execute, the memory controller 210 can immediately use another set of first read parameters that have been prepared to execute another first data read operation TR1.2 without requiring additional parameter preparation time. Figure 6 Compared with the embodiment shown in FIG. 1 , this preventive preparation mechanism further reduces the response time in the case of a read failure. Figure 7 In the example, it can be seen that each read operation can be executed continuously and closely.

[0155] At time point T3, if another first read operation TR1.2 is successfully completed, the memory controller 210 can directly start executing the second data read operation TR2 that has been prepared. This mechanism ensures that even if multiple attempts to read the first data are required, subsequent read operations can be started in time, thereby maintaining overall read efficiency.

[0156] It is worth mentioning that this preventive preparation mechanism is particularly suitable for error handling scenarios. Since different read voltages may need to be tried multiple times during error handling, preparing the next set of parameters that may need to be used in advance can significantly reduce the delay time between each retry. This solution not only improves the response speed of a single read operation, but also improves the overall data reading efficiency.

[0157] In some embodiments, the memory controller 210 may optimize the parameter selection for preventive preparation based on historical data and error pattern analysis. For example, if historical data shows that certain voltage value combinations are more likely to result in successful reads, the memory controller 210 may prioritize the parameters corresponding to these voltage values.

[0158] In another embodiment, the memory controller 210 (e.g., the integrated read module 300) improves the data read efficiency by properly utilizing the multi-plane structure of the rewritable non-volatile memory module 220. Specifically, the rewritable non-volatile memory module 220 includes multiple memory planes, each of which is equipped with an independent register set and command queue.

[0159] Specifically, when multiple data need to be read, the integrated read module 300 will first check the physical location distribution of these data in the rewritable non-volatile memory module 220. For example, when the integrated read module 300 is ready to perform a first data read operation, it will simultaneously query the storage location information of the second data. If it is confirmed that the first data and the second data are located in different storage planes, the memory controller 210 can make full use of the relevant processing resources (such as register groups and command queues) of each storage plane to optimize the reading process.

[0160] More specifically, in one embodiment, such parallel parameter setting includes, for example:

[0161] (1) Register group configuration: The integrated read module 300 can simultaneously write the required parameters to the register groups of different storage planes. For example, when the first data read operation is using the register group of the first storage plane, the integrated read module 300 can concurrently write the voltage value, address information and other parameters of the second data read operation into the register group of the second storage plane.

[0162] (2) Command queue management: The integrated read module 300 can load the command sequence of the second data read operation into the command queue of the second storage plane in advance without interfering with the command queue currently being executed by the first storage plane. These command sequences include, for example: a command to set a read voltage value, a command to set a target address, a command to preload a data buffer, and a command to trigger a read operation.

[0163] (3) Resource allocation: The integrated read module 300 allocates independent system resources for the parallel operations of different storage planes, including, for example, respective data buffer spaces, independent status monitoring registers, separate data transmission channels, and dedicated error detection resources.

[0164] For example, after confirming that the multiple data to be read are distributed in different planes, the integrated read module 300 can adopt a further parallel processing strategy. When the first data read operation is being executed, the integrated read module 300 will simultaneously set parameters for the second data read operation. Since different storage planes have independent register groups and command queues, this parallel parameter setting will not interfere with the ongoing first data read operation. For example, when the first data read operation is using the hardware resources of the first storage plane, the integrated read module 300 can simultaneously use the register group of the second storage plane to prepare the read parameters of the second data.

[0165] It is worth mentioning that the independent hardware resources of different storage planes ensure that the two read operations will not interfere with each other. If the memory controller 210 determines that the second data is located in a storage plane different from the first data, then the second data read operation can be triggered even before the first data read operation is completed. For example, during the operation of the first data read operation and after obtaining the second voltage corresponding to the second data read operation, the second data read operation can be directly executed without waiting for the completion of the first data read operation, thereby realizing parallel reading operations and significantly improving the overall reading efficiency. Assuming that another first voltage is also obtained during the execution of the second data read operation, when the first data read operation is completed, another first data read operation can also be directly performed based on the other first voltage using the hardware resources of the first storage plane.

[0166] In addition, the memory controller 210 also dynamically manages the resource usage of each storage plane. When it is detected that a read operation is about to be completed, the memory controller 210 will plan the next read operation to use the storage plane in advance to ensure that the hardware resources of the storage plane are fully utilized. This dynamic scheduling mechanism based on the storage plane not only improves the overall reading efficiency, but also improves the utilization of hardware resources.

[0167] In actual applications, the memory controller 210 may maintain a storage plane status table to record the usage status of each storage plane, queue length and other information in real time, so as to better schedule the read operation. In addition, according to factors such as the reading frequency and importance of the data, the frequently accessed data may be allocated to different storage planes when the data is written, so as to create a more efficient operation for subsequent parallel reading.

[0168] This embodiment also provides a computer program product, including a computer readable code, or a non-volatile computer readable storage medium carrying the computer readable code, when the computer readable code is executed in a processor, the processor executes the steps of the above storage device testing method. The computer program product can be implemented in hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium, and in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0169] Based on the above, the memory management method and memory controller provided by one or more embodiments of the present disclosure improve the data reading efficiency by using an innovative integrated reading module and a corresponding parallel processing mechanism, especially for the reading operation in the error handling program. Specifically, the present disclosure effectively reduces the time overhead required for simple serial processing by overlapping the execution process of the first data reading operation with the parameter preparation process of the second data reading operation. In addition, the present disclosure uses an integrated reading module to encapsulate multiple conventional reading steps into a unified interface, which simplifies the operation process of the processor 211 and improves the maintainability of the code.

[0170] Furthermore, the present disclosure also provides a flexible error handling mechanism. When the first data read operation fails, the system can quickly switch to another set of pre-prepared read parameters, greatly reducing the response time of the retry process. At the same time, the present disclosure makes full use of the multi-plane architecture of the rewritable non-volatile memory module, and by determining the storage plane where the data is located, it realizes true parallel data reading under appropriate conditions, further improving the overall performance.

[0171] It is particularly worth mentioning that the present disclosure coordinates the operation of various functional units by integrating the reading module, while ensuring the reliability of data reading, maximizing the performance of the hardware resources of the storage device and reducing the processing burden of the processor itself. This design not only improves the data reading speed during error handling, but also provides a new technical idea for the performance integration and optimization of storage devices, which has important practical value.

[0172] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, applicable to a storage device equipped with a rewritable non-volatile memory module, characterized in that: The method comprises: Acquire a first voltage value corresponding to a first data read operation of first data; Setting the first voltage value and a first reading parameter corresponding to the first data to an integrated reading module, so as to perform the first data reading operation via the integrated reading module; While executing the first data reading operation, acquiring in parallel a second voltage value of a second data reading operation corresponding to second data; and In response to the completion of the first data read operation, the second voltage value and a second read parameter corresponding to the second data are set to the integrated read module, so as to perform the second data read operation via the integrated read module.

2. The memory management method according to claim 1, characterized in that: The first reading parameter includes one or more of the following: a target physical address of the first data in the rewritable non-volatile memory module; a first data length of the first data; Physical page size information of the first data; a read mode identifier of the first data; an error detection parameter of the first data; as well as The metadata of the first data.

3. The memory management method according to claim 1, characterized in that: The method further comprises: If the first data reading operation fails, acquiring another first voltage value for re-reading the first data, wherein the another first voltage value is different from the first voltage value; and The another first voltage value and the first read parameter are set to the integrated read module to re-execute the first data read operation via the integrated read module.

4. The memory management method according to claim 1 or 3, characterized in that: During the execution of the first data reading operation: If the first data reading operation fails, the second data reading operation is suspended until it is confirmed that the first data reading operation is successfully completed.

5. The memory management method according to claim 1, characterized in that: The method further comprises: storing the first voltage value and the corresponding first reading result used in each execution of the first data reading operation; and An optimal voltage value for reading the first data is determined based on the first voltage value and the first reading result.

6. The memory management method according to claim 5, characterized in that: Determining the optimal voltage value includes: Recording a plurality of first voltage values ​​and a plurality of corresponding first read error bit numbers; and A specific first voltage value corresponding to the minimum first read error bit number is used as the optimal voltage value.

7. The memory management method according to claim 1, characterized in that: The integrated reading module performs the first data reading operation including: Based on the first voltage value and the first read parameter, sending a read command sequence to the rewritable non-volatile memory module; and The read first data is obtained from the rewritable non-volatile memory module.

8. The memory management method according to claim 1, characterized in that: The integrated reading module comprises: A parameter configuration module, used for storing the first voltage value and the first read parameter; A command generation module, used for generating a read command sequence for the rewritable non-volatile memory module according to the first voltage value and the first read parameter; an execution module, configured to send the read command sequence to the rewritable non-volatile memory module and receive the read first data; and A state feedback module is used to store the execution state information of the first data reading operation.

9. The memory management method according to claim 1, characterized in that: The rewritable non-volatile memory module includes a plurality of storage planes, each of which has a corresponding register group and command queue; as well as The integrated reading module is configured to perform parallel parameter setting for the reading operation of the second data located on different storage planes when executing the first data reading operation.

10. The memory management method according to claim 9, characterized in that: The method further comprises: determining whether the first data and the second data are located in different storage planes; and In response to the first data and the second data being located in different storage planes, the second data reading operation is triggered to be executed before the first data reading operation is completed.

11. A memory controller for controlling a storage device equipped with a rewritable non-volatile memory module, characterized in that: The memory controller comprises: A memory interface control circuit, for electrically connecting to the rewritable non-volatile memory module; and A processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to the connection interface circuit of the storage device to electrically connect to the host system, wherein the processor is configured to: Acquire a first voltage value corresponding to a first data read operation of first data; Setting the first voltage value and a first reading parameter corresponding to the first data to an integrated reading module, so as to perform the first data reading operation via the integrated reading module; While executing the first data reading operation, acquiring in parallel a second voltage value of a second data reading operation corresponding to second data; and In response to the completion of the first data read operation, the second voltage value and a second read parameter corresponding to the second data are set to the integrated read module, so as to perform the second data read operation via the integrated read module.

12. The memory controller according to claim 11, wherein: The first reading parameter includes one or more of the following: a target physical address of the first data in the rewritable non-volatile memory module; a first data length of the first data; Physical page size information of the first data; a read mode identifier of the first data; an error detection parameter of the first data; as well as The metadata of the first data.

13. The memory controller according to claim 11, wherein: The processor is also configured to: If the first data reading operation fails, acquiring another first voltage value for re-reading the first data, wherein the another first voltage value is different from the first voltage value; as well as The another first voltage value and the first read parameter are set to the integrated read module to re-execute the first data read operation via the integrated read module.

14. The memory controller according to claim 11 or 13, characterized in that: The processor is also configured to: During the execution of the first data reading operation, if the first data reading operation fails, the execution of the second data reading operation is suspended until it is confirmed that the first data reading operation is successfully completed.

15. The memory controller according to claim 11, wherein: The processor is also configured to: storing the first voltage value and the corresponding first reading result used in each execution of the first data reading operation; as well as An optimal voltage value for reading the first data is determined based on the first voltage value and the first reading result.

16. The memory controller according to claim 15, characterized in that: Determining the optimal voltage value includes: Recording a plurality of first voltage values ​​and a plurality of corresponding first read error bit numbers; and A specific first voltage value corresponding to the minimum first read error bit number is used as the optimal voltage value.

17. The memory controller according to claim 11, wherein: The manner in which the processor performs the first data reading operation through the integrated reading module includes: Based on the first voltage value and the first read parameter, sending a read command sequence to the rewritable non-volatile memory module; and The read first data is obtained from the rewritable non-volatile memory module.

18. The memory controller according to claim 11, wherein: The processor comprises: A parameter configuration module, used for storing the first voltage value and the first read parameter; A command generation module, used for generating a read command sequence for the rewritable non-volatile memory module according to the first voltage value and the first read parameter; an execution module, configured to send the read command sequence to the rewritable non-volatile memory module and receive the read first data; and A state feedback module is used to store the execution state information of the first data reading operation.

19. The memory controller according to claim 11, wherein: The rewritable non-volatile memory module includes a plurality of storage planes, each of which has a corresponding register group and command queue; as well as The integrated reading module is configured to perform parallel parameter setting for the reading operation of the second data located on different storage planes when executing the first data reading operation.

20. The memory controller according to claim 19, wherein: The processor is also configured to: determining whether the first data and the second data are located in different storage planes; and In response to the first data and the second data being located in different storage planes, the second data reading operation is triggered to be executed before the first data reading operation is completed.

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