Command distribution method and device, computer device, storage medium and program product

Abstract

The application relates to the technical field of storage, and discloses a command distribution method and device, computer equipment, a storage medium and a program product, which comprise the following steps: obtaining a target total command and storage position information of the target total command; determining at least one subcommand corresponding to the target total command according to a target start address, a target data length and a preset strip size in the target total command and the storage position information; determining first strip identification information of the first subcommand according to a substart address and the strip size included in the first subcommand; obtaining a target correspondence table of numbers and distribution index values of a hardware computing accelerator; determining a target hardware computing accelerator in a plurality of pre-constructed hardware computing accelerators according to the first strip identification information, a preset distribution algorithm and the target correspondence table; and distributing the first subcommand to the target hardware computing accelerator. The application can improve the command processing efficiency.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more specifically to command allocation methods, apparatus, computer equipment, storage media, and program products. Background Technology

[0002] In data center server systems, server manufacturers use Redundant Array of Independent Disks (RAID) controllers to manage hard drives in order to improve hard drive read / write performance, storage scalability, and data security.

[0003] RAID can generally be configured via software using the operating system, or via hardware by integrating a RAID controller card into the server. In the latter case, the RAID controller card integrates a RAID controller, which in turn integrates a dedicated hardware computing accelerator (RAID Acceleration Cluster, RAC) for RAID operations. To further improve system command read / write performance, multiple copies of this RAC can be replicated within the RAID controller. Each RAC can process commands in parallel, thereby increasing command throughput and improving overall performance.

[0004] However, since different commands can operate on the same stripe, if these commands are assigned to different RACs for processing, the stripes are typically locked to avoid data inconsistency. For example, if commands 1 and 2 both process stripe 1, but command 1 is assigned to RAC1 and command 2 to RAC2, then when RAC1 processes command 1, it will acquire a mutex lock on stripe 1. Only after processing command 1 will it release the mutex lock, allowing RAC2 to process stripe 1. This results in underutilization of RAC hardware resources, leading to low command processing efficiency. Summary of the Invention

[0005] In view of this, the present invention provides a command allocation method, apparatus, computer device, storage medium, and program product to solve the problem of low command processing efficiency.

[0006] In a first aspect, the present invention provides a command allocation method, the method comprising:

[0007] Obtain the target's overall command, which includes the target's starting address and the target's data length;

[0008] Obtain the storage location information of the target command;

[0009] determine at least one sub-command corresponding to the target total command according to the target start address, the target data length, the preset strip size, and the storage location information, wherein the sub-start address and the sub-data length are included in each sub-command;

[0010] determine first strip identification information of the first sub-command according to the sub-start address included in the first sub-command and the strip size, wherein the first sub-command is any one of the at least one sub-command;

[0011] obtain a target correspondence table of numbers and allocation index values of hardware computing accelerators;

[0012] determine the target hardware computing accelerator from the pre-constructed plurality of hardware computing accelerators according to the first strip identification information, the preset allocation algorithm, and the target correspondence table;

[0013] allocate the first sub-command to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first sub-command to obtain a return result corresponding to the first sub-command.

[0014] The command allocation method provided by the application has the following advantages:

[0015] Firstly, the total command and the storage location information thereof can be obtained. Then, the total command can be processed to obtain at least one sub-command according to the start address, the data length, the storage location information, and the strip size in the total command. Each sub-command can have its own sub-start address and sub-data length. Further, the strip identification information of the sub-command can be determined according to the sub-start address and the strip size. Finally, the hardware computing accelerator corresponding to the sub-command can be determined according to the strip identification information, the preset allocation algorithm, and the target correspondence table of the numbers and allocation index values of the hardware computing accelerators, so that the hardware computing accelerator can process the sub-command. Through the above processing mode, each total command can be divided into one or more sub-commands, and each sub-command can be allocated to the corresponding hardware computing accelerator according to the strip identification information thereof. In this way, the sub-commands with the same strip identification information can be allocated to the same hardware computing accelerator, without the need for strip locking operation, so that the hardware resources can be fully utilized, and the command processing efficiency can be improved.

[0016] In an optional embodiment, determining at least one sub-command corresponding to the target total command according to the target start address, the target data length, the preset strip size, and the storage location information comprises:

[0017] determining at least one sub-start address and the sub-data length corresponding to each sub-start address according to the target start address, the target data length, and the strip size;

[0018] determining an order of each sub-starting address according to a size of each sub-starting address;

[0019] generating a sub-command corresponding to each sub-starting address according to the storage location information of the target total command, each sub-starting address, a sub-data length corresponding to each sub-starting address, and the order of each sub-starting address.

[0020] Specifically, in the sub-command obtained according to the storage location information of the target total command, each sub-starting address, the order of each sub-starting address, and the sub-data length corresponding to each sub-starting address, both the original information of the target total command and the information of the sub-command itself are added, so that the consistency of command processing can be ensured.

[0021] In an optional implementation, the at least one sub-starting address and the sub-data length corresponding to each starting address are determined according to the target starting address, the target data length, and the strip size, including:

[0022] determining a target strip offset according to the target starting address and the strip size;

[0023] In the first processing round, the target starting address is determined as the first sub-starting address.

[0024] determining a first sub-data length corresponding to the first sub-starting address according to the strip size and the target strip offset;

[0025] determining whether the first sub-data length is less than the target data length;

[0026] when it is determined that the first sub-data length is equal to the target data length, ending the processing to obtain one sub-starting address and one sub-data length.

[0027] Specifically, by the division manner of the scheme, it can be ensured that each sub-command corresponds to only one strip.

[0028] In an optional implementation, the method further includes:

[0029] when it is determined that the first sub-data length is less than the target data length, entering a next processing round corresponding to the first processing round;

[0030] in a current processing round of a non-first processing round, determining a sub-starting address of the current processing round according to a sub-starting address and a sub-data length corresponding to a previous processing round corresponding to the current processing round;

[0031] determining a remaining data length according to the sub-data length corresponding to each processing round before the current processing round and the target data length;

[0032] determining whether the remaining data length is greater than the stripe size;

[0033] When the remaining data length is greater than the stripe size, the stripe size is determined as the sub-data length of the current processing round, and the next processing round is entered.

[0034] Specifically, by the division manner of the present solution, it can be ensured that each sub-command corresponds to only one stripe.

[0035] In an optional implementation, when it is determined that the remaining data length is less than or equal to the stripe size, the remaining data length is determined as the sub-data length of the current processing round, and the processing is ended to obtain a plurality of sub-starting addresses and a sub-data length corresponding to each of the plurality of sub-starting addresses.

[0036] Specifically, by the division manner of the present solution, it can be ensured that each sub-command corresponds to only one stripe.

[0037] In an optional implementation, the target total command further includes split indication information, and the split indication information includes a plurality of bits.

[0038] After generating the sub-command corresponding to each sub-starting address according to the storage location information of the target total command, the sub-data length corresponding to each sub-starting address, and the ordering of each sub-starting address, the method further includes:

[0039] According to the ordering of each sub-starting address, the bit corresponding to the ordering of each sub-starting address is determined in the plurality of bits.

[0040] The bit corresponding to the ordering of each sub-starting address is set to a first preset value, and the first preset value is used to indicate that the first sub-command is not processed by any hardware computing accelerator.

[0041] Specifically, by the split indication information, it is convenient to understand the execution progress of the target total command, so as to timely feedback the processing result of the target total command after completing the processing of each sub-command corresponding to the target total command.

[0042] In an optional implementation, the target hardware computing accelerator is determined from the plurality of pre-constructed hardware computing accelerators according to the first stripe identifier information, a preset allocation algorithm, and a target correspondence table, including:

[0043] According to the first stripe identifier information and the preset allocation algorithm, a target allocation index value is determined.

[0044] It is determined whether the target correspondence table includes a number of a hardware computing accelerator corresponding to the target allocation index value.

[0045] When it is determined that the target assignment index value corresponds to a target number in the target correspondence table, a hardware computing accelerator corresponding to the target number is determined as the target hardware computing accelerator.

[0046] Specifically, the target hardware computing accelerator can be quickly determined by the preset assignment algorithm, avoiding traversal of all possible hardware computing accelerators, and improving processing efficiency. Since the information of the strip identifier and the preset assignment algorithm are used, it is ensured that each task assignment is based on certain rules, reducing the uncertainty that may be caused by random selection.

[0047] In an optional embodiment, when it is determined that the target assignment index value does not correspond to a target number in the target correspondence table, the method further comprises:

[0048] Obtaining the number of unfinished sub-commands of each hardware computing accelerator in the plurality of hardware computing accelerators;

[0049] Determining the target hardware computing accelerator according to the number of unfinished sub-commands of each hardware computing accelerator.

[0050] Specifically, the load size of the hardware computing accelerator can be determined by the number of unfinished sub-commands of the hardware computing accelerator, and a suitable target hardware computing accelerator can be selected according to the load size of the hardware computing accelerator, so as to improve the processing efficiency of the sub-commands, that is, the processing efficiency of the total command.

[0051] In an optional embodiment, the target hardware computing accelerator is determined according to the number of unfinished sub-commands of each hardware computing accelerator, comprising:

[0052] Determining the hardware computing accelerator with the least number of unfinished sub-commands according to the number of unfinished sub-commands of each hardware computing accelerator;

[0053] When the hardware computing accelerator with the least number of sub-commands is one, the hardware computing accelerator with the least number of sub-commands is directly determined as the target hardware computing accelerator;

[0054] Or,

[0055] When the hardware computing accelerator with the least number of sub-commands is multiple, the hardware computing accelerator with the least number of sub-commands is selected as the target hardware computing accelerator.

[0056] Specifically, by selecting the hardware computing accelerator with the least number of sub-commands as the target hardware computing accelerator, load balancing of different hardware computing accelerators can be achieved, and the data processing efficiency of the sub-commands can be improved.

[0057] In an optional implementation, the method further includes:

[0058] extracting the storage location information of the target total command and the ordering of the first sub-starting address from the first sub-command when the target hardware computing accelerator finishes processing the first sub-command;

[0059] determining the target total command according to the storage location information of the target total command;

[0060] determining a first bit position corresponding to the ordering of the first sub-starting address in the multiple bit positions of the target total command according to the ordering of the first sub-starting address;

[0061] setting the first bit position to a second preset value, wherein the second preset value is used to indicate that the first sub-command has been processed by the target hardware computing accelerator.

[0062] Specifically, by setting a specific bit position to mark the processing state of a sub-command, it can be ensured that it can be accurately known which sub-commands have been processed, thereby preventing the occurrence of repeated processing or missed processing.

[0063] In an optional implementation, the method further includes:

[0064] adding the first sub-command to the tail of a target queue corresponding to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first sub-command when it is determined according to the ordering of each sub-command in the target queue that the processing order of the first sub-command is due, and obtains a return result corresponding to the first sub-command.

[0065] Specifically, by adding sub-commands to the queue in order, it is ensured that the sub-commands are processed in the order in which they entered the queue, which can maintain the logical order of task processing and avoid data processing errors.

[0066] In an optional implementation, the method further includes:

[0067] obtaining a target host command sent by a host end;

[0068] obtaining a preset total command data structure;

[0069] converting the target host command to obtain the target total command according to the total command data structure.

[0070] Specifically, by using a preset total command data structure, different formats of target host commands can be uniformly converted into a consistent format, thereby simplifying subsequent processing steps and improving the compatibility and interoperability of the system.

[0071] In an optional implementation, after the first bit is set to the second preset value, the method further comprises:

[0072] determining whether each bit of the target total command is the second preset value;

[0073] when it is determined that each bit of the split indication information of the target total command is the second preset value, obtaining a return result corresponding to each subcommand corresponding to the target total command;

[0074] determining a total return result corresponding to the target total command according to the return result corresponding to each subcommand corresponding to the target total command;

[0075] feeding back the total return result to the host end.

[0076] Specifically, by checking whether all bits of the target total command have been set to the second preset value, it can be ensured that all subcommands have been processed. In this way, the problem of incomplete results caused by the fact that a subcommand has not been processed can be prevented. After all subcommands are processed, the results are summarized to ensure the consistency and accuracy of the final results, avoiding problems caused by unsynchronized or incorrect summary of intermediate results. Once it is confirmed that all subcommands have been processed, the total result is immediately fed back to the host end, ensuring the timeliness of task feedback.

[0077] In an optional implementation, the target allocation index value is determined according to the first stripe identifier information and a preset allocation algorithm, and the following expression is used:

[0078] Hash Key = StripeID % K

[0079] wherein Hash Key is the target allocation index value, StripeID is the first stripe identifier information, and K is a third preset value.

[0080] Specifically, by using the modulo operation, it can be ensured that different stripes are uniformly mapped to a fixed range (0 to K-1). This ensures the consistency of the allocation index value, i.e., the same stripe identifier information will always be allocated to the same hardware computing accelerator. In addition, the modulo operation is particularly simple and fast, and can be completed with only one division operation and a remainder operation, which has high computational efficiency. By adjusting the value of K, the allocation strategy can be easily adjusted. For example, if the number of target nodes or disks needs to be increased or decreased, the value of K can be adjusted accordingly, and the resource allocation strategy can be flexibly adjusted.

[0081] In an alternative embodiment, after the target hardware computing accelerator is determined according to the number of sub-commands not completed by each hardware computing accelerator, the method further comprises:

[0082] obtaining the number of the target hardware computing accelerator;

[0083] updating the target correspondence table according to the target allocation index value and the number of the target hardware computing accelerator.

[0084] Specifically, the dynamic updating mechanism can reduce the management cost and does not require real-time management by technical personnel.

[0085] In an alternative embodiment, the first stripe identification information of the first sub-command is determined according to the sub-starting address included in the first sub-command and the stripe size, and the following expression is used:

[0086] StripeID=ZSLBA%Stripe_Length

[0087] wherein StripeID is the first stripe identification information, ZSLBA is the sub-starting address included in the first sub-command, and Stripe_Length is the stripe size.

[0088] In a second aspect, the present application provides a command allocation device, which comprises:

[0089] an obtaining module, configured to obtain a target total command and obtain storage location information of the target total command, wherein the target total command comprises a target starting address and a target data length;

[0090] a determining module, configured to determine at least one sub-command corresponding to the target total command according to the target starting address, the target data length, a preset stripe size, and the storage location information, wherein each sub-command comprises a sub-starting address and a sub-data length; and determine first stripe identification information of a first sub-command according to the sub-starting address included in the first sub-command and the stripe size, wherein the first sub-command is any one of the at least one sub-command;

[0091] the obtaining module is further configured to obtain a target correspondence table of the number of hardware computing accelerators and allocation index values;

[0092] the determining module is further configured to determine a target hardware computing accelerator from a plurality of pre-constructed hardware computing accelerators according to the first stripe identification information, a preset allocation algorithm, and the target correspondence table;

[0093] an allocation module, configured to allocate the first sub-command to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first sub-command to obtain a return result corresponding to the first sub-command.

[0094] In a third aspect, the present application provides a computer device, comprising: a memory and a processor, which are connected with each other in communication, and the memory stores computer instructions, and the processor executes the command allocation method of the first aspect or any of the corresponding embodiments by executing the computer instructions.

[0095] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer instructions for making a computer execute the command allocation method of the first aspect or any of the corresponding embodiments.

[0096] In a fifth aspect, the present application provides a computer program product, which comprises computer instructions for making a computer execute the command allocation method of the first aspect or any of the corresponding embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0097] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the technical solutions in the related art, the drawings needed to be used in the specific embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0098] Figure 1 is a schematic diagram of the architecture of the RAID controller according to an embodiment of the present application;

[0099] Figure 2 is a schematic diagram of the flow of the command allocation method according to an embodiment of the present application;

[0100] Figure 3 is a schematic diagram of the total command data structure and the sub-command data structure according to an embodiment of the present application;

[0101] Figure 4 is a schematic diagram of the IO splitting according to an embodiment of the present application;

[0102] Figure 5 is a schematic diagram of the hash representation according to an embodiment of the present application;

[0103] Figure 6 is another schematic diagram of the IO splitting according to an embodiment of the present application;

[0104] Figure 7 is a schematic diagram of the IO allocation according to an embodiment of the present application;

[0105] Figure 8 is a schematic diagram of the analysis of the IO processing duration according to an embodiment of the present application;

[0106] Figure 9 is a structural block diagram of a command distribution device according to an embodiment of the present application;

[0107] Figure 10 is a hardware structure schematic diagram of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION

[0108] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0109] The special terms related to the present application are explained below.

[0110] Raw command (RAW IO): refers to a way of performing raw read and write operations on a storage device, that is, directly accessing data blocks on the storage device without passing through the intermediate layer of the operating system or the file system.

[0111] Redundant array of independent disks (RAID) technology: a fault safety mechanism for data loss is created by combining two or more hard disk drives (HDD) or solid state drives (SSD) into a coordinated storage unit or array. Common RAID types include RAID0, RAID1, RAID5, and RAID6.

[0112] RAID5: the main feature is to use parity checking to protect data while allowing parallel access to multiple disks to improve read and write speed.

[0113] Stripe: a concept in RAID, RAID technology divides data into stripes, and a stripe spans all data disks, with each disk storing a part of the stripe.

[0114] The present application provides a RAID controller, as shown in Figure 1 The RAID controller can include an IO receiver, a load balancer, a plurality of hardware computing accelerators (RAC), an IO replacer, and other hardware components. Figure 1 The number of RACs is 2.

[0115] The command (IO) receiver is used to receive host IO (e.g., ) sent by the host. Figure 1 The system uses IO-1, IO-2, IO-3, and IO-4 to convert host IO into RAW IO according to the preset total command data structure.

[0116] A load balancer may include a RAW IO splitter, a memory, a subcommand distributor, and multiple RAC IO reclaimers. The RAW IO splitter can be used to split RAW IO to obtain at least one RAC IO (e.g., Figure 1 The memory can be used to store the target mapping table of RAW IOs, hardware computing accelerator numbers, and allocation index values, as well as multiple RAC IO queues. The subcommand allocator can be configured with a preset allocation algorithm. The subcommand allocator is used to submit RAC IOs to the corresponding RAC IO queues based on the RAC IOs, the preset allocation algorithm, and the target mapping table. The number of RAC IO reclaimers can be the same as the number of RACs, and there is a one-to-one correspondence; that is, one RAC IO reclaimer is used to reclaim the IOs processed by its corresponding RAC. "Reclaiming" refers to releasing the resources occupied by the corresponding IO. The RAC IO queues can be First-In-First-Out (FIFO) queues. The number of RAC IO queues can be the same as the number of RACs, and there is a one-to-one correspondence; that is, one RAC IO queue is used to store subcommands allocated to the corresponding RAC. RAC (Remote Access Control) can include I / O calculators, I / O readers / writers, I / O terminators, and I / O counters. These are used to read subcommands from their corresponding RAC I / O queues, process them, and obtain the corresponding return results for the RAC I / O. An I / O responder is used to respond to host I / O based on the return results of the subcommands. Other hardware components may include memory management, interrupt management, and buses.

[0117] This invention provides a command allocation method that splits the target total command and then allocates it to RACs to fully utilize hardware resources and improve command processing efficiency.

[0118] According to an embodiment of the present invention, a command assignment method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0119] A command distribution method is provided in the embodiment, which can be executed by a computer device, for example, the computer device can be the RAID controller as described above, i.e. the command distribution method is completed by cooperation of each hardware component included in the RAID controller, or can be other device with computing capability. The flow of the command distribution method is described below taking the RAID controller as the execution subject.

[0120] Figure 2 is a flowchart of the command distribution method according to the embodiment of the present application, as shown in the figure, the flow includes the following steps: Figure 2

[0121] Step S201, obtaining a target total command.

[0122] The target total command can be generated according to the received host command, for example, the RAW IO as described above, or can also be a command automatically generated by the IO receiver according to the preset business processing logic.

[0123] Specifically, when the target total command is generated according to the received host command, the specific generation process can be as follows:

[0124] Step one, obtaining the target host command sent by the host end.

[0125] Step two, obtaining the preset total command data structure.

[0126] Step three, converting the target host command according to the total command data structure to obtain the target total command.

[0127] The target host command can be the host IO as described above. The total command data structure includes split indication information, start address, data length, and operation type. The split indication information can include multiple bits, and the number of bits can be the same as the number of sub-commands that the total command can be split into at most. The start address can be a start logical address (SLBA) in particular. The operation type can be a read operation or a write operation. For example, the total command data structure can be as shown in IO-1 and IO-2 in Figure 3 , wherein "split_bitmap" is the split indication information.

[0128] Specifically, when the IO receiver in the RAID controller receives the target host command sent by the host end, the preset total command data structure can be obtained, and the target host command can be parsed to parse out the split indication information, the target start address, the target data length, and the operation type, and these information can be recombined according to the preset total command data structure to obtain the target total command.

[0129] ​In step S202, the storage location information of the target total command is obtained.

[0130] The storage location information can be a pointer indicating the storage location of the target total command in the memory.

[0131] Specifically, after obtaining the target total command, the IO receiver can transmit the target total command to the RAW IO splitter, which processes the target total command and stores it in the memory.

[0132] In step S203, at least one sub-command corresponding to the target total command is determined according to the target start address, the target data length, the preset strip size, and the storage location information.

[0133] The sub-command can be the RAC IO described above.

[0134] Since the target total command can be a cross-strip operation command or a non-cross-strip operation command, the target total command can be processed to divide it into sub-commands that do not require cross-strip operation. Accordingly, the specific steps of processing the target total command by the RAW IO splitter can be as follows:

[0135] In step 1, at least one sub-start address and the sub-data length corresponding to each sub-start address are determined according to the target start address, the target data length, and the strip size.

[0136] Step 1: Determine the target strip offset according to the target start address and the strip size.

[0137] Step 2: In the first processing round, the target start address is determined as the first sub-start address.

[0138] Step 3: Determine the first sub-data length corresponding to the first sub-start address according to the strip size and the target strip offset.

[0139] Step 4: Determine whether the first sub-data length is less than the target data length.

[0140] Step 5: When it is determined that the first sub-data length is equal to the target data length, the processing is ended, and one sub-start address and one sub-data length are obtained.

[0141] Step 6: When it is determined that the first sub-data length is less than the target data length, the next processing round corresponding to the first processing round is entered.

[0142] Step 7: In the current processing round of the non-first processing round, the sub-start address of the current processing round is determined according to the sub-start address and the sub-data length corresponding to the previous processing round corresponding to the current processing round.

[0143] Step 8, determining the remaining data length according to the target data length and the sub data length corresponding to each of all processing rounds before the current processing round.

[0144] Step 9, determining whether the remaining data length is greater than the stripe size.

[0145] Step 10, when the remaining data length is greater than the stripe size, determining the stripe size as the sub data length of the current processing round, and entering the next processing round.

[0146] Step 11, when determining that the remaining data length is less than or equal to the stripe size, determining the remaining data length as the sub data length of the current processing round, and ending the processing to obtain the plurality of sub start addresses and the sub data length corresponding to each of the plurality of sub start addresses.

[0147] Specifically, the RAW IO splitter can determine the target stripe offset by using the following expression:

[0148] O = MSLBA Mod Stripe_Length

[0149] wherein, O is the target stripe offset, MSLBA is the target start address, Stripe_Length is the stripe size, and Mod is a modulo operation.

[0150] When determining the first sub command, the RAW IO splitter can determine the target start address as the sub start address corresponding to the first sub command (i.e., the first sub start address), and determine the remaining data length obtained by subtracting the target stripe offset from the stripe size as the sub data length corresponding to the first sub command (i.e., the first sub data length). Then, the RAW IO splitter can determine whether the sub data length is equal to the target data length. If yes, no splitting is needed, i.e., the target total command only corresponds to one sub command, which is itself. If no, it indicates that the target total command needs to be split, and the RAW IO splitter can enter the next processing round to determine the sub start address and the sub data length of the next sub command.

[0151] The RAW IO splitter can determine the sum of the first sub start address and the first sub data length as the second sub start address. And, the RAW IO splitter can determine the remaining data length by subtracting the first sub data length from the target data length. At this time, it can be determined whether the remaining data length is greater than the stripe size. If yes, it indicates that further splitting is needed, and the RAW IO splitter can determine the stripe size as the second sub data length. If no, it indicates that the second sub command is the last sub command in the target total command, and the RAW IO splitter can determine the remaining data length as the second sub data length.

[0152] In this way, at least one sub-starting address and at least one sub-data length corresponding to the target total command can be obtained.

[0153] In step two, the order of each sub-starting address is determined according to the size of each sub-starting address.

[0154] Specifically, the RAW IO splitter can sort each sub-starting address in descending order of the size of each sub-starting address.

[0155] In step three, a sub-command corresponding to each sub-starting address is generated according to the storage location information of the target total command, each sub-starting address, the sub-data length corresponding to each sub-starting address, and the order of each sub-starting address.

[0156] Specifically, the RAW IO splitter can process the storage location information of the target total command, each sub-starting address, the sub-data length corresponding to each sub-starting address, and the order of each sub-starting address according to a preset sub-command data structure to obtain at least one sub-command corresponding to the target total command.

[0157] In some optional embodiments, the RAW IO splitter can also obtain the operation type of the target total command and use the operation type as information in the sub-command. For example, the sub-command data structure can be as shown in Figure 3 , where "parent_addr" is the storage location information of the target total command, and "split_bit_pos" is the order of the sub-starting address.

[0158] In Figure 3 , IO-1 is split into two sub-commands, IO-1-1 and IO-1-2, and IO-2 is not split. Accordingly, as shown in Figure 4 , after processing IO1, IO-1-1 operates on stripe 0, IO-1-2 operates on stripe 1, and IO-2 is not split and only operates on stripe 1.

[0159] In some optional embodiments, after step one in step S203, the RAW IO splitter can also determine a bit position corresponding to the order of each sub-starting address in a plurality of bit positions according to the order of each sub-starting address. The bit position corresponding to the order of each sub-starting address is set to a first preset value. The default value of each bit position can be a second preset value. The first preset value can be 0, and the second preset value can be 1.

[0160] In this way, by setting a specific bit position to mark the processing status of the sub-command, it can be ensured that it can be accurately known which sub-commands have been processed, thereby preventing the occurrence of repeated processing or missed processing.

[0161] In step S204, the first stripe identification information of the first sub-command is determined according to the sub-starting address and the stripe size included in the first sub-command.

[0162] The first sub-command is any one of the at least one sub-command.

[0163] Specifically, the sub-command distributor can calculate the identification information of the stripe where the data operated by the first sub-command is located, i.e., the first stripe identification information, according to the sub-starting address and the stripe size included in the first sub-command.

[0164] For example, the calculation of the first stripe identification information can adopt the following expression:

[0165] StripeID = ZSLBA % Stripe_Length

[0166] Wherein, StripeID is the first stripe identification information, ZSLBA is the sub-starting address included in the first sub-command, and Stripe_Length is the stripe size.

[0167] In step S205, a target correspondence table of the number of hardware computing accelerators and the allocation index value is obtained.

[0168] The target correspondence table can be a Hash table. For example, the Hash table can be as shown in Figure 5

[0169] Specifically, the sub-command distributor can read the target correspondence table from the memory.

[0170] In step S206, the target hardware computing accelerator is determined in the pre-constructed plurality of hardware computing accelerators according to the first stripe identification information, the preset allocation algorithm and the target correspondence table.

[0171] The preset allocation algorithm is a Hash algorithm.

[0172] Specifically, after the sub-command distributor determines the first stripe identification information and obtains the target correspondence table, the target hardware computing accelerator is determined in the plurality of hardware computing accelerators of the RAID controller according to the following steps:

[0173] In step one, the target allocation index value is determined according to the first stripe identification information and the preset allocation algorithm.

[0174] For example, step one can adopt the following expression:

[0175] Hash Key = StripeID % K

[0176] ​The preset allocation algorithm can be a hash algorithm. The Hash Key is a target allocation index value, the StripeID is first stripe identification information, and the K is a third preset numerical value. For example, the K can be 128, and can be the same as the length of the target correspondence table.

[0177] Step two, determining whether the target correspondence table has a target number corresponding to the target allocation index value.

[0178] Step three, when it is determined that the target correspondence table has a target number corresponding to the target allocation index value, the hardware computing accelerator corresponding to the target number is determined as the target hardware computing accelerator.

[0179] Step four, when it is determined that the target correspondence table does not have a target number corresponding to the target allocation index value, the number of uncompleted sub-commands of each hardware computing accelerator is obtained.

[0180] Step five, according to the number of uncompleted sub-commands of each hardware computing accelerator, the target hardware computing accelerator is determined.

[0181] Step 1, according to the number of uncompleted sub-commands of each hardware computing accelerator, the hardware computing accelerator with the least number of uncompleted sub-commands is determined.

[0182] Step 2, when the hardware computing accelerator with the least number of sub-commands is one, the hardware computing accelerator with the least number of sub-commands is directly determined as the target hardware computing accelerator.

[0183] Step 3, when the hardware computing accelerator with the least number of sub-commands is multiple, the hardware computing accelerator with the smallest number from the multiple hardware computing accelerators with the least number of sub-commands is selected as the target hardware computing accelerator.

[0184] Specifically, the sub-command allocator can first calculate the target allocation index value according to the first stripe identification information and the preset allocation algorithm. Further, it can be determined in the target correspondence table whether there is a target number bound to the target allocation index value. If yes, the target number hardware computing accelerator can be directly determined according to the target number. If not, the number of uncompleted sub-commands of each hardware computing accelerator can be obtained, and the hardware computing accelerator with the least number of sub-commands can be determined. If the hardware computing accelerator with the least number of sub-commands is only one, the hardware computing accelerator with the least number of sub-commands can be determined as the target hardware computing accelerator. If there are multiple hardware computing accelerators with the least number of sub-commands, the hardware computing accelerator with the smallest number from the multiple hardware computing accelerators with the least number of sub-commands can be selected as the target hardware computing accelerator.

[0185] In this way, the hardware computing accelerator with the least number of sub-commands is selected as the target hardware computing accelerator, and the data processing efficiency of the first sub-command is improved.

[0186] In some optional embodiments, after step five, the sub-command distributor can further obtain the number of the target hardware computing accelerator. According to the target allocation index value and the number of the target hardware computing accelerator, the target correspondence table is updated.

[0187] Specifically, the sub-command distributor can bind the target allocation index value and the number of the target hardware computing accelerator.

[0188] In the related art, the correspondence between the type of the strip identification information and the number of the target hardware computing accelerator can be predefined, for example, when the strip identification information of the command is odd, the first hardware computing accelerator is allocated, and when the strip identification information of the command is even, the second hardware computing accelerator is allocated. However, there can be a situation where the number of commands with even strip identification information is large, resulting in a large load on a certain hardware computing accelerator, load imbalance, and insufficient use of hardware resources.

[0189] The present scheme does not need to pre-create a complete correspondence table, but can improve the target correspondence table according to the actual processing of the sub-commands by the hardware computing accelerator, which is more in line with the actual situation, can ensure load balancing, and fully utilize hardware resources.

[0190] Step S207, the first sub-command is allocated to the target hardware computing accelerator.

[0191] Specifically, the RAID controller can add the first sub-command to the tail of the target queue corresponding to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first sub-command when it is determined according to the order of each sub-command in the target queue that the processing order of the first sub-command has come, and obtains the return result corresponding to the first sub-command. The target queue can be a queue corresponding to the target hardware computing accelerator in the plurality of RAC IO queues. When the operation type included in the first sub-command is a read operation, the return result can include the read data, and when the operation type included in the first sub-command is a write operation, the return result can include success indication information or failure indication information.

[0192] When the target hardware computing accelerator finishes processing the first sub-command, the storage location information of the target total command and the ordering of the first sub-starting address can be extracted from the first sub-command. According to the storage location information of the target total command, the target total command is determined. According to the ordering of the first sub-starting address, the first bit position corresponding to the ordering of the first sub-starting address is determined in the plurality of bit positions of the target total command. The first bit position is set to the second preset value.

[0193] The first preset value is used to indicate that the first sub-command is not processed by any hardware computing accelerator. The second preset value is used to indicate that the first sub-command has been processed by the target hardware computing accelerator.

[0194] In some optional embodiments, after the first bit position is set to the second preset value, the IO replyer can further determine whether the values of each bit position in the plurality of bit positions of the target total command are all the second preset value. When it is determined that the values of each bit position in the plurality of bit positions in the split indication information of the target total command are all the second preset value, the return results corresponding to the at least one sub-command corresponding to the target total command are obtained. According to the return results corresponding to the at least one sub-command corresponding to the target total command, the total return result corresponding to the target total command is determined. The total return result is fed back to the host end.

[0195] Specifically, after the target hardware computing accelerator finishes processing the first sub-command, the first sub-command can be sent to the RAC IO recycler, and the RAC IO recycler can recycle the storage resources and computing resources occupied by the RAC, and send the first sub-command and the return result of the first sub-command to the IO replyer. The IO replyer determines the target total command in the memory according to the memory location information, and further modifies the bit position corresponding to the ordering of the first sub-starting address in the target total command to the second preset value according to the ordering of the sub-starting address included in the first sub-command. When the IO replyer determines that the values of each bit position in the target total command are all the second preset value, it can be determined that the target total command is completed, and the total return result can be constructed according to the return result of each sub-command corresponding to the target total command and sent to the host end.

[0196] In this way, once it is confirmed that all sub-commands have been processed, the total result is immediately fed back to the host end, ensuring the timeliness of task feedback.

[0197] The command distribution method provided by the embodiment can first acquire the total command and storage location information thereof. Then, at least one sub-command can be obtained by processing the total command according to the start address, data length, storage location information and strip size in the total command. Each sub-command can have its own sub-start address and sub-data length. Further, the strip identifier of the sub-command can be determined according to the sub-start address and the strip size. Finally, the hardware computing accelerator corresponding to the sub-command can be determined according to the strip identifier information, the preset distribution algorithm, and the target correspondence relationship table of the number of hardware computing accelerators and the distribution index value, so that the hardware computing accelerator can process the sub-command. Through the above processing mode, each total command can be divided into one or more sub-commands, and each sub-command can be distributed to the corresponding hardware computing accelerator according to the corresponding strip identifier information. In this way, the sub-commands with the same strip identifier information can be distributed to the same hardware computing accelerator, without the need for strip locking operation, fully utilizing the hardware resources, and improving the command processing efficiency.

[0198] The distribution of the four IOs in the strip is shown in the following specific example. Figure 6 As shown in the figure, IO-1 and IO-3 are in strip 0, IO-2 is in strip 1, and IO4 is in strip 129.

[0199] For each IO, the process of distributing the hardware computing accelerator can be as follows:

[0200] IO-1: the distribution index value is calculated as 0, at this time the distribution index value has not been bound, then the number of unfinished sub-commands of each hardware computing accelerator is queried, here the number of unfinished sub-commands of RAC0 and RAC1 is 0, then the distribution index value is bound to RAC0, and RAC IO is submitted to RAC0.

[0201] IO-2: the distribution index value is calculated as 1, at this time the distribution index value has not been bound, then the number of unfinished sub-commands of RAC is queried, at this time the number of unfinished sub-commands of RAC0 is 1 and the number of unfinished sub-commands of RAC1 is 0, it can be considered that the load of RAC0 is greater than that of RAC1, therefore the distribution index value = 1 is bound to RAC1, and then IO-2 is submitted to RAC1.

[0202] IO-3: the distribution index value is calculated as 0, at this time the distribution index value has been bound to RAC0, and RAC IO is submitted to RAC0.

[0203] IO-4: the distribution index value is calculated as 1, at this time the distribution index value has been bound to RAC1, and RAC IO is submitted to RAC1.

[0204] After the load balancing algorithm processing, two RACs each process two IOs, IO-1 and IO-3 are submitted to RAC0 for execution, and IO-2 and IO-4 are submitted to RAC1 for execution, achieving load balancing. The RAC binding relationship in the final hash table is as shown in Figure 7 .

[0205] As shown in Figure 8 , the sub-command distributor can continuously submit IOs to the RAC IO queue, that is, after the sub-command distributor processes one RAC IO, it will immediately process the next RAC IO. Referring to the time dimension effect diagram in the following figure, after the sub-command distributor processes IO-1, it immediately processes IO-2. It can be seen that although IO-1 and IO-2 are not simultaneously executed on the RAC, they can achieve parallelism. In addition, since the processing speed of the sub-command distributor is much faster than that of the RAC, the difference in the start timing of IO-1 and IO-2 on the RAC module is relatively small. In the following figure, IO-1 and IO-3 are executed on RAC0 in turn. Since the RAC supports pipelining, that is, one IO processing may involve multiple stages. When the RAC ends the processing of the first stage of IO-1, it can simultaneously execute the processing of the second stage of IO-1 and the processing of the first stage of IO-3. Therefore, IO-1 and IO-3 can also be considered as parallel execution. In this way, the overall IO processing efficiency is relatively high.

[0206] In the embodiment, a command distribution device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware is also possible and is contemplated.

[0207] The embodiment provides a command distribution device, as shown in Figure 9 , comprising:

[0208] The acquisition module 901 is configured to acquire a target total command and acquire storage location information of the target total command, wherein the target total command comprises a target start address and a target data length.

[0209] The determination module 902 is configured to determine at least one sub-command corresponding to the target total command according to the target start address, the target data length, a preset strip size, and the storage location information, wherein each sub-command comprises a sub-start address and a sub-data length; and determine first strip identification information of a first sub-command according to the sub-start address included in the first sub-command and the strip size, wherein the first sub-command is any one of the at least one sub-command.

[0210] The obtaining module 901 is further configured to obtain a target correspondence relationship table of numbers of hardware computing accelerators and assigned index values;

[0211] The determining module 902 is further configured to determine, according to the first strip identification information, a preset assignment algorithm, and the target correspondence relationship table, a target hardware computing accelerator from among the pre-constructed plurality of hardware computing accelerators;

[0212] The assigning module 903 is configured to assign the first sub-command to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first sub-command to obtain a return result corresponding to the first sub-command.

[0213] In some optional embodiments, the determining module 902 is specifically configured to:

[0214] determine at least one sub-starting address and a sub-data length corresponding to each sub-starting address according to the target starting address, the target data length, and the strip size;

[0215] determine an order of each sub-starting address according to a size of each sub-starting address;

[0216] generate a sub-command corresponding to each sub-starting address according to the storage location information of the target total command, each sub-starting address, a sub-data length corresponding to each sub-starting address, and the order of each sub-starting address.

[0217] In some optional embodiments, the determining module 902 is specifically configured to:

[0218] determine a target strip offset according to the target starting address and the strip size;

[0219] determine the target starting address as a first sub-starting address in a first processing round;

[0220] determine a first sub-data length corresponding to the first sub-starting address according to the strip size and the target strip offset;

[0221] determine whether the first sub-data length is less than the target data length;

[0222] when it is determined that the first sub-data length is equal to the target data length, end the processing to obtain one sub-starting address and one sub-data length.

[0223] In some optional embodiments, the determining module 902 is further configured to:

[0224] when it is determined that the first sub-data length is less than the target data length, enter a next processing round corresponding to the first processing round;

[0225] In the current processing round which is not the first processing round, the sub-starting address of the current processing round is determined according to the sub-starting address and the sub-data length corresponding to the last processing round corresponding to the current processing round;

[0226] The remaining data length is determined according to the sub-data lengths corresponding to all processing rounds before the current processing round and the target data length;

[0227] It is determined whether the remaining data length is greater than the strip size;

[0228] When the remaining data length is greater than the strip size, the strip size is determined as the sub-data length of the current processing round, and the next processing round is entered.

[0229] In some optional embodiments, the determining module 902 is further configured to:

[0230] When it is determined that the remaining data length is less than or equal to the strip size, the remaining data length is determined as the sub-data length of the current processing round, and the processing is ended to obtain the plurality of sub-starting addresses and the sub-data length corresponding to each of the plurality of sub-starting addresses.

[0231] In some optional embodiments, the target total command further includes split indication information, and the split indication information includes a plurality of bits.

[0232] The determining module 902 is further configured to:

[0233] According to the order of each sub-starting address, a bit corresponding to the order of each sub-starting address is determined in the plurality of bits.

[0234] The bit corresponding to the order of each sub-starting address is set to a first preset value, and the first preset value is used to indicate that the first sub-command is not processed by any hardware computing accelerator.

[0235] In some optional embodiments, the determining module 902 is specifically configured to:

[0236] The target allocation index value is determined according to the first strip identification information and a preset allocation algorithm.

[0237] It is determined whether the target corresponding relationship table includes a target number corresponding to the target allocation index value.

[0238] When it is determined that the target corresponding relationship table includes the target number corresponding to the target allocation index value, the hardware computing accelerator corresponding to the target number is determined as the target hardware computing accelerator.

[0239] In some optional embodiments, the determining module 902 is further configured to:

[0240] When it is determined that the target assignment index value does not correspond to the target number in the target correspondence table, the number of sub-commands not completed by each of the plurality of hardware computing accelerators is obtained;

[0241] According to the number of sub-commands not completed by each of the plurality of hardware computing accelerators, the target hardware computing accelerator is determined.

[0242] In some optional embodiments, the determining module 902 is specifically configured to:

[0243] According to the number of sub-commands not completed by each of the plurality of hardware computing accelerators, the hardware computing accelerator with the least number of sub-commands not completed is determined.

[0244] When the hardware computing accelerator with the least number of sub-commands not completed is one, the hardware computing accelerator with the least number of sub-commands not completed is directly determined as the target hardware computing accelerator.

[0245] Alternatively,

[0246] When the hardware computing accelerator with the least number of sub-commands not completed is multiple, the hardware computing accelerator with the least number of sub-commands not completed is selected as the target hardware computing accelerator.

[0247] In some optional embodiments, the apparatus further includes a setting module 904.

[0248] The setting module 904 is configured to:

[0249] When the target hardware computing accelerator processes the first sub-command, the storage location information of the target total command and the order of the first sub-starting address are extracted from the first sub-command.

[0250] According to the storage location information of the target total command, the target total command is determined.

[0251] According to the order of the first sub-starting address, the first bit corresponding to the order of the first sub-starting address is determined in the plurality of bits of the target total command.

[0252] The first bit is set to a second preset value, wherein the second preset value is used to indicate that the first sub-command has been processed by the target hardware computing accelerator.

[0253] In some optional embodiments, the assigning module 903 is configured to:

[0254] The first sub-command is added to the tail of the target queue corresponding to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first sub-command when it is determined that the first sub-command is in turn according to the order of each sub-command in the target queue, and obtains a return result corresponding to the first sub-command.

[0255] In some optional embodiments, the acquisition module 901 is specifically configured to:

[0256] acquire a target host command sent by a host end;

[0257] acquire a preset total command data structure;

[0258] convert the target host command according to the total command data structure to obtain a target total command.

[0259] In some optional embodiments, the apparatus further comprises a feedback module 905.

[0260] The feedback module 905 is configured to:

[0261] determine whether the value of each bit of a plurality of bits in the target total command is the second preset value;

[0262] when it is determined that the value of each bit of the plurality of bits in the split indication information of the target total command is the second preset value, acquire a return result corresponding to at least one sub-command corresponding to the target total command respectively;

[0263] determine a total return result corresponding to the target total command according to the return result corresponding to the at least one sub-command corresponding to the target total command respectively;

[0264] feed back the total return result to the host end.

[0265] In some optional embodiments, the target allocation index value is determined according to the first stripe identifier information and a preset allocation algorithm, and the following expression is adopted:

[0266] Hash Key = StripeID % K

[0267] wherein Hash Key is the target allocation index value, StripeID is the first stripe identifier information, and K is a third preset value.

[0268] In some optional embodiments, the apparatus further comprises an updating module 906.

[0269] The updating module 906 is specifically configured to:

[0270] acquire a number of a target hardware computing accelerator;

[0271] update the target correspondence table according to the target allocation index value and the number of the target hardware computing accelerator.

[0272] In some alternative embodiments, the first stripe identification information of the first sub-command is determined according to the sub-starting address and the stripe size included in the first sub-command, using the following expression:

[0273] StripeID = ZSLBA % Stripe_Length

[0274] Wherein, the StripeID is the first stripe identification information, the ZSLBA is the sub-starting address included in the first sub-command, and the Stripe_Length is the stripe size.

[0275] Further function descriptions of the above-mentioned modules and units are the same as those of the corresponding embodiments, and will not be repeated here.

[0276] The command distribution apparatus in the embodiment is in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory executing one or more software or fixed programs, and / or other devices capable of providing the above functions.

[0277] The embodiment of the present application also provides a computer device having the above-mentioned Figure 9 command distribution apparatus.

[0278] Please refer to Figure 10 , Figure 10 is a structural schematic diagram of a computer device provided by an alternative embodiment of the present application, as shown in Figure 10 , the computer device includes one or more processors 10, a memory 20, and an interface for connecting various components, including a high-speed interface and a low-speed interface. Various components are communicatively connected to each other by different buses, and can be installed on a common mainboard or in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in the memory or on the memory to display graphical information on a GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memories, if necessary. Similarly, multiple computer devices can be connected, each providing part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 10 In the figure, the processor 10 is taken as an example.

[0279] The processor 10 can be a central processor, a network processor, or a combination thereof. The processor 10 can further include hardware integrated circuits. The hardware integrated circuits can be application specific integrated circuits, programmable logic devices, or a combination thereof. The programmable logic devices can be complex programmable logic devices, field programmable gate arrays, general array logic, or any combination thereof.

[0280] The memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods illustrated by the above embodiments.

[0281] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system, application programs required by at least one function, and the like. The data storage area can store data created according to the use of the computer device, and the like. In addition, the memory 20 can include a high-speed random access memory, and can further include a non-transitory memory such as at least one disk storage device, a flash memory device, or other non-transitory solid state memory device. In some alternative embodiments, the memory 20 can optionally include a memory disposed remotely from the processor 10, which can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0282] The memory 20 can include a volatile memory such as a random access memory, and can also include a non-volatile memory such as a flash memory, a hard disk, or a solid state disk. The memory 20 can further include a combination of the above-mentioned types of memories.

[0283] The computer device further includes a communication interface 30 for communication of the computer device with other devices or communication networks.

[0284] The embodiments of the present application also provide a computer readable storage medium. The above-mentioned methods according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium through network downloading, so that the methods described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can further include a combination of the above-mentioned types of memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods illustrated by the above embodiments are implemented.

[0285] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, can invoke or provide the method and / or technical solutions according to the present application. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source files, executable files, installation package files, etc., and accordingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0286] Although the embodiments of the present application are described in conjunction with the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A command distribution method characterized by comprising: The method comprises: acquiring a target total command, wherein the target total command comprises a target start address and a target data length; acquiring storage location information of the target total command; determining at least one sub-command corresponding to the target total command according to the target start address, the target data length, a preset strip size, and the storage location information, wherein each of the sub-commands comprises a sub-start address and a sub-data length; determining first strip identification information of a first sub-command according to the sub-start address included in the first sub-command and the strip size, wherein the first sub-command is any one of the at least one sub-command; acquiring a target correspondence table of numbers and allocation index values of hardware computing accelerators; determining a target hardware computing accelerator from a plurality of pre-constructed hardware computing accelerators according to the first strip identification information, a preset allocation algorithm, and the target correspondence table; allocating the first sub-command to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first sub-command to obtain a return result corresponding to the first sub-command.

2. The method of claim 1, wherein, The determining at least one sub-start address and a sub-data length corresponding to each of the sub-start addresses according to the target start address, the target data length, and the strip size comprises: determining at least one sub-start address and a sub-data length corresponding to each of the sub-start addresses according to the target start address, the target data length, and the strip size; determining an order of each of the sub-start addresses according to a size of each of the sub-start addresses; generating a sub-command corresponding to each of the sub-start addresses according to the storage location information of the target total command, each of the sub-start addresses, a sub-data length corresponding to each of the sub-start addresses, and the order of each of the sub-start addresses.

3. The method of claim 2, wherein, The determining at least one sub-start address and a sub-data length corresponding to each of the sub-start addresses according to the target start address, the target data length, and the strip size comprises: determining a target strip offset according to the target start address and the strip size; determining the target start address as a first sub-start address in a first processing round; determining a first sub-data length corresponding to the first sub-start address according to the strip size and the target strip offset; determining whether the first sub-data length is less than the target data length; when it is determined that the first sub-data length is equal to the target data length, ending the processing to obtain one sub-start address and one sub-data length.

4. The method of claim 3, wherein, The method further comprises: when it is determined that the first sub-data length is less than the target data length, entering a next processing round corresponding to the first processing round; in a current processing round in a non-first processing round, determining a sub-start address of the current processing round according to a sub-start address and a sub-data length corresponding to a previous processing round corresponding to the current processing round; determining a remaining data length according to the target data length and the sub data lengths corresponding to all processing rounds before the current processing round; determining whether the remaining data length is greater than the strip size; when the remaining data length is greater than the strip size, determining the strip size as the sub data length of the current processing round, and entering a next processing round.

5. The method of claim 4, wherein, The method further comprises: when it is determined that the remaining data length is less than or equal to the strip size, determining the remaining data length as the sub data length of the current processing round, and ending the processing to obtain a plurality of sub start addresses and a sub data length corresponding to each of the plurality of sub start addresses.

6. The method according to any one of claims 2 to 5, characterized in that, The target total command further comprises split indication information, and the split indication information comprises a plurality of bits. After the sub command corresponding to each of the sub start addresses is generated according to the storage location information of the target total command, each of the sub start addresses, the sub data length corresponding to each of the sub start addresses, and the order of each of the sub start addresses, the method further comprises: determining, according to the order of each of the sub start addresses, a bit corresponding to the order of each of the sub start addresses in the plurality of bits; setting the bit corresponding to the order of each of the sub start addresses as a first preset value, and the first preset value is used to indicate that the first sub command is not processed by any hardware computing accelerator.

7. The method according to any one of claims 1 to 5, characterized in that, The determining of the target hardware computing accelerator from the plurality of pre-constructed hardware computing accelerators according to the first strip identifier information, a preset allocation algorithm, and the target correspondence table comprises: determining a target allocation index value according to the first strip identifier information and the preset allocation algorithm; determining whether there is a target number corresponding to the target allocation index value in the target correspondence table; when it is determined that there is a target number corresponding to the target allocation index value in the target correspondence table, determining the hardware computing accelerator corresponding to the target number as the target hardware computing accelerator.

8. The method of claim 7, wherein, When it is determined that there is no target number corresponding to the target allocation index value in the target correspondence table, the method further comprises: obtaining the number of sub commands not completed by each of the plurality of hardware computing accelerators; determining the target hardware computing accelerator according to the number of sub commands not completed by each of the hardware computing accelerators.

9. The method of claim 8, wherein, The determining of the target hardware computing accelerator according to the number of sub commands not completed by each of the hardware computing accelerators comprises: determining a hardware computing accelerator with the least number of sub commands not completed according to the number of sub commands not completed by each of the hardware computing accelerators; when the hardware computing accelerator with the least number of sub commands not completed is one, directly determining the hardware computing accelerator with the least number of sub commands not completed as the target hardware computing accelerator; or ​ When the number of hardware computing accelerators with the least number of sub-commands is multiple, the hardware computing accelerator with the smallest number is selected from the multiple hardware computing accelerators with the least number of sub-commands as the target hardware computing accelerator.

10. The method of claim 6, wherein, The method further comprises: After the target hardware computing accelerator processes the first sub-command, the storage location information of the target total command and the order of the first sub-starting address are extracted from the first sub-command; The target total command is determined according to the storage location information of the target total command; The first bit position corresponding to the order of the first sub-starting address is determined in the multiple bit positions of the target total command according to the order of the first sub-starting address; The first bit position is set to a second preset value, wherein the second preset value is used to indicate that the first sub-command has been processed by the target hardware computing accelerator.

11. The method according to any one of claims 1 to 5, characterized in that, The first sub-command is distributed to the target hardware computing accelerator, comprising: The first sub-command is added to the tail of the target queue corresponding to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first sub-command when it is determined according to the order of each sub-command in the target queue that the processing order of the first sub-command is due, and obtains the return result corresponding to the first sub-command.

12. The method of claim 10, wherein, The target total command is obtained, comprising: The target host command sent by the host end is obtained; A preset total command data structure is obtained; The target host command is converted to obtain the target total command according to the total command data structure.

13. The method of claim 12, wherein, After the first bit position is set to the second preset value, the method further comprises: Determine whether the value of each bit position of the target total command is the second preset value; When it is determined that the value of each bit position in the split indication information of the target total command is the second preset value, the return result corresponding to at least one sub-command corresponding to the target total command is obtained; According to the return result corresponding to at least one sub-command corresponding to the target total command, the total return result corresponding to the target total command is determined; The total return result is fed back to the host end.

14. The method of claim 7, wherein, The target allocation index value is determined according to the first stripe identification information and the preset allocation algorithm, which adopts the following expression: Hash Key = StripeID % K Wherein, Hash Key is the target allocation index value, StripeID is the first stripe identification information, and K is a third preset value.

15. The method of claim 8, wherein, After the target hardware computing accelerator is determined according to the number of sub-commands not completed by each hardware computing accelerator, the method further comprises: The number of the target hardware computing accelerator is obtained; The target correspondence table is updated according to the target allocation index value and the number of the target hardware computing accelerator.

16. The method according to any one of claims 1 to 5, characterized in that, The first stripe identification information of the first sub-command is determined according to the sub-starting address included in the first sub-command and the stripe size, which adopts the following expression: StripeID=ZSLBA%Stripe_Length Wherein, the StripeID is the first stripe identification information, the ZSLBA is the sub-starting address included in the first sub-command, and the Stripe_Length is the stripe size.

17. A command distribution apparatus characterized by comprising: The device comprises: An acquisition module, configured to acquire a target total command and acquire storage location information of the target total command, wherein the target total command comprises a target starting address and a target data length; A determination module, configured to determine at least one sub-command corresponding to the target total command according to the target starting address, the target data length, a preset stripe size, and the storage location information, wherein each of the sub-commands comprises a sub-starting address and a sub-data length; determine first stripe identification information of a first sub-command according to a sub-starting address included in the first sub-command and the stripe size, wherein the first sub-command is any one of the at least one sub-command; The acquisition module is further configured to acquire a target correspondence table of a number and an allocation index value of a hardware computing accelerator; The determination module is further configured to determine a target hardware computing accelerator from a plurality of pre-constructed hardware computing accelerators according to the first stripe identification information, a preset allocation algorithm, and the target correspondence table; An allocation module, configured to allocate the first sub-command to the target hardware computing accelerator, so that the target hardware computing accelerator processes the first sub-command to obtain a return result corresponding to the first sub-command.

18. A computer device, comprising: Comprise: A memory and a processor, which are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the command allocation method in any one of claims 1 to 16.

19. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions, and the computer instructions are used to make a computer execute the command allocation method in any one of claims 1 to 16.

20. A computer program product, characterised in that, The computer instructions are used to make a computer execute the command allocation method in any one of claims 1 to 16.

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