A heterogeneous many-core chip task scheduling method for realizing core group pre-judgment frequency modulation

Abstract

The application discloses a heterogeneous many-core chip task scheduling method for realizing core group pre-judgment frequency modulation, and relates to the field of heterogeneous many-core chips. In the heterogeneous many-core chip task scheduling method, when a main core issues a to-be-executed task to a task storage space, task description information is added to each to-be-executed task, so that when a task scheduler schedules and allocates any target to-be-executed task, the task frequency and whether the target to-be-executed task contains a predetermined instruction can be determined in advance according to the task description information of the target to-be-executed task, and in the case that the execution performance of the target to-be-executed task by a target slave core group is not ideal, a frequency modulation request interruption is initiated to trigger a frequency modulation management module to adjust the working clock of the target slave core group, so that the target slave core group can execute the target to-be-executed task at a working frequency matched with the task frequency of the target to-be-executed task, thereby optimizing the execution performance of the target to-be-executed task and avoiding risks such as instantaneous large current during task execution.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of heterogeneous many-core chips, and particularly relates to a heterogeneous many-core chip task scheduling method for realizing core group pre-judgment frequency adjustment. BACKGROUND

[0002] Heterogeneous many-core chips adopt a combination of master cores and slave cores to process various computing tasks, and generally the master cores are used to issue tasks and the slave cores are used to execute tasks. The cooperation of the master cores and the slave cores can provide higher computing power, computing density and performance power ratio, and thus is widely applied in various high-performance computing systems.

[0003] With the continuous improvement of chip working frequency and integration, chip power consumption gradually increases, and thus various frequency adjustment and temperature adjustment technologies are applied to chips. By adjusting the working frequency of the chip, the chip power consumption can be effectively reduced to meet the low power consumption requirement. The existing heterogeneous many-core chips also introduce frequency adjustment and temperature adjustment technologies. A scheduling subsystem is used in the heterogeneous many-core chips to be responsible for task scheduling, so as to allocate the tasks issued by the master cores to appropriate slave cores for execution. In addition, the scheduling subsystem also uses a dynamic voltage and frequency scaling (DVFS) technology to adjust the working frequency of the slave cores according to the task load of the slave cores, that is, the scheduling subsystem monitors the task load on the slave cores in real time. When the task load on the slave cores is low, the working frequency of the slave cores is adjusted to be low. When the task load running on the slave cores is high, the working frequency of the slave cores is adjusted to be high, so that the slave cores work at different frequencies according to the actual task load requirement. However, because the tasks executed by the slave cores are complex and diverse, the working frequency of the slave cores will affect the performance of the slave cores when executing different tasks. Therefore, adjusting the working frequency of the slave cores only according to the task load running on the slave cores will affect the execution performance of the slave cores on the tasks, and even cause a transient large current overshoot of the slave cores when executing the tasks, resulting in a voltage transient drop and thus causing power failure and card drop. At this time, a restart is needed, which affects the normal operation of the chip and the entire system. SUMMARY

[0004] In view of the above problems and technical requirements, the present application provides a heterogeneous many-core chip task scheduling method for realizing core group pre-judgment frequency adjustment. The technical scheme of the present application is as follows:

[0005] The present application provides a heterogeneous many-core chip task scheduling method for realizing core group pre-judgment frequency adjustment. The heterogeneous many-core chip includes a master core and a plurality of slave cores. Each slave core group includes a plurality of slave cores constituting an array. The heterogeneous many-core chip further includes a task scheduler, a frequency adjustment management module and a task storage space. The heterogeneous many-core chip task scheduling method includes the following steps:

[0006] The main core adds corresponding task description information to each to-be-executed task, and then sends the to-be-executed task to a task storage space; the task description information corresponding to each to-be-executed task carries a task frequency of the to-be-executed task and an interrupt valid identifier; the main core sets the interrupt valid identifier to a valid value when detecting that the to-be-executed task contains a predetermined instruction; the predetermined instruction is an instruction that has a risk of transient current overshoot;

[0007] The task scheduler reads a target to-be-executed task from the task storage space and parses the corresponding task description information to determine the task frequency and the interrupt valid identifier of the target to-be-executed task; the task scheduler initiates a frequency adjustment interrupt request to the frequency adjustment management module when determining that the task frequency of the target to-be-executed task does not match the clock frequency of the current working clock of the target slave core group and determining that the interrupt valid identifier of the target to-be-executed task is a valid value; the target slave core group is a slave core group used to execute the target to-be-executed task;

[0008] The frequency adjustment management module reads the task frequency of the target to-be-executed task from the task scheduler in response to the received frequency adjustment interrupt request, and controls the clock module to adjust the clock frequency of the working clock provided to the target slave core group to match the task frequency;

[0009] The target slave core group executes the target to-be-executed task assigned by the task scheduler according to the working clock provided by the clock module.

[0010] Further, the task description information corresponding to each to-be-executed task further carries a synchronization identifier, and the main core configures the synchronization identifier according to the instruction execution order of the predetermined instruction in the to-be-executed task; the task scheduler parses the synchronization identifier from the task description information corresponding to the target to-be-executed task, and assigns the target to-be-executed task to the target slave core group according to the working mode matched by the synchronization identifier.

[0011] Further, the main core configures the synchronization identifier according to the instruction execution order of the predetermined instruction in the to-be-executed task includes:

[0012] The estimated execution time of the slave core completing program initialization and executing to the predetermined instruction according to the instruction execution order of the to-be-executed task, and the estimated frequency adjustment time of the frequency adjustment management module controlling the clock module to adjust the clock frequency of the working clock provided to the slave core to match the task frequency;

[0013] In the case where the estimated execution time is greater than the estimated frequency adjustment time, the synchronization identifier is set to a valid value, otherwise the synchronization identifier is set to an invalid value.

[0014] Further, the task scheduler assigns the target to-be-executed task to the target slave core group according to the working mode matched by the synchronization identifier includes:

[0015] When the task scheduler parses the synchronization identifier as a valid value, the task scheduler allocates the target to-be-executed task to the target slave core group when initiating a frequency adjustment interrupt request to the frequency adjustment management module;

[0016] In the process of the frequency adjustment management module controlling the clock module to adjust the clock frequency of the working clock provided to the target slave core group, the target slave core group performs program initialization and executes each instruction in the target to-be-executed task in sequence according to the instruction execution order of the target to-be-executed task after completing the program initialization; and before the target slave core group executes a predetermined instruction in the target to-be-executed task, the frequency adjustment management module completes the adjustment of the clock frequency of the working clock of the target slave core group.

[0017] A further technical solution is that the task scheduler allocates the target to-be-executed task to the target slave core group according to the working mode matched by the synchronization identifier, including:

[0018] When the task scheduler parses the synchronization identifier as an invalid value, the task scheduler initiates a frequency adjustment interrupt request to the frequency adjustment management module and waits until it is determined that the frequency adjustment management module completes the adjustment of the clock frequency of the working clock of the target slave core group, and then allocates the target to-be-executed task to the target slave core group.

[0019] A further technical solution is that the heterogeneous many-core chip task scheduling method further includes:

[0020] The frequency adjustment management module clears the frequency adjustment interrupt request initiated by the task scheduler after controlling the clock module to adjust the clock frequency of the working clock provided to the target slave core group to match the task frequency;

[0021] The task scheduler determines that the frequency adjustment management module completes the adjustment of the clock frequency of the working clock of the target slave core group after detecting that the frequency adjustment interrupt request is cleared.

[0022] A further technical solution is that the master core adds an interrupt valid identifier to each to-be-executed task, including:

[0023] The master core sets the interrupt valid identifier as a valid value when detecting that the to-be-executed task does not contain a predetermined instruction and the frequency adjustment management module is in a normal frequency adjustment state;

[0024] The master core sets the interrupt valid identifier as an invalid value when detecting that the to-be-executed task does not contain a predetermined instruction and the frequency adjustment management module is in a shielded frequency adjustment state.

[0025] A further technical solution is that each slave core group is connected to multiple clock sources in the clock module, and the frequency adjustment management module controls the clock module to adjust the clock frequency of the working clock provided to the target slave core group to match the task frequency, including:

[0026] The frequency adjustment management module detects a clock frequency of a real-time working clock provided by a clock source currently connected to the target slave core group to the target slave core group;

[0027] When the clock frequency of the real-time working clock of the target slave core group matches the task frequency of the task to be executed by the target, the frequency adjustment management module keeps the real-time working clock of the target slave core group unchanged and determines that the clock frequency adjustment of the working clock of the target slave core group is completed;

[0028] When the clock frequency of the real-time working clock of the target slave core group does not match the task frequency of the task to be executed by the target, but there is a working clock provided by another clock source connected to the target slave core group, and the clock frequency of the working clock matches the task frequency of the task to be executed by the target, the frequency adjustment management module controls switching to the working clock provided by the other clock source to the target slave core group, and determines that the clock frequency adjustment of the working clock of the target slave core group is completed;

[0029] When the clock frequency of the real-time working clock of the target slave core group does not match the task frequency of the task to be executed by the target, and the clock frequency of the working clock provided by all clock sources connected to the target slave core group does not match the task frequency of the task to be executed by the target, the frequency adjustment management module controls the clock source currently connected to the target slave core group to adjust the clock frequency of the working clock provided to the target slave core group to match the task frequency.

[0030] Further, the technical scheme is that the task scheduler detects whether the task frequency of the task to be executed by the target matches the clock frequency of the working clock of the target slave core group currently.

[0031] When the task scheduler detects that the task frequency of the task to be executed by the target matches the task frequency of the last task to be executed by the target slave core group, the task scheduler determines that the task scheduler detects that the task frequency of the task to be executed by the target matches the clock frequency of the working clock of the target slave core group currently, otherwise the task scheduler determines that the task scheduler detects that the task frequency of the task to be executed by the target does not match the clock frequency of the working clock of the target slave core group currently.

[0032] Further, the technical scheme is that the heterogeneous many-core chip task scheduling method further includes:

[0033] When the task scheduler determines that the task frequency of the task to be executed by the target matches the clock frequency of the working clock of the target slave core group currently, or detects that the interrupt valid identifier of the task to be executed by the target is an invalid value, the task scheduler directly assigns the task to be executed by the target to the corresponding target slave core group.

[0034] The beneficial technical effects of the present application are:

[0035] The application discloses a heterogeneous many-core chip task scheduling method for realizing core group pre-judgment frequency modulation.

[0036] The task description information added by the master core to each to-be-executed task further includes a synchronization identifier related to an instruction execution sequence in which the predetermined instruction is located, and the task scheduler can synchronously issue the target to-be-executed task according to the synchronization identifier, or first initiates the frequency modulation request interrupt and then issues the target to-be-executed task after waiting for the frequency modulation to be completed, so that different working modes are adopted according to different conditions of the predetermined instruction included in the target to-be-executed task, the efficiency of task execution is improved, and the waiting time caused by frequency modulation is reduced on the premise of avoiding risks such as instantaneous large current during task execution.

[0037] The method is analyzed by the task scheduler and implemented by the task scheduler, the frequency modulation operation is performed by the frequency modulation management module, the frequency modulation management module performs frequency modulation under the interruption of the task scheduler, real-time monitoring of the operation of the slave core is not needed, and the occupation of the frequency modulation management module is reduced. The frequency modulation operation of the slave core is completed by the frequency modulation management module, and the slave core itself does not participate in the frequency modulation, so the slave core will not be disturbed in the frequency modulation process and can normally execute programs, and the influence of the frequency modulation process on the task execution process of the slave core is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 is a system architecture block diagram in an embodiment of the application.

[0039] Figure 2 is an execution method flowchart of the task scheduler in an embodiment of the application.

[0040] Figure 3 is a heterogeneous many-core chip task scheduling method flowchart in an embodiment of the application.

[0041] Figure 4 is an execution method flowchart of the task scheduler in another embodiment of the application.

[0042] Figure 5 is another embodiment of the application. DETAILED DESCRIPTION

[0043] The specific embodiments of the application will be further described below with reference to the accompanying drawings.

[0044] The application discloses a heterogeneous many-core chip task scheduling method for realizing core group pre-judgment frequency modulation. The heterogeneous many-core chip comprises a master core and a plurality of slave core groups, each of which comprises a plurality of slave cores constituting an array. All the slave cores in the same slave core group use the same working clock and are used to jointly complete a task.

[0045] The heterogeneous many-core chip of the application further comprises a task scheduler, a frequency modulation management module and a task storage space. Please refer to the system structure diagram shown in Figure 1 The master core can read and write the task storage space, and the task scheduler can read and write the task storage space. The task scheduler and the frequency modulation management module realize communication, and the task scheduler also realizes communication with the slave core. The frequency modulation management module is connected with and controls a clock module for providing a working clock for the slave core in the heterogeneous many-core chip.

[0046] Based on Figure 1 the system structure diagram shown, the heterogeneous many-core chip task scheduling method comprises the following processes:

[0047] 1. The master core adds corresponding task description information to each to-be-executed task, and then issues the to-be-executed task carrying the task description information to the task storage space.

[0048] The task description information corresponding to each to-be-executed task carries the task frequency of the to-be-executed task and an interrupt valid identifier. The master core sets the interrupt valid identifier to a valid value when detecting that the to-be-executed task contains a predetermined instruction.

[0049] The master core can directly determine the task frequency of each to-be-executed task when generating the to-be-executed task. In actual implementation, the task frequency of each to-be-executed task is usually a frequency interval. Therefore, one embodiment uses a frequency gear value to represent the task frequency of the to-be-executed task. Different frequency gear values represent different frequency intervals, and the frequency gear value can be self-defined. The frequency gear value of the task frequency of each to-be-executed task is included in the task description information corresponding to the to-be-executed task.

[0050] In addition, the main core also analyzes the instructions in the to-be-executed task to add the interrupt valid identifier to the to-be-executed task, and sets the interrupt valid identifier to a valid value when detecting that the to-be-executed task contains a predetermined instruction. The predetermined instruction is an instruction that has a risk of transient current overshoot, that is, an instruction that is prone to generate a large transient current. If multiple slave cores in the same slave core group execute the predetermined instruction, it is easy to cause a voltage drop and a risk of transient current. Therefore, when the to-be-executed task contains the predetermined instruction, it indicates that the slave core group is more likely to generate a risk of transient current overshoot when executing the to-be-executed task. The specific instructions that belong to the predetermined instruction are preconfigured.

[0051] When it is detected that the to-be-executed task does not contain the predetermined instruction, it indicates that the slave core group has a low risk of generating a transient current overshoot when executing the to-be-executed task. One way is to directly set the interrupt valid identifier to an invalid value. In another embodiment, considering that when the working frequency of the slave core group does not match the task frequency of the to-be-executed task, even if the slave core group has a low risk of generating a transient current overshoot when executing the to-be-executed task, due to the problem of frequency mismatch, the performance of the slave core group when executing the to-be-executed task is not ideal, and therefore the interrupt valid identifier can also be set to a valid value.

[0052] Or in another embodiment, since the application needs to use a frequency modulation management module to control the adjustment of the working frequency of the slave core group, the main core detects the working state of the frequency modulation management module and determines whether to set the interrupt valid identifier to a valid value or an invalid value according to the working state of the frequency modulation management module, including:

[0053] When the main core detects that the to-be-executed task does not contain the predetermined instruction and the frequency modulation management module is in a normal frequency modulation state, the main core sets the interrupt valid identifier to a valid value. The normal frequency modulation state of the frequency modulation management module is a state in which the frequency modulation management module can normally adjust the working frequency of the slave core group. At this time, although the slave core group has a small risk of generating a transient current overshoot when executing the to-be-executed task, the performance of the slave core group when executing the to-be-executed task is still prioritized to set the interrupt valid identifier to a valid value.

[0054] When the main core detects that the to-be-executed task does not contain the predetermined instruction and the frequency modulation management module is in a shielding frequency modulation state, the main core sets the interrupt valid identifier to an invalid value. The shielding frequency modulation state of the frequency modulation management module is a state in which the frequency modulation management module is busy or executing other transactions. At this time, since the slave core group has a small risk of generating a transient current overshoot when executing the to-be-executed task, the execution performance of the to-be-executed task is temporarily reduced under the condition of meeting the safety, and therefore the interrupt valid identifier is set to an invalid value.

[0055] 2、The main core issues to the task storage space in each of the tasks to be executed by the task scheduler to read and schedule the delivery. For the convenience of description, the definition of the task scheduler to read the target to be executed task, the task scheduler will first determine the target slave core group, the target slave core group is used to execute one of the slave core group of the target to be executed task, this part is similar to the existing practice, can be determined according to the task load of each slave core group which slave core group as the target slave core group, this application does not repeat. In actual operation, the task scheduler will manage and schedule multiple slave core groups. Different target to be executed tasks may be assigned to different target slave core groups, but the task scheduling process is the same.

[0056] Since the task to be executed in the main core of the present application is issued to the task scheduler, the target to be executed task read from the task storage space also carries the task description information, and the task scheduler does not directly issue the target to be executed task to the target slave core group, but first analyzes the task description information of the target to be executed task to determine the task frequency and the interrupt effective identifier of the target to be executed task.

[0057] 3、The task scheduler determines that the task frequency of the target to be executed task does not match the clock frequency of the current working clock of the target slave core group, and determines that the interrupt effective identifier of the target to be executed task is a valid value. The task scheduler can predict that the execution performance of the target slave core group executing the target to be executed task according to the current working clock is not ideal, and initiates a frequency adjustment interrupt request to the frequency adjustment management module. Please refer to the execution flow diagram of the task scheduler shown in Figure 2 and the task scheduling flow diagram in this case shown in Figure 3 .

[0058] In this step, when the difference between the task frequency of the target to be executed task and the clock frequency of the current working clock of the target slave core group reaches the frequency difference threshold, it is determined that the task frequency of the target to be executed task does not match the clock frequency of the current working clock of the target slave core group, otherwise it is determined that the task frequency of the target to be executed task matches the clock frequency of the current working clock of the target slave core group.

[0059] When the interrupt valid identifier of the target to-be-executed task is a valid value, it indicates that the target to-be-executed task contains a predetermined instruction that has a risk of transient current overshoot, at this time, if the task frequency of the target to-be-executed task does not match the clock frequency of the current working clock of the target slave core group, the target slave core group has a very high risk of abnormal conditions such as transient current overshoot when executing the target to-be-executed task, and the clock frequency of the working clock of the target slave core group must be adjusted to ensure that the target to-be-executed task is in its required task frequency range during execution, thereby avoiding abnormal conditions such as transient current overshoot and enabling the target slave core group to execute the target to-be-executed task with better performance.

[0060] Since the task scheduler cannot directly detect the actual clock frequency of the working clock of the target slave core group, the task scheduler infers the current clock frequency of the working clock of the target slave core group through the task frequency of each task that has been assigned to the target slave core group. In an embodiment, the task scheduler registers the task frequency of the last task assigned to each slave core group, and then reads the registered task frequency of the last to-be-executed task assigned to the target slave core group. When it is detected that the task frequency of the target to-be-executed task matches the task frequency of the last to-be-executed task assigned to the target slave core group, it is determined that the task scheduler detects that the task frequency of the target to-be-executed task matches the clock frequency of the current working clock of the target slave core group, otherwise it is determined that the task scheduler detects that the task frequency of the target to-be-executed task does not match the clock frequency of the current working clock of the target slave core group. As described above, the task frequency of each to-be-executed task is usually represented by a corresponding frequency level value, so when the frequency level value of the target to-be-executed task matches the frequency level value of the last to-be-executed task assigned to the target slave core group, it indicates that the two clock frequencies match.

[0061] When the task scheduler determines that the task frequency of the target to-be-executed task matches the clock frequency of the current working clock of the target slave core group, or detects that the interrupt valid identifier of the target to-be-executed task is an invalid value, the task scheduler can predict that the execution performance of the target slave core group executing the target to-be-executed task directly according to the current working clock is better, and then directly assigns the target to-be-executed task to the corresponding target slave core group.

[0062] 4. The frequency adjustment management module reads the task frequency of the target to-be-executed task from the task scheduler in response to the received frequency adjustment interrupt request, and controls the clock module to adjust the clock frequency of the working clock provided to the target slave core group to match the task frequency.

[0063] The frequency adjustment operation of the frequency adjustment management module is triggered by the task scheduler actively reporting the frequency adjustment interrupt request, and the frequency adjustment management module does not need to monitor the task scheduling process in real time, thereby reducing the occupation time of the frequency adjustment management module.

[0064] The frequency adjustment management module first detects the clock frequency of the real-time working clock provided by the clock source currently connected to the target slave core group to the target slave core group when the control clock module adjusts the clock frequency of the working clock provided to the target slave core group to match the task frequency. As described above, when the task scheduler compares the task frequency of the task to be executed by the target with the clock frequency of the current working clock of the target slave core group, the task frequency of the last task assigned to the target slave core group is taken as the clock frequency of the current working clock of the target slave core group. However, the clock frequency of the target slave core group thus determined is only a theoretical value, and the clock frequency of the real-time working clock actually adopted by the target slave core group can not be equal to the theoretical value. For example, the target slave core group can automatically reduce the clock frequency due to chip overheating during the execution of the last task, which can cause the real-time working clock of the target slave core group to be lower than the theoretical clock frequency determined by the task scheduler.

[0065] Therefore, after the frequency adjustment management module receives the frequency adjustment interrupt request, it does not directly perform the frequency adjustment operation, but further detects the clock frequency of the real-time working clock of the target slave core group and determines whether the clock frequency of the real-time working clock matches the task frequency of the task to be executed by the target.

[0066] When the clock frequency of the real-time working clock of the target slave core group matches the task frequency of the task to be executed by the target, the frequency adjustment management module directly keeps the real-time working clock of the target slave core group unchanged and determines that the adjustment of the clock frequency of the working clock of the target slave core group is completed.

[0067] When the clock frequency of the real-time working clock of the target slave core group does not match the task frequency of the task to be executed by the target, the frequency adjustment management module first detects whether there is a working clock provided by another clock source in the clock sources connected to the target slave core group, the clock frequency of which matches the task frequency of the task to be executed by the target. This is because in a heterogeneous many-core chip, the clock module generally uses multiple clock sources to provide working clocks to the same slave core group, so each slave core group is connected to multiple clock sources in the clock module, and different clock sources output different working clocks. When there is a working clock provided by another clock source in the clock sources connected to the target slave core group, the clock frequency of which matches the task frequency of the task to be executed by the target, the working clock output by the clock source does not need to be adjusted at this time. The frequency adjustment management module only needs to control the switching to the working clock provided by the other clock source to the target slave core group, which matches the task frequency of the task to be executed by the target, and does not need to truly adjust the clock source. After adjustment, it can be determined that the adjustment of the clock frequency of the working clock of the target slave core group is completed.

[0068] When the clock frequency of the working clock provided by the clock source connected to the target slave core group does not match the task frequency of the target task to be executed, and the frequency adjustment management module detects that the clock frequencies of the working clocks provided by all the clock sources connected to the target slave core group do not match the task frequency of the target task to be executed, the clock source switching method is not feasible, and the frequency adjustment management module controls the clock source currently connected to the target slave core group to adjust the clock frequency of the working clock provided to the target slave core group to match the task frequency.

[0069] After the frequency adjustment management module controls the clock module to adjust the clock frequency of the working clock provided to the target slave core group to match the task frequency, the frequency adjustment interrupt request initiated by the task scheduler is cleared.

[0070] 5. The target slave core group executes the target task to be executed assigned by the task scheduler according to the working clock provided by the clock module. After the target slave core group executes the target task to be executed, the task scheduler writes the task execution result of the target task to be executed into the task storage space and receives the write feedback returned by the task storage space.

[0071] In one embodiment, after the task scheduler initiates the frequency adjustment interrupt request to the frequency adjustment management module, the task scheduler waits until it is determined that the frequency adjustment management module completes the adjustment of the clock frequency of the working clock of the target slave core group, and then assigns the target task to be executed to the target slave core group, so that the target slave core group can execute the target task to be executed according to the adjusted clock frequency, avoiding the risk of instantaneous current overshoot and improving the task execution efficiency. When the task scheduler detects that the frequency adjustment interrupt request is cleared, it is determined that the frequency adjustment management module completes the adjustment of the clock frequency of the working clock of the target slave core group, Figure 2 and Figure 3 the flowchart is taken as an example.

[0072] However, in order to improve the task execution efficiency, it is considered that the risk of instantaneous large current is often caused by the target slave core group executing the predetermined instructions according to the unmatched working frequency, so as long as the target slave core group can execute the predetermined instructions according to the working frequency matched with the task frequency, the risk of instantaneous large current can be avoided. Therefore, in another embodiment, the master core adds a synchronization identifier to the task description information of each task to be executed, and the master core configures the synchronization identifier according to the instruction execution order of the predetermined instructions in the task to be executed. Thus, when the task scheduler parses the task description information corresponding to the target task to be executed, the synchronization identifier can also be obtained, and the target task to be executed is assigned to the target slave core group according to the matched working mode of the synchronization identifier. In this embodiment, the task scheduler can adopt two different working modes according to different values of the synchronization identifier: the target task to be executed is issued synchronously with the frequency adjustment interrupt request, or the target task to be executed is issued after the frequency adjustment management module completes the adjustment of the clock frequency of the working clock of the target slave core group.

[0073] When a slave core group executes a task, it first performs program initialization. After initialization, it executes the instructions in the task sequentially. In one embodiment, the master core estimates the estimated execution time for the slave core group to complete program initialization and execute the instructions in the order of the task to be executed up to the predetermined instructions. The estimated frequency modulation management module controls the clock module to adjust the clock frequency provided to the slave core group to match the estimated frequency modulation time. If the estimated execution time is greater than the estimated frequency modulation time, the synchronization identifier is set to a valid value; otherwise, the synchronization identifier is set to an invalid value.

[0074] In this embodiment, when the synchronization identifier parsed by the task scheduler is a valid value, it indicates that the estimated execution time of the target slave core group in executing the target task is greater than the estimated frequency modulation time. Even if the target slave core group and the frequency modulation management module start working synchronously, by the time the target slave core group completes program initialization and executes the predetermined instruction of the target task, the frequency modulation management module has already completed the frequency modulation action. This ensures that the target slave core group is using a working clock that matches the task frequency of the target task when executing the predetermined instruction. Therefore, when the task scheduler initiates a frequency modulation interrupt request to the frequency modulation management module, it synchronously allocates the target task to the target slave core group. Since the target slave core group passively adjusts its working clock and does not participate in the frequency modulation process, it can execute the program normally during the frequency modulation process of the frequency modulation management module. During the process of the frequency modulation management module controlling the clock module to adjust the clock frequency provided to the target slave core group, the target slave core group performs program initialization. After completing program initialization, it executes each instruction in the target task in the order of instruction execution. Furthermore, before the target slave core group executes the predetermined instructions in the target task, the frequency modulation management module has already adjusted the clock frequency of the target slave core group's working clock. This approach can improve task execution efficiency while ensuring task execution performance and avoiding excessive waiting time. Figure 4 The execution flowchart of the task scheduler shown is as follows: Figure 5 The task scheduling flowchart shown is based on this scenario.

[0075] When the synchronization identifier parsed by the task scheduler is an invalid value, it indicates that the estimated execution time of the target slave core group to execute the task to be executed by the target is not greater than the estimated frequency adjustment time. At this time, if the target slave core group and the frequency adjustment management module start working synchronously, when the target slave core group completes program initialization and executes the scheduled instruction of the task to be executed by the target, the frequency adjustment management module has not completed the adjustment of the clock frequency of the working clock of the target slave core group. The target slave core group executes the scheduled instruction according to the unmatched working clock, which may cause a risk of instantaneous large current. Therefore, after the task scheduler initiates a frequency adjustment interrupt request to the frequency adjustment management module, the task scheduler waits until it is determined that the frequency adjustment management module has completed the adjustment of the clock frequency of the working clock of the target slave core group, and then allocates the task to be executed by the target to the target slave core group, so as to ensure safety and task execution performance.

[0076] The above is only the preferred embodiment of the present application, and the present application is not limited to the above embodiments. It can be understood that other improvements and changes directly derived or thought of by those skilled in the art without departing from the spirit and concept of the present application should be considered to be within the scope of protection of the present application.

Claims

1. A heterogeneous many-core chip task scheduling method for implementing core group pre-judgment frequency modulation, the heterogeneous many-core chip comprising a master core and a plurality of slave core groups, each slave core group comprising a plurality of slave cores constituting an array, characterized by, The heterogeneous many-core chip further comprises a task scheduler, a frequency management module and a task storage space, and the task scheduling method of the heterogeneous many-core chip comprises: The master core adds corresponding task description information to each item of the to-be-executed task, and then issues the to-be-executed task to the task storage space; the task description information corresponding to each item of the to-be-executed task carries the task frequency of the to-be-executed task and an interrupt valid identifier, and the master core sets the interrupt valid identifier to a valid value when detecting that the to-be-executed task contains a predetermined instruction; wherein the predetermined instruction is an instruction that has a risk of transient current overshoot; The task scheduler reads a target to-be-executed task from the task storage space and parses the corresponding task description information to determine the task frequency and the interrupt valid identifier of the target to-be-executed task; the task scheduler initiates a frequency adjustment interrupt request to the frequency management module when determining that the task frequency of the target to-be-executed task does not match the clock frequency of the current working clock of the target slave core group and determining that the interrupt valid identifier of the target to-be-executed task is a valid value; the target slave core group is a slave core group used for executing the target to-be-executed task; The frequency management module reads the task frequency of the target to-be-executed task from the task scheduler in response to the received frequency adjustment interrupt request, and controls the clock module to adjust the clock frequency of the working clock provided to the target slave core group to match the task frequency; The target slave core group executes the target to-be-executed task assigned by the task scheduler according to the working clock provided by the clock module.

2. The heterogeneous many-core chip task scheduling method according to claim 1, characterized in that, The task description information corresponding to each item of the to-be-executed task further carries a synchronization identifier, and the master core configures the synchronization identifier according to the instruction execution order of the predetermined instruction in the to-be-executed task; the task scheduler parses the synchronization identifier from the task description information corresponding to the target to-be-executed task, and assigns the target to-be-executed task to the target slave core group according to the working mode matched by the synchronization identifier.

3. The heterogeneous many-core chip task scheduling method of claim 2, wherein, The master core configuring the synchronization identifier according to the instruction execution order of the predetermined instruction in the to-be-executed task comprises: estimating the estimated execution time of the slave core group completing program initialization and executing to the predetermined instruction according to the instruction execution order of the to-be-executed task, and estimating the estimated frequency adjustment time of the frequency management module controlling the clock module to adjust the clock frequency of the working clock provided to the slave core group to match the task frequency; setting the synchronization identifier to a valid value in the case that the estimated execution time is greater than the estimated frequency adjustment time, and otherwise setting the synchronization identifier to an invalid value.

4. The heterogeneous many-core chip task scheduling method of claim 3, wherein, The task scheduler assigning the target to-be-executed task to the target slave core group according to the working mode matched by the synchronization identifier comprises: when the synchronization identifier parsed by the task scheduler is a valid value, the task scheduler synchronously assigns the target to-be-executed task to the target slave core group when initiating the frequency adjustment interrupt request to the frequency management module; In the process that the frequency management module controls the clock module to adjust the clock frequency of the working clock provided to the target slave core group, the target slave core group performs program initialization and executes instructions in the target to-be-executed task in sequence according to the execution order of the instructions in the target to-be-executed task after completing the program initialization; and before the target slave core group executes a predetermined instruction in the target to-be-executed task, the frequency management module completes the adjustment of the clock frequency of the working clock of the target slave core group.

5. The heterogeneous many-core chip task scheduling method of claim 3, wherein, The task scheduler allocates the target to-be-executed task to the target slave core group according to the working mode matched by the synchronization identifier, and the method further comprises: When the synchronization identifier parsed by the task scheduler is an invalid value, the task scheduler initiates a frequency adjustment interrupt request to the frequency management module, and waits until it is determined that the frequency management module completes the adjustment of the clock frequency of the working clock of the target slave core group, and then allocates the target to-be-executed task to the target slave core group.

6. The heterogeneous many-core chip task scheduling method of claim 5, wherein, The heterogeneous many-core chip task scheduling method further comprises: After the frequency management module controls the clock module to adjust the clock frequency of the working clock provided to the target slave core group to match the task frequency, the frequency management module clears the frequency adjustment interrupt request initiated by the task scheduler; After the task scheduler detects that the frequency adjustment interrupt request is cleared, it is determined that the frequency management module completes the adjustment of the clock frequency of the working clock of the target slave core group.

7. The heterogeneous many-core chip task scheduling method of claim 1, wherein, The master core adds an interrupt valid identifier to each to-be-executed task, and the method further comprises: When the master core detects that the to-be-executed task does not contain a predetermined instruction and the frequency management module is in a normal frequency adjustment state, the master core sets the interrupt valid identifier to a valid value; When the master core detects that the to-be-executed task does not contain a predetermined instruction and the frequency management module is in a shielding frequency adjustment state, the master core sets the interrupt valid identifier to an invalid value.

8. The heterogeneous many-core chip task scheduling method of claim 1, wherein, Each slave core group is connected to a plurality of clock sources in the clock module, and the frequency management module controls the clock module to adjust the clock frequency of the working clock provided to the target slave core group to match the task frequency, and the method further comprises: The frequency management module detects the clock frequency of the real-time working clock provided to the target slave core group by the clock source currently connected to the target slave core group; When the clock frequency of the real-time working clock of the target slave core group matches the task frequency of the target to-be-executed task, the frequency management module keeps the real-time working clock of the target slave core group unchanged and determines that the adjustment of the clock frequency of the working clock of the target slave core group is completed; When the clock frequency of the real-time working clock of the target slave core group does not match the task frequency of the target to-be-executed task, but there is another clock source providing a working clock with a clock frequency matching the task frequency of the target to-be-executed task among the clock sources connected to the target slave core group, the frequency management module controls to switch to the working clock provided to the target slave core group by the other clock source which matches the task frequency of the target to-be-executed task, and determines that the adjustment of the clock frequency of the working clock of the target slave core group is completed. When the clock frequency of the working clock of the target slave core group from the clock source currently connected to the target slave core group does not match the task frequency of the target task to be executed, and the clock frequency of the working clock of all clock sources connected to the target slave core group does not match the task frequency of the target task to be executed, the frequency management module controls the clock source currently connected to the target slave core group to adjust the clock frequency of the working clock of the target slave core group to match the task frequency.

9. The heterogeneous many-core chip task scheduling method of claim 1, wherein, The task scheduler detects whether the task frequency of the target task to be executed matches the clock frequency of the working clock of the target slave core group currently. When the task scheduler detects that the task frequency of the target task to be executed matches the task frequency of the last task to be executed assigned to the target slave core group, the task scheduler determines that the task frequency of the target task to be executed matches the clock frequency of the working clock of the target slave core group currently, otherwise the task scheduler determines that the task frequency of the target task to be executed does not match the clock frequency of the working clock of the target slave core group currently.

10. The heterogeneous many-core chip task scheduling method of claim 7, wherein, The heterogeneous many-core chip task scheduling method further comprises: When the task scheduler determines that the task frequency of the target task to be executed matches the clock frequency of the working clock of the target slave core group currently, or detects that the interrupt valid identifier of the target task to be executed is an invalid value, the task scheduler directly assigns the target task to be executed to the corresponding target slave core group.

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