Semiconductor memory device guided error check and erase

Abstract

The invention relates to semiconductor memory device boot error check and erase. Methods, systems, and apparatus are described for a memory device (e.g., a DRAM) containing a booted error check and erase (ECS) program. When an error is detected in a codeword, the booted ECS program may include a read-modify-write cycle. In some embodiments, the memory device may perform the booted ECS program on a codeword in which an error was previously detected (e.g., in response to a read command). The booted ECS program described herein may facilitate correcting codeword errors before excessive errors exceeding the detection and / or correction capabilities of the memory device accumulate in the codeword.

Description

Technical Field

[0001] The present disclosure relates generally to memory devices, and more particularly, to error checking and erasure directed by semiconductor memory devices. Background Art

[0002] Memory devices are widely used to store information associated with various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices may be volatile or nonvolatile, and may be of various types, such as magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), and others. Information is stored in various types of RAM by charging memory cells so that they have different states. Improvements to RAM memory devices may generally include increasing memory cell density, increasing read / write speeds or otherwise reducing operating latency, improving reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other things. Summary of the invention

[0003] One aspect of the present disclosure discloses a memory device, comprising: a memory array comprising a plurality of codewords; an error correction code (ECC) circuit coupled to the memory array; and a circuit system coupled to the memory array and the ECC circuit, the circuit system being configured to: receive an error check and erase (ECS) command from a host device; determine, in response to receiving the ECS command, that an error was detected in the memory array before receiving the ECS command; and perform an ECS procedure on a codeword associated with the error using the ECC circuit in response to determining that an error was detected in the memory array before receiving the ECS command.

[0004] Another aspect of the present disclosure discloses a method comprising: receiving a read command at a memory device from a host device coupled to the memory device; retrieving data from a memory array of the memory device in response to the received read command, wherein the data comprises a codeword; detecting at least one error in the codeword of the retrieved data; storing a memory array address associated with the codeword to a mode register in response to detecting the at least one error in the codeword; sending an indication to the host device that an error was detected in response to the read command in response to detecting the at least one error in the codeword; and performing an internal read-modify-write cycle on the codeword associated with the memory array address in the mode register, wherein the internal read-modify-write cycle comprises correcting the at least one error in the codeword. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0006] Figure 1 The Description schematically illustrates a simplified block diagram of a memory device in accordance with embodiments of the present technology.

[0007] Figure 2 is a simplified block diagram of an example memory device illustrating various components for performing an error check and scrub (ECS) procedure in accordance with an embodiment of the present disclosure.

[0008] Figure 3 is an example flow chart for guiding an ECS program according to an embodiment of the present disclosure.

[0009] Figure 4 is an example flow chart for executing an ECS program according to an embodiment of the present disclosure.

[0010] Figure 5 is a simplified block diagram schematically illustrating an example memory system according to an embodiment of the present disclosure.

[0011] Figure 6 is a block diagram of an example computer system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Methods, systems, and apparatus for semiconductor memory devices (DRAM) are disclosed that include error checking and erasure (ECS) programs that can be directed by a memory device (i.e., a memory device having directed ECS). The described ECS program can be considered to be "directed" by the memory device because the ECS program can be executed in response to information from the memory device (e.g., indicating the detection of an error in the memory device). The described ECS program can further be considered to be "directed" by the memory device because the ECS program can preferentially operate on memory device addresses identified by the memory device (e.g., memory device addresses where errors are detected).

[0013] Some semiconductor memory devices (e.g., DRAM) store information as charge accumulated in cell capacitors ("cells"), where cells are organized in rows. In some cases, due to the voltage difference between the capacitor and surrounding components (e.g., metal lines, semiconductor junctions of switching transistors) connected to the cell capacitor, the charge accumulated in the cell capacitor may escape from the cell capacitor (which may be referred to as "leakage") to the surrounding components. As a result, the charge of the cell may change. The charge of the cell may also change in response to particle impacts.

[0014] An error may occur if the charge of a cell has changed enough that the charge is interpreted as an erroneous logic value (i.e., the bit "flips" from the correct logic value, resulting in a "flip" error or bit error). In some cases, a memory device may be configured to perform an error correction code (ECC) function (e.g., using an on-die ECC engine or ECC circuit) that can detect and correct one or more errors in data (e.g., codewords) stored in a memory array. In some cases, the ECC function is performed as part of a read operation of the memory device (e.g., in response to a read command issued from a host coupled to the memory device) such that corrected read data is provided to the host. However, in conventional memory devices, the corrected read data generated by the ECC function during a read operation is not written back to the memory device (i.e., the corrected data is sent to the host, but the errors will remain in the data residing in the memory device itself). In some cases, the ECC function is performed as part of an ECC operation, where the memory device reads data bits, corrects detected errors (e.g., using the ECC function), and writes the corrected data bits back to the memory device. That is, the ECS operation erases errors of the memory device.

[0015] An ECS operation may involve executing an ECS program one or more times, where each ECS program operates on a portion of a memory device. For example, an ECS program may operate on a codeword representing a portion of a row of a memory device (e.g., 128 data bits and an additional check bit). The ECS program may perform an internal read-modify-write cycle, where the ECS program reads a codeword from a memory device, corrects errors detected in the codeword, and writes the correct codeword back to the memory device. The ECS program may be initiated in response to a command received from a host device coupled to the memory device to execute the ECS program ("manual ECS"). The ECS program may additionally be initiated automatically - for example, without receiving a command from a host device ("auto ECS").

[0016] In a conventional memory device with ECS, the ECS program performs an internal read-modify-write cycle on an address determined based on an ECS address counter. For example, the codeword for which the internal read-modify-write cycle of the ECS program is performed may be based on an address in a column counter, a row counter, a bank counter, and / or a bank group counter. After the ECS program is completed (e.g., after the write of the internal read-modify-write cycle), the column counter is incremented so that the next codeword is selected for the next ECS program. Once the column counter wraps (i.e., all codewords on a row have been accessed), the row counter is incremented until all codewords on each of the rows within the bank have been accessed. When the row counter wraps (i.e., all rows within the bank have been accessed), the bank counter is incremented and the next bank within the bank group repeats the process of accessing each codeword. When the bank counter wraps, the bank group counter is incremented and the next bank group repeats the process of accessing each codeword until all bank groups are accessed. Once the bank group counter wraps, all codewords within the device have been evaluated through the internal read-modify-write cycle, and the ECS operation will restart for the next ECS process (e.g., at the starting column, row, bank, and / or bank group). That is, the consecutive ECS process will operate on the next codeword based on incrementing the ECS address counter, where the number of ECS processes to complete the ECS operation of the entire memory device depends on the number of codewords per memory device.

[0017] Conventional memory devices with ECS may be configured to perform a full ECS operation (e.g., perform an ECS procedure at each codeword of the device) within a recommended period (e.g., every 24 hours). That is, for example, a host coupled to the memory device may be configured to issue a manual ECS command at a frequency sufficient to erase the entire memory device within 24 hours, and / or the memory device may be configured to perform automatic ECS at a frequency sufficient to erase the entire memory device within 24 hours. Therefore, in a conventional memory device with ECS, a significant period of time may pass between erasures of a particular codeword (e.g., once every 24 hours). However, this delay may increase the likelihood of having a number of errors in data (e.g., codewords) that exceed the correction capacity of the ECC function. For example, the ECC function is only capable of detecting single-bit errors in a codeword and may suffer certain disadvantages when there are two or more bit errors in the codeword. For example, if a codeword with two bit errors is presented to an ECC function that is only capable of detecting single-bit errors, it may interpret the codeword as having a single-bit error at a location other than the locations of the two actual bit errors, thereby causing aliasing. Therefore, it is advantageous to preferentially erase codewords with single-bit errors. By doing so, the likelihood that a codeword will accumulate two or more bit errors that may exceed the detection and / or correction capabilities of the ECC function is reduced.

[0018] Thus, a memory device with a guided ECS is described herein that erases a codeword (i.e., performs an ECS procedure on the codeword) when an error is detected. Like a conventional memory device, a memory device with a guided ECS performs an ECC function on data read from the memory device in response to a host read request and corrects detected errors before transmitting the data to the host. Unlike a conventional memory device, a memory device with a guided ECS additionally notifies the host whether an error is detected in the read data. As described herein, a memory device with a guided ECS may notify the host of a detected error via a dedicated pin (e.g., a data mask (DM) pin of the memory device when the memory device is coupled to the host via a compute fast link (CXL) interface) and / or a shared bus (e.g., a sideband bus shared by memory devices that conform to a double data rate synchronous dynamic random access memory (DDR SDRAM) standard (e.g., DDR6)). In some embodiments, the indication additionally includes information identifying which memory device detected the error. For example, the memory device may notify the host of an identification of the memory device (e.g., using a pin, a sideband bus, etc.). In some embodiments, notification of a detected error is sent to the host without an indication of a particular memory device. For example, the host may determine a memory rank associated with a DRAM device error. When the host receives an indication of a detected error (e.g., via a DM pin and / or a sideband bus), it may initiate a manual ECS operation. Furthermore, the host may initiate manual ECS in response to an error indication faster than it would normally initiate manual ECS (e.g., faster than necessary to complete an ECS operation of the memory device within a recommended time period).

[0019] In addition, when a memory device with a directed ECS detects an error during a data read, the memory device may store information about the address of the detected error. For example, a memory device with a directed ECS may save the column, row, bank, and / or bank group address of the codeword in which the error was detected during a read. In addition, a memory device with a directed ECS may save a bit (e.g., a valid bit) to indicate that the address of the codeword in which the error was detected has been saved. Information (e.g., the codeword address and the valid bit) may be saved in a mode register for the directed ECS. In some embodiments, a memory device with a directed ECS includes multiple directed ECS mode registers so that addresses of multiple codewords in the memory device can be stored.

[0020] When a memory device with guided ECS performs an ECS procedure (e.g., in response to manual ECS or automatic ECS), it evaluates whether the address of any previously detected error has been saved. For example, it may evaluate whether the valid bit in any of the guided ECS mode registers is set. If the address of any previously detected error has been saved (e.g., the valid bit of the guided ECS mode register is set), the memory device with guided ECS performs the ECS procedure on the corresponding address (e.g., the address at the row, column, bank, and / or bank group stored in the ECS mode register) instead of the address identified by the ECS address counter. By doing so, the memory device with guided ECS performs erase operations on the codewords in which the errors are detected in priority order. Therefore, the memory device with guided ECS reduces the probability of another error occurring in the codeword before the codeword is erased. After the ECS procedure is completed, the memory device with guided ECS clears the valid bit of the guided ECS mode register corresponding to the erase address so that the address no longer marks the need for guided ECS. When the ECS procedure is executed again, if none of the ECS mode register valid bits are set, the memory device with the directed ECS will execute the ECS procedure according to the ECS address counter (e.g., conventionally). In embodiments where multiple ECS mode registers store addresses of multiple detected errors, the memory device with the directed ECS may prioritize between the addresses stored in the ECS mode registers based on which one is the oldest (e.g., which one that has not been erased was first detected during a data read) among the addresses.

[0021] Figure 1 The description schematically illustrates a simplified block diagram of a memory device 100 according to an embodiment of the present technology. The memory device 100 may include an array of memory cells, such as a memory array 150. The memory array 150 may include a plurality of memory banks (e.g., Figure 1 1 to 15 in the example of ), and each memory bank may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at the intersections of the word lines and the bit lines. The selection of the word line WL may be performed by a row decoder 140, and the selection of the bit line BL may be performed by a column decoder 145. A sense amplifier (SAMP) may be provided for the corresponding bit line BL and connected to at least one corresponding local input / output (I / O) line pair (LIOT / B), which in turn may be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transfer gate (TG) that may be used as a switch.

[0022] The memory device 100 may employ a plurality of external terminals, including command and address terminals respectively coupled to a command bus and an address bus to receive a command signal CMD and an address signal ADDR. The memory device may further include a chip select terminal for receiving a chip select signal CS, a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI (for a data bus inversion function) and DMI (for a data mask inversion function), power supply terminals VDD, VSS, VDDQ and VSSQ, and an on-chip termination terminal ODT.

[0023] The address signal and the memory bank address signal may be supplied to the command terminal and the address terminal from the outside. The address signal and the memory bank address signal supplied to the address terminal may be transmitted to the address decoder 110 via the address / command input circuit 105. The address decoder 110 may receive the address signal and supply the decoded row address signal (XADD) to the row decoder 140, and supply the decoded column address signal (YADD) to the column decoder 145. The address decoder 110 may also receive the memory bank address portion of the ADDR input and supply the decoded memory bank address signal (BADD) and the memory bank address signal to both the row decoder 140 and the column decoder 145.

[0024] A command signal CMD, an address signal ADDR, and a chip select signal CS may be supplied from a memory controller to the command and address terminals. The command signal may represent various memory commands (e.g., including access commands, which may include read commands and write commands) from the memory controller. The select signal CS may be used to select the memory device 100 in response to the command and address provided to the command and address terminals. When a valid CS signal is provided to the memory device 100, the command and address may be decoded, and a memory operation may be performed. The command signal CMD may be provided to the command decoder 115 as an internal command signal ICMD via the address / command input circuit 105. The command decoder 115 may include circuits to decode the internal command signal ICMD to generate various internal signals and commands for performing memory operations, such as a row command signal for selecting a word line and a column command signal for selecting a bit line. The internal command signal may also include output and input activation commands, such as a timing command CMDCK ( Figure 1 not shown).

[0025] In some embodiments, command decoder 115 may further include one or more registers for tracking various counts or values, such as a count of refresh commands received by memory device 100 or self-refresh operations performed by memory device 100. In some embodiments, a subset of registers may be referred to as mode registers and configured to store user-defined variables to provide flexibility in executing various functions, features, and modes. For example, a memory device may receive signaling from a host device at a mode register indicating whether an ECC mode of the memory device is enabled or disabled.

[0026] When a read command is issued to a memory bank having an open row and a column address is supplied in time as part of the read command, read data may be read from a memory cell in the memory array 150 specified by the row address (which may have been provided as part of an activation command identifying the open row) and the column address. The read command may be received by a command decoder 115, which may provide an internal command to the IO circuit 160 so that the read data may be output from the data terminals DQ, RDQS, DBI, and DMI via the read / write amplifier 155 and the IO circuit 160 according to the RDQS clock signal. The memory device 100 may perform an ECC function (e.g., to detect and correct errors) on the read data read from the memory array 150 before outputting the data terminals using an ECC circuit (described below). The read data may be provided at a time defined by read latency information (RL) programmable in the memory device 100 (e.g., in a mode register). The read latency information RL may be defined in terms of a clock cycle of the CK clock signal. For example, the read latency information RL may be the number of clock cycles of the CK signal after a read command is received by the memory device 100 when associated read data is provided.

[0027] When a write command is issued to a memory bank with an open row and a column address is supplied in time as part of the write command, write data may be supplied to data terminals DQ, DBI, and DMI according to WCK and WCKF clock signals. The write command may be received by a command decoder 115, which may provide an internal command to an IO circuit 160 so that the write data may be received by a data receiver in the IO circuit 160 and supplied to the memory array 150 via the IO circuit 160 and the read / write amplifier 155. The write data may be written in a memory cell specified by a row address and a column address. The write data may be provided to the data terminal at a time defined by write latency WL information. The write latency WL information may be programmable in the memory device 100 (e.g., in a mode register). The write latency WL information may be defined according to a clock cycle of a CK clock signal. For example, the write latency information WL may be the number of clock cycles of a CK signal after the write command is received by the memory device 100 when the associated write data is received.

[0028] Power supply potentials VDD and VSS may be supplied to the power supply terminals. These power supply potentials VDD and VSS may be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 may generate various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS. The internal potential VPP may be used in the row decoder 140, the internal potentials VOD and VARY may be used in the sense amplifiers included in the memory array 150, and the internal potential VPERI may be used in many other circuit blocks.

[0029] A power supply potential VDDQ may also be supplied to the power supply terminal. The power supply potential VDDQ may be supplied to the IO circuit 160 together with the power supply potential VSS. In an embodiment of the present technology, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of the present technology, the power supply potential VDDQ may be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for the IO circuit 160 so that the power supply noise generated by the IO circuit 160 does not propagate to other circuit blocks.

[0030] The on-die termination terminal may be supplied with an on-die termination signal ODT. The on-die termination signal ODT may be supplied to the IO circuit 160 to instruct the memory device 100 to enter an on-die termination mode (eg, to provide one of a predetermined number of impedance levels at one or more of the other terminals of the memory device 100).

[0031] An external clock signal and a complementary external clock signal may be supplied to the clock terminal and the data clock terminal. The external clock signals CK, CKF, WCK, and WCKF may be supplied to the clock input circuit 120. The CK and CKF signals may be complementary, and the WCK and WCKF signals may also be complementary. The complementary clock signals may have opposite clock levels and simultaneously transition between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. In addition, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0032] An input buffer included in the clock input circuit 120 may receive an external clock signal. For example, when enabled by the CKE signal from the command decoder 115, the input buffer may receive the CK and CKF signals and the WCK and WCKF signals. The clock input circuit 120 may receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK may be supplied to the internal clock circuit 130. The internal clock circuit 130 may provide various phase and frequency controllable internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from the command decoder 115. For example, the internal clock circuit 130 may include a clock path ( Figure 1 The internal clock circuit 130 may further provide an input / output (IO) clock signal. The IO clock signal may be supplied to the IO circuit 160 and may be used as a timing signal for determining the output timing of read data and the input timing of write data. The IO clock signal may be provided at multiple clock frequencies so that data may be output from and input to the memory device 100 at different data rates. When high memory speed is desired, a higher clock frequency may be desired. When low power consumption is desired, a lower clock frequency may be desired. The internal clock signal ICLK may also be supplied to the timing generator 135 and various internal clock signals may be generated accordingly.

[0033] The memory device 100 further includes an ECS circuit 175. The ECS circuit 175 may include an ECC engine and / or controls for a directed ECS. The ECS circuit 175 (in combination with the address / command input circuit 105) may be configured to determine when the memory device 100 receives a read command directed to the memory array 150 and performs an ECC function (e.g., using an ECC engine) to detect and correct errors in the data read from the memory array. If the ECS circuit 175 detects an error in the data read from the memory array 150 in response to the read command, the memory device 100 may notify the host and / or controller that issued the read command that the error was detected. The memory device 100 may notify the host via a DM pin and / or a sideband bus (not shown) coupled to the memory device. The notification of the detected error may further include an identifier associated with the memory device 100 (e.g., to identify the memory device from other memory devices also coupled to the host). If the ECS circuit 175 detects an error in the data read from the memory array 150 in response to a read command, the ECS engine may additionally record information about the detected error in a directed ECS mode register (not shown), which may be part of the directed ECS control. For example, the ECS circuit 175 may store the column, row, bank, and / or bank group address of the codeword in which the error was detected in the data read from the memory array 150 to the directed ECS mode register. The ECS circuit 175 may also set a valid bit associated with the directed ECS mode register to indicate that the corresponding directed ECS mode register contains valid data (e.g., the address of the codeword in which the error was detected but has not been erased). In some embodiments, the memory device 100 includes a single directed ECS mode register so that it can store the address of only one codeword at a time. In some embodiments, the memory device 100 includes multiple directed ECS mode registers so that it can store the addresses of multiple codewords (e.g., multiple codewords in which errors were detected but have not been erased) at a time. In some embodiments where the memory device 100 includes multiple directed ECS mode registers, if multiple codewords in the data read from the memory array 150 have errors, the ECS circuit 175 may store the addresses of the multiple codewords to the directed ECS mode registers in response to a single read command from the host.

[0034] The ECS circuit (in combination with the address / command input circuit 105) may be additionally configured to receive an erase command directed to the memory array 150 (e.g., from a host device or controller coupled to the memory device 100) and to perform an ECS procedure. In some embodiments, the ECS circuit 175 may be configured to automatically perform the ECS procedure (e.g., as a background operation). When the ECS circuit 175 (e.g., in response to an erase command and / or an automatic start procedure from a host device) performs an ECS procedure, the directed ECS control of the ECS circuit determines the address of the memory array 150 on which the ECS procedure should be performed. For example, if the directed ECS control determines that there are codewords in the memory array 150 for which errors have been detected but have not yet been erased (e.g., there is valid data in one or more directed ECS mode registers), then the directed ECS control selects one of those codewords (e.g., corresponding to the least recently written valid directed ECS mode register) for the ECS procedure. If the directed ECS control determines that there is no codeword in the memory array 150 for which an error is detected but which has not been erased (e.g., there is no valid data in any of the directed ECS mode registers), then the directed ECS control selects an alternative codeword for the ECS procedure. For example, the ECS control may select the codeword based on an ECS address counter (not shown) that iterates through the addresses of the memory array 150. Data may then be retrieved from the memory array 150 (e.g., at an address corresponding to the directed ECS mode register or the ECS address counter) based on the determination made by the directed ECS control.

[0035] Subsequently, the memory device 100 (e.g., the ECS circuit 175) may detect and correct one or more errors in the codeword of the retrieved data. In some embodiments, the memory device 100 may utilize an ECC circuit (e.g., an ECC engine included in the ECS circuit 175) to detect and correct one or more errors. The corrected codeword may be written back to the memory array 150, thereby completing the internal read-modify-write cycle of the ECS program. After the corrected codeword is written back to the memory array 150 (e.g., after the internal read-modify-write cycle of the ECS program has been completed), the ECS circuit 175 may update the guided ECS mode register accordingly. For example, the ECS circuit 175 may update the guided ECS mode register corresponding to the codeword erased by the current ECS program (e.g., the ECS mode register storing the address of the codeword) so that the guided ECS mode register no longer appears to have valid data (e.g., by clearing the valid bit of the register). That is, the updated directed ECS mode register will no longer report codewords for which errors were detected but which have not yet been erased (because the corresponding codewords have been erased by the current ECS program).

[0036] Figure 2 2 is a block diagram 200 schematically illustrating a memory device 210 according to an embodiment of the present technology. Block diagram 200 also illustrates a host device 205 coupled to memory device 210. Memory device 210 may be a reference Figure 1 1. The memory device 210 may include an example of the memory device 100 or include aspects of the memory device 100. The memory device 210 may include an ECS circuit 275 (which may be an example of the ECS circuit 175 or include aspects of the ECS circuit 175), an ECC circuit 220 (which may be a reference Figure 1 200 and 210. The ECS circuit 275 may include an ECS address counter 225, an address incrementer 230, a directed ECS mode register 235, a directed ECS control 240, and an ECS multiplexer 245. As described herein, the ECS circuit 275 may be configured to perform an ECS program (i.e., an erase codeword) on a codeword identified by the ECS address counter 225 or the directed ECS mode register 235. In addition, the ECC circuit 220 may be configured to perform ECC functions on a codeword as part of an ECS program and during a read of the memory array 250 (e.g., requested by the host 205).

[0037] The memory array 250 may be configured to include a number of memory bank groups 251 (e.g., memory bank groups 251a to 251n). Each individual memory bank group 251 may include a set of memory banks of memory cells (e.g., memory banks 252a to 252k in memory bank group 251a). Each individual memory bank of memory cells (e.g., memory bank 252a) may include a set of rows, wherein each row includes a set of addresses (e.g., columns) that may each correspond to a codeword. For example, a row may include 128 addresses (or columns) that each correspond to a codeword having 8 bytes. That is, in this example, a row may include 1,024 bytes of data.

[0038] During a read of the memory array 250 (e.g., in response to a read request from the host 205), the ECC circuit 220 may be configured to perform an ECC function on the read data to detect and correct errors before transmitting the data to the host. That is, the ECC circuit 220 may detect a codeword in the read data that flips one or more bits and correct those flipped bits before transmitting them to the host. However, the corrected codeword may not be immediately written back to the memory array 250. Instead, the address of the codeword in which the error was detected may be stored in the directed ECS mode register 235. For example, the bank group, bank, row, and column address of any codeword in which an error was detected by the ECC circuit 220 when performing the ECC function on the read data may be stored in the directed ECS mode register 235. A flag (e.g., a valid bit) may also be set in an individual directed ECS mode register 235 to indicate that the corresponding mode register has valid data (e.g., the address of the codeword in which the error was detected). Additionally, memory device 210 (eg, via ECC circuit 220 and / or ECS circuit 275 ) may notify host 205 of any errors detected in data read from memory array 250 .

[0039] When the ECS circuit 275 is to execute an ECS procedure (e.g., in response to a manual ECS request received from the host 205 and / or when the ECS circuit or other elements of the memory device 210 automatically trigger the ECS), the guided ECS control 240 determines the codeword address on which the ECS procedure is to be executed. If the guided ECS control 240 detects that the guided ECS mode registers 235 contain any valid data (indicating that at least one register contains the address of a codeword in which an error was detected but has not yet been erased), the guided ECS control may configure the ECS multiplexer 245 to select the codeword address (e.g., bank group, bank, row, and / or column) from the guided ECS mode registers with valid data. If multiple guided ECS mode registers 235 contain valid data (e.g., errors were detected in multiple codewords that have not yet been erased), the guided ECS control 240 may configure the ECS multiplexer 245 to select the guided ECS mode register 235 with the oldest valid data. In embodiments with multiple directed ECS mode registers 235, other methods may be used to select an ECS mode register when multiple ECS mode registers have valid data (e.g., first-in, first-out (FIFO), round-robin selection, random selection, and / or prioritizing certain ECS mode registers). Figure 2The directed ECS mode registers 235 are illustrated as being coupled to only a single input of the ECS multiplexer 245, but the ECS multiplexer may actually be coupled to and select from any of the ECS mode registers 245 (e.g., the ECS multiplexer may be many-to-one, rather than two-to-one as illustrated). However, if the directed ECS control 240 detects that none of the directed ECS mode registers 235 contain valid data, the directed ECS control may configure the ECS multiplexer 245 to select a codeword address (e.g., a bank group, bank, row, and / or column) from the ECS address counter 225.

[0040] The output of the ECS multiplexer 245 (as selected by the directed ECS control 240) includes the address information of the codeword in the memory array 250 on which the ECS procedure is to be performed. The memory device 210 (including the ECS circuit 275 and the ECC circuit 220) reads the codeword from the memory array 250, performs the ECC function to detect and correct any errors in the codeword, and writes any corrected data back to the address of the codeword in the memory array, thereby completing the internal read-modify-write cycle. It should be appreciated that if the ECS procedure is performed on the codeword selected by the ECS address counter 225, the ECS procedure may not detect any errors in the codeword (as described above, because the ECS address counter iterates through all addresses in the memory array 250, most of which should be error-free). However, if the ECS procedure is performed on the codeword selected by the directed ECS mode register 235, the ECS program should detect errors in the codeword (e.g., errors that cause the address of the codeword to be saved in the directed ECS mode register) and correct them. Advantageously, directed erasure of codewords increases the likelihood of correcting errors in a codeword before more errors accumulate in the codeword than can be detected and / or corrected (e.g., by ECC circuit 220). For example, if ECC circuit 220 can only detect and / or correct single-bit errors, then single-bit errors can be corrected (before double-bit errors occur), if the ECC circuit can only detect and / or correct up to double-bit errors, then double-bit errors can be corrected (before triple-bit errors occur), and so on.

[0041] After the internal read-modify-write cycle of the ECS program has completed (e.g., the corrected data has been written back to the address of the codeword in the memory array 250), the ECS circuit 275 updates the state accordingly. For example, if the ECS program is executed on the codeword address stored in the directed ECS mode register 235, the directed ECS control 240 may update the directed ECS mode register so that it no longer indicates that valid data is stored (e.g., clearing the valid bit associated with the register). If the ECS program is executed on the codeword address from the ECS address counter 225, the directed ECS control 240 may update the ECS address counter with the next incremented address (e.g., generated by the address incrementer 230). As described herein, the ECS address counter 225 and / or the address incrementer 230 may be configured so that the address in the ECS address counter iterates through all addresses of the memory array 250 (e.g., iterates through all columns within a row, all rows within a bank, all banks within a bank group, and all bank groups within the memory device 210) in a sufficient number of increments.

[0042] Figure 3 is an example flow chart illustrating a process 300 for booting an ECS program according to an embodiment of the present disclosure. Aspects of the process 300 may be performed by a memory device, such as by Figure 1 The memory device 100 (including the ECS circuit 175), Figure 2 The memory device 210 (including the ECS circuit 275 and the ECC circuit 220) and / or a combination thereof is executed.

[0043] Process 300 begins at block 305, where a memory device receives a read command from a host device or controller coupled to the memory device. The read command may include a target row within a memory array of the memory device.

[0044] At block 310, the memory device activates a target row of the memory array in response to receiving a read command and retrieves data from the target row. The data may include one or more codewords, each of which may correspond to an address (eg, a column address) associated with the target row.

[0045] At decision block 315, the memory device determines whether any of the codewords of the retrieved data contain at least one error. In some embodiments, the memory device may utilize an ECC engine to detect any errors in the codewords. If the memory device determines that at least one codeword has at least one error, the process continues to block 320. If the memory device determines that the codeword does not have any errors, the process continues to block 335.

[0046] At block 320, a memory device (eg, using an ECC engine, such as Figure 1 or Figure 2 As described herein, it should be appreciated that the correction (performed in response to a received read command) is reflected in the read data ultimately sent to the requesting host and / or controller but is not written back to the memory array of the memory device.

[0047] At block 325, the memory device stores the address of the codeword in which the error was detected (e.g., at decision block 315) to a register. For example, the memory device may store the address to the directed ECS mode register 235 (at Figure 2 ). The address information may include information for accessing each of the corresponding codewords in the memory array, including the bank group, bank, row, and column associated with the codeword. In some embodiments where the memory device can detect errors in multiple codewords, the address of each of the codewords is stored to a different register. The memory device may also update a valid bit associated with each write register to indicate that the register has valid data.

[0048] At block 330, the memory device signals the requesting host and / or controller that at least one error was detected in the codeword retrieved in response to the read command. In embodiments where the memory device includes a CXL interface with the host and / or controller, the memory device may signal the occurrence of the detected error via a DM pin. In embodiments where the memory device includes a DDR interface with the host and / or controller, the memory device may signal the occurrence of the detected error via a sideband bus. It should be appreciated that the host and / or controller may use the error detection signal to initiate an ECS operation.

[0049] At block 335, the memory device responds to the read command with the read data, including any error correction performed (eg, at block 320). Process 300 then ends.

[0050] Figure 4 4 is an example flow chart illustrating a process 400 for executing an ECS program according to an embodiment of the present disclosure. Aspects of the process 400 may be executed by a memory device, such as by Figure 1 The memory device 100 (including the ECS circuit 175), Figure 2 The memory device 210 (including the ECS circuit 275 and the ECC circuit 220) and / or a combination thereof is executed.

[0051] Process 400 begins at block 405, where the memory device receives an indication to start an ECS procedure. For example, the memory device may receive an indication from a host and / or memory controller coupled to the memory device (e.g., it may receive a command to perform a manual ECS). As another example, the memory device may automatically start an ECS procedure after a threshold time has passed since the last ECS procedure (e.g., it may start an automatic ECS). In some embodiments, the memory device starts ECS at a frequency such that ECS will be performed on the entire memory device within a period of time (e.g., within 24 hours).

[0052] At decision block 410, the memory device determines whether there are any codewords for which directed ECS is to be performed. For example, the memory device may include one or more mode registers (e.g., directed ECS mode registers) in which addresses of codewords having detected errors are stored, indicating that directed ECS should be performed on the corresponding codewords. The codeword addresses may be addresses of a memory array (e.g., columns, rows, banks, and / or groups of banks) in the memory device in which the codewords are stored. In response to a read command received by the memory device (e.g., a read command received by the memory device), directed ECS may be performed on the memory device in response to a read command received by ... Figure 3 If the memory device determines that there is a codeword on which the directed ECS is performed, then process 400 continues to block 415. If the memory device determines that there is no codeword on which the directed ECS is performed, then process 400 continues to block 425.

[0053] At block 415, the memory device performs a guided ECS procedure on a codeword for which an error has previously been detected (e.g., a codeword identified by decision block 410). As described herein, the ECS procedure may perform an internal read-modify-write cycle on the codeword, wherein data from the codeword is read from a memory array of the memory device, an ECC function is performed on the read data to identify and correct errors in the data, and the corrected data is written back to the address of the codeword in the memory array. In some embodiments, the memory device may be able to store the locations of multiple codewords in which errors were detected (e.g., the memory device may include multiple guided ECS mode registers). In such embodiments, the memory device may perform a guided ECS procedure on any of the codewords in which an error was detected. For example, the memory device may perform a guided ECS procedure on the oldest detected error; that is, the codeword for which the most time has passed since an error was detected in the codeword.

[0054] At block 420, the memory device updates a state associated with the codeword on which the guided ECS procedure was executed. For example, the memory device may clear a valid bit of a guided ECS mode register storing the address of the codeword on which the guided ECS procedure was executed, such that the guided ECS mode register no longer appears to have valid data. That is, the codeword on which the guided ECS procedure was executed (i.e., at decision block 410) will no longer appear to require a guided ECS. It should be appreciated that in embodiments where the memory device stores multiple codewords at locations where errors were detected (e.g., multiple guided ECS mode registers), other codewords may later appear to require a guided ECS (e.g., when the memory device next receives a manual ECS request). Process 400 then ends.

[0055] However, if it is determined at decision block 410 that there is no codeword for which to perform directed ECS, then at block 425 the memory device performs an ECS procedure on the codeword at the address based on the ECS address counter. At block 430, the memory device increments the address in the ECS address counter. By doing so, the next time the ECS procedure is performed using the address in the ECS address counter, the ECS procedure will be performed on the next codeword in the memory array. As described herein, the ECS address counter may be incremented to iterate through all columns within a row, all rows within a memory bank, all memory banks within a memory bank group, and all memory bank groups in order to iterate through the addresses of all codewords in the memory array of the memory device in the ECS procedure. Process 400 then ends.

[0056] Figure 5 5 is a simplified block diagram schematically illustrating a memory system 500 according to an embodiment of the present technology. The memory system 500 includes a host device 510 operably coupled to a memory module 520 (e.g., a dual in-line memory module (DIMM)). The memory module 520 may include a controller circuit system 530 operably connected to a plurality of memory devices 550 via a bus 540. According to one aspect of the present disclosure, the memory devices 550 may execute a guided ECS procedure in response to initiating an automatic ECS or receiving a request to execute a manual ECS (e.g., from the host 510). It should be understood that in response to executing ECS ​​(e.g., in response to a request to execute a manual ECS from the host device 510), some memory devices 550 may execute a guided ECS procedure (e.g., if that memory device 550 previously identified an error in a codeword that has not yet been erased) and some memory devices 500 may execute a conventional ECS procedure using an address counter (e.g., if that memory device 550 has not yet identified an error in a codeword that has not yet been erased).

[0057] Figure 6An example machine is illustrated of a computer system 600 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0058] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0059] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 618, which communicate with each other via a bus 630. According to one aspect of the present disclosure, the main memory 604 can execute a booted ECS.

[0060] The processing device 602 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 602 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate over a network 620.

[0061] The data storage device 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media.

[0062] Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methodologies of the present disclosure. Thus, the term "machine-readable storage medium" should be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0063] The devices discussed herein, including processors or memory devices, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0064] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the present disclosure and the appended claims. Features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0065] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0066] As used herein, the terms "vertical," "lateral," "up," "down," "above," and "below" may refer to the relative direction or position of features in a semiconductor device in view of the orientation shown in the figure. For example, "upper" or "uppermost" may refer to a feature being located closer to the top of the page than another feature. However, these terms should be broadly interpreted to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, over / under, above / under, up / down, and left / right may be interchanged depending on the orientation.

[0067] It should be noted that the above methods describe possible implementations, and the operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, embodiments from two or more of the methods may be combined.

[0068] It should be understood from the foregoing that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present invention. Specifically, in the foregoing description, numerous specific details are discussed to provide a thorough and feasible description of embodiments of the present technology. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific details. In other examples, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid obscuring other aspects of the present technology. In general, it should be understood that various other devices, systems, and methods other than those specific embodiments disclosed herein may also be within the scope of the present technology.

Claims

1. A memory device, comprising: a memory array comprising a plurality of codewords; an error correction code (ECC) circuit coupled to the memory array; and a circuit system coupled to the memory array and the ECC circuit, the circuit system being configured to: receiving an error check and erase ECS command from a host device; determining, in response to receiving the ECS command, that an error was detected in the memory array prior to receiving the ECS command; and In response to determining that an error was detected in the memory array prior to receiving the ECS command, an ECS procedure is performed using the ECC circuit on a codeword associated with the error.

2. The memory device of claim 1 , further comprising a mode register configured to store a codeword address and a valid indicator, wherein: determining that an error was detected in the memory array prior to receiving the ECS command is based on the valid indicator of the mode register; and The codeword on which the ECS procedure is executed corresponds to the codeword address stored in the mode register.

3. The memory device of claim 2, wherein the codeword address comprises a column address, a row address, a bank address, and a bank group address.

4. The memory device of claim 1 , wherein performing the ECS procedure on the codeword comprises: retrieving the codeword from the memory array; updating the retrieved codeword based on an ECC function using the ECC circuit; and The updated codeword is stored to the memory array.

5. The memory device of claim 1 , wherein the circuitry is further configured to: receiving a read command directed to the memory array from the host device; retrieving data from the memory array in response to the received read command, the data comprising a second codeword; detecting at least one error in the second codeword using the ECC circuit, wherein the second codeword is associated with an address; and The address is stored in the mode register.

6. The memory device of claim 5, wherein determining that an error is detected in the memory array prior to receiving the ECS command is based on the address stored in the mode register, and wherein the codeword for which the ECS procedure is executed corresponds to the address stored in the mode register.

7. The memory device of claim 5, wherein the memory device is configured to transmit an indication of a detected error to the host device in response to detecting the at least one error in the second codeword.

8. The memory device of claim 7, wherein the memory device further comprises a compute fast link (CXL) interface, wherein the CXL interface comprises a data mask (DM) pin, and wherein the memory device transmits the indication of a detected error to the host device using the DM pin.

9. The memory device of claim 7, wherein the memory device further comprises a DDR6 interface, wherein the DDR6 interface comprises a sideband bus, and wherein the memory device transmits the indication of a detected error to the host device using the sideband bus.

10. The memory device of claim 1, wherein the circuitry is further configured to clear a valid bit associated with the error after executing the ECS procedure on a codeword associated with the error.

11. The memory device of claim 1 , further comprising a plurality of mode registers, wherein each mode register is configured to store a codeword address and a valid bit, and wherein: determining that an error was detected in the memory array prior to receiving the ECS command comprises identifying at least one mode register having an asserted valid bit; and Executing the ECS program includes selecting one of the identified mode registers, wherein the codeword on which the ECS program is executed is associated with the codeword address stored in the selected mode register.

12. The memory device of claim 11 , wherein selecting one of the recognition mode registers comprises: determining from the identified mode registers which mode register has had its valid bit asserted longest; and The mode register having the longest-asserted valid bit is selected.

13. The memory device of claim 11, wherein the circuitry is further configured to execute a plurality of ECS procedures without receiving ECS ​​commands from the host device.

14. The memory device of claim 13, wherein each of the plurality of ECS programs operates on a different codeword than a previous one of the plurality of ECS programs, and wherein the circuitry is further configured to execute the plurality of ECS programs such that all codewords in the memory array are operated on during a 24 hour period.

15. The memory device of claim 1, wherein the circuitry is further configured to: An ECS procedure is performed on a second codeword in response to determining that no errors were detected in the memory array prior to receiving the ECS command, wherein the second codeword is associated with an address stored in an address counter.

16. A method comprising: receiving, at a memory device, a read command from a host device coupled to the memory device; retrieving data from a memory array of the memory device in response to the received read command, wherein the data comprises a codeword; detecting at least one error in said codeword of said retrieved data; storing a memory array address associated with the codeword to a mode register in response to detecting the at least one error in the codeword; sending, in response to detecting the at least one error in the codeword, an indication to the host device that an error was detected in response to the read command; and An internal read-modify-write cycle is performed on the codeword associated with the memory array address in the mode register, wherein the internal read-modify-write cycle includes correcting the at least one error in the codeword.

17. The method of claim 16, wherein correcting the at least one error in the codeword comprises using an ECC circuit of the memory device.

18. The method according to claim 16, further comprising: The memory array address is cleared from the mode register after performing the internal read-modify-write cycle on the codeword.

19. The method of claim 16, wherein the memory device sends the indication of a detected error using a data mask (DM) pin of the memory device.

20. The method of claim 16, wherein the memory device is coupled to the host device via a sideband bus to which at least one other memory device is coupled, and wherein the memory device sends the indication of a detected error using the sideband bus.

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