Hardware monitoring switching circuit and monitoring switching method for dual-processor system

Abstract

The invention discloses a hardware monitoring switching circuit and a hardware monitoring switching method for a dual-processor system. The circuit comprises an output circuit, a three-time falling edge detection circuit and a logical judgment circuit which are respectively connected with each processor, and a discrete magnitude output switching control circuit, the output end of each processor is connected to the input end of the corresponding output circuit and is used for transmitting discrete magnitude to the corresponding output circuit; the detection end of each processor is connected to the input end of the corresponding three-time falling edge detection circuit, and the output end of the three-time falling edge detection circuit, the heartbeat signal port of the processor and the external reset signal port of the processor are respectively connected to the input end of the corresponding logic judgment circuit. The logic judgment circuit is used for comprehensively judging the three paths of signals to form state signals of the processors; the output ends of the two logic judgment circuits are respectively connected to the input end of the discrete magnitude output switching control circuit, and the output end of the discrete magnitude output switching control circuit is respectively connected to the control ends of the two output circuits, so that state signals of the two processors are synchronously and respectively sent to the two output circuits through the discrete magnitude output switching control circuit; therefore, the two output circuits are controlled to output in combination with the state signals of the two processors.

Description

Technical Field

[0001] This invention relates to, but is not limited to, the field of embedded dual-CPU processor operating status monitoring technology, and particularly to a hardware monitoring switching circuit and monitoring switching method for dual-processor systems. Background Technology

[0002] In a system with two processors (e.g., dual DSPs, dual PPCs, or DSP+PPC) as the core processor, one processor acts as the main processor, and the other as a coprocessor. Each processor is responsible for different functions. External discrete and analog signals enter each processor and are output separately. The two processors exchange data via I / O ports. Each processor has an independent watchdog circuit. When the watchdog signal of one processor is valid, the processor's internal software enters an interrupt state. After more than three interrupts, the software enters a safe mode, waiting for a reset and not outputting anything. Simultaneously, the processor sends a command to the other processor via I / O ports, causing it to stop working. Neither processor outputs anything. Figure 1 The diagram shown is a schematic of the architecture of a dual-processor system with two processors as the core processors. Figure 2 for Figure 1 The diagram shows the signal characteristics of the dual-processor system.

[0003] The above dual-processor system operates as follows: the two processors have different processing functions, and if either processor malfunctions, the entire system will not output anything. Summary of the Invention

[0004] The purpose of this invention is to solve the above-mentioned technical problems. This invention provides a hardware monitoring and switching circuit and a monitoring and switching method for a dual-processor system, in order to solve the problem that in existing dual-processor systems, due to the different processing functions of the two processors, the entire system will not output anything if either processor malfunctions, resulting in an uncontrollable output state.

[0005] The technical solution of the present invention: In a first aspect, the embodiments of the present invention provide a hardware monitoring and switching circuit for a dual-processor system, wherein the two processors in the dual-processor system are a master processor and a slave processor, and the hardware monitoring and switching circuit includes: an output circuit, a three-falling-edge detection circuit and a logic judgment circuit respectively connected to each processor, and a discrete output switching control circuit.

[0006] Each processor's output is connected to the input of its corresponding output circuit, which is used to transmit discrete quantities to the corresponding output circuit.

[0007] Each processor's detection terminal is connected to the input terminal of the corresponding three falling edge detection circuit, and the output terminal of the three falling edge detection circuit, the processor's heartbeat signal port, and the external reset signal port are respectively connected to the input terminal of the corresponding logic judgment circuit, so that the logic judgment circuit can comprehensively judge the three signals to form the status signal of each processor.

[0008] The outputs of the two logic judgment circuits are connected to the inputs of the discrete output switching control circuit, and the outputs of the discrete output switching control circuit are connected to the control terminals of the two output circuits. The discrete output switching control circuit synchronously sends the status signals of the two processors to the two output circuits, thereby controlling the two output circuits to output based on the status signals of the two processors.

[0009] Optionally, in the hardware monitoring switching circuit for a dual-processor system as described above,

[0010] Each of the three falling edge detection circuits is used to output a three falling edge signal after detecting three falling edges of the dog barking signal inside the corresponding processor; so that the corresponding logic judgment circuit generates an abnormal state signal of the corresponding processor after making a logical judgment based on the three falling edge signal, the external reset signal and the processor heartbeat signal.

[0011] Optionally, in the hardware monitoring switching circuit for a dual-processor system as described above,

[0012] Each processor is equipped with an external watchdog timer. The processor generates a barking signal when feeding the watchdog within a specified time interval, and the barking signal outputs a high level. If the processor fails to feed the watchdog within the specified time, the barking signal outputs a low level until the next successful feeding, at which point the barking signal outputs a high level. The heartbeat signal of each processor always outputs a high level during normal operation.

[0013] When one of the processors outputs a low-level dog bark signal three times, indicating three falling edges, it signifies that the processor is malfunctioning. In the malfunctioning state of the processor, the heartbeat signal is low.

[0014] Optionally, in the hardware monitoring switching circuit for a dual-processor system as described above,

[0015] The discrete output switching control circuit integrates the processor status signals input to the two logic judgment circuits and outputs an integrated status enable signal so that the two output circuits can output according to the integrated status enable signal.

[0016] The correspondence between the processor status signal and the synthesis status enable signal is as follows:

[0017]

[0018] Each output circuit outputs when the corresponding integrated state enable signal is 0.

[0019] Optionally, the hardware monitoring switching circuit for a dual-processor system described above further includes: parallel debugging resistors R1 and R2, and pull-up resistor R3.

[0020] The external reset signal is connected to the front end of the debugging resistors R1 and R2, and the front end of the debugging resistors R1 and R2 is also connected to the power supply voltage through the pull-up resistor R3, which is used to pull the external reset signal to a high level through the pull-up resistor R3. The external reset signal is connected to the reset terminal of the main processor and the corresponding logic judgment circuit after passing through the debugging resistor R1, and the external reset signal is connected to the reset terminal of the slave processor and the corresponding logic judgment circuit after passing through the debugging resistor R2.

[0021] Optionally, in the hardware monitoring switching circuit for a dual-processor system as described above, the three falling edge detection circuit includes: a NOT gate, a counter chip, and a NAND gate;

[0022] The counter chip is used to count on the rising edge of the signal. The detection terminal of the processor is connected to the clock terminal of the counter chip through an NOT gate. When the dog bark signal is abnormal, a falling edge will appear. After the dog bark signal is inverted by the NOT gate, the counter chip counts the rising edge. After counting three times, the counter chip stops counting.

[0023] The output ports QA, QB, QC, and QD of the counter chip are binary outputs. QC and QD are pulled low by internal pins of the chip, always outputting a low level. Output ports QA and QB are connected to a NAND gate. After the counter chip counts three times, QA and QB are at a high level. After performing a NAND operation on QA and QB through the NAND gate, a low level is output.

[0024] Optionally, in the hardware monitoring switching circuit for a dual-processor system described above, the dual-processor system is configured as: dual DSP processors, dual PPC processors, or DSP+PPC processors.

[0025] When the dual-processor system is configured with a DSP+PPC processor, the control method for monitoring and switching is as follows:

[0026] 1) After the dual-processor system is powered on, the PPC processor and DSP processor work normally, and the output is provided by the output circuit of the PPC processor; if the DSP processor fails, it will not affect the normal output of the PPC processor.

[0027] 2) When the dog barking signal of the PPC processor has 3 falling edges, or when the heartbeat signal of the PPC processor is abnormal, the output circuit of the discrete output switching control circuit controls the output circuit of the DSP processor to switch to output.

[0028] 3) When both the PPC processor and the DSP processor fail, the discrete output switching control circuit will not enable each output circuit to output, and the output will be in a high impedance state.

[0029] Secondly, embodiments of the present invention also provide a monitoring and switching method for a dual-processor system, wherein the monitoring and switching method is performed on the dual-processor system using a hardware monitoring and switching circuit as described in any of the above claims, comprising:

[0030] Step 1: Collect the three falling edge signals, processor heartbeat signal, and external reset signal for each processor respectively;

[0031] Step 2: By comprehensively processing the external reset signal, the three falling edge signals of each processor, and the processor heartbeat signal, a status signal for each processor is generated.

[0032] Step 3: Based on the status signal of each processor, determine whether the output should be made by the output circuit corresponding to the main processor or the slave processor, or output a high configuration.

[0033] Optionally, in the monitoring switching method for a dual-processor system described above, after step 2, the method further includes:

[0034] Step 2a: After synthesizing the status signals of each processor, output the synthesized status enable signal;

[0035] In step 3, each output circuit outputs according to the integrated state enable signal; wherein, the correspondence between the processor state signal and the integrated state enable signal is as follows:

[0036]

[0037] Each output circuit outputs when the corresponding integrated state enable signal is 0.

[0038] The beneficial effects of this invention: The hardware monitoring and switching circuit and monitoring and switching method provided by this embodiment of the invention are suitable for hardware monitoring and output switching of dual DSPs, dual PPCs, or DSP+PPC as core processors. Using this hardware monitoring and switching circuit, in the normal state of the dual-processor system, the main processor outputs the signal. When one processor malfunctions during the operation of the dual-processor system, a three-falling-edge detection circuit detects three falling edges in the corresponding processor's internal dog bark signal and outputs a three-falling-edge signal. This signal, combined with an externally input reset signal and the processor's output heartbeat signal HB, forms the processor's status signal and is transmitted to the discrete output switching control circuit. This control circuit then outputs the correct instructions, synchronously transmitting the status signals of both processors to two output circuits, which then combine the status signals of the two processors for output. When both processors malfunction, a high-impedance state is output. Obviously, when using the hardware monitoring and switching circuit provided in this embodiment of the invention to monitor the operating status of a dual-processor system, when a fault occurs in the dual-processor system with DSP or PPC, the output status of the two processors can be quickly switched to ensure that the correct instructions are output, thereby ensuring that the two processors achieve redundant design and controllable output. Attached Figure Description

[0039] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions of the present invention.

[0040] Figure 1 The diagram shown is a schematic of the structure of a dual-processor system with two processors as the core processors.

[0041] Figure 2 for Figure 1 The diagram shows the signal characteristics of the dual-processor system.

[0042] Figure 3 A schematic diagram of a hardware monitoring and switching circuit for a dual-processor system provided in an embodiment of the present invention;

[0043] Figure 4 for Figure 3 The illustrated embodiment provides a schematic diagram of the three falling edge detection circuit in the hardware monitoring switching circuit for a dual-processor system.

[0044] Figure 5 The hardware monitoring switching circuit provided in the embodiment of the present invention is a schematic diagram of the signal of the three falling edge detection circuit in the simulation software. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0046] As explained in the background section above, in existing dual-processor systems, one processor acts as the main processor and the other as a coprocessor. The two processors have different processing functions, and if either processor malfunctions, the entire system will stop outputting data, resulting in an uncontrollable output state.

[0047] To address the aforementioned issues, this invention provides a hardware monitoring and switching circuit and a monitoring and switching method for a dual-processor system. By monitoring the operating status of the two processors and switching the output of abnormal signals, the invention ensures that the two processors achieve redundant design and that their outputs are controllable.

[0048] The present invention provides the following specific embodiments, which can be combined with each other. For the same or similar concepts or processes, they may not be described again in some embodiments.

[0049] Figure 3 This is a schematic diagram of a hardware monitoring and switching circuit for a dual-processor system provided in an embodiment of the present invention. In this embodiment, the two processors in the dual-processor system are a master processor and a slave processor, as shown below. Figure 3 As shown, the main structure of the hardware monitoring and switching circuit for a dual-processor system provided in this embodiment of the invention includes: an output circuit connected to each processor, a three-falling-edge detection circuit, a logic judgment circuit, and a discrete output switching control circuit. The hardware monitoring and switching circuit provided in this embodiment of the invention is suitable for hardware monitoring and output switching of dual-processor systems with dual DSPs, dual PowerPCs (hereinafter referred to as PPCs), or DSP+PPC as the core processor.

[0050] like Figure 3 In the structure of the hardware monitoring switching circuit shown, the output terminal of each processor is connected to the input terminal of the corresponding output circuit to transmit discrete quantities to the corresponding output circuit.

[0051] In this embodiment of the invention, the detection terminal of each processor is connected to the input terminal of the corresponding three falling edge detection circuit, and the output terminal of the three falling edge detection circuit, the heartbeat signal port of the processor, and the external reset signal port are respectively connected to the input terminal of the corresponding logic judgment circuit, so as to form the status signal of each processor after the logic judgment circuit performs comprehensive judgment on the three signals.

[0052] In this embodiment of the invention, the output terminals of the two logic judgment circuits are respectively connected to the input terminals of the discrete output switching control circuit, and the output terminals of the discrete output switching control circuit are respectively connected to the control terminals of the two output circuits, so that the discrete output switching control circuit synchronously sends the status signals of the two processors to the two output circuits, thereby controlling the two output circuits to output in combination with the status signals of the two processors.

[0053] In the hardware monitoring switching circuit provided in this embodiment of the invention, each three-falling-edge detection circuit is used to output a three-falling-edge signal after detecting three falling edges of the dog barking signal inside the corresponding processor; so that the corresponding logic judgment circuit performs a logical judgment based on the three-falling-edge signal, the external reset signal and the processor heartbeat signal, and generates an abnormal state signal for the corresponding processor.

[0054] In one implementation of this invention, each processor is equipped with an external watchdog. The processor feeds the watchdog within a specified time interval, generating a barking signal, which is output at a high level. If the processor fails to feed the watchdog within the specified time, the barking signal is output at a low level until the next successful feeding, at which point the barking signal is output at a high level. The heartbeat signal of each processor is always output at a high level during normal operation.

[0055] When one of the processors outputs a low-level dog bark signal three times, indicating three falling edges, it signifies that the processor is malfunctioning. In the malfunctioning state of the processor, the heartbeat signal is low.

[0056] In one implementation of this invention, the discrete output switching control circuit synthesizes the processor status signals input to the two logic judgment circuits and outputs a synthesis state enable signal, so that the two output circuits output according to the synthesis state enable signal.

[0057] The correspondence between processor status signals and synthesis status enable signals is shown in the table below:

[0058]

[0059] Correspondingly, each output circuit outputs when the corresponding integrated state enable signal is 0.

[0060] In one implementation of this invention, such as Figure 3 As shown, the hardware monitoring switching circuit also includes: parallel debugging resistors R1 and R2, and pull-up resistor R3.

[0061] In this implementation, the external reset signal is connected to the front end of the debugging resistors R1 and R2, and the front end of the debugging resistors R1 and R2 is also connected to the power supply voltage through the pull-up resistor R3, which is used to pull the external reset signal to a high level through the pull-up resistor R3; and the external reset signal is connected to the reset terminal of the main processor and the corresponding logic judgment circuit after passing through the debugging resistor R1, and the external reset signal is connected to the reset terminal of the slave processor and the corresponding logic judgment circuit after passing through the debugging resistor R2.

[0062] In this implementation, each processor is manually reset via external processing, that is, the reset signal is pulled low by external operation to reset each processor. This method is only used during the debugging process of a dual-processor system.

[0063] In one implementation of this invention, Figure 4 for Figure 3 The illustrated embodiment provides a schematic diagram of the three-falling-edge detection circuit in the hardware monitoring switching circuit for a dual-processor system. The three-falling-edge detection circuit in this implementation includes: a NOT gate, a counter chip, and a NAND gate.

[0064] like Figure 4 As shown, the counter chip is used to count on the rising edge of the signal; the processor's detection terminal is connected to the clock terminal of the counter chip through an NOT gate. When the dog barking signal is abnormal, a falling edge will appear. After the dog barking signal is inverted by the NOT gate, the counter chip counts the rising edge. After counting three times, the counter chip stops counting.

[0065] The counter chip's output ports QA, QB, QC, and QD are binary outputs. QC and QD are pulled low by internal pins, always outputting a low level. Output ports QA and QB are connected to a NAND gate. After the counter chip counts three times, QA and QB are at a high level. After performing a NAND operation on QA and QB through the NAND gate, a low level is output.

[0066] Based on the hardware monitoring and switching circuit for a dual-processor system provided in the above embodiments of the present invention, the present invention also provides a monitoring and switching method for a dual-processor system, wherein the monitoring and switching method is performed on the dual-processor system using the hardware monitoring and switching circuit provided in any of the above embodiments, including:

[0067] Step 1: Collect the three falling edge signals, processor heartbeat signal, and external reset signal for each processor respectively;

[0068] Step 2: By comprehensively processing the external reset signal, the three falling edge signals of each processor, and the processor heartbeat signal, a status signal for each processor is generated.

[0069] Step 3: Based on the status signal of each processor, determine whether the output should be made by the output circuit corresponding to the main processor or the slave processor, or output a high configuration.

[0070] The monitoring switching method provided in this embodiment of the invention further includes, after step 2:

[0071] Step 2a: After synthesizing the status signals of each processor, output the synthesized status enable signal;

[0072] Accordingly, in step 3, each output circuit outputs according to the synthesis state enable signal; the correspondence between the processor state signal and the synthesis state enable signal is shown in the table below:

[0073]

[0074] Each output circuit outputs when the corresponding integrated state enable signal is 0.

[0075] The hardware monitoring and switching circuit and method for dual-processor systems provided in this invention are applicable to hardware monitoring and output switching for dual DSPs, dual PPCs, or DSP+PPC as core processors. Using this hardware monitoring and switching circuit, in the normal state of the dual-processor system, the main processor provides the output. When one processor malfunctions during operation, a three-falling-edge detection circuit detects three falling edges in the corresponding processor's internal dog barking signal and outputs a three-falling-edge signal. This signal, combined with an externally input reset signal and the processor's output heartbeat signal HB, forms the processor's status signal and is transmitted to the discrete output switching control circuit. This control circuit then outputs the correct instructions, synchronously transmitting the status signals of both processors to two output circuits, which in turn combine the status signals of the two processors for output. When both processors malfunction, a high-impedance output is generated. Obviously, when using the hardware monitoring and switching circuit provided in this embodiment of the invention to monitor the operating status of a dual-processor system, when a fault occurs in the dual-processor system with DSP or PPC, the output status of the two processors can be quickly switched to ensure that the correct instructions are output, thereby ensuring that the two processors achieve redundant design and controllable output.

[0076] The following implementation example illustrates the implementation of the hardware monitoring and switching circuit and monitoring and switching method for a dual-processor system provided in this invention.

[0077] Implementation Example

[0078] like Figure 3 and Figure 4As shown, the hardware monitoring switching circuit for a dual-processor system provided in this embodiment includes: an output circuit connected to a single processor, a three-falling-edge detection circuit and a logic judgment circuit, and a discrete output switching control circuit.

[0079] The hardware monitoring switching circuit provided in this implementation example operates on the following principle: the hardware monitoring switching circuit is applied to dual-DSP, dual-PPC, or DSP+PPC dual-processor systems, and the framework is as follows: Figure 3 As shown in the table below, the names and meanings of the signals in the hardware monitoring switching circuit are listed.

[0080]

[0081]

[0082] like Figure 3 In the diagram, R3 is a pull-up resistor, and R1 and R2 are 0-ohm resistors (for easy debugging). DI_RST is pulled high by R3, allowing for manual reset of each processor externally. This is achieved by externally pulling the reset signal low to reset the processor, used during debugging. Both the master and slave processors are equipped with external watchdogs. Each processor feeds the watchdog at specified time intervals, generating a barking signal (WDO1 / WDO2). If a processor fails to feed the watchdog within the specified time, the barking signal is pulled low until the next feeding. If a processor's barking signal is pulled low three times, it indicates a malfunction. The heartbeat signals HB1 / HB2 are always high during normal software operation. The operating status of the master and slave processors can be logically determined by combining the processor's barking signal, heartbeat signal, and external reset signal. When the dual-processor system is configured as a DSP+PPC processor, the monitoring and switching control method is as follows:

[0083] 1) After the dual-processor system is powered on, the PPC processor and DSP processor work normally, and the output is provided by the output circuit of the PPC processor. When the DSP processor malfunctions (i.e., when the dog bark signal has 3 falling edges or the DSP processor heartbeat signal HB signal goes low), it does not affect the normal output of the PPC processor.

[0084] 2) When the dog barking signal of the PPC processor WDO1 shows 3 falling edges, or when the heartbeat signal HB1 of the PPC processor is abnormal, the output circuit of the discrete output switching control circuit controls the output to switch to the output circuit of the DSP processor.

[0085] 3) When both the PPC processor and the DSP processor fail, the discrete output switching control circuit will not enable each output circuit (e.g., the SM16245 chip) to output, and the output will be in a high impedance state.

[0086] In this implementation example, the principle of the three-falling-edge detection circuit for detecting dog barks is as follows: the three-falling-edge detection circuit is used to detect unstable low-level pulses in the dog bark signal. When three unstable low-level pulses occur, the three-falling-edge detection circuit outputs a WDO1_NEG3 / WDO2_NEG3 low-level signal. Figure 5 The diagram shows a simulation of a three-falling-edge detection circuit in simulation software, based on the hardware monitoring switching circuit provided in this embodiment of the invention. A signal generator (XFG6) generates a frequency signal to simulate a dog barking signal. A counter chip (74LS161D) starts counting at the rising edge of the CLK clock. The dog barking signal WDO is normally high. When the dog barking signal is abnormal, a falling edge appears, inverting the signal (from normally high to normally low) and connecting it to the clock port of the counter chip. Each time the dog barking signal jitters (a falling edge appears, which is then inverted to a rising edge), it counts once. After three jitters, the counter chip stops counting. The chip output ports QA, QB, QC, and QD are binary outputs. QC and QD are pulled low through internal pins, always outputting a low level. After counting three times (i.e., counting to 3), QA and QB go high, and a NAND operation is performed between QA and QB to output a low level. Figure 5 It can be seen that after three falling edges, the processor status signal output by the three falling edge detection circuit is low.

[0087] In this implementation example, the principle of the output switching control circuit is as follows: Taking the main processor as an example, it performs an AND operation on the dog bark signal and heartbeat signal (DI_RST is always high during normal operation) after three falling edge detections, and outputs S1. Figure 5 As shown, similar to the main processor, after logical operations on S1 and S2, two enable signals EN_Satae1 and EN_Satae2 are output. When the enable signal is low, the SM164245 chip is enabled to output. The truth table for S1, S2, EN_Satae1, and EN_Satae2 is shown in Table 2. Based on the truth table, the logical relationship can be derived and simplified to obtain the following formula. Based on the logical relationship, the hardware circuit and simulation results are as follows: Figure 5 The S1 and S2 signal states are simulated by using XFG1 and XFG2 to generate high and low levels. The simulation results on the oscilloscope are S1, S2, EN_Satae1, and EN_Satae2 from top to bottom.

[0088]

[0089] While the embodiments disclosed in this invention are as described above, they are merely illustrative of the embodiments to facilitate understanding of the invention and are not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and variations in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection for this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A hardware monitoring switching circuit for a dual-processor system, characterized in that: The two processors in the dual-processor system are respectively a master processor and a slave processor, and the hardware monitoring switching circuit comprises: an output circuit connected to each processor, a three-falling edge detection circuit and a logic judgment circuit, and a discrete quantity output switching control circuit; Wherein, the output terminal of each processor is connected to the input terminal of the corresponding output circuit for transmitting the discrete quantity to the corresponding output circuit; The detection end of each processor is connected to the input end of the corresponding three-falling edge detection circuit, and the output end of the three-falling edge detection circuit, the heartbeat signal port and the external reset signal port of the processor are respectively connected to the input end of the corresponding logic judgment circuit, so as to form the state signal of each processor after comprehensive judgment of the three-way signal by the logic judgment circuit; The output ends of the two logic judgment circuits are respectively connected to the input ends of the discrete output switching control circuit, and the output ends of the discrete output switching control circuit are respectively connected to the control ends of the two output circuits, so that the status signals of the two processors are synchronously sent to the two output circuits through the discrete output switching control circuit, thereby controlling the two output circuits to output in combination with the status signals of the two processors.

2. The hardware monitoring switching circuit for a dual-processor system according to claim 1, characterized in that: Each of the three falling edge detection circuits is used to output a three-edge falling signal after detecting three falling edges of the dog barking signal inside the corresponding processor; so that the corresponding logic judgment circuit performs logic judgment based on the three-edge falling signal, the external reset signal and the processor heartbeat signal, and generates an abnormal status signal of the corresponding processor.

3. The hardware monitoring switching circuit for a dual-processor system according to claim 2, characterized in that: Each processor is equipped with an external watchdog. When the processor feeds the dog within the specified time interval, a barking signal is generated, and the barking signal outputs a high level. If the processor fails to feed the dog within the specified time, the barking signal outputs a low level until the next time the dog is fed successfully, the barking signal outputs a high level. The heartbeat signal of each processor always outputs a high level during normal operation. When one of the processors outputs a low level barking signal three times, three falling edge signals are detected, indicating that the processor is abnormal, and the heartbeat signal is low level when the processor is in an abnormal state.

4. The hardware monitoring switching circuit for a dual-processor system according to claim 3, characterized in that: The discrete output switching control circuit integrates the processor status signals input to the two logic judgment circuits and outputs a comprehensive status enable signal, so that the two output circuits output according to the comprehensive status enable signal; Among them, the corresponding relationship between the processor status signal and the comprehensive status enable signal is: Each output circuit outputs when the corresponding integrated state enable signal is 0.

5. The hardware monitoring switching circuit for a dual processor system according to any one of claims 1 to 4, characterized in that: Also includes: Debug resistors R1 and R2 connected in parallel, and pull-up resistor R3; Among them, the external reset signal is connected to the front end of the debugging resistors R1 and R2, and the front end of the debugging resistors R1 and R2 is also connected to the power supply voltage through the pull-up resistor R3, which is used to pull the external reset signal to a high level through the pull-up resistor R3; and the external reset signal is connected to the reset end of the main processor and the corresponding logic judgment circuit respectively after passing through the debugging resistor R1, and the external reset signal is connected to the reset end of the slave processor and the corresponding logic judgment circuit respectively after passing through the debugging resistor R2.

6. The hardware monitoring switching circuit for a dual processor system according to any one of claims 1 to 4, characterized in that: The three falling edge detection circuit comprises: a NOT gate, a counter chip, and a NAND gate; The counter chip is used to count on the rising edge of the signal; the detection end of the processor is connected to the clock end of the counter chip through a NOT gate. When the dog barking signal is abnormal, a falling edge will appear. After the dog barking signal is inverted through the NOT gate, the counter chip counts the rising edge. After counting three times, the counter chip stops counting. The output ports QA, QB, QC, and QD of the counter chip are binary outputs, wherein QC and QD are pulled low by the internal pins of the chip and always output a low level; the output ports QA and QB are connected to the NAND gate, and after the counter chip counts three times, QA and QB are high levels, and a low level is output after a NAND operation is performed on QA and QB through the NAND gate.

7. The hardware monitoring switching circuit for a dual processor system according to any one of claims 1 to 4, characterized in that: The dual processor system is configured as: dual DSP processors, dual PPC processors, or DSP+PPC processors; When the dual-processor system is configured as DSP+PPC processor, the control method of monitoring switching is: 1) After the dual-processor system is powered on, the PPC processor and DSP processor work normally, and the output circuit of the PPC processor performs the output; when the DSP processor fails, the normal output of the PPC processor is not affected; 2) When the barking signal of the PPC processor has three falling edges, or the heartbeat signal of the PPC processor is abnormal, the discrete output switching control circuit outputs a comprehensive state enable signal to switch to the output circuit of the DSP processor for output; 3) When both the PPC processor and the DSP processor fail, the discrete output switching control circuit does not enable each output circuit to output, and the output is in a high impedance state.

8. A monitoring switching method for a dual-processor system, characterized in that: A method for performing monitoring switching on a dual processor system using the hardware monitoring switching circuit according to any one of claims 1 to 7 comprises: Step 1, respectively collecting three falling edge signals of each processor, the processor heartbeat signal, and collecting the external reset signal; Step 2, generating a status signal of each processor by comprehensively processing the external reset signal, the three falling edge signals of each processor, and the processor heartbeat signal; Step 3: Based on each processor status signal, determine whether the output circuit corresponding to the master processor or the slave processor performs output, or outputs a high configuration.

9. The monitoring switching method for a dual-processor system according to claim 8, characterized in that: After step 2, the method further includes: Step 2a, after synthesizing the state signal of each processor, outputting a comprehensive state enable signal; In step 3, each output circuit performs output according to the comprehensive state enable signal; wherein the corresponding relationship between the processor state signal and the comprehensive state enable signal is: Each output circuit outputs when the corresponding integrated state enable signal is 0.

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