Cache device, cache access method, processor, chip and electronic equipment

Abstract

The invention discloses a cache device, a cache access method, a processor, a chip and electronic equipment, and belongs to the field of processors. The cache device comprises a cache unit and an output merging unit; the cache unit is used for sending the at least two sub-requests or hit state information of the at least two sub-requests to the output merging unit under the condition that the at least two sub-requests are obtained, the at least two sub-requests are obtained by responding to splitting of the memory access request, and the request granularity of the memory access request is larger than the cache line granularity corresponding to the cache unit; and the output merging unit is used for sending the memory access request to a downstream storage device under the condition that the at least two sub-requests are received, or sending the memory access request and the hit state information of the at least two sub-requests to the downstream storage device under the condition that the hit state information of the at least two sub-requests is received. The invention provides a cache device capable of supporting larger request granularity.

Description

Technical Field

[0001] The present application relates to the field of processors, and in particular to a cache device, a cache access method, a processor, a chip, and an electronic device. Background Art

[0002] Cache is an essential device in modern processors. Cache is located between the processor core and the main memory to make up for the difference in operating speed between the processor core and the main memory.

[0003] In the related art, the request initiating unit will initiate a memory access request to the cache. Generally, the request granularity of the memory access request is not larger than the cache line size. If the request granularity of the memory access request is larger than the cache line size, the request initiating unit will also split the original memory access request into multiple sub-requests with a maximum request granularity of the cache line size, and each sub-request accesses the cache independently.

[0004] In the related art, the cache can only support memory access requests with a maximum granularity of cache lines, and even memory access requests with a larger request granularity will be split into sub-requests with a smaller request granularity. In some scenarios, the cache can only support memory access requests with a maximum granularity of cache lines, resulting in low transmission efficiency. Summary of the invention

[0005] The present application provides a cache device, a cache access method, a processor, a chip and an electronic device, wherein the cache device can support memory access requests with a larger request granularity.

[0006] According to one aspect of the present application, a cache device is provided, the cache device comprising a cache unit and an output merging unit;

[0007] A cache unit, configured to send the at least two sub-requests or hit status information of the at least two sub-requests to the output merging unit when at least two sub-requests are obtained, the at least two sub-requests being obtained in response to splitting the memory access request, and the request granularity of the memory access request being greater than the cache line granularity corresponding to the cache unit;

[0008] The output merging unit is used to send the memory access request to the downstream storage device when at least two sub-requests are collected, or to send the memory access request and the hit status information of at least two sub-requests to the downstream storage device when the hit status information of at least two sub-requests is collected.

[0009] According to one aspect of the present application, a cache access method is provided, the method being applied to the cache device as described above, the method comprising:

[0010] The cache unit determines hit status information of at least two sub-requests, where the at least two sub-requests are obtained in response to splitting memory access requests, and a request granularity of the memory access request is greater than a cache line granularity corresponding to the cache unit;

[0011] The output merging unit sends the memory access request to the downstream storage device when at least two sub-requests are received, or sends the memory access request and the hit status information of at least two sub-requests to the downstream storage device when the hit status information of at least two sub-requests are received.

[0012] According to one aspect of the present application, a processor is provided, the processor including a cache device for implementing the above-mentioned cache device.

[0013] According to one aspect of the present application, a chip is provided, the chip includes a processor, and the processor includes the cache device as described above.

[0014] According to one aspect of the present application, a graphics card is provided, and the graphics card includes the cache device as described above.

[0015] According to one aspect of the present application, a server is provided, and the server includes the cache device as described above.

[0016] According to one aspect of the present application, an electronic device is provided, the electronic device comprising: a processor, the processor comprising the cache device as described above. The electronic device may be a terminal device. The terminal device may be a mobile phone, a computer, an intelligent voice interaction device, a smart home appliance, a vehicle-mounted terminal, etc., but is not limited thereto.

[0017] The beneficial effects brought about by the technical solution provided in the embodiments of the present application include at least the following.

[0018] In the present application, by building a cache unit and an output merging unit in a cache device, the cache device responds to a memory access request with a split request granularity greater than a cache line granularity, and obtains at least two sub-requests; the cache unit is used to send the split sub-requests or the hit status information of the split sub-requests to the output merging unit, and the output merging unit is used to send the memory access request to the downstream storage device when at least two sub-requests are collected, or, when the hit status information of at least two sub-requests are collected, send the memory access request and the hit status information of at least two sub-requests to the downstream storage device, so that the cache device supports memory access requests with larger request granularity. The input of the cache device can be a memory access request with a larger request granularity, and then the output of the cache device can be data of a larger size, rather than being able to output only one cache line granularity at most. For cross-die (basic unit with complete functions on a chip) or cross-chip access scenarios, the larger size of the output makes the amount of other auxiliary information transmitted by the downstream transmission unit (such as PCIE) smaller (other auxiliary information is the auxiliary information required when transmitting the output of the cache), and then the downstream transmission unit has a greater transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 It is a schematic diagram of the structure of a cache device provided by an embodiment of the present application.

[0021] Figure 2 It is a schematic diagram of a processing procedure for a first read request provided by an embodiment of the present application.

[0022] Figure 3 It is a schematic diagram of a processing procedure for a first read request provided by another embodiment of the present application.

[0023] Figure 4 It is a schematic diagram of a method for determining a cache set for a memory access request in a normal mode provided by an embodiment of the present application.

[0024] Figure 5 It is a schematic diagram of a processing procedure for a first write request provided by an embodiment of the present application.

[0025] Figure 6 It is a schematic diagram of the processing process for the first write request provided by another embodiment of the present application.

[0026] Figure 7It is a schematic diagram of a processing procedure for a second read request provided by an embodiment of the present application.

[0027] Figure 8 It is a schematic diagram of a processing procedure for a second read request provided by another embodiment of the present application.

[0028] Fig. 9 It is a schematic diagram of a method for determining a cache set for a memory access request in bypass mode provided by an embodiment of the present application.

[0029] Fig.10 It is a schematic diagram of a processing procedure for a second write request provided by an embodiment of the present application.

[0030] Fig.11 It is a schematic diagram of the processing process for the second write request provided by another embodiment of the present application.

[0031] Fig.12 It is a structural block diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0033] First, the nouns involved in the embodiments of the present application are briefly introduced.

[0034] Cache: It is a buffer for data exchange. When the processor core wants to read data, it will first search for the required data from the cache. If the target data is found in the cache, it will be executed directly. If the target data cannot be found in the cache, it will be searched from the main memory (main memory). The cache is located between the processor core and the main memory. The running speed of the cache is faster than the main memory. It is used to make up for the difference in running speed between the processor core and the main memory, so as to facilitate fast access to data and help the processor core run faster.

[0035] Cache line size: the size of a cache line. Optionally, the cache line size is 32 bytes, 64 bytes, 128 bytes, etc. Request granularity refers to the size of data to be accessed by a memory access request (read request or write request). In the related art, the cache only supports memory access requests that are no larger than a cache line size. That is, the maximum granularity of the memory access request in the related art is R (cache line size), in bytes. This application will provide a cache that supports a larger request granularity, which can be (1 to N)*R bytes.

[0036] Cache Bank: To improve the parallel read efficiency of the cache, the cache is divided into multiple cache banks, each of which has its own read and write peripheral circuits, so that the processor core can access multiple cache banks in parallel. For a cache bank, the cache bank includes at least one cache group and at least one cache way.

[0037] Hash operation: In this application, it refers to the operation of mapping the address of a memory access request to the identifier (Bank id) of a target cache set in multiple cache sets. In this application, a hash operation is performed based on the address of a memory access request, aiming to achieve load balancing of multiple cache sets. When a series of memory access requests access the cache, the cache set identifiers corresponding to each of these memory access requests are obtained through a hash operation, and then assigned to their respective cache sets, that is, the purpose of the hash operation is to try to evenly distribute these memory access requests to multiple cache sets, and multiple cache sets process these memory access requests in parallel. If the hash operation is not performed and it is directly assigned to a cache set, it may cause serious conflicts in the cache sets, that is, only one cache set may be working at the same time, and the performance of other cache sets is wasted.

[0038] Figure 1 A schematic diagram of a cache device provided by an exemplary embodiment of the present application is shown, and the cache device 100 includes a request splitting unit 101, a cache unit 102, an output merging unit 103 and a read data merging unit 104. The input end 1011 of the request splitting unit 101 is used to connect to the output end 1051 of the external request initiating unit 105. The output end 1012 of the request splitting unit 101 is connected to the input end 1021 of the cache unit 102. Optionally, the cache unit 102 includes at least one cache bank. The request splitting unit 101 is used to split a memory access request into at least two sub-requests, and the request granularity of the memory access request is larger than the cache line granularity corresponding to the cache unit 102. It should be noted that the "connected" referred to in the present application can be a direct connection between two hardware units, or it can be an indirect connection, that is, the two hardware units are electrically connected.

[0039] The first output terminal 1022 of the cache unit 102 is connected to the input terminal 1031 of the output merging unit 103. The output terminal 1032 of the output merging unit 103 is used to connect to the external downstream storage device 106. The downstream storage device 106 can be a lower-level cache or a main memory. The output merging unit 103 is used to collect at least two sub-requests or the hit status information of at least two sub-requests.

[0040] The first input terminal 1041 of the read data merging unit 104 is used to connect to the downstream storage device 106, the second input terminal 1042 of the read data merging unit 104 is connected to the second output terminal 1023 of the cache unit 102, the output terminal 1043 of the read data merging unit 104 is used to connect to the input terminal 1052 of the request initiating unit 105, and return the aggregated read data to the request initiating unit 105. The read data merging unit 104 is used to merge the read data read from the cache unit 102 and / or the downstream storage device 106.

[0041] In the embodiment of the present application, the cache unit 102, when obtaining at least two sub-requests, sends the at least two sub-requests or the hit status information of at least two sub-requests to the output merging unit 103, the at least two sub-requests are obtained in response to splitting the memory access request, and the request granularity of the memory access request is greater than the cache line granularity corresponding to the cache unit. Optionally, the at least two sub-requests are obtained by splitting the memory access request by the cache device 100, or the at least two sub-requests are obtained by splitting the memory access request by a device outside the cache device 100.

[0042] The output merging unit 103, when receiving at least two sub-requests, sends the memory access request to the downstream memory device 106. It can be understood that at this time, the cache device 100 does not respond to the memory access request to perform read and write operations, but sends the memory access request to the downstream memory device 106 for response. Alternatively, when the hit status information of at least two sub-requests is collected, the memory access request and the hit status information of at least two sub-requests are sent to the downstream memory device 106. It can be understood that at this time, the cache device 100 sends the hit status information to the downstream memory device 106, and the downstream memory device 106 performs read and write operations in response to the sub-request in the missing state, and the cache device 100 performs read and write operations in response to the sub-request in the hit state.

[0043] For normal mode read request:

[0044] based on Figure 1 The cache device 100 shown, Figure 2 A schematic diagram of a method for processing a memory access request provided by an exemplary embodiment of the present application is shown. Figure 2 The processing method for the first read request is shown.

[0045] The request initiating unit 105 sends a memory access request to the request splitting unit 101 .

[0046] The request splitting unit 101 determines that the received memory access request is a normal mode read request, and the data requested by the memory access request is distributed on M cache lines, where M is a positive integer greater than 1, that is, the request splitting unit 101 determines that the memory access request is a first read request.

[0047] In one embodiment, the request splitting unit 101 determines that the read request is the first read request based on the starting address and request length of the received normal mode read request. Schematically, the request splitting unit 101 determines whether the sum of the starting address and request length of the received normal mode read request exceeds the address range of the cache line corresponding to the starting address. If it exceeds, it means that the data requested by the read request is distributed on multiple cache lines, that is, the read request is the first read request. If it does not exceed, the read request is processed according to the relevant technology, and the request granularity of the read request must be smaller than the cache line granularity.

[0048] The request splitting unit 101 splits the first read request into M (a positive integer greater than 1) sub-requests, where the M sub-requests correspond one-to-one to the M cache lines. The request splitting unit 101 sends the M sub-requests to the cache unit 102 .

[0049] Combined with reference Figure 2 , the cache unit 102 is used to perform a hit test on the M sub-requests, and send the hit status or miss status of each sub-request in the M sub-requests to the output merging unit 103. The cache unit 102 includes at least one cache set (Cache Bank), each cache set is a cache organization form of a set-associative cache (multi-way set-associative cache), each cache set includes multiple cache groups (often referred to as: groups) and multiple cache ways (often referred to as: ways), and the intersection unit of a cache group and a cache way is a cache line. For each sub-request in the M sub-requests, the cache unit 102 is used to perform a hit test on the sub-request, that is, to determine whether the cache unit 102 stores the cache line corresponding to the sub-request. If the cache unit 102 stores the cache line corresponding to the sub-request, it is determined that the sub-request is in a hit state; if the cache unit 102 does not store the cache line corresponding to the sub-request, it is determined that the sub-request is in a miss state.

[0050] The cache unit 102 sends the hit status or miss status of each of the M sub-requests to the output merging unit 103. The output merging unit 103 is used to collect the hit status or miss status of the M sub-requests, and when the hit status or miss status of the M sub-requests are collected, send the first read request and the hit status or miss status of the M sub-requests to the downstream storage device 106.

[0051] Exemplarily, the output merging unit 103 checks whether the received first read request corresponds to M sub-requests. If so, it needs to wait until the hit status or the missing status corresponding to each of the M sub-requests is successfully received.

[0052] When the hit status or miss status of M sub-requests are collected, the output merging unit 103 generates a read need data mask (read_need_data_mask), which includes M bits. The i-th bit of the M bits corresponds to the i-th sub-request, and the value of each bit indicates that the corresponding sub-request is a hit status or a miss status. For example, a bit value of 1 indicates that the corresponding sub-request is a hit status, and a bit value of 0 indicates that the corresponding sub-request is a miss status.

[0053] The output merging unit 103 sends a first read request and a read required data mask to the downstream memory device 106 .

[0054] The downstream storage device 106 returns the cache line corresponding to the sub-request in the missing state, that is, the first data, to the read data merging unit 104 according to the hit state or the miss state of the M sub-requests. The read data merging unit 104 is used to aggregate the first data and the second data to obtain the merged data, and return the merged data to the request initiating unit 105. The cache unit 102 sends the cache line corresponding to the sub-request in the hit state, that is, the second data, to the read data merging unit 104. The read data merging unit 104 aggregates the first data and the second data to obtain the merged data, and returns the merged data to the request initiating unit 105.

[0055] Based on the above embodiment, the data requested by the first read request supported by the cache device 100 is distributed on M cache lines, where M is a positive integer greater than 1. The present application splits the first read request into M sub-requests corresponding to the M cache lines one by one through the request splitting unit 101, so that the request granularity of each sub-request is not greater than the cache line granularity, that is, the present application provides a cache device 100 supporting a larger request granularity, and the request granularity of the first read request can be greater than 1 cache line granularity. For cross-die (basic unit with complete functions on a chip) or cross-chip access scenarios, the larger size of the output makes the amount of other auxiliary information transmitted by the downstream transmission unit (such as PCIE) smaller, and thus the downstream transmission unit has a greater transmission efficiency.

[0056] based on Figure 2 The first read request processing method shown is, optionally, Figure 2 The cache unit 102 includes B cache banks, where B is a positive integer of 1 or greater than 1, and optionally, B is four.

[0057] For B being a positive integer greater than 1:

[0058] Combined with reference Figure 3After the request splitting unit 101 splits and obtains M sub-requests, for the first sub-request among the M sub-requests, the first sub-request is any sub-request among the M sub-requests, and the first sub-request is sent to the first cache set 301 among the B cache sets, and the first cache set 301 is the cache set corresponding to the first sub-request. The first cache set 301 is used to perform a hit test on the first sub-request. For the other sub-requests among the M sub-requests, they are all sent to their corresponding cache sets.

[0059] When performing a hit test, if the first cache set 301 stores a cache line corresponding to the first sub-request, it is determined that the first sub-request is in a hit state; if the first cache set 301 does not store a cache line corresponding to the first sub-request, it is determined that the first sub-request is in a miss state. The first cache set 301 sends the hit state or miss state of the first sub-request to the output merging unit 103.

[0060] In an optional embodiment, the first cache set 301 is also used to mark the first cache line corresponding to the first sub-request as a locked state when the first sub-request is in a hit state; and mark the first cache line as an unlocked state when the read data merging unit 104 aggregates the merged data. In the locked state, if there are other memory access requests to access the first cache line, it is necessary to wait for the first cache line to be unlocked before accessing the first cache line. By locking the first cache line in advance and unlocking the first cache line after aggregation, the data consistency of the first cache line can be guaranteed (the cache data read is the cache data written before, not the initialization data in the main memory), avoiding other memory access requests from accessing the first cache line that has not been read.

[0061] In an optional embodiment, the first cache set 301 is also used to backfill the first cache line based on the first cache line requested by the first sub-request returned by the downstream storage device 106 when the first sub-request is in a missing state and the first sub-request carries an indication of allocating a cache line. Schematically, if the first sub-request is in a missing state, whether to allocate a cache line for it is selected according to the read allocate hint information (read allocate hint) carried by the first sub-request, and if there is an indication of allocating a cache line, the first cache line returned by the downstream storage device 106 is backfilled into the first cache set 301. The backfill operation refers to the operation of obtaining the first cache line corresponding to the first read request from the downstream storage device 106 and storing the first cache line in the first cache set 301 when the first cache line corresponding to the first read request is missing in the first cache set 301.

[0062] Next, a method for determining the first cache set 301 corresponding to the first sub-request is introduced.

[0063] After the request splitting unit 101 splits out M sub-requests, it is necessary to determine the cache set corresponding to each sub-request. For the first sub-request, the request splitting unit 101 is also used to perform a hash operation based on the base address of the first cache line to obtain the identifier of the first cache set 301; based on the identifier of the first cache set 301, the first sub-request is sent to the first cache set 301. Among them, the first cache line is the cache line corresponding to the first sub-request. The hash operation is an operation of extracting bits from the base address. Exemplarily, the base addresses of the M cache lines correspond to Addr0, Addr1, ..., Addr(M-1) in sequence.

[0064] In one embodiment, the request splitting unit 101 is also used to obtain an identifier of the first cache set 301 based on a first bit sequence, and the starting bit of the first bit sequence is determined in the base address of the first cache line using a hash operation based on a first parameter R and a second parameter B. The first parameter R is the cache line size (Cache line size) in bytes, and the second parameter B is the number of cache sets in the cache unit 102.

[0065] In one possible implementation, the starting bit of the first bit sequence has a first numerical value in a sorting position from low to high in the base address of the first cache line, and the first numerical value is a value obtained by subtracting one from the sum of the base-two logarithm of the first parameter R and the base-two logarithm of the second parameter B, wherein the starting value of the sorting position is zero, that is, the first sorting position is bit 0.

[0066] The end bit of the first bit sequence is determined in the base address of the first cache line by using a hash operation based on the first parameter R. In one possible implementation, the end bit of the first bit sequence is sorted from low to high in the base address of the first cache line as a second value, and the second value is the base-two logarithm of the first parameter R, wherein the starting value of the sorting position is zero, that is, the first sorting position is bit 0.

[0067] Combined with reference Figure 4 , Figure 4 The base addresses of the cache lines corresponding to different sub-requests are shown. Figure 4 In the case shown, the cache line granularity R is 32, that is, the base address interval between two cache lines is 32 bytes (0x20), and B is the number of cache sets, four. At this time, the first value is [log2R]+[log2B]-1==6, and the second value is log2R==5. Figure 4 It shows the situation where four sub-requests are split from a read request (that is, the data requested by the read request is distributed in four cache lines). Figure 4 Subrequests 0, 1, 2, and 3 are split from one read request, and subrequests 4, 5, 6, and 7 are split from another read request.

[0068] The hexadecimal base address of subrequest 0 is 10000, and the binary base address is 0001 0000 0000 00000000. Counting from low to high, the sixth bit (i.e., the seventh bit) is 0, and the fifth bit (i.e., the sixth bit) is 0. Therefore, the cache set identifier corresponding to subrequest 0 is 00.

[0069] The hexadecimal base address of subrequest 1 is 10020, and the binary base address is 0001 0000 0000 00100000. Counting from low to high, the 6th bit (i.e., the 7th bit) is 0, and the 5th bit (i.e., the 6th bit) is 1. Therefore, the cache set identifier corresponding to subrequest 1 is 01, and so on.

[0070] It can be found that according to the above-mentioned method for determining the cache set identifier, every N (optional, N is 4) sub-requests will be evenly distributed in B (optional, B is 4) cache sets. The present application provides a cache set balancing solution for memory access requests with larger request granularity, and the M sub-requests split out are evenly distributed in B cache sets.

[0071] The above describes the processing method of the first read request in the normal mode. The data requested by the first read request is distributed in M ​​cache lines, where M is a positive integer greater than 1. For the third read request in the normal mode, the data requested by the third read request is distributed in one cache line. The processing method provided is as follows:

[0072] For the third read request in which the requested data is distributed on a cache line, the request splitting unit 101 sends the third read request to the cache unit 102, and the cache unit 102 is used to perform a hit test on the third read request. If the cache line corresponding to the third read request is stored in the cache unit 102, it is determined that the third read request is in a hit state; if the cache line corresponding to the third read request is not stored in the cache unit 102, it is determined that the third read request is in a missing state.

[0073] The cache unit 102 is used to send the hit status or miss status of the third read request to the output merging unit 103. The output merging unit 103 is used to send the miss status of the third read request to the downstream storage device 106 when the third read request is in the miss status. The downstream storage device 106 sends the cache line corresponding to the third read request to the read data merging unit 104, and the read data merging unit 104 returns the cache line corresponding to the third read request to the request initiating unit 105.

[0074] Optionally, the cache unit 102 includes B cache sets, where B is a positive integer greater than 1. For the case where B is a positive integer greater than 1, the request splitting unit 101 is used to send the third read request to the corresponding cache set. The request splitting unit 101 performs a hash operation based on the starting address of the third read request to obtain an identifier of the corresponding cache set; and sends the third read request to the corresponding cache set. This is similar to the method of calculating the identifier of the first cache set corresponding to the first sub-request mentioned above and will not be repeated here.

[0075] It is worth noting that, in the present application, no matter the request granularity of the input memory access request is greater than a cache line granularity or less than a cache line granularity, the cache device 100 provided in the present application can support the memory access request. Specifically, the request splitting unit 101, the cache unit 102, the output merging unit 103, and the read data merging unit 104 will each provide a certain processing function for the input memory access request.

[0076] For normal mode write requests:

[0077] based on Figure 1 The cache device 100 shown, Figure 5 A schematic diagram of a method for processing a memory access request provided by an exemplary embodiment of the present application is shown. Figure 5 The processing method for the first write request is shown.

[0078] The request initiating unit 105 sends a memory access request to the request splitting unit 101 .

[0079] The request splitting unit 101 determines that the received memory access request is a normal mode write request, and the data requested by the memory access request is distributed on P cache lines, where P is a positive integer greater than 1, that is, the request splitting unit 101 determines that the memory access request is a first write request.

[0080] The request splitting unit 101 determines that the write request is the first write request based on the start address and request length of the received write request in the normal mode. Schematically, the request splitting unit 101 determines whether the sum of the start address and request length of the received write request exceeds the address range of the cache line corresponding to the start address. If it exceeds, it means that the data requested by the write request is distributed on multiple cache lines, that is, the write request is the first write request. If it does not exceed, the request granularity of the write request must be smaller than the cache line granularity.

[0081] The request splitting unit 101 splits the first write request into P (a positive integer greater than 1) sub-requests, where the P sub-requests correspond one-to-one to the P cache lines, and sends the P sub-requests to the cache unit 102 .

[0082] The cache unit 102 is used to perform a hit test on the P sub-requests, and send the hit status or miss status of each of the P sub-requests to the output merging unit 103. For a sub-request in the P sub-requests that is in a hit status, the cache line corresponding to the sub-request is set to an invalid state, and the cache line is not written.

[0083] By setting the cache line corresponding to the sub-request in the hit state to an invalid state and not writing the cache line, the data consistency of the cache line can be guaranteed (the cache data read is the cache data written before, not the initialized data in the main memory). In the present application, even if the cache line in the cache unit 102 is hit, the data of the cache line will not be changed. When the next memory access request arrives, if the memory access request hits the cache line, since the cache line is set to an invalid state in the cache unit 102, the next memory access request will access the downstream storage device 106 and read and write based on the cache line in the downstream storage device 106.

[0084] Combined with reference Figure 6 , the cache unit 102 sends the P sub-requests to the output merging unit 103. The output merging unit 103 is used to send a first write request to the downstream storage device 106 when all the P sub-requests are received. The output merging unit 103 checks whether the received first write request corresponds to the P sub-requests. If so, it is necessary to wait until all the P sub-requests are successfully received. When all the P sub-requests are received, the first write request is sent to the downstream storage device 106. The downstream storage device 106 sends a first write response corresponding to the first write request to the cache device 100, and the cache device 100 feeds the first write response back to the request initiating unit 105. The cache device 100 does not process the first write response, and bypasses the first write response to the request initiating unit 105.

[0085] Based on the above embodiment, the data requested by the first write request supported by the cache device 100 is distributed on P cache lines, where P is a positive integer greater than 1. The present application splits the first write request into P sub-requests corresponding to the P cache lines one by one through the request splitting unit 101, so that the request granularity of each sub-request is not greater than the cache line granularity, that is, the present application provides a cache device 100 supporting a larger request granularity, and the request granularity of the first write request can be greater than 1 cache line granularity. For cross-die (basic unit with complete functions on a chip) or cross-chip access scenarios, the downstream transmission unit has greater transmission efficiency.

[0086] based on Figure 5 The first write request processing method shown is optional. Figure 5 The cache unit 102 includes B cache banks, where B is a positive integer of 1 or greater than 1, and optionally, B is four.

[0087] For B being a positive integer greater than 1:

[0088] Combined with reference Figure 6 After the request splitting unit 101 splits and obtains P sub-requests, for the second sub-request among the P sub-requests, the second sub-request is any one of the P sub-requests, and the second sub-request is sent to the second cache set 601 among the B cache sets, and the second cache set 601 is the cache set corresponding to the second sub-request. The second cache set 601 is used to perform a hit test on the second sub-request. The second cache set 601 is also used to send the second sub-request to the output merging unit 103. For the other sub-requests among the P sub-requests, they are all sent to their corresponding cache sets.

[0089] Next, a method for determining the second cache set 601 corresponding to the second sub-request is introduced.

[0090] After the request splitting unit 101 splits out P sub-requests, it is necessary to determine the cache set corresponding to each sub-request. For the second sub-request, the request splitting unit 101 is also used to perform a hash operation based on the base address of the second cache line to obtain the identifier of the second cache set; based on the identifier of the second cache set, the second sub-request is sent to the second cache set. Among them, the second cache line is the cache line requested by the second sub-request. The hash operation is an operation of extracting bits from the base address. Exemplarily, the base addresses of the P cache lines correspond to Addr0, Addr1, ..., Addr(P-1) in sequence.

[0091] In one embodiment, the request splitting unit is also used to obtain an identifier of a second cache set based on a second bit sequence; wherein the starting bit of the second bit sequence is determined in the base address of the second cache line using a hash operation based on a first parameter R and a second parameter B, the first parameter R is the cache line size, in bytes, and the second parameter B is the number of cache sets in the cache unit 102.

[0092] In one possible implementation, the starting bit of the second bit sequence has a first value in a sorting position from low to high in the base address of the second cache line, and the first value is a value obtained by subtracting one from the sum of the base-two logarithm of the first parameter R and the base-two logarithm of the second parameter B, wherein the starting value of the sorting position is zero, that is, the first sorting position is bit 0.

[0093] The end bit of the second bit sequence is determined in the base address of the second cache line by using a hash operation based on the first parameter R. In one possible implementation, the end bit of the second bit sequence is sorted from low to high in the base address of the second cache line as a second numerical value, and the second numerical value is the base-two logarithm of the first parameter R, wherein the starting value of the sorting position is zero, that is, the first sorting position is bit 0.

[0094] Combined with reference Figure 4 , similar to the case of the first read request, Figure 4 It can also be regarded as a process of calculating the cache set identifiers corresponding to each of the multiple base addresses split from the first write request.

[0095] Figure 4 The base addresses of the different subrequests are shown. Figure 4 In the case shown, the cache line granularity R is 32, that is, the base address interval between the two sub-requests is 32 bytes (0x20), and B is the number of cache sets, four. At this time, the first value is [log2R]+[log2B]-1==6, and the second value is log2R==5. Figure 4 It shows the situation where four sub-requests are split from a write request (that is, the data requested by the write request is distributed in four cache lines). Figure 4 Subrequests 0, 1, 2, and 3 are split from one write request, and subrequests 4, 5, 6, and 7 are split from another write request.

[0096] The hexadecimal base address of subrequest 0 is 10000, and the binary base address is 0001 0000 0000 00000000. Counting from low to high, the sixth bit (i.e., the seventh bit) is 0, and the fifth bit (i.e., the sixth bit) is 0. Therefore, the cache set identifier corresponding to subrequest 0 is 00.

[0097] The hexadecimal base address of sub-request 1 is 10020, and the binary base address is 0001 0000 0000 00100000. Counting from low to high, the 6th bit (i.e., the 7th bit) is 0, and the 5th bit (i.e., the 6th bit) is 1, then the cache set identifier corresponding to sub-request 1 is 01, and so on. It can be found that according to the above-mentioned method for determining the cache set identifier, every N (optional, N is 4) sub-requests will be evenly distributed in B (optional, B is 4) cache sets. The present application provides a cache set balancing solution for memory access requests with a larger request granularity, and the P split sub-requests fall evenly in B cache sets.

[0098] The above describes the processing method of the first write request in the normal mode. The data requested by the first write request is distributed in M ​​cache lines, where M is a positive integer greater than 1. For the third write request in the normal mode, the data requested by the third write request is distributed in one cache line. The processing method is as follows:

[0099] For a third write request in which the requested data is distributed on a cache line, the request splitting unit 101 sends the third write request to the cache unit 102, and the cache unit 102 is used to perform a hit test on the third write request. If the cache line corresponding to the third write request is stored in the cache unit 102, it is determined that the third write request is in a hit state, and the cache line corresponding to the third write request is processed according to the write hit strategy of the third write request. If the cache line corresponding to the third write request is not stored in the cache unit 102, it is determined that the third write request is in a missing state, and the cache unit 102 processes the cache line corresponding to the third write request according to the write miss strategy of the third write request.

[0100] The cache unit 102 is used to send the third write request, the hit status or the miss status of the third write request to the output merging unit 103. The output merging unit 103 is used to send the third write request, the hit status or the miss status of the third write request to the downstream storage device 106. The downstream storage device 106 processes the cache line corresponding to the third write request according to the write hit strategy of the third write request. Alternatively, the downstream storage device 106 processes the cache line corresponding to the third write request according to the write miss strategy of the third write request.

[0101] Optionally, the cache unit 102 includes B cache sets, where B is a positive integer greater than 1. In the case where B is a positive integer greater than 1, the request splitting unit 101 is used to send the third write request to the corresponding cache set. The request splitting unit 101 performs a hash operation based on the starting address of the third write request to obtain an identifier of the corresponding cache set; and sends the third write request to the corresponding cache set. This is similar to the calculation of the identifier of the second cache set corresponding to the second sub-request above, and will not be repeated.

[0102] It is worth noting that in the present application, no matter the request granularity of the input memory access request is greater than or less than a cache line granularity, the cache device 100 provided in the present application can support it. Specifically, the request splitting unit 101, the cache unit 102, the output merging unit 103, and the read data merging unit 104 will each provide a certain processing function for the input memory access request.

[0103] Read request for bypass mode:

[0104] based on Figure 1 The cache device 100 shown, Figure 1A schematic diagram of a method for processing a memory access request provided by an exemplary embodiment of the present application is shown. Figure 7 The processing method for the second read request is shown.

[0105] The request initiating unit 105 sends a memory access request to the request splitting unit 101 .

[0106] The request splitting unit 101 determines that the received memory access request is a second read request, and the second read request is a bypass mode request (Bypass request).

[0107] The request splitting unit 101 bypasses the second read request to the cache unit 102; the cache unit 102 is used to bypass the second read request to the output merging unit 103; the output merging unit 103 is used to bypass the second read request to the downstream storage device 106; the read data merging unit 104 is used to bypass the data returned by the downstream storage device 106 to the request initiating unit 105.

[0108] Bypass transmission refers to a transmission method that allows data to pass directly without processing it.

[0109] In the present application, for the read request in the bypass mode, the request will not be split, but the request will be transmitted to the downstream storage device 106 by bypass transmission to read the cache data in the downstream storage device 106. At this time, for the request in the bypass mode, it is necessary to ensure the data consistency of the request in the bypass mode in advance, that is, to ensure in advance that there are no duplicate addresses between the request in the bypass mode and the request in the normal mode.

[0110] In the above embodiment, the request granularity of the second read request in the bypass mode can be (1~N)*R bytes. The above embodiment sends the second read request in the bypass mode to the downstream storage device 106 through the bypass to read the cache data in the downstream storage device 106. At this time, it can be considered that the cache device 100 provided in the present application can support a larger request granularity, and the cache device 100 supports processing read requests with a request granularity greater than 1 cache line granularity.

[0111] based on Figure 7 The second read request processing method shown is optional. Figure 7 The cache unit 102 includes B cache banks, where B is a positive integer of 1 or greater than 1, and optionally, B is four.

[0112] For B being a positive integer greater than 1:

[0113] Combined with reference Figure 8The request splitting unit 101 is also used to bypass the second read request to the third cache set 801, which is the cache set corresponding to the second read request; the third cache set 801 is also used to bypass the second read request to the output merging unit 103.

[0114] Next, a method for determining the third cache set 801 corresponding to the second read request is introduced.

[0115] After receiving the second read request, the request splitting unit 101 determines the identifier of the cache set (i.e., the third cache set 801) corresponding to the second read request according to the starting address (memory access address) of the second read request, and bypasses the second read request to the third cache set 801. The third cache set 801 bypasses the second read request to the output merging unit 103.

[0116] In one embodiment, the request splitting unit 101 is further configured to perform a hash operation based on the starting address of the second read request to obtain an identifier of a third cache set, and to bypass the second read request to the third cache set based on the identifier of the third cache set. A hash operation refers to an operation of extracting bits from a starting address.

[0117] In one embodiment, the request splitting unit 101 is further configured to perform a bit sequence XOR operation based on the third bit sequence and the fourth bit sequence to obtain an identifier of a third cache set;

[0118] The bit sequence XOR operation refers to an operation of performing XOR calculation on the i-th third bit in the third bit sequence and the i-th fourth bit in the fourth bit sequence, where i is a positive integer. In the bit sequence XOR operation, each third bit in the third bit sequence and each fourth bit in the fourth bit sequence participate.

[0119] The starting bit of the third bit sequence is determined in the starting address of the second read request by using a hash operation based on the first parameter R and the second parameter B, where the first parameter R is the cache line granularity in bytes, and B is the number of cache sets. In a possible implementation, the starting bit of the third bit sequence is sorted from low to high in the starting address of the second read request as a first value, the first value being the sum of the base-two logarithm of the first parameter R and the base-two logarithm of the second parameter B minus one, wherein the starting value of the sorting position is zero, that is, the first sorting position is bit 0.

[0120] The end bit of the third bit sequence is determined in the starting address of the second read request by using a hash operation based on the first parameter R. In a possible implementation, the end bit of the third bit sequence is a second numerical value in a sorting position from low to high in the starting address of the second read request, and the second numerical value is a base-two logarithm of the first parameter R, wherein the starting value of the sorting position is zero, that is, the first sorting position is bit 0.

[0121] The starting bit of the fourth bit sequence is determined in the starting address of the second read request by using a hash operation based on the first parameter R, the second parameter B and the third parameter N, and the third parameter N is the ratio of the maximum request granularity to the cache line granularity. In a possible implementation, the starting bit of the fourth bit sequence is sorted from low to high in the starting address of the second read request as a third value, and the third value is the sum of the logarithm of the first parameter R with base 2, twice the logarithm of the second parameter B with base 2, and the logarithm of the third parameter N with base 2 minus one, wherein the starting value of the sorting position is zero, that is, the first sorting position is bit 0.

[0122] The end bit of the fourth bit sequence is determined in the starting address of the second read request by using a hash operation based on the first parameter R, the second parameter B, and the third parameter N. In a possible implementation, the end bit of the fourth bit sequence is a fourth value in a sorting position from low to high in the starting address of the second read request, and the fourth value is a sum of the logarithm with base 2 of the first parameter R, the logarithm with base 2 of the second parameter B, and the logarithm with base 2 of the third parameter N, wherein the starting value of the sorting position is zero, that is, the first sorting position is bit 0.

[0123] Combined with reference Fig. 9 , Fig. 9 The starting addresses of different bypass requests are shown.

[0124] Fig. 9 In the illustrated case, the cache line granularity R is 32, that is, the start address interval between two bypass requests is N*R==128 bytes (0x80), B is the number of cache sets four, and N is four. At this time, the first value is log2(R*B)-1==6, the second value is log2(R)==5, the third value is log2(R*B*N)+log2(B)-1==10, and the fourth value is log2(R*B*N)==9.

[0125] Fig. 9 The case of 16 bypass requests is shown, and the start addresses of two bypass requests are spaced 0x80 apart.

[0126] Taking bypass request 0 as an example, the hexadecimal address of bypass request 0 is 10000, and the binary address is 0001 00000000 0000 0000. Counting from low to high, the 10th bit is 0, the 9th bit is 0, the 6th bit is 0, and the 5th bit is 0. The XOR result of the 10th bit and the 6th bit is 0, and the XOR result of the 9th bit and the 5th bit is 0. Therefore, the identifier of the cache set corresponding to bypass request 0 is 00.

[0127] Similarly, for bypass request 1 (hexadecimal address is 10080), bypass request 2 (hexadecimal address is 10100), and bypass request 3 (hexadecimal address is 10180), based on a similar XOR method, the cache set identifier 00 can be obtained.

[0128] Taking bypass request 4 as an example again, the hexadecimal address of bypass request 4 is 10200, and the binary address is 00010000 0010 0000 0000. Counting from low to high, the 10th bit is 0, the 9th bit is 1, the 6th bit is 0, and the 5th bit is 0. The XOR result of the 10th bit and the 6th bit is 0, and the XOR result of the 9th bit and the 5th bit is 1. Therefore, the identifier of the cache set corresponding to bypass request 4 is 01.

[0129] And so on, I won’t go into details.

[0130] It can be found that through the method for determining the cache set identifier provided by the present application, when the request granularity is N*R bytes, in the continuous address mode, every N (N is the ratio of the maximum request granularity to the cache line granularity, optionally, N is 4) bypass requests fall on the same cache set, and the corresponding cache set will be replaced every N bypass requests. Therefore, the present application provides a cache set balancing method for bypass requests, achieving the effect of balancing between cache sets.

[0131] For write requests in bypass mode:

[0132] based on Figure 1 The cache device 100 shown, Fig.10 A schematic diagram of a method for processing a memory access request provided by an exemplary embodiment of the present application is shown. Fig.10 The processing method for the second write request is shown.

[0133] The request initiating unit 105 sends a memory access request to the request splitting unit 101 .

[0134] The request splitting unit 101 determines that the received memory access request is a second write request, and the second write request is a bypass mode request (Bypass request).

[0135] The request splitting unit 101 bypasses the second write request to the cache unit 102; the cache unit 102 is used to bypass the second write request to the output merging unit 103; the output merging unit 103 is used to bypass the second write request to the downstream storage device 106. The downstream storage device 106 returns a second write response corresponding to the second write request to the cache device 100, and the cache device 100 bypasses the second write response to the request initiating unit 105. The cache device 100 does not process the second write response, and bypasses the second write response to the request initiating unit 105.

[0136] Bypass transmission refers to a transmission method that allows data to pass directly without processing it.

[0137] In the present application, for write requests in bypass mode, request splitting will not be performed. Instead, the request is transmitted to the downstream storage device 106 by bypass transmission, and a write operation is performed on the cached data in the downstream storage device 106. At this time, for the request in bypass mode, it is necessary to ensure the data consistency of the request in bypass mode in advance, that is, to ensure in advance that there are no duplicate addresses between the request in bypass mode and the ordinary request.

[0138] In the above embodiment, the request granularity of the second write request in the bypass mode is (1~N)*R bytes. The above embodiment sends the second write request in the bypass mode to the downstream storage device 106 through the bypass to write the cache data in the downstream storage device 106. At this time, it can be considered that the cache device 100 provided in the present application can support a larger request granularity, and the cache device 100 supports processing write requests with a request granularity greater than 1 cache line granularity.

[0139] based on Fig.10 The second write request processing method shown is optional. Fig.10 The cache unit 102 includes B cache banks, where B is a positive integer of 1 or greater than 1, and optionally, B is four.

[0140] For B being a positive integer greater than 1:

[0141] Combined with reference Fig.11 The request splitting unit 101 is also used to bypass the second write request to the fourth cache set 1101, which is the cache set corresponding to the second write request; the fourth cache set 1101 is also used to bypass the second write request to the output merging unit 103.

[0142] Next, a method for determining the fourth cache set 1101 corresponding to the second write request is introduced.

[0143] The request splitting unit 101 is further used to perform a hash operation based on the start address of the second write request to obtain an identifier of the fourth cache set 1101 ; and based on the identifier of the fourth cache set 1101 , bypass transmit the second write request to the fourth cache set 1101 .

[0144] In one embodiment, the request splitting unit 101 is further configured to perform a bit sequence XOR operation based on the fifth bit sequence and the sixth bit sequence to obtain an identifier of a fourth cache set;

[0145] Among them, the bit sequence XOR operation refers to the operation of performing XOR calculation on the i-th fifth bit in the fifth bit sequence and the i-th sixth bit in the sixth bit sequence, where i is a positive integer; in the bit sequence XOR operation, every fifth bit in the fifth bit sequence and every sixth bit in the sixth bit sequence participate.

[0146] The starting bit of the fifth bit sequence is determined in the starting address of the second write request by using a hash operation based on the first parameter R and the second parameter B, where the first parameter R is a cache line granularity in bytes. In a possible implementation, the starting bit of the fifth bit sequence is sorted from low to high in the starting address of the second write request as a first value, where the first value is the sum of the logarithm with base 2 of the first parameter R and the logarithm with base 2 of the second parameter B minus one, where the starting value of the sorting position is zero, that is, the first sorting position is bit 0.

[0147] The end bit of the fifth bit sequence is determined in the starting address of the second write request by using a hash operation based on the first parameter R. In a possible implementation, the end bit of the fifth bit sequence is a second numerical value in a sorting position from low to high in the starting address of the second write request, and the second numerical value is a base-two logarithm of the first parameter R, wherein the starting value of the sorting position is zero, that is, the first sorting position is bit 0.

[0148] The starting bit of the sixth bit sequence is determined in the starting address of the second write request by using a hash operation based on the first parameter R, the second parameter B, and the third parameter N, and the third parameter N is the ratio of the maximum request granularity to the cache line granularity. In a possible implementation, the starting bit of the sixth bit sequence is sorted from low to high in the starting address of the second write request as a third value, and the third value is the sum of the logarithm of the first parameter R with base two, twice the logarithm of the second parameter B with base two, and the logarithm of the third parameter N with base two minus one, wherein the starting value of the sorting position is zero, that is, the first sorting position is bit 0.

[0149] The end bit of the sixth bit sequence is determined in the starting address of the second write request by using a hash operation based on the first parameter R, the second parameter B and the third parameter N; in one possible implementation, the end bit of the sixth bit sequence is sorted from low to high in the starting address of the second write request as a fourth value, and the fourth value is the sum of the base-two logarithm of the first parameter R, the base-two logarithm of the second parameter B, and the base-two logarithm of the third parameter N, wherein the starting value of the sorting position is zero, that is, the first sorting position is bit 0.

[0150] Combined with reference Fig. 9 , similar to the case of the second read request, Fig. 9 It can also be viewed as a process of calculating the cache set identifier corresponding to the second write request based on the start address of the second write request.

[0151] Combined with reference Fig. 9 , Fig. 9 The starting addresses of different bypass requests are shown.

[0152] Fig. 9 In the illustrated case, the cache line granularity R is 32, that is, the start address interval between two bypass requests is N*R==128 bytes (0x80), B is the number of cache sets four, and N is four. At this time, the first value is log2(R*B)-1==6, the second value is log2(R)==5, the third value is log2(R*B*N)+log2(B)-1==10, and the fourth value is log2(R*B*N)==9.

[0153] Fig. 9 The case of 16 bypass requests is shown, and the start addresses of two bypass requests are spaced 0x80 apart.

[0154] Taking bypass request 0 as an example, the hexadecimal address of bypass request 0 is 10000, and the binary address is 0001 00000000 0000 0000. Counting from low to high, the 10th bit is 0, the 9th bit is 0, the 6th bit is 0, and the 5th bit is 0. The XOR result of the 10th bit and the 6th bit is 0, and the XOR result of the 9th bit and the 5th bit is 0. Therefore, the identifier of the cache set corresponding to bypass request 0 is 00.

[0155] Similarly, for bypass request 1 (hexadecimal address is 10080), bypass request 2 (hexadecimal address is 10100), and bypass request 3 (hexadecimal address is 10180), based on a similar XOR method, the cache set identifier 00 can be obtained.

[0156] Taking bypass request 4 as an example again, the hexadecimal address of bypass request 4 is 10200, and the binary address is 00010000 0010 0000 0000. Counting from low to high, the 10th bit is 0, the 9th bit is 1, the 6th bit is 0, and the 5th bit is 0. The XOR result of the 10th bit and the 6th bit is 0, and the XOR result of the 9th bit and the 5th bit is 1. Therefore, the identifier of the cache set corresponding to bypass request 4 is 01.

[0157] And so on, I won’t go into details.

[0158] It can be found that through the method for determining the cache set identifier provided by the present application, when the request granularity is N*R bytes, in the continuous address mode, every N (N is the ratio of the maximum request granularity to the cache line granularity, optionally, N is 4) bypass requests fall on the same cache set, and the corresponding cache set will be replaced every N bypass requests. Therefore, the present application provides a cache set balancing method for bypass requests, achieving the effect of balancing between cache sets.

[0159] The above has introduced a method for processing four memory access requests, namely, a read request in normal mode, a write request in normal mode, a read request in bypass mode, and a write request in bypass mode. The cache device provided in the present application supports processing at least one of the above four memory access requests, for example, supports four memory access requests.

[0160] In one embodiment, the request initiating unit 105 adds a prompt information of the request type to the memory access request, for example, a bit value of 1 indicates that the type of the memory access request is a bypass request (request in bypass mode), and a bit value of 0 indicates that the type of the memory access request is a normal request. The request splitting unit 101 receives the memory access request and determines the type of the memory access request according to the prompt information.

[0161] Fig.12 The block diagram of the structure of an electronic device 1200 provided by an exemplary embodiment of the present application is shown. The electronic device 1200 may be a portable mobile terminal, such as a smart phone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III), an MP4 player (Moving Picture Experts Group Audio Layer IV), a laptop computer or a desktop computer. The electronic device 1200 may also be called a user device, a portable terminal, a laptop terminal, a desktop terminal or other names.

[0162] Typically, the electronic device 1200 includes a processor 1201 and a memory 1202 .

[0163] The processor 1201 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 1201 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 1201 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 1201 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1201 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0164] The processor 1201 includes the cache device provided by the above embodiment.

[0165] The memory 1202 may include one or more computer-readable storage media, which may be non-transitory. The memory 1202 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices.

[0166] In some embodiments, the computer device 1200 may further include: a peripheral device interface 1203 and at least one peripheral device. Those skilled in the art will appreciate that Fig.12 The structure shown in the figure does not constitute a limitation on the computer device 1200, and the computer device 1200 may include more or less components than shown in the figure, or combine some components, or adopt a different component arrangement.

[0167] The present application also provides a processor, which includes the cache device as described in the above embodiment.

[0168] The present application also provides a chip, the chip includes a processor, and the processor includes the cache device as described in the above embodiment.

[0169] The present application also provides a graphics card, which includes a cache device as described in the above embodiment.

[0170] The present application also provides a server, which includes the cache device as described in the above embodiment.

[0171] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0172] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0173] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A cache device, characterized in that: The cache device includes a cache unit and an output merging unit; The cache unit is configured to send the at least two sub-requests or hit status information of the at least two sub-requests to the output merging unit when at least two sub-requests are obtained, the at least two sub-requests being obtained in response to splitting a memory access request, and the request granularity of the memory access request being greater than the cache line granularity corresponding to the cache unit; The output merging unit is used to send the memory access request to the downstream storage device when the at least two sub-requests are collected, or to send the memory access request and the hit status information of the at least two sub-requests to the downstream storage device when the hit status information of the at least two sub-requests are collected.

2. The device according to claim 1, characterized in that The cache device also includes a request splitting unit; The request splitting unit is used to obtain the memory access request sent by the external request initiating unit, and split the memory access request into the at least two sub-requests; The at least two sub-requests are sent to the cache unit.

3. The device according to claim 1, characterized in that The cache device also includes a read data merging unit; The read data merging unit is used to merge the read data read from the cache unit and / or the downstream storage device, and output the merged read data to an external request initiating unit.

4. The device according to any one of claims 1 to 3, characterized in that: The cache device comprises a request splitting unit, the cache unit, the output merging unit and a read data merging unit; The request splitting unit is configured to receive a first read request sent by a request initiating unit, wherein the data requested by the first read request is distributed on M cache lines, where M is a positive integer greater than 1; split the first read request into M sub-requests, wherein the M sub-requests correspond one-to-one to the M cache lines; and send the M sub-requests to the cache unit; The cache unit is used to perform a hit test on the M sub-requests, and send a hit status or a miss status of each sub-request in the M sub-requests to the output merging unit; The output merging unit is used to collect the hit status or the miss status of the M sub-requests, and send the first read request and the hit status or the miss status of the M sub-requests to the downstream storage device; The read data merging unit is used to aggregate the first data and the second data to obtain merged data, and return the merged data to the request initiating unit, the first data includes the cache line corresponding to the sub-request belonging to the missing state among the M sub-requests returned by the downstream storage device, and the second data includes the cache line corresponding to the sub-request belonging to the hit state among the M sub-requests.

5. The device according to claim 2, characterized in that The memory access request includes a first read request, the at least two sub-requests include a first sub-request, and the first sub-request is any one of the at least two sub-requests; the cache unit includes B cache sets, B is a positive integer greater than 1, and the B cache sets include the first cache set; The request splitting unit is further used to perform a hash operation based on the base address of the first cache line to obtain an identifier of the first cache set; Based on the identifier of the first cache set, sending the first sub-request to the first cache set; The first cache line is the cache line requested by the first sub-request.

6. The device according to claim 5, characterized in that The request splitting unit is further used to obtain an identifier of the first cache set based on the first bit sequence; Among them, the starting bit of the first bit sequence is determined in the base address of the first cache line by using a hash operation based on a first parameter R and a second parameter B, and the ending bit of the first bit sequence is determined in the base address of the first cache line by using a hash operation based on the first parameter R, and the first parameter R is the cache line granularity in bytes.

7. The device according to claim 6, characterized in that The starting bit of the first bit sequence has a first value in a sorting position from low to high in the base address of the first cache line, the first value is a value obtained by subtracting one from the sum of the logarithm with base 2 of the first parameter R and the logarithm with base 2 of the second parameter B, and the starting value of the sorting position is zero; The sorting position of the end bit of the first bit sequence from low to high in the base address of the first cache line is a second value, the second value is the base-two logarithm of the first parameter R, and the starting value of the sorting position is zero.

8. The device according to any one of claims 5 to 7, characterized in that The cache device also includes a read data merging unit; The first cache set is further used to mark the first cache line corresponding to the first sub-request as a locked state when the first sub-request is in a hit state; When the read data merging unit obtains the merged data through aggregation, the first cache line is marked as being in an unlocked state.

9. The device according to any one of claims 1 to 3, characterized in that: The cache device comprises a request splitting unit, the cache unit and the output merging unit; The request splitting unit is configured to receive a first write request sent by the request initiating unit, wherein the data requested by the first write request is distributed on P cache lines, where P is a positive integer greater than 1; Splitting the first write request into P sub-requests, where the P sub-requests correspond one-to-one to the P cache lines; Sending the P sub-requests to the cache unit; The cache unit is used to perform a hit test on the P sub-requests, and for a sub-request in a hit state among the P sub-requests, set a cache line corresponding to the sub-request to an invalid state, and not write the cache line; and, sending the P sub-requests to the output merging unit; The output merging unit is used to collect the P sub-requests and send the first write request to the downstream storage device. The downstream storage device returns a first write response corresponding to the first write request to the cache device. The cache device feeds back the first write response to the request initiating unit.

10. The device according to claim 2, characterized in that The memory access request includes a first write request, the at least two sub-requests include a second sub-request, and the second sub-request is any one of the at least two sub-requests; the cache unit includes B cache sets, B is a positive integer greater than 1, and the B cache sets include the second cache set; The request splitting unit is further used to perform a hash operation based on the base address of the second cache line to obtain an identifier of the second cache set; Based on the identifier of the second cache set, sending the second sub-request to the second cache set; The second cache line is the cache line requested by the second sub-request.

11. The device according to claim 10, characterized in that The request splitting unit is further used to obtain an identifier of the second cache set based on a second bit sequence; Among them, the starting bit of the second bit sequence is determined in the base address of the second cache line by using a hash operation based on the first parameter R and the second parameter B, and the ending bit of the second bit sequence is determined in the base address of the second cache line by using a hash operation based on the first parameter R, and the first parameter R is the cache line granularity, in bytes.

12. The device according to claim 11, characterized in that The starting bit of the second bit sequence has a first value in a sorting position from low to high in the base address of the second cache line, the first value is a value obtained by subtracting one from the sum of the logarithm with base 2 of the first parameter R and the logarithm with base 2 of the second parameter B, and the starting value of the sorting position is zero; The end bit of the second bit sequence has a second numerical value in a sorting position from low to high in the base address of the second cache line, the second numerical value is the base-two logarithm of the first parameter R, and the starting value of the sorting position is zero.

13. The device according to any one of claims 1 to 3, characterized in that: The cache device comprises a request splitting unit, the cache unit, the output merging unit and a read data merging unit; The request splitting unit is configured to receive a second read request sent by the request initiating unit, where the second read request is a bypass mode request; bypass transmitting the second read request to the cache unit; The cache unit is used to bypass the second read request to the output merging unit; The output merging unit is used to bypass the second read request to the downstream storage device; The read data merging unit is used to bypass the data returned by the downstream storage device to the request initiating unit.

14. The device according to claim 13, characterized in that The memory access request includes a second read request, and the second read request is a bypass mode request; the cache unit includes B cache sets, and the B cache sets include a third cache set; The request splitting unit is further used to bypass the second read request to the third cache set, where the third cache set is a cache set corresponding to the second read request; The third cache set is further used to bypass transmit the second read request to the output merging unit.

15. The device according to claim 14, characterized in that The request splitting unit is further used to perform a hash operation based on the starting address of the second read request to obtain an identifier of the third cache set; and based on the identifier of the third cache set, bypass the second read request to the third cache set.

16. The device according to claim 15, characterized in that The request splitting unit is further used to perform a bit sequence XOR operation based on the third bit sequence and the fourth bit sequence to obtain an identifier of the third cache set; The bit sequence XOR operation refers to an operation of performing an XOR calculation on the i-th third bit in the third bit sequence and the i-th fourth bit in the fourth bit sequence, where i is a positive integer; The start bit of the third bit sequence is determined in the start address of the second read request by using a hash operation based on a first parameter R and a second parameter B, and the end bit of the third bit sequence is determined in the start address of the second read request by using a hash operation based on the first parameter R, wherein the first parameter R is the cache line granularity in bytes; The starting bit of the fourth bit sequence is determined in the starting address of the second read request by using a hash operation based on the first parameter R, the second parameter B and the third parameter N, and the ending bit of the fourth bit sequence is determined in the starting address of the second read request by using a hash operation based on the first parameter R, the second parameter B and the third parameter N, and the third parameter N is the ratio of the maximum request granularity to the cache line granularity.

17. The device according to claim 16, characterized in that The starting bit of the third bit sequence has a first value in a sorting position from low to high in the starting address of the second read request, the first value is a value obtained by subtracting one from the sum of the logarithm with base 2 of the first parameter R and the logarithm with base 2 of the second parameter B, and the starting value of the sorting position is zero; The sorting position of the end bit of the third bit sequence from low to high in the starting address of the second read request is a second value, the second value is the base-two logarithm of the first parameter R, and the starting value of the sorting position is zero; The starting bit of the fourth bit sequence is at a third value in a sorting position from low to high in the starting address of the second read request, the third value is a value obtained by subtracting one from the sum of the logarithm with base 2 of the first parameter R, twice the logarithm with base 2 of the second parameter B, and the logarithm with base 2 of the third parameter N, and the starting value of the sorting position is zero; The end bit of the fourth bit sequence is sorted from low to high in the starting address of the second read request as a fourth numerical value, and the fourth numerical value is the sum of the base-two logarithm of the first parameter R, the base-two logarithm of the second parameter B, and the base-two logarithm of the third parameter N, and the starting value of the sorting position is zero.

18. The device according to any one of claims 1 to 3, characterized in that The cache device comprises a request splitting unit, the cache unit and the output merging unit; The request splitting unit is configured to receive a second write request sent by the request initiating unit, where the second write request is a bypass mode request; bypass transmitting the second write request to the cache unit; The cache unit is used to bypass the second write request to the output merging unit; The output merging unit is further used to bypass transmit the second write request to the downstream storage device, the downstream storage device returns a second write response corresponding to the second write request to the cache device, and the cache device bypass transmits the second write response to the request initiating unit.

19. The device according to claim 18, characterized in that The cache unit includes B cache sets, the B cache sets include a fourth cache set, and B is a positive integer greater than 1; The request splitting unit is further used to bypass the second write request to the fourth cache set, where the fourth cache set is a cache set corresponding to the second write request; The fourth cache set is further used to bypass transmit the second write request to the output merging unit.

20. The device according to claim 19, characterized in that The request splitting unit is further used to perform a hash operation based on the starting address of the second write request to obtain an identifier of the fourth cache set; and based on the identifier of the fourth cache set, bypass transmit the second write request to the fourth cache set.

21. The device according to claim 20, characterized in that The request splitting unit is further used to perform a bit sequence XOR operation based on the fifth bit sequence and the sixth bit sequence to obtain an identifier of the fourth cache set; The bit sequence XOR operation refers to an operation of performing an XOR calculation on the i-th fifth bit in the fifth bit sequence and the i-th sixth bit in the sixth bit sequence, where i is a positive integer; The start bit of the fifth bit sequence is determined in the start address of the second write request by using a hash operation based on a first parameter R and a second parameter B, and the end bit of the fifth bit sequence is determined in the start address of the second write request by using a hash operation based on the first parameter R, wherein the first parameter R is the cache line granularity in bytes; The starting bit of the sixth bit sequence is determined in the starting address of the second write request by using a hash operation based on the first parameter R, the second parameter B and the third parameter N, and the ending bit of the sixth bit sequence is determined in the starting address of the second write request by using a hash operation based on the first parameter R, the second parameter B and the third parameter N, and the third parameter N is the ratio of the maximum request granularity to the cache line granularity.

22. The device according to claim 21, characterized in that The starting bit of the fifth bit sequence has a first value in a sorting position from low to high in the starting address of the second write request, the first value is a value obtained by subtracting one from the sum of the logarithm with base 2 of the first parameter R and the logarithm with base 2 of the second parameter B, and the starting value of the sorting position is zero; The sorting position of the end bit of the fifth bit sequence from low to high in the start address of the second write request is a second value, the second value is the base-two logarithm of the first parameter R, and the start value of the sorting position is zero; The starting bit of the sixth bit sequence has a third value in a sorting position from low to high in the starting address of the second write request, the third value being a value obtained by subtracting one from the sum of the logarithm with base 2 of the first parameter R, twice the logarithm with base 2 of the second parameter B, and the logarithm with base 2 of the third parameter N, and the starting value of the sorting position is zero; The end bit of the sixth bit sequence is at a fourth value in a sorting position from low to high in the starting address of the second write request, and the fourth value is the sum of the base-two logarithm of the first parameter R, the base-two logarithm of the second parameter B, and the base-two logarithm of the third parameter N, and the starting value of the sorting position is zero.

23. A cache access method, characterized in that: Applied to the cache device according to claim 1, the method comprises: The cache unit determines hit status information of at least two sub-requests, where the at least two sub-requests are obtained in response to splitting a memory access request, and a request granularity of the memory access request is greater than a cache line granularity corresponding to the cache unit; The output merging unit sends the memory access request to the downstream storage device when the at least two sub-requests are collected, or sends the memory access request and the hit status information of the at least two sub-requests to the downstream storage device when the hit status information of the at least two sub-requests are collected.

24. A processor, characterized in that: The processor comprises a cache device as claimed in any one of claims 1 to 22.

25. A chip, characterized in that: The chip includes a processor, and the processor includes the cache device as described in any one of claims 1 to 22.

26. A server, characterized in that: The server comprises a cache device as described in any one of claims 1 to 22.

27. An electronic device, characterized in that: The electronic device comprises a processor, and the processor comprises a cache device as described in any one of claims 1 to 22.

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