PCIe-P2P communication device and method

Abstract

The invention provides PCIe-P2P (Peripheral Component Interconnect Express-Peer-to-Peer) communication equipment and a PCIe-P2P communication method. The communication equipment comprises a user layer module, a unified management module and a driving layer module, the communication device is connected with a plurality of EP devices through a PCIe network; the user layer module is used for applying for a communication path from the unified management module; the unified management module is used for collecting information of PCIe equipment and selecting and processing P2P channels; the unified management module uniformly manages resource allocation of a memory buffer area and selection of a DMA engine; and the unified management module plans the reading operation of the user layer module to execute the writing operation on the target data party EP1 to the reading data party EP2. And the driving layer module is used for carrying DMA data and operating a plurality of EP devices. According to the scheme, the read operation is converted into the write transaction operation of the DMA, so that the available bandwidth of the PCIe network is greatly increased; according to the scheme, the memory resources of the whole PCIe network are uniformly and reasonably planned, memory allocation conflicts are reduced, the bandwidth utilization rate of the whole PCIe network is improved, and the transmission performance of the PCIe network is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the fields of data communication and integrated circuit data processing, and in particular to a PCIe-P2P communication device and method based on unified resource planning. Background Art

[0002] The communication mode of the PCIe bus is direct shared memory read and write. In the PCIe switching system, the space mapping relationship needs to be set in advance, that is, each PCIe EP maps its own memory to the PCIe address space, and at the same time, it also needs to map the PCIe address space to its own memory space. After setting the space mapping relationship, EP1 writes a message to the mapped memory space of EP2, and the message can be sent to the memory space of EP2.

[0003] For PCIe-based P2P communication, the sender needs to know the address of the operable memory space of the peer end, and needs a mechanism to notify the peer EP that the operation has been completed so that the peer EP and the local EP can proceed to the next step.

[0004] DMA, the full name of which is Direct Memory Access, copies data from one address space to another, providing high-speed data transfer between peripherals and memory or between memory and memory.

[0005] Due to the design of the PCIe specification, the efficiency of PCIe write operations is much greater than the efficiency of read operations. Therefore, how to reduce read operations in software operations is a key factor in improving PCIe efficiency.

[0006] The existing PCIe switching network has the following problems: (1) PCIe read and write operations coexist, especially in networks with large data access. This phenomenon is more obvious. Due to efficiency issues, the network is flooded with a large number of READ request operations, i.e., read operation requests. (2) In a PCIe network that uses DMA for acceleration, improper use of conventional DMA often leads to many PCIe read request operations. Summary of the invention

[0007] In view of this, in order to solve the above problems existing in the prior art, an embodiment of the present invention provides a PCIe-P2P communication device and method. Specifically, the following technical solutions are provided: In one aspect, the present invention provides a PCIe-P2P communication device, the communication device comprising: User layer module, unified management module and driver layer module; the communication device is connected to multiple EP devices via a PCIe network; The user layer module is used to apply for a communication path from the unified management module; The unified management module is used to collect information of PCIe devices, and select and process P2P channels; the unified management module uniformly manages the allocation of user data buffer resources and the allocation of DMA engines; the unified management module plans the read operation of the user layer module to perform a write operation on the destination data party EP1 to the reading data party EP2; the user data buffer includes a sending buffer allocated for EP1 and a receiving buffer allocated for EP2; The driver layer module receives the communication operation descriptor or register operation control data sent by the unified management module, and is used to control DMA data transfer and operate multiple EP devices.

[0008] Preferably, when performing P2P communication, the destination data party EP1 performs the following process: S11, EP1 applies to the unified management module to establish an EP1-EP2 channel; S12, the unified management module allocates the best DMA engine and allocates user data buffers for EP1 and EP2 to form a communication operation descriptor; S13, the unified management module sends the communication operation descriptor to EP1; S14, after receiving the communication operation descriptor, EP1 starts the DMA operation, starts the allocated DMA engine, and constructs the DMA descriptor; S15. Execute data transfer through the allocated DMA engine to transfer the data in the sending buffer to the receiving buffer; the data in the sending buffer is the data from EP1 to be read by EP2.

[0009] Preferably, when performing P2P communication, the data reading party EP2 performs the following process: S21, apply to the unified management module for access to EP1; S22, the unified management module checks whether the path has been allocated, and if so, sends the result to EP2; if not, allocates the path and sends the allocation result to EP2; S23, the unified management module sends a notification that communication can be started to EP1 and EP2; S24. After receiving the communication start notification, EP2 establishes a polling thread and prepares to receive data; S25. When EP1 has finished sending the data, EP2 polls all the data and completes the data reading operation.

[0010] Preferably, in S12, the specific manner of allocating user data buffers for EP1 and EP2 is: The unified management module records the memory information in the collected PCIe device information as M{Addr1{start, end, bdf1}, ..., Addrp{start, end, bdfp}}, where p represents the total number of EP devices in the PCIe network, bdf refers to the BDF address of the EP device in the PCIe, Addrp represents the memory on EPp, start represents the starting address of the corresponding memory, and end represents the ending address of the corresponding memory; Find all free memories in M ​​to form a free memory set, and select the free memories closest to EP1 and EP2 from the free memory set respectively; Allocate the sending buffer H1 in the free memory closest to EP1, and allocate the receiving buffer H2 in the free memory closest to EP2; If no free memory exists, the allocation fails.

[0011] Preferably, the method for determining the closest distance is: determining the distance based on the number of links spanned between the free memory and the target node, the smaller the number of links, the closer the distance; the target nodes are EP1 and EP2.

[0012] Preferably, in S11, the data structure of the path is: {DMA engine, sending buffer, receiving buffer, data length}, and the data length is the length of data to be transmitted between EP1 and EP2.

[0013] Preferably, in 12, the priority of allocating the best DMA engine is: Priority 1: EP1 DMA engine is preferred; Priority 2: If priority 1 does not exist or is unavailable, the DMA engine on the swap device is selected; Priority 3: If both priority 1 and priority 2 do not exist or are unavailable, the DMA engine on the EP device other than EP1 is selected; If priority 1, priority 2, and priority 3 do not exist, a DMA engine allocation failure signal is returned.

[0014] Preferably, in S12, the specific method of allocating the best DMA engine is: S121, the unified management module collects PCIe network topology information and records it as , where k represents the cost between two nodes in the PCIe network, m and n represent the node numbers, and n represents the total number of PCIe network nodes; S122, sum up to obtain a DMA set, recorded as D{DMA1, ..., DMAc}, where c represents the number of DMAs, and c is less than n; S123, filtering out the cost set C associated with the DMA in the set D and the destination data party from the set T, denoted as C{C1, ..., CI}, where I is a positive integer, and its maximum value is 2c; if the set C is empty, returning a DMA engine allocation failure signal; S124, the node with the smallest cost in the screening set C is recorded as Cmin, and the DMA on the node numbered min is set as the optimal DMA engine.

[0015] Preferably, the communication operation descriptor includes whether it is a sender, an allocated DMA engine, a sending buffer, and a receiving buffer.

[0016] Preferably, after the DMA engine allocation failure signal is returned, data transmission between the destination data party EP1 and the reading data party EP2 is performed according to the non-DMA controlled PCIe read communication process.

[0017] On the other hand, the present invention further provides a PCIe-P2P communication method, which is applied to the communication device as described above, and includes: Step 1: The user terminal applies for a communication channel from the unified management module to enable the data reader EP2 to read data from the target data party EP1; Step 2: The unified management module allocates the DMA engine based on the application of the user end; Step 3: The unified management module allocates user data buffer resources based on the application of the user terminal, and the user data buffer includes a sending buffer allocated to EP1 and a receiving buffer allocated to EP2; Step 4: The unified management module establishes the EP1-EP2 path; Step 5: After the path is established, EP1 starts the DMA operation and transfers the data to be read from the send buffer of the destination data party to the receive buffer of the data reader through the allocated DMA engine; Step 6: After completing the data transfer, end.

[0018] Preferably, if step 2 fails, data transmission between the destination data party EP1 and the reading data party EP2 is performed according to the non-DMA controlled PCIe read communication process.

[0019] Compared with the prior art, the technical solution of the present invention converts the communication requirements between user programs into Write operations after planning channels at the unified management level, thereby minimizing the READ operations in the PCIe network and improving the bandwidth utilization of the entire network. Therefore, compared with the PCIe P2P communication in the prior art, this solution has the following advantages: (1) The READ operation in the user program operation is converted into the Write transaction operation of the PCIe DMA, which minimizes the READ operation of the PCIe network and greatly increases the available bandwidth of the PCIe network.

[0020] (2) The unified management layer makes a unified and reasonable plan for the memory resources of the entire PCIe network, reducing memory allocation conflicts and trying to select the allocation method closest to the source. This can greatly save the path length of PCIe messages in the PCIe network, thereby improving the bandwidth utilization of the entire PCIe network.

[0021] This solution is particularly suitable for some PCIe bus networking environments, where there is P2P communication processing based on DMA engine, etc., which can greatly reduce the READ transactions in the network, thereby increasing the available bandwidth of the entire network, and reasonably planning memory buffer resources based on the memory planning of the entire network. Through these two measures, the P2P transmission performance of the PCIe network will be greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the system architecture of an embodiment of the present invention; Figure 2 A schematic diagram of a user P2P communication data processing flow in an embodiment of the present invention; Figure 3 The figure is a flowchart of an execution method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] Those skilled in the art should know that the following specific embodiments or specific implementations are a series of optimized settings listed by the present invention to further explain the specific content of the invention, and these settings can be combined or used in association with each other, unless the present invention clearly states that some or a specific embodiment or implementation cannot be associated or used together with other embodiments or implementations. At the same time, the following specific embodiments or implementations are only used as the most optimized settings, and are not to be understood as limiting the scope of protection of the present invention.

[0026] Embodiment 1:

[0027] In order to solve the shortcomings of the existing PCIe switching network P2P communication, this solution proposes a high-speed PCIe-P2P communication method and device based on unified resource planning. This solution uses a centralized control module to centrally plan the DMA and cache used in P2P communication. For P2P communication, this embodiment follows the following principles: (1) buff (i.e. user data buffer) resource allocation and DMA engine selection are performed through a unified management module; in this embodiment, the user data buffer includes a sending buffer and a receiving buffer, which are allocated to the destination data party and the data reader party respectively; (2) For the user's read operation, plan to perform a write operation on the destination data side to the data side that needs to be read; in this way, the user's read operation can generate a PCIe write transaction; (3) For DMA operations, if DMA engines exist on both EPs (i.e., PCIe endpoint devices that support P2P), the DMA engine on the EP where the data source is located is selected according to the principle of being closest to the source. This ensures that all DMA operations are DMA write operations, thereby avoiding read operations and saving data operation resources.

[0028] In this embodiment, the system framework of this solution is as follows Figure 1 As shown, the top layer is the user program layer, that is, the user space, followed by the unified management layer, the driver layer and the hardware device layer, among which: (1) The user program is mainly responsible for applying for a communication path from the unified management module. This can be represented by a user layer module, and the user program, that is, each user end, is included in the user layer module.

[0029] (2) The unified management module is mainly responsible for collecting PCIe device information, including topology information, Bar address (i.e., the range of operable memory address space), and DMA information. At the same time, this module is also responsible for unified memory application and release, DMA engine selection, and P2P channel selection processing. The Bar addresses of the main memory and peripheral EP collected by initialization are unified into a memory pool. Subsequent allocation and release are managed from the memory pool. The DMA engine selection follows the principle of being closest to the data source. After determining the DMA engine, an idle communication channel or queue is selected in the selected DMA engine as the P2P channel.

[0030] (3) The driver layer is mainly responsible for operating DMA to transfer data, receiving processing operations from the unified management module, and operating specific hardware devices downward.

[0031] (4) The hardware device layer mainly includes various PCIe EP devices.

[0032] Next, continue to combine Figure 2 , the P2P communication process of this solution is described. In this embodiment, the EP2 user program wants to access the data of EP1 (that is, the EP2 user program wants to read the data of EP1) as an example: 1. First, in this embodiment, the selection of the DMA engine by the unified management module can be set according to the priority order: (1) First, select the DMA engine on EP1, the data source (i.e., the destination data party); (2) If (1) does not exist or is unavailable, select the DMA on the PCIe Switch; here, preferably, the selection of the DMA engine can be based on the lowest cost or the shortest distance; (3) If (1) and (2) are both unavailable or do not exist, select the DMA on other EP devices that are not the data source (i.e., the destination data party); if there are multiple EP devices, they can also be selected based on the lowest cost or the closest distance; (4) If it still does not exist, it fails, that is, there is no DMA engine that can be recommended for use, then the non-DMA controlled PCIe read communication process is executed. The non-DMA controlled PCIe read communication process belongs to the conventional data reading process in this field and will not be described here.

[0033] 2. In this embodiment, the unified management module data memory buffer allocation method is set to find the nearest data memory cache, and the nearest distance is determined by the number of links between the cache and the target node. The smaller the number, the closer the distance. The specific setting process is as follows: (1) First, search for all free P2P caches in the memory pool of the unified management module; (2) If it does not exist, the feedback allocation fails; if the allocation fails, the communication fails; (3) Otherwise, the sender (i.e., the destination data party EP1 in this embodiment) cache is selected. Based on the selection of the DMA engine in the previous step, the cache closest to the DMA engine is selected and allocated to the sender. (4) Then the receiving end cache is selected, and the cache closest to the receiving end is selected.

[0034] In this embodiment, the unified management layer makes unified and reasonable planning for the memory resources of the entire PCIe network, reduces memory allocation conflicts, and tries to select the allocation method closest to the source, which can greatly save the path length of PCIe messages propagating in the PCIe network, thereby improving the bandwidth utilization of the entire PCIe network.

[0035] 3. In this embodiment, the specific data execution process for EP1 is as follows: (1) The EP1 user terminal first applies to the unified management module to establish a path between EP1 and EP2. In a preferred embodiment, the constituent elements of the path are set to {DMA engine, send buffer, receive buffer, data length}, where the data length refers to the length of data to be transmitted between EP1 and EP2. (2) When selecting a DMA engine, a more preferred method in this embodiment is as follows: the unified management module records the collected PCIe network topology information as , where kmn represents the cost between two nodes in the PCIe network, m and n are the node numbers in the PCIe network, m and n are positive integers, and n represents the total number of nodes. Here, the nodes include EP, Switch and other nodes in the PCIe network. First, select the DMA set and record it as set D{DMA1, ..., DMAc}, where c is a positive integer, c is less than the number of nodes n, and filter out the cost set associated with the DMA in the DMA set and the destination node h in T and record it as C{C1, ..., Cl}, where I is a positive integer and its maximum value is 2c. Select the node with the smallest cost in C, record it as Cmin, and the DMA on the node with number min is the DMA engine to be selected. If the set C is empty, the selection fails, there is no valid DMA in this communication, and the selection fails.

[0036] (4) The unified management module records the memory information in the collected PCIe device information as M{Addr1{start, end, bdf1}, …, Addrp{start, end, bdfp}}, wherein p is a positive integer, indicating the total number of EPs in the PCIe network, bdf refers to the BDF address of the EP device in the PCIe, Addrp is the memory on EPp, a sending buffer H1 is allocated on Addr1, and a receiving buffer H2 is allocated on Addr2. If there is no free memory, the allocation fails. At this time, due to the failure of buffer allocation, P2P communication cannot be performed, and a cache allocation failure signal is returned; in a more preferred embodiment, after obtaining the memory information set M, the free memory set therein is first screened. If the memory corresponding to EP1 and / or EP2 is not free, that is, it is not in the free memory set, the buffer is allocated in the closest distance manner. At this time, the sending buffer H1 is allocated to the data sender in the free memory closest to the data sender, and the receiving buffer H2 is allocated to the data receiver in the free memory closest to the data receiver; the judgment of the closest distance is determined by the number of links spanned between the cache and the target node. The smaller the number, the closer the distance.

[0037] It is more preferred here that the allocation of the buffer is first allocated on the memory of the data sender and the data receiver. If the memory of the two EP devices is not free, then it is allocated in other free memories in the closest way. It can also be considered that the memory of the data sender and the memory of the data receiver are the two memories closest to each other, that is, their links are 0. If there is only one free memory left, and the free memory is enough to allocate two buffers, then they can be set in the same free memory. If the memory size is not enough for allocation, the allocation failure is returned.

[0038] (5) The unified management module returns the processing result (i.e., the communication operation descriptor) to the EP1 user end. The processing result includes whether it is the sender, the allocated DMA engine device (i.e., the best DMA engine), the sending buffer and the receiving buffer, etc.; wherein, whether EP1 is the sender can be notified by, for example, identifying it through a specific field, such as setting a field in a certain signal to 1 to indicate that EP1 is the sender, and setting the field to 0 to indicate that it is the receiver.

[0039] (6) When the EP1 user finds that it is selected as the sender for this operation, it starts the DMA operation to the EP1 driver.

[0040] Here, it should be further pointed out that if EP1 finds that this operation is not designated as the sender but as the receiver, it will follow the read operation process of EP2, which will degenerate into a non-optimized read operation process (that is, the conventional read operation process); if EP1 finds that this operation is not designated as the sender or the receiver, it will report an exception and the communication will fail.

[0041] (7) After receiving the start DMA operation, the EP1 driver starts the hardware DMA, that is, starts the allocated DMA engine and constructs a DMA descriptor; the DMA descriptor here carries information such as the send buffer, receive buffer, and data length; (8) After receiving the command, the assigned DMA engine executes data transfer, transfers the data in the source buffer (i.e., the sending buffer) to the receiving buffer (i.e., the buffer H2 of EP2 in this embodiment), and triggers the doorbell of the receiving EP2. The doorbell triggering method is a conventional method in the art and will not be described here.

[0042] 4. The processing flow for EP2 is as follows: (1) EP2 first applies to the unified management module to establish a channel with EP1; (2) After receiving the above request, the unified management module first checks whether the EP1-EP2 channel has been allocated. If not, it turns to the EP1 channel allocation process to allocate the channel. If the EP1-EP2 channel has been allocated, it directly sends the EP1-EP2 channel information back to the EP2 user end; (3) The unified management module simultaneously notifies the sender (i.e., EP1 in this embodiment) that communication can begin, and simultaneously notifies EP2 that the user end can begin communication; (4) After receiving the communication start notification information, the EP2 user terminal establishes a polling thread and prepares to receive data; (5) After EP1 finishes sending the data, EP2 polls all the data and performs subsequent business processing.

[0043] In this embodiment, it is described in detail how to convert the READ operation in the user-side operation into the Write transaction operation of the PCIe DMA. This method effectively reduces the READ operations of the PCIe network and greatly increases the available bandwidth of the PCIe network.

[0044] Embodiment 2:

[0045] Combination Figure 3 As shown, in another implementation manner, this solution can be implemented by an executable communication method. The method includes: Step 1: The user terminal applies for a communication channel from the unified management module to enable the data reader EP2 to read data from the target data party EP1; Step 2: The unified management module allocates the DMA engine based on the application of the user end; Step 3: The unified management module allocates user data buffer resources based on the application of the user terminal, and the user data buffer includes a sending buffer allocated to EP1 and a receiving buffer allocated to EP2; Step 4: The unified management module establishes the EP1-EP2 path; Step 5: After the path is established, EP1 starts the DMA operation and transfers the data to be read from the send buffer of the destination data party to the receive buffer of the data reader through the allocated DMA engine; Step 6: After completing the data transfer, end.

[0046] The execution of this method can be used in the communication device in Example 1.

[0047] In addition, it is understood that any process or method description in the flowchart or otherwise described herein can be understood as a module, fragment or portion of a code representing one or more executable instructions for implementing a specific logical function or step of a process, and the scope of the preferred embodiment of the present solution includes other implementations, in which the functions may not be performed in the order shown or discussed, including performing the functions in a substantially simultaneous manner or in a reverse order according to the functions involved, which should be understood by a person skilled in the art of the present embodiment. The processor performs the various methods and processes described above. For example, the method implementation in the present solution can be implemented as a software program, which is tangibly contained in a machine-readable medium, such as a memory. In some embodiments, part or all of the software program can be loaded and / or installed via a memory and / or a communication interface. When the software program is loaded into the memory and executed by the processor, one or more steps in the method described above can be performed. Alternatively, in other embodiments, the processor can be configured to perform one of the above methods in any other appropriate manner (e.g., by means of firmware).

[0048] The logic and / or steps represented in the flowchart or otherwise described herein may be embodied in any readable storage medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch instructions from and execute instructions on an instruction execution system, apparatus, or device), or in combination with such instruction execution systems, apparatuses, or devices.

[0049] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A PCIe-P2P communication device, characterized in that: The communication device comprises: User layer module, unified management module and driver layer module; the communication device is connected to multiple EP devices via a PCIe network; The user layer module is used to apply for a communication path from the unified management module; The unified management module is used to collect information of PCIe devices, and select and process P2P channels; the unified management module uniformly manages the allocation of user data buffer resources and the allocation of DMA engines; the unified management module plans the read operation of the user layer module to perform a write operation on the destination data party EP1 to the reading data party EP2; the user data buffer includes a sending buffer allocated for EP1 and a receiving buffer allocated for EP2; The driver layer module receives the communication operation descriptor or register operation control data sent by the unified management module, and is used to control DMA data transfer and operate multiple EP devices.

2. The communication device according to claim 1, characterized in that When performing P2P communication, the destination data party EP1 performs the following process: S11, EP1 applies to the unified management module to establish an EP1-EP2 channel; S12, the unified management module allocates the best DMA engine and allocates user data buffers for EP1 and EP2 to form a communication operation descriptor; S13, the unified management module sends the communication operation descriptor to EP1; S14, after receiving the communication operation descriptor, EP1 starts the DMA operation, starts the allocated DMA engine, and constructs the DMA descriptor; S15. Execute data transfer through the allocated DMA engine to transfer the data in the sending buffer to the receiving buffer; the data in the sending buffer is the data from EP1 to be read by EP2.

3. The communication device according to claim 1, characterized in that When performing P2P communication, the data reading party EP2 executes the following process: S21, apply to the unified management module for access to EP1; S22, the unified management module checks whether the path has been allocated, and if so, sends the result to EP2; if not, allocates the path and sends the allocation result to EP2; S23, the unified management module sends a notification that communication can be started to EP1 and EP2; S24. After receiving the communication start notification, EP2 establishes a polling thread and prepares to receive data; S25. When EP1 has finished sending the data, EP2 polls all the data and completes the data reading operation.

4. The communication device according to claim 2, characterized in that In S12, the specific method of allocating user data buffers for EP1 and EP2 is: The unified management module records the memory information in the collected PCIe device information as M{Addr1{start, end, bdf1}, ..., Addrp{start, end, bdfp}}, where p represents the total number of EP devices in the PCIe network, bdf refers to the BDF address of the EP device in the PCIe, Addrp represents the memory on EPp, start represents the starting address of the corresponding memory, and end represents the ending address of the corresponding memory; Search all free memories in M ​​to form a free memory set, and select the free memories closest to EP1 and EP2 from the free memory set respectively; Allocate the sending buffer H1 in the free memory closest to EP1, and allocate the receiving buffer H2 in the free memory closest to EP2; If no free memory exists, the allocation fails.

5. The communication device according to claim 4, characterized in that The method for determining the closest distance is: determining the distance based on the number of links spanned between the free memory and the target node, the smaller the number of links, the closer the distance; the target nodes are EP1 and EP2.

6. The communication device according to claim 2, characterized in that In the S11, the data structure of the path is: {DMA engine, sending buffer, receiving buffer, data length}, and the data length is the length of data to be transmitted between EP1 and EP2.

7. The communication device according to claim 2, characterized in that In 12, the priority of allocating the best DMA engine is: Priority 1: EP1 DMA engine is preferred; Priority 2: If priority 1 does not exist or is unavailable, the DMA engine on the swap device is selected; Priority 3: If both priority 1 and priority 2 do not exist or are unavailable, the DMA engine on the EP device other than EP1 is selected; If priority 1, priority 2, and priority 3 do not exist, a DMA engine allocation failure signal is returned.

8. The communication device according to claim 7, characterized in that: In S12, the specific method of allocating the best DMA engine is: S121, the unified management module collects PCIe network topology information and records it as , where k represents the cost between two nodes in the PCIe network, m and n represent the node numbers, and n represents the total number of PCIe network nodes; S122, sum up to obtain a DMA set, recorded as D{DMA1, ..., DMAc}, where c represents the number of DMAs, and c is less than n; S123, filtering out the cost set C associated with the DMA in the set D and the destination data party from the set T, denoted as C{C1, ..., CI}, where I is a positive integer, and its maximum value is 2c; if the set C is empty, returning a DMA engine allocation failure signal; S124, the node with the smallest cost in the screening set C is recorded as Cmin, and the DMA on the node numbered min is set as the optimal DMA engine.

9. The communication device according to claim 1, characterized in that The communication operation descriptor includes whether it is a sender, an allocated DMA engine, a send buffer, and a receive buffer.

10. A PCIe-P2P communication method, characterized in that: The method is applied to the communication device according to any one of claims 1 to 9, and the method comprises: Step 1: The user terminal applies for a communication channel from the unified management module to enable the data reader EP2 to read data from the target data party EP1; Step 2: The unified management module allocates the DMA engine based on the application of the user end; Step 3: The unified management module allocates user data buffer resources based on the application of the user terminal, and the user data buffer includes a sending buffer allocated to EP1 and a receiving buffer allocated to EP2; Step 4: The unified management module establishes the EP1-EP2 path; Step 5: After the path is established, EP1 starts the DMA operation and transfers the data to be read from the send buffer of the destination data party to the receive buffer of the data reader through the allocated DMA engine; Step 6: After completing the data transfer, end.

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