Dual-redundancy high-reliability calculation device based on PSOC

Abstract

The invention provides a dual-redundancy high-reliability computing device based on a PSOC. The dual-redundancy high-reliability computing device based on the PSOC comprises two PSOC computing units which are both in communication interaction with an avionics system through an FC bus; a dual-redundancy mechanism is realized between the two PSOC calculation units through a CCDL (Charge Coupled Device Language) protocol; the two PSOC computing units are respectively integrated with a 1394 bus daughter card, and the 1394 daughter card is used as a physical link for realizing a CCDL protocol between the two PSOC computing units; the two PSOC calculation units are respectively connected with a remote interface unit (RIU) through 1394 bus daughter cards, and are used for controlling execution mechanisms related to the remote interface unit (RIU) to execute service actions. According to the invention, the logic and physical interchangeability of the system is improved through the completely consistent dual-redundancy calculation unit design; the PSOC circuit is selected to realize integrated fusion of programmable logic and general calculation of the calculation unit, and the reliability and the energy consumption level of the system are improved; data communication and dual-redundancy function enabling realized by adopting a CCDL protocol provide an efficient path.

Description

Technical Field

[0001] The invention belongs to the technical field of avionics control and relates to a dual-redundancy high-reliability computing device based on PSOC. Background Art

[0002] With the rapid development of avionics technology and aviation computing technology, the efficient integration of aircraft electromechanical and control equipment, and the efficient integration of avionics and mission systems are important trends in the development of airborne electronic systems in the future. As a complex aircraft, helicopters have a wide variety of electromechanical and electrical equipment on their carrier platforms, and the management and control strategies are complex, which places increasingly high demands on the safety, certainty, and reliability of the airborne electromechanical integrated management system.

[0003] The management and control of the electromechanical systems of new helicopters show a trend of integration and comprehensiveness. The integrated airborne electromechanical integrated management system aims to integrate the aircraft electromechanical systems in terms of physics, information, and management, and to uniformly manage, scientifically combine, and dynamically schedule the entire aircraft's electromechanical systems. In addition to completing their own individual functions, each subsystem can also complete tasks such as coordinated resource allocation and post-fault system reconstruction, thereby optimizing the electromechanical system in terms of layout, quality, energy utilization, control, and information sharing.

[0004] The above functional requirements also place high demands on the architectural design, functional performance planning, and reliability design of electromechanical management computers.

[0005] Therefore, how to provide a high-reliability, high-performance, low-power consumption dual-redundancy high-reliability computing device based on PSOC is a problem that those skilled in the art need to solve urgently. Summary of the invention

[0006] In view of this, the present invention proposes a dual-redundancy high-reliability computing device based on PSOC, which improves the logical and physical interchangeability of the system through the design of completely consistent dual-redundant computing units; the PSOC circuit is selected to realize the integrated fusion of the programmable logic and general computing of the computing unit, thereby improving the reliability and energy consumption level of the system; the data communication and dual-redundancy functions realized by the CCDL protocol enable the provision of an efficient path.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] The present invention discloses a dual-redundancy high-reliability computing device based on PSOC, comprising: two isomorphic PSOC computing units, a 1394 bus daughter card and a remote interface unit; wherein:

[0009] Both PSOC computing units communicate and interact with the avionics system via the FC bus, and are used to receive and process electromechanical management task commands issued by the avionics system;

[0010] The two PSOC computing units implement a dual redundancy mechanism through a CCDL protocol;

[0011] The two PSOC computing units are respectively integrated with a 1394 bus daughter card, and the 1394 daughter card is used as a point-to-point physical link to implement the CCDL protocol between the two PSOC computing units to form a dual redundant interconnection mechanism;

[0012] The two PSOC computing units are respectively connected to a remote interface unit RIU through the 1394 bus daughter card integrated therein, and are used to control the execution mechanism related to the remote interface unit RIU to execute business actions.

[0013] Preferably, the PSOC computing unit includes: a PS end composed of a CPU, and a PL end composed of an FPGA; the PL end of the PSOC computing unit is used to implement data communication protocols and interface logic control; after the PS end of the PSOC computing unit receives the electromechanical management task command sent by the avionics system, it parses the command, obtains the task to be executed, and performs electromechanical management on the upper-layer application according to different task control operations.

[0014] Preferably, the PSOC computing unit has an internal integrated PCIE controller, and the 1394 interface of the 1394 bus daughter card and the FC interface of the FC bus are expanded through the PCIE interface.

[0015] Preferably, the 1394 bus daughter card adopts a CTOLC interface connector to realize data transmission of a PCIe interface and a 1394B signal; the 1394 bus daughter card uses a TOLC interface connector to be connected to the motherboard of the PSOC computing unit by a snap-on manner.

[0016] Preferably, the 1394 bus daughter card includes an FPGA core processing module, an IEEE1394B interface module, a host interface module and a power supply module; wherein

[0017] The FPGA core processing module is connected to the 1394B interface module via a 1394 physical layer interface, and is used to convert the data packets generated by the FPGA core processing module into physical signals that comply with the IEEE 1394 standard, and convert the received physical signals into data packets for processing by the FPGA core processing module;

[0018] The FPGA core processing module is connected to the host interface module via a PCIe bus to implement data interaction with the corresponding PSOC computing unit;

[0019] The power supply module provides power for the FPGA core processing module, the IEEE1394B interface module, and the host interface module.

[0020] Preferably, it also includes a fault logic circuit; a fault channel is constructed between the two PSOC computing units through the channel fault logic circuit, and the channel fault logic circuit is used to terminate its control over the interface module when a fault occurs in the current PSOC computing unit, and the other PSOC computing unit takes over and outputs the electromechanical management task.

[0021] Preferably, under the dual redundancy mechanism, each communication channel between the PSOC computing units is provided with a hardware synchronization indicator, which continuously monitors the operating status of the two PSOC computing units and sends a synchronization signal; the real-time transmission of the synchronization signal between the two PSOC computing units is completed through the synchronization bus, so that the two PSOC computing units always maintain a consistent operating status.

[0022] Preferably, the 1394 bus daughter card includes three CC nodes; two CC nodes are used to connect the transceiver transmission channels of the data cross link CCDL between the PSOC computing units, and the other CC node is used to communicate with the remote interface unit.

[0023] Preferably, it further comprises a lightning protection processing unit, and the lightning protection processing unit is connected to the two PSOC computing units via an FMC connector.

[0024] The present invention also provides an airborne electromechanical integrated management device, including the PSOC-based dual-redundancy high-reliability computing device.

[0025] It can be seen from the above technical solution that, compared with the prior art, the beneficial effects of the present invention include:

[0026] 1. The two computing units adopt a homogeneous design, and the hardware substrate adopts the same design. For the expansion requirements of differentiated modules, a standardized daughter card integration method is adopted to ensure the logical and physical interchangeability of the two computing units;

[0027] Second, each computing node adopts a new PSOC heterogeneous architecture that integrates CPU and FPGA, realizing the heterogeneous and integrated integration of the host control system software (PS side) and the core interface logic (PL side), improving the reliability and energy consumption level of the system;

[0028] 3. According to the system requirements, the CCDL protocol is used to implement the dual redundancy mechanism between the two computing units. Therefore, this solution designs a 1394 communication interface on the two computing units to realize the efficient operation of the CCDL protocol between the two computing units, which can provide an efficient channel for data communication and dual redundancy function enablement under the CCDL protocol;

[0029] 4. A unified adapter board and lightning protection board are designed for the two computing units to ensure high-speed interconnection and high-reliability communication of the external interfaces of the two computing units. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without creative work.

[0031] Figure 1 A schematic diagram of a dual-redundancy high-reliability computing device based on PSOC provided in an embodiment of the present invention;

[0032] Figure 2 A connection structure diagram of a dual-redundancy high-reliability computing device based on PSOC provided in an embodiment of the present invention;

[0033] Figure 3 A hardware design structure diagram of a PSOC computing unit provided by an embodiment of the present invention;

[0034] Figure 4 A software and hardware system diagram of a PSOC computing unit provided by an embodiment of the present invention;

[0035] Figure 5 A diagram of a 1394 bus daughter board interface provided by an embodiment of the present invention;

[0036] Figure 6 This is a CCDL interconnection topology diagram of a 1394 bus daughter board provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] The embodiment of the present invention provides a dual-redundancy high-reliability computing device based on PSOC, comprising: two isomorphic PSOC computing units, a 1394 bus daughter card and a remote interface unit; wherein the two PSOC computing units communicate and interact with an avionics system via an FC bus, and are used to receive and process electromechanical management task commands issued by the avionics system; a dual-redundancy mechanism is implemented between the two PSOC computing units via a CCDL protocol; the two PSOC computing units are respectively integrated with a 1394 bus daughter card, and the 1394 daughter card serves as a point-to-point physical link for implementing the CCDL protocol between the two PSOC computing units, forming a dual-redundancy interconnection mechanism; the two PSOC computing units are respectively connected to a remote interface unit RIU via their respective integrated 1394 bus daughter cards, and are used to control an actuator related to the remote interface unit RIU to execute business actions.

[0039] The present invention adopts a homogeneous dual-redundancy design, and the whole system includes two independent computer devices, each of which includes a power supply unit and a SPOC computing unit (computing unit A, computing unit B). The two computing units of the two computing unit nodes (computing unit A and computing unit B) adopt a homogeneous design, and the hardware substrate adopts a completely identical design. For the expansion requirements of differentiated modules, a standardized sub-card integration method is adopted. The two computing units back up each other, and their software and hardware resources remain completely identical, ensuring the logical and physical interchangeability of the two computing units. Mutual coordination and high-reliability mutual backup are achieved through redundant buses and software design. For critical tasks, the two node machines are redundant with each other and run the corresponding application software on the same hardware platform. For important tasks, the two machines are completed in collaboration, that is, the software is executed simultaneously on the two USMC node machines, and the I / O output is completed by the local host.

[0040] like Figure 1 As shown, computing unit A and computing unit B realize data interaction through CCDL. Cross Channel Data Link (CCDL) is an important way to exchange data and information between redundant computers. It is a key component to ensure the normal operation of the redundant flight control system. It ensures that when a single computing unit fails, another computing unit can take over the work and provide another level of fault tolerance. CCDL realizes cross-data transmission between various computing units. In order to eliminate the influence between channels and prevent the spread of faults, CCDL design adopts a point-to-point method. Computing unit A and computing unit B send synchronization signals to each other, and perform real-time fault judgment through the fault logic interface. Computing unit A and computing unit B realize data interaction with the helicopter control system through 8-way RS422 interface and 8-way discrete input and output interface, realize data interaction with the remote interface unit configured by each through 1394 bus, and realize data interaction with the avionics system through FC bus.

[0041] In one embodiment, in the dual redundancy mechanism, three buses are used in each redundancy, each bus communicates independently, and the buses adopt a ring structure (Bus1 and Bus2, which can tolerate the failure of a node connection) and a tree structure (Bus3), and the tree structure of the CCDL method is used between redundancies. The redundancy management system includes: synchronization, cross data transmission, fault synthesis, input data voting monitoring, output data voting monitoring, etc. A point-to-point, reliable data transmission, and cross channel data link with the function of preventing fault propagation is designed.

[0042] In one embodiment, Figure 2 As shown, it also includes a lightning protection processing unit, which is connected to two PSOC computing units through an FMC connector. The two PSOC computing units are connected to the lightning protection processing unit through an FMC connector adapter board. The various lightning protection circuits and interface circuits are integrated to avoid multiple transfers and discrete designs, further reduce weight and improve reliability.

[0043] In one embodiment, Figure 3-4 As shown in the figure, the PSOC computing unit includes: a PS end composed of a CPU and a PL end composed of an FPGA; the PL end of the PSOC computing unit is used to implement data communication protocols and interface logic control; after receiving the electromechanical management task command sent by the avionics system, the PSOC computing unit parses the command, obtains the task to be executed, and performs electromechanical management according to the upper-layer application of different task control operations. The new PSOC heterogeneous architecture chip with CPU+FPGA fusion is selected to realize the heterogeneous and integrated fusion of the host control system software (PS end) and the core interface logic (PL end).

[0044] The computing device hardware of this embodiment integrates general computing resources and logical programmable resources, can run system software, and realize highly customized interfaces, control systems and other logical functions. Different from the traditional dual-redundancy computing system that only uses CPU components, this embodiment uses the PSOC that integrates CPU and programmable logic resources as the core of the hardware and software system, where the CPU can run various software as a general computing resource, and the programmable logic resources can efficiently realize hardware acceleration of various communication protocols, management control and other functions. Through the combination of software and hardware, the operating efficiency and reliability level of traditional CPU software execution are greatly improved, and the overall system flexibility and reliable redundancy characteristics are greatly enhanced.

[0045] The system software runs in the general computing resource domain, mainly based on the embedded operating system, supplemented by various peripheral drivers and special function software, mainly realizing functions such as interface communication and dual-redundancy collaborative scheduling. The logical function is mainly achieved by carrying out hardware description language design in the programmable logic domain to form a standard interface or customized interface protocol, as well as some control logic. The hardware, system software, and logic system work together with clear boundaries and moderate coupling to achieve the overall function and performance of the electromechanical management computer.

[0046] In specific implementation, this embodiment develops system software and logic system on CPU and FPGA respectively, wherein:

[0047] Hardware architecture such as Figure 3 As shown in the figure, it conforms to the high integration development trend of airborne embedded computing systems and realizes the moderate coupling of software and hardware. At the same time, the clear boundary and modular component design facilitate the subsequent local upgrade maintenance and problem fault isolation and location. It is one of the best technical routes for realizing embedded computing systems.

[0048] The principle of software and hardware integration is as follows Figure 4 As shown. The hardware core PSOC consists of two parts: FPGA and CPU. The embedded operating system runs on a RAM7 core on the CPU side, and the other three cores are bound to the customer's specific tasks to run the upper-level application software. As an extended peripheral of the CPU, FPGA communicates with the CPU using high-speed buses such as AXI, mainly realizing various external interfaces and other control logics of the electromechanical management computer, such as discrete quantity acquisition, discrete quantity output, FC optoelectronic card PCIe communication, 1394 daughter card PCIe communication, RS-422A communication, DDR memory control, SRAM memory control, and AXI communication between the CPU, synchronization control, fault logic channel, etc.

[0049] The electromechanical management computer communicates with the surrounding avionics systems, display terminals, and remote interface units in a timely manner through the close cooperation of the CPU and FPGA. It completes dual redundancy management through the cooperation of cross data links CCDL, synchronization logic, and fault logic, thereby achieving the reliability of the electromechanical management system.

[0050] The CPU frequency is up to 1GHz, the PSOC is connected to an external 128Mb FLASH for program storage, and is equipped with a 128KB non-volatile static random access memory NVRAM for storing important information. The processor system PS side and the programmable logic PL side are tightly coupled through multiple data interfaces and numerous interconnection control signals. Designers can efficiently integrate user-created hardware accelerators, custom functions or interfaces in the PL. The processor can access the PL, and the PL can also access the memory resources in the PS.

[0051] The processor in the SOC is started first, and the configuration of the FPGA (bitstream download) can be done as part of the system startup or at some point in the future. In addition, the FPGA can be reconfigured completely or partially dynamically while in use. Partial reconfiguration allows only a portion of the FPGA to be configured. This gives the user the option of making partial modifications to the design. For example, updating coefficients or, if necessary, time-division multiplexing FPGA resources by replacing algorithms. The latter is similar to dynamically loading and unloading software modules.

[0052] PSOC has an integrated PCIE controller, which expands the 1394 interface and FC interface through the PCIE interface. The PS and PL sides are equipped with 1GB and 2GB high-speed DDR3SDRAM chips respectively, and the reception and output of ground / open signals and the protocol conversion of the RS-422A interface are completed through the PL logic. At the same time, the computing unit reserves RS232 serial port and network port to support system maintenance. The bus width of the DDR3SDRAM on the PS side is 32bit, and the maximum operating frequency is 533MHz (data rate can reach 1066Mbps), and the bus width of the DDR3SDRAM on the PL side is 64bit, and the maximum operating frequency can reach 800MHz (data rate can reach 1600Mbps). PSOC is connected to an external 128Mb FLASH for program storage, equipped with 128KB non-volatile static random access memory NVRAM, and the 1394 bus is used between the two computing units to implement the CCDL protocol.

[0053] In one embodiment, the 1394 bus is implemented in the form of a daughter card, a PCIE controller is integrated inside the PSOC computing unit, and the 1394 interface of the 1394 bus daughter card and the FC interface of the FC bus are extended through the PCIE interface. The daughter card uses a dedicated connector for the CTOLC interface to realize the data transmission of the PCIe interface and the 1394B signal, and the electrical performance of the PCIe complies with the PCIe2.0 specification. The daughter card is connected to the motherboard by a TOLC connector through a buckle method, the insertion height is 10mm, and the daughter card connector and the device are designed in a non-conforming manner.

[0054] In one embodiment, Figure 5 As shown, the 1394 bus daughter card uses a CTOLC interface connector to realize data transmission of the PCIe interface and the 1394B signal; the 1394 bus daughter card uses a TOLC interface connector to connect to the motherboard of the PSOC computing unit in a snap-on manner.

[0055] In this embodiment, each motherboard is connected to various communication modules, such as FC modules, 1394 communication modules, etc., through snap-in cards, which not only ensures normal communication and data acquisition functions, but also has good interchangeability.

[0056] In one embodiment, the 1394 bus daughter card includes an FPGA core processing module, an IEEE1394B interface module, a host interface module, a power module and other modules. ; Wherein

[0057] The FPGA core processing module is connected to the 1394B interface module via the 1394 physical layer interface, and is used to convert the data packets generated by the FPGA core processing module into physical signals that comply with the IEEE1394 standard, and convert the received physical signals into data packets for processing by the FPGA core processing module;

[0058] The FPGA core processing module is connected to the host interface module through the PCIe bus to realize data interaction with the corresponding PSOC computing unit;

[0059] The power module provides power for the FPGA core processing module, IEEE1394B interface module, and host interface module;

[0060] FPGA is also connected to other auxiliary modules such as Flash memory, clock module, debug interface, etc. to store user configuration files, network operation parameters, provide stable clock signals and support debugging functions.

[0061] The daughter card hardware design is based on a super-large-scale FPGA, which implements the AS5643 protocol stack, PCIE host interface, 1394 link layer, network operation parameter loading, data packet transceiver processing, CCDL data forwarding and reverse forwarding, etc. The 1394 physical layer implements the transceiver level conversion of IEEE1394 protocol data packets. Flash is used to store user configuration files and network operation parameters. The host interface uses PCIE×4 to implement data interaction with the host. Each module is interconnected through FPGA logic.

[0062] In one embodiment, a fault logic circuit is also included. A dedicated fault channel is designed between the two PSOC computing unit channels. The two channel fault logics are key components of the control system, which determine whether the computer can be controlled normally. The channel fault logic circuit is used to terminate its control of the interface module when the current PSOC computing unit fails, and the other PSOC computing unit takes over and outputs the electromechanical management task.

[0063] During the specific implementation of this embodiment, after the electromechanical management computer is powered on normally, computing unit A and computing unit B are synchronized through a hard-wired connection. After the synchronization is completed, when the main processor module of computing unit A fails, the channel failure logic circuit on the main processor module terminates its control over the interface module. After the backup processor module of computing unit B detects the failure of the main module, it takes over the output control task.

[0064] In one embodiment, under the dual redundancy mechanism, each communication channel between the PSOC computing units is provided with a hardware synchronization indicator, which continuously monitors the operating status of the two PSOC computing units and sends a synchronization signal; the real-time transmission of the synchronization signal between the two PSOC computing units is completed through the synchronization bus, so that the two PSOC computing units always maintain a consistent operating status.

[0065] It should be noted that the work adopts a software-based, soft / hard combined double handshake synchronization algorithm. The two channels always run the same task.

[0066] In one embodiment, in the implementation path of the CCDL data link, the present invention selects the 1394 bus that complies with the IEEE 1394b standard as the physical link for implementing the CCDL. The 1394 bus daughter card includes three CC nodes; two CC nodes are used to connect the transceiver transmission channels of the data cross link CCDL between the PSOC computing units, and the other CC node is used to communicate with the remote interface unit.

[0067] In this embodiment, in order to support external information exchange and data collection, the device integrates two isomorphic PSOC computing unit motherboards, each of which integrates a 1394 communication daughter card. Two of the three nodes of the daughter card are used for the transmission channel of the data cross link CCDL, and the other node is used to communicate with the remote interface unit, with a communication rate of 200M. Through the 1394 channel, the electromechanical management computer sends instructions to the remote interface unit to control the relevant actuators to perform business actions; through the 1394 channel, the collected data of the remote interface unit is transmitted to the electromechanical management computer, and the corresponding processing is reported to the avionics system through the FC photoelectric path.

[0068] In the specific implementation, the dual bus topology based on the 1394 bus is as follows Figure 6 As shown in the figure, the redundant structure is composed of two flight control computers. The communication subcard of each computing unit (electromechanical management computer) has three CC nodes. Each node is connected to the communication subcards of other remote interface units as a CC to form a bus. Each CC node is responsible for bus synchronization and bus control management. The dual-redundancy computing nodes are connected through a cross-connection link (CCDL) to realize the dual-redundancy electromechanical management data interaction function and provide another level of fault tolerance. The CCDL of each computing unit uses three 1394 buses, including one sending bus and two receiving buses. Each bus supports a rate of 400Mbps. The three 1394 buses are independent of each other and do not affect each other.

[0069] Each 1394 bus daughter card forms a dual redundant interconnection mechanism with a remote interface unit (RIU)'s respective 1394 interface unit. Among them, the external system collects status information through FC and FPGA communication, issues commands based on the status, and performs parameter binding and other services through the FC bus. The PL side of the PSOC performs data transmission. After receiving the command, the PS side software first parses the command, understands the task to be performed by the main processing module, and performs different operations according to different tasks to complete the electromechanical management work. Discrete quantities are multiple channels. These multiple channels can be input for collection and output for driving. All channels can be arbitrarily extracted and combined to complete the corresponding business functions. After detecting the status of the input channel, it is necessary to be able to promptly feedback to the avionics system. One is to immediately notify the main control center of any status change; the other is to uniformly report the status of each channel after a specific time.

[0070] The dual-redundancy high-reliability computing device based on PSOC provided by the present invention is introduced in detail above. In this embodiment, specific examples are applied to illustrate the principle and implementation mode of the present invention. The description of the above embodiment is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

[0071] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined in the present embodiments may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown in the present embodiment, but will conform to the widest range consistent with the principles and novel features disclosed in the present embodiment.

Claims

1. A dual-redundancy high-reliability computing device based on PSOC, characterized in that: include: Two isomorphic PSOC computing units, 1394 bus daughter card and remote interface unit; Both PSOC computing units communicate and interact with the avionics system via the FC bus, and are used to receive and process electromechanical management task commands issued by the avionics system; The two PSOC computing units implement a dual redundancy mechanism through a CCDL protocol; The two PSOC computing units are respectively integrated with a 1394 bus daughter card, and the 1394 daughter card is used as a point-to-point physical link to implement the CCDL protocol between the two PSOC computing units to form a dual redundant interconnection mechanism; The two PSOC computing units are respectively connected to a remote interface unit RIU through the 1394 bus daughter card integrated therein, and are used to control the execution mechanism related to the remote interface unit RIU to execute business actions.

2. A dual-redundancy high-reliability computing device based on PSOC according to claim 1, characterized in that: The PSOC computing unit includes: a PS end composed of a CPU, and a PL end composed of an FPGA; the PL end of the PSOC computing unit is used to implement data communication protocols and interface logic control; after the PS end of the PSOC computing unit receives the electromechanical management task command sent by the avionics system, it parses the command, obtains the task to be executed, and performs electromechanical management on the upper-layer application according to different task control operations.

3. A dual-redundancy high-reliability computing device based on PSOC according to claim 1, characterized in that: The PSOC computing unit has an integrated PCIE controller, which expands the 1394 interface of the 1394 bus daughter card and the FC interface of the FC bus through the PCIE interface.

4. A dual-redundancy high-reliability computing device based on PSOC according to claim 3, characterized in that: The 1394 bus daughter card adopts a CTOLC interface connector to realize data transmission between the PCIe interface and the 1394B signal; the 1394 bus daughter card uses a TOLC interface connector to be connected to the motherboard of the PSOC computing unit in a snap-on manner.

5. A dual-redundancy high-reliability computing device based on PSOC according to claim 1, characterized in that: The 1394 bus daughter card includes an FPGA core processing module, an IEEE1394B interface module, a host interface module and a power supply module; in The FPGA core processing module is connected to the 1394B interface module via a 1394 physical layer interface, and is used to convert the data packets generated by the FPGA core processing module into physical signals that comply with the IEEE 1394 standard, and convert the received physical signals into data packets for processing by the FPGA core processing module; The FPGA core processing module is connected to the host interface module via a PCIe bus to implement data interaction with the corresponding PSOC computing unit; The power supply module provides power for the FPGA core processing module, the IEEE1394B interface module, and the host interface module.

6. A dual-redundancy high-reliability computing device based on PSOC according to claim 1, characterized in that: It also includes a fault logic circuit; a fault channel is constructed between the two PSOC computing units through the channel fault logic circuit, and the channel fault logic circuit is used to terminate its control over the interface module when a fault occurs in the current PSOC computing unit, and the other PSOC computing unit takes over and outputs the electromechanical management task.

7. A dual-redundancy high-reliability computing device based on PSOC according to claim 1, characterized in that: Under the dual redundancy mechanism, each communication channel between the PSOC computing units is provided with a hardware synchronization indicator, which continuously monitors the operating status of the two PSOC computing units and sends a synchronization signal; the two PSOC computing units complete the real-time transmission of the synchronization signal through the synchronization bus, so that the two PSOC computing units always maintain a consistent operating status.

8. A dual-redundancy high-reliability computing device based on PSOC according to claim 1, characterized in that: The 1394 bus daughter card includes three CC nodes; two CC nodes are used to connect the transceiver transmission channels of the data cross link CCDL between the PSOC computing units, and the other CC node is used to communicate with the remote interface unit.

9. A dual-redundancy high-reliability computing device based on PSOC according to claim 1, characterized in that: It also includes a lightning protection processing unit, which is connected to the two PSOC computing units via an FMC connector adapter board.

10. An airborne electromechanical integrated management device, characterized in that: A dual-redundancy high-reliability computing device based on PSOC comprising any one of claims 1-9.

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