Resource packaging method and device, electronic equipment and storage medium

Abstract

The invention discloses a resource packaging method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring a design netlist file of a chip to be arranged, wherein the design netlist file comprises a plurality of resources to be packaged; obtaining a preset packaging rule; a connected graph is generated based on a preset packaging rule, nodes of the connected graph represent the to-be-packaged resources, and the to-be-packaged resources represented by at least two nodes connected with edges of the connected graph are allowed to be packaged; scoring the edges of the connected graph to obtain scores of the edges; and packaging the connected graph according to the scores of the edges. According to the technical scheme provided by the embodiment of the invention, the scale of the layout unit can be reduced, the difficulty of distributing the position for the layout unit is reduced, the efficiency and success rate of distributing the position for the layout unit are improved, and the layout efficiency is further improved.

Description

Technical Field

[0001] The present application relates to the field of chip layout technology, and in particular to a resource packaging method, device, electronic device and storage medium. Background Art

[0002] Chip layout is an important part of the chip design process. It refers to the process of placing circuit components (such as lookup tables, triggers, etc.) at specific locations on the chip and connecting these components to each other during the chip design process.

[0003] In the related art, electronic devices use layout algorithms to implement chip layout, wherein the layout algorithm takes line length, timing, density, etc. as optimization targets. That is, when laying out the chip, it is necessary to make the total line length in the design netlist shorter, the density of the design netlist smaller, and the timing of the design netlist more optimized.

[0004] However, when faced with ultra-large-scale chips with hundreds of millions of gates, their design netlists usually have millions of lookup tables and triggers. When the above-mentioned layout algorithm is used to layout ultra-large-scale chips with hundreds of millions of gates, the layout efficiency is greatly reduced. Summary of the invention

[0005] The present application proposes a resource packaging method, device, electronic device and storage medium.

[0006] In a first aspect, an embodiment of the present application provides a resource packaging method, the method comprising: obtaining a design netlist file of a chip to be laid out, the design netlist file comprising multiple resources to be packaged; obtaining a preset packaging rule, the preset packaging rule representing a rule that must be satisfied for packaging at least two of the multiple resources to be packaged; generating a connected graph based on the preset packaging rule, the nodes of the connected graph representing the resources to be packaged, and the resources to be packaged represented by at least two nodes connected by the edges of the connected graph are allowed to be packaged; scoring the edges of the connected graph respectively to obtain edge scores; and packaging the connected graph according to the edge scores.

[0007] In a second aspect, an embodiment of the present application provides a resource packaging device, the device comprising: a file acquisition module, used to acquire a design netlist file of a chip to be laid out, the design netlist file comprising multiple resources to be packaged; a rule acquisition module, used to acquire a preset packaging rule, the preset packaging rule represents a rule that needs to be satisfied for packaging at least two of the multiple resources to be packaged; a connectivity graph generation module, used to generate a connectivity graph based on the preset packaging rule, the nodes of the connectivity graph represent the resources to be packaged, and the resources to be packaged represented by at least two nodes connected by the edges of the connectivity graph are allowed to be packaged; a scoring module, used to score the edges of the connectivity graph respectively to obtain the scores of the edges; and a packaging module, used to package the connectivity graph according to the scores of the edges.

[0008] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a memory; one or more processors coupled to the memory; and one or more programs, wherein one or more applications are stored in the memory and configured to be executed by one or more processors, and the one or more programs are configured to execute the method described in the first aspect.

[0009] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer program instructions are stored. The computer program instructions can be called by a processor to execute the method described in the first aspect.

[0010] In a fifth aspect, an embodiment of the present application provides a computer program product, which, when instructions in the computer program product are executed, is used to implement the method described in the first aspect.

[0011] Compared with the prior art, the technical solution provided by the embodiment of the present application generates a connectivity graph based on preset packing rules after obtaining the design netlist file of the chip to be laid out. The nodes in the connectivity graph represent the resources to be packed. The resources to be packed represented by at least two nodes connected by the edges in the connectivity graph are allowed to be packed. The electronic device packs the resources to be packed based on the connectivity graph to obtain resource packages, and then packs and encapsulates the resources of the same resource package. In this way, the layout units to be determined are changed from the original resources to resource packages. The number of resource packages is much smaller than the number of resources. Therefore, the scale of the layout unit is greatly reduced, and the difficulty of allocating positions for the layout units is greatly reduced. The efficiency and success rate of allocating positions for the above-mentioned layout units are improved, thereby improving the layout efficiency. In addition, since the resources in the same resource package meet the preset packing rules, the legality and feasibility of the layout can be ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 This is a flowchart of a resource packaging method provided by an embodiment of the present application.

[0014] Figure 2 It is a schematic diagram of a connectivity graph provided by an embodiment of the present application.

[0015] Figure 3 This is a flowchart of a resource packaging method provided by another embodiment of the present application.

[0016] Figure 4It is a block diagram of a resource packaging device provided by an embodiment of the present application.

[0017] Figure 5 It is a structural block diagram of an electronic device provided by an embodiment of the present application.

[0018] Figure 6 It is a structural block diagram of a computer-readable storage medium provided by an embodiment of the present application. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0020] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0021] In the related technologies, for ultra-large-scale chips with hundreds of millions of gates, the design netlist usually contains millions of heterogeneous resources such as lookup tables and triggers. The chip layout must not only consider the line length, density, and timing, but also needs to allocate accurate positions for the above heterogeneous resources. If the above heterogeneous resources are not allocated accurate positions, it may cause thread and timing deterioration, increase the burden on the wiring link, and even cause layout failure.

[0022] Based on this, the embodiment of the present application provides a new resource packaging solution. After obtaining the design netlist file of the chip to be laid out, a connectivity graph is generated based on preset packaging rules. The nodes in the connectivity graph represent the resources to be packaged. The resources to be packaged represented by at least two nodes connected by the edges in the connectivity graph are allowed to be packaged. The electronic device packages the resources to be packaged based on the connectivity graph to obtain resource packages, and then packages and encapsulates the resources of the same resource package. In this way, the layout units to be determined are changed from the original resources to resource packages. The number of resource packages is much smaller than the number of resources. Therefore, the scale of the layout unit is greatly reduced, and the difficulty of allocating positions for the layout units is greatly reduced. The efficiency and success rate of allocating positions for the above-mentioned layout units are improved, thereby improving the layout efficiency. In addition, since the resources in the same resource package meet the preset packaging rules, the legality and feasibility of the layout can be ensured.

[0023] In this embodiment, the execution subject of each step may be an electronic device with powerful computing power, such as a personal computer, a server, etc. Optionally, a layout software is installed in the electronic device to implement the layout function of the chip to be laid out, and the execution subject of each step may be the layout software.

[0024] Please refer to Figure 1 , which shows a flow chart of a resource packaging method provided by an embodiment of the present application. The method includes the following process.

[0025] S101, obtaining a design netlist file of a chip to be laid out.

[0026] The chip to be laid out may be a Field Programmable Gate Array (FPGA) chip, a Programmable Logic Device (PLD), or a Complex Programmable Logic Device (CPLD).

[0027] The design netlist file of the chip to be laid out includes multiple resources for realizing the functions of the chip to be laid out. In the present embodiment, the above-mentioned multiple resources include programmable input and output units, configurable logic blocks, digital clock management modules, embedded blocks, embedded bottom functional units, embedded dedicated hard cores, etc. The programmable input and output unit (Input / Output Block, IOB) is used to manage and adapt to a variety of electrical standards. The configurable logic block (Configurable Logic Block, CLB) is the main logic resource for realizing sequential logic circuits and combinational logic circuits. CLB includes a lookup table (Look-Up Table, LUT) and FF (Flip-Flop, i.e., trigger). The lookup table is the basic unit for realizing combinational logic in the chip to be laid out. The trigger is used to realize the sequential logic function. The digital clock management module (Digital Clock Manager, DCM) is used to provide digital clock management functions, including the frequency division and multiplication functions of the clock, and can maintain the phase relationship between the clocks. The embedded low-level functional units provide additional functions and performance, such as (Delay Locked Loop, DLL), (Phase Locked Loop, PLL), and Digital System Processing (DSP). The embedded dedicated hard core provides specific hardware functions.

[0028] In this embodiment, the design netlist file includes multiple resources to be packaged. The above-mentioned resources to be packaged include heterogeneous resources such as lookup tables and triggers, and the resources to be packaged may also include homogeneous resources, which is not limited in this embodiment of the present application. After obtaining the layout instructions corresponding to the chip to be laid out, the electronic device can read the above-mentioned design netlist file from the local, and parse the above-mentioned design netlist file to obtain relevant information of the resources to be packaged in the design netlist file, such as connection relationships.

[0029] S102, obtaining preset packaging rules.

[0030] The preset packaging rule represents the rules that must be met when packaging at least two of the multiple resources to be packaged. The preset packaging rule is used to ensure the legality and feasibility of the layout. In some embodiments, the preset packaging rule includes at least one of the following: a first packaging rule, a second packaging rule, and a third packaging rule.

[0031] The first packing rule is a packing rule set by a user, which can be customized by the user before triggering the layout instruction of the chip to be laid out.

[0032] The second packing rule is a packing rule determined based on the hardware connection information of the chip to be laid out. The second packing rule is used to indicate the maximum number limit of resource packages. For example, if the maximum number of resource packages is limited to 5, then a resource package includes at most 5 resources to be packaged. The second packing rule can be generated by the electronic device to obtain the hardware connection information of the chip to be laid out from the design netlist file and based on the above hardware connection information. The hardware connection information of different chips to be laid out is usually different, so when laying out different chips to be laid out, the second packing rule is also different.

[0033] The third packing rule is a packing rule determined based on the architectural feature information of the chip to be laid out, and the third packing rule is used to indicate the architectural constraints of the resources to be packaged in the resource package. For example, there is a configuration logic block in the chip to be laid out, and in the same configuration logic block, the lookup table and the trigger need to follow certain layout rules. The third packing rule can be generated by the electronic device to obtain the architectural feature information of the chip to be laid out from the design netlist file and based on the above architectural feature information. Since the architectural feature information of different chips to be laid out is usually different, the third packing rule is also different when laying out different chips to be laid out.

[0034] S103: Generate a connectivity graph based on preset packing rules.

[0035] The connectivity graph is a mathematical model of the internal resources of the chip to be laid out and the connection relationship between them, and is mainly used to describe how the logical resources and interconnection resources of the chip to be laid out are physically connected to each other. The connectivity graph includes nodes and edges. In an embodiment of the present application, the nodes of the connectivity graph represent the resources to be packaged, and the resources to be packaged represented by at least two nodes connected by the edges of the connectivity graph are allowed to be packaged.

[0036] The electronic device detects whether any two resources to be packaged among a plurality of resources to be packaged satisfy the preset packaging rule based on the preset packaging rule, and if so, determines the above-mentioned any two resources to be packaged as two nodes connected to the same edge.

[0037] When there are multiple preset packing rules, for example, when the preset packing rules include a first packing rule, a second packing rule, and a third packing rule, the electronic device will determine multiple resources to be packaged that simultaneously meet the first packing rule, the second packing rule, and the third packing rule as nodes connected to the same edge.

[0038] Please refer to Figure 2 , which shows a schematic diagram of a connectivity graph provided by an embodiment of the present application. The chips to be laid out include A1, A2, A3, A4, B1, B2, B3, C1, C2, C3, C4, C5, D1, D2, and E waiting for packaged resources, wherein A1, A2, A3, and A4 belong to one resource package, A3 and C2 belong to one resource package, C1, C2, and C3 belong to one resource package, C2 and C4 belong to one resource package, C4 and C5 belong to one resource package, C3 and C5 belong to one resource package, B1 and B2 belong to one resource package, B2 and B3 belong to one resource package, B2 and A3 belong to one resource package, and D1 and D2 belong to one resource package.

[0039] S104, scoring the edges of the connected graph to obtain edge scores.

[0040] The edge scores are used to indicate the order in which the resources to be packaged in the connected graph are packaged. The packaging process will be described in the following embodiments.

[0041] S105, packing the connected graph based on the edge scores.

[0042] Packaging refers to the process of packaging multiple resources into an independent resource. The specific packaging process will be described in the following embodiments.

[0043] After packaging and encapsulating at least one resource package, the layout units in the chip to be laid out are changed from the original resources to resource packages. The number of resource packages included in the chip to be laid out is much smaller than the number of resources included in the chip to be laid out. Therefore, the scale of the layout unit is greatly reduced, which can improve the layout efficiency. In addition, since the resources in the same resource package all meet the preset packaging rules, the layout legality and feasibility of the packaging unit can be guaranteed.

[0044] In some embodiments, the electronic device allocates a location for the resource package, and then uses line length, density, and timing as optimization targets to implement the layout of the chip to be laid out, and obtains a layout file of the chip to be laid out.

[0045] In summary, the technical solution provided by the embodiment of the present application, after obtaining the design netlist file of the chip to be laid out, generates a connectivity graph based on preset packaging rules, the nodes in the connectivity graph represent the resources to be packaged, and the resources to be packaged represented by at least two nodes connected by the edges in the connectivity graph are allowed to be packaged, and the electronic device packages the resources to be packaged based on the connectivity graph to obtain resource packages, and then packages and encapsulates the resources of the same resource package, so that the layout units to be determined are changed from the original resources to resource packages, and the number of resource packages is much smaller than the number of resources, so the scale of the layout unit is greatly reduced, and the difficulty of allocating positions for the layout units is greatly reduced, which improves the efficiency and success rate of allocating positions for the above-mentioned layout units, thereby improving the layout efficiency. In addition, since the resources in the same resource package meet the preset packaging rules, the legality and feasibility of the layout can be ensured.

[0046] Please refer to Figure 3 , which shows a flow chart of a packaging method provided by an embodiment of the present application. In the embodiment of the present application, S104 is replaced by S304, and the method includes the following process.

[0047] S301, obtaining a design netlist file of a chip to be laid out.

[0048] The design netlist file of the chip to be laid out includes multiple resources to be packaged.

[0049] In some embodiments, the electronic device obtains the number of resources to be packaged, and if the number of resources to be packaged is greater than a preset number, the subsequent steps are executed, and if the number of resources to be packaged is less than the preset number, the subsequent steps are not executed, and the resource to be packaged is directly allocated a position. The preset number can be set based on experiments or experience, and the embodiments of the present application are not limited to this.

[0050] S302, obtaining preset packaging rules.

[0051] The preset packaging rule represents a rule that needs to be satisfied when packaging at least two resources to be packaged among the multiple resources to be packaged.

[0052] S303: Generate a connectivity graph based on preset packing rules.

[0053] The nodes in the connected graph represent resources to be packaged, and the resources to be packaged represented by at least two nodes connected by the edges in the connected graph belong to one resource package.

[0054] S304 , scoring the edge based on the number of nodes connected to the edge and the latency of the resources represented by each node connected to the edge to obtain a score of the edge.

[0055] The delay of the resources represented by each node connected by the edge is determined based on the connection relationship between the above resources. The electronic device obtains the connection relationship between the above resources, then obtains the delay corresponding to each connection line, and determines the sum of the delays of all connection lines as the delay of the resources represented by each node connected by the edge.

[0056] The score of an edge is positively correlated with the number of nodes connected to the edge, that is, the greater the number of nodes connected to the edge, the higher the score of the edge. Similarly, the score of an edge is positively correlated with the latency of the resources represented by each node connected to the edge, that is, the greater the latency of the resources represented by each node connected to the edge, the higher the score of the edge.

[0057] In some embodiments, S304 is implemented as the following sub-steps:

[0058] S3041, determining a connection score based on the number of nodes connected by the edge.

[0059] The connection score is positively correlated with the number of nodes connected by the edge. The larger the number of nodes connected by the edge, the larger the connection score.

[0060] In some embodiments, the electronic device directly determines the number of nodes connected by the edge as the connection score. In other embodiments, the electronic device determines the connection score based on the first mapping relationship and the number of nodes connected by the edge. The first mapping relationship is a mapping relationship between different numbers of nodes connected by the edge and different connection scores. The first mapping relationship is set according to experiments or experience.

[0061] S3042: Determine a delay score based on the delay of the resources represented by each node connected to the edge.

[0062] The delay score is positively correlated with the delay of the resources represented by each node connected to the edge. The greater the delay of the resources represented by each node connected to the edge, the greater the delay score.

[0063] In some embodiments, the electronic device directly determines the delay of the resources represented by each node connected to the edge as the delay score. In other embodiments, the electronic device determines the connection score based on the second mapping relationship and the delay of the resources represented by each node connected to the edge. The second mapping relationship is a mapping relationship between different delays of the resources represented by each node connected to the edge and different delay scores. The second mapping relationship is set according to experiments or experience.

[0064] S3043: Determine the score of the edge based on the connection score and the delay score.

[0065] The edge score is positively correlated with the connection score, and the edge score is positively correlated with the delay score.

[0066] In some embodiments, the electronic device obtains a first weight corresponding to the connection score and a second weight corresponding to the delay score; obtains a first product between the connection score and the first weight; obtains a second product between the second weight and the delay score; and determines the score of the edge by summing the first product and the second product.

[0067] The value of the first weight is 0 to 1. The value of the second weight is 0 to 1. Both the first weight and the second weight can be set according to experiments or experience. In some embodiments, the sum of the first weight and the second weight is 1. Therefore, the first weight and the second weight can be called balance coefficients. If the user chooses to prioritize the resource packages corresponding to the edges with a larger number of connected nodes, the first weight can be set to be greater than the second weight; if the user chooses to prioritize the resource packages corresponding to the edges with a larger number of experimental resources represented by each connected node, the second weight can be set to be greater than the first weight.

[0068] Exemplarily, the process of determining the edge score can be expressed by the following calculation formula:

[0069] score=α*score connect +(1-α)*score delay .

[0070] Among them, α is the first weight, (1-α) is the second weight, and score connect Indicates the connection score, score delay Indicates the delay fraction.

[0071] S305 , packaging the resources to be packaged represented by the nodes connected to the edges that meet the packaging conditions in the connectivity graph in sequence according to the arrangement order of the scores of the edges in the connectivity graph.

[0072] Optionally, the electronic device packages the resource packages corresponding to the edges in descending order of the edge scores. The packaging condition means that the edge score is greater than a specified threshold, which is set based on experiments or experience, and is not limited in the present embodiment.

[0073] In some embodiments, the electronic device updates the connectivity graph after each packaging until there are no edges in the connectivity graph that meet the packaging conditions. Wherein, updating the connectivity graph means replacing the edges and the nodes connected by the edges with the identifiers of the resource packages. In this way, as the number of resource packages packaged by the electronic device increases, the scale of the entire connectivity graph will gradually decrease until it disappears.

[0074] Please refer again Figure 3 The electronic device performs packing based on the connectivity graph shown in part (a). Specifically, A1, A2, A3, and A4 are packed into A, B1 and B2 are packed into B12, C1, C2, and C3 are packed into C123, C4 and C5 are packed into C45, and D1 and D2 are packed into D. The electronic device also updates the connectivity graph based on the above packing process to obtain the connectivity graph shown in part (b). After that, the electronic device continues to pack and packs B12 and B3 into B, and packs C123 and C45 into C. The electronic device also updates the connectivity graph based on the above packing process to obtain the connectivity graph shown in part (c).

[0075] S306, implementing the layout of the chip to be laid out based on the packaged connectivity graph, and obtaining a layout file of the chip to be laid out.

[0076] In summary, the technical solution provided by the embodiment of the present application, after obtaining the design netlist file of the chip to be laid out, divides the multiple resources to be packaged included in the design netlist file into at least one resource package based on the preset packaging rules, and then generates a resource connectivity graph represented by nodes, and multiple resources to be packaged connected by an edge in the connectivity graph are allowed to be packaged, and the electronic device scores each edge, and packages the resource packages corresponding to the edge in the connectivity graph based on the score of each edge, and iterates the connectivity graph until all resource packages are packaged. In this way, the layout unit to be determined is changed from the original resource to a resource package, and the number of resource packages is much smaller than the number of resources. Therefore, the scale of the layout unit is greatly reduced, and the difficulty of allocating a position to the layout unit is greatly reduced, which improves the efficiency and success rate of allocating a position to the above-mentioned layout unit, thereby improving the layout efficiency. In addition, since the resources in the same resource package meet the preset packaging rules, the legality and feasibility of the layout can be ensured.

[0077] Please refer to Figure 4 , which shows a structural block diagram of a packaging device provided by an embodiment of the present application. The device includes: a file acquisition module 410, a rule acquisition module 420, a connectivity graph generation module 430, a scoring module 440, and a packaging module 450.

[0078] The file acquisition module 410 is used to acquire a design netlist file of a chip to be laid out, wherein the design netlist file includes a plurality of resources to be packaged.

[0079] The rule acquisition module 420 is used to acquire a preset packaging rule, where the preset packaging rule represents a rule that needs to be satisfied when packaging at least two resources to be packaged among the multiple resources to be packaged.

[0080] The connectivity graph generation module 430 is used to generate a connectivity graph based on preset packaging rules, wherein the nodes of the connectivity graph represent resources to be packaged, and the resources to be packaged represented by at least two nodes connected by the edges of the connectivity graph are allowed to be packaged.

[0081] The scoring module 440 is used to score the edges of the connected graph respectively to obtain the scores of the edges.

[0082] The packing module 450 is used to pack the connected graph according to the edge scores.

[0083] In some embodiments, the scoring module 440 is used to score the edge based on the number of nodes connected to the edge and the latency of the resources to be packaged represented by each node connected to the edge to obtain the score of the edge. The packaging module 450 is used to package the resources to be packaged represented by at least two nodes connected to the edge in the connected graph that meet the packaging condition in sequence according to the arrangement order of the scores of each edge in the connected graph, and the packaging condition means that the score of the edge is greater than a specified threshold; after each packaging is completed, the connected graph is updated until there is no edge that meets the packaging condition in the connected graph.

[0084] In some embodiments, the packaging module 450 is used to determine the connection score based on the number of nodes connected to the edge; determine the delay score based on the delay of the resources to be packaged represented by each node connected to the edge; determine the edge score based on the connection score and the delay score, and the edge score is positively correlated with the connection score, and the edge score is positively correlated with the delay score.

[0085] In some embodiments, the packaging module 450 is used to obtain a first weight corresponding to the connection score and a second weight corresponding to the delay score; obtain a first product between the connection score and the first weight; obtain a second product between the second weight and the delay score; and determine the sum of the first product and the second product as the score of the edge.

[0086] In some embodiments, the preset packing rules include at least one of the following: a first packing rule, a second packing rule, and a third packing rule; wherein the first packing rule is a packing rule set by a user, the second packing rule is a packing rule determined based on hardware connection information of the chip to be laid out, and the third packing rule is a packing rule determined based on architectural feature information of the chip to be laid out.

[0087] In some embodiments, when the preset packing rules include a first packing rule, a second packing rule, and a third packing rule, the connectivity graph generation module 430 is used to represent multiple resources to be packaged that simultaneously satisfy the first packing rule, the second packing rule, and the third packing rule as nodes connected to the same edge.

[0088] In some embodiments, the device further includes: a quantity acquisition module (not shown in the figure). The quantity acquisition module is used to acquire the quantity of resources to be packaged. The rule acquisition module 420 is used to execute the step of acquiring a preset packaging rule when the quantity of resources to be packaged is greater than a preset quantity.

[0089] In summary, the technical solution provided by the embodiment of the present application, after obtaining the design netlist file of the chip to be laid out, generates a connectivity graph based on preset packaging rules, the nodes in the connectivity graph represent the resources to be packaged, and the resources to be packaged represented by at least two nodes connected by the edges in the connectivity graph are allowed to be packaged, and the electronic device packages the resources to be packaged based on the connectivity graph to obtain resource packages, and then packages and encapsulates the resources of the same resource package, so that the layout units to be determined are changed from the original resources to resource packages, and the number of resource packages is much smaller than the number of resources, so the scale of the layout unit is greatly reduced, and the difficulty of allocating positions for the layout units is greatly reduced, which improves the efficiency and success rate of allocating positions for the above-mentioned layout units, thereby improving the layout efficiency. In addition, since the resources in the same resource package meet the preset packaging rules, the legality and feasibility of the layout can be ensured.

[0090] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0091] In several embodiments provided in the present application, the coupling between modules may be electrical, mechanical or other forms of coupling.

[0092] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0093] See also Figure 5, which shows that the embodiment of the present application also provides an electronic device 500, which includes: one or more multi-core processors 510, a memory 520, and one or more applications. Among them, the one or more applications are stored in the memory 520 and are configured to be executed by the one or more multi-core processors 510, and the one or more applications are configured to execute the method described in the above embodiment.

[0094] The multi-core processor 510 may include one or more processing cores. The multi-core processor 510 uses various interfaces and lines to connect various parts of the entire battery management system, and executes various functions and processes data of the battery management system by running or executing instructions, programs, code sets or instruction sets stored in the memory 520, and calling data stored in the memory 520. Optionally, the multi-core processor 510 can be implemented in at least one hardware form of digital signal processing (DSP), field programmable gate array (FPGA), and programmable logic array (PLA). The multi-core processor 510 can integrate one or more combinations of a central multi-core processor 510 (CPU), a graphics multi-core processor 510 (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the multi-core processor 510, but may be implemented separately through a communication chip.

[0095] The memory 520 may include a random access memory 520 (Random Access Memory, RAM), and may also include a read-only memory 520 (Read-Only Memory). The memory 520 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 520 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the various method embodiments described below, etc. The data storage area may also store data created by the electronic device during use (such as a phone book, audio and video data, chat record data), etc.

[0096] See also Figure 6, which shows that an embodiment of the present application also provides a computer-readable storage medium 600, in which computer program instructions 610 are stored. The computer program instructions 610 can be called by a processor to execute the method described in the above embodiment.

[0097] The computer-readable storage medium 600 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer-readable storage medium 600 includes a non-transitory computer-readable storage medium. The computer-readable storage medium 600 has storage space for computer program instructions 610 for executing any method steps in the above method. These computer program instructions 610 may be read from or written to one or more computer program products. The computer program instructions 610 may be compressed in an appropriate form.

[0098] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A resource packaging method, characterized in that: The method comprises: Obtaining a design netlist file of a chip to be laid out, wherein the design netlist file includes a plurality of resources to be packaged; Obtaining a preset packaging rule, where the preset packaging rule represents a rule that needs to be satisfied when packaging at least two of the multiple resources to be packaged; Generate a connectivity graph based on the preset packaging rule, wherein the nodes of the connectivity graph represent the resources to be packaged, and the resources to be packaged represented by at least two nodes connected by the edges of the connectivity graph are allowed to be packaged; Scoring the edges of the connected graph respectively to obtain scores of the edges; The connected graph is packed according to the scores of the edges.

2. The method according to claim 1, characterized in that Scoring the edges of the connected graph respectively to obtain scores of the edges includes: Based on the number of nodes connected to the edge and the latency of the resources to be packaged represented by each node connected to the edge, the edge is scored to obtain a score of the edge; The packing of the connected graph according to the scores of the edges includes: According to the arrangement order of the scores of the edges in the connected graph, the resources to be packaged represented by at least two nodes connected by the edges that meet the packaging condition in the connected graph are packaged respectively, wherein the packaging condition refers to that the score of the edge is greater than a specified threshold; After each packing is completed, the connected graph is updated until there are no edges in the connected graph that meet the packing condition.

3. The method according to claim 2, characterized in that Scoring the edge based on the number of nodes connected to the edge and the latency of the resources to be packaged represented by each node connected to the edge to obtain the score of the edge includes: determining a connection score based on the number of nodes connected by the edge; Determine a delay score based on the delays of the resources to be packaged represented by the nodes connected to the edge; Based on the connection score and the delay score, a score of the edge is determined, the score of the edge is positively correlated with the connection score, and the score of the edge is positively correlated with the delay score.

4. The method according to claim 3, characterized in that The determining the score of the edge based on the connection score, the delay score and the balance coefficient includes: Obtaining a first weight corresponding to the connection score and a second weight corresponding to the delay score; Obtaining a first product between the connection score and the first weight; Obtaining a second product between the second weight and the delay fraction; The sum of the first product and the second product is determined as the score of the edge.

5. The method according to any one of claims 1 to 4, characterized in that: The preset packaging rule includes at least one of the following: a first packaging rule, a second packaging rule, and a third packaging rule; The first packing rule is a packing rule set by a user, the second packing rule is a packing rule determined based on hardware connection information of the chip to be laid out, and the third packing rule is a packing rule determined based on architectural feature information of the chip to be laid out.

6. The method according to claim 5, characterized in that In a case where the preset packing rules include the first packing rule, the second packing rule, and the third packing rule, generating a connectivity graph based on the preset packing rules includes: A plurality of resources to be packaged that simultaneously satisfy the first packaging rule, the second packaging rule, and the third packaging rule are respectively characterized as nodes connected to the same edge.

7. The method according to any one of claims 1 to 4, characterized in that Before obtaining the preset packaging rule, the method further includes: Obtain the number of resources to be packaged; When the number of the resources to be packaged is greater than a preset number, the step of obtaining the preset packaging rule is performed.

8. A resource packaging device, characterized in that: The device comprises: A file acquisition module, used to acquire a design netlist file of a chip to be laid out, wherein the design netlist file includes a plurality of resources to be packaged; A rule acquisition module, used to acquire a preset packaging rule, wherein the preset packaging rule represents a rule that needs to be satisfied when packaging at least two of the plurality of resources to be packaged; A connectivity graph generation module, configured to generate a connectivity graph based on the preset packaging rule, wherein the nodes of the connectivity graph represent the resources to be packaged, and the resources to be packaged represented by at least two nodes connected by the edges of the connectivity graph are allowed to be packaged; A scoring module, used for scoring the edges of the connected graph respectively to obtain the scores of the edges; A packing module is used to pack the connected graph according to the scores of the edges.

9. An electronic device, characterized in that: include: Memory; One or more processors coupled to the memory; One or more programs, wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs are configured to execute the method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and the computer program instructions can be called by a processor to execute the method according to any one of claims 1 to 7.

Images